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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(11// CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> [[VD]], ptr [[RS1]], <vscale x 1 x i64> [[RS2]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]15//16vbfloat16mf4_t test_vluxei64_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1,17 vuint64m1_t rs2, size_t vl) {18 return __riscv_vluxei64_tu(vd, rs1, rs2, vl);19}20 21// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(22// CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {23// CHECK-RV64-NEXT: entry:24// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> [[VD]], ptr [[RS1]], <vscale x 2 x i64> [[RS2]], i64 [[VL]])25// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]26//27vbfloat16mf2_t test_vluxei64_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1,28 vuint64m2_t rs2, size_t vl) {29 return __riscv_vluxei64_tu(vd, rs1, rs2, vl);30}31 32// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(33// CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {34// CHECK-RV64-NEXT: entry:35// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> [[VD]], ptr [[RS1]], <vscale x 4 x i64> [[RS2]], i64 [[VL]])36// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]37//38vbfloat16m1_t test_vluxei64_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1,39 vuint64m4_t rs2, size_t vl) {40 return __riscv_vluxei64_tu(vd, rs1, rs2, vl);41}42 43// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(44// CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {45// CHECK-RV64-NEXT: entry:46// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> [[VD]], ptr [[RS1]], <vscale x 8 x i64> [[RS2]], i64 [[VL]])47// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]48//49vbfloat16m2_t test_vluxei64_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1,50 vuint64m8_t rs2, size_t vl) {51 return __riscv_vluxei64_tu(vd, rs1, rs2, vl);52}53 54// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(55// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {56// CHECK-RV64-NEXT: entry:57// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> [[VD]], ptr [[RS1]], <vscale x 1 x i64> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)58// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]59//60vbfloat16mf4_t test_vluxei64_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd,61 const __bf16 *rs1, vuint64m1_t rs2,62 size_t vl) {63 return __riscv_vluxei64_tum(vm, vd, rs1, rs2, vl);64}65 66// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(67// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {68// CHECK-RV64-NEXT: entry:69// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> [[VD]], ptr [[RS1]], <vscale x 2 x i64> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)70// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]71//72vbfloat16mf2_t test_vluxei64_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd,73 const __bf16 *rs1, vuint64m2_t rs2,74 size_t vl) {75 return __riscv_vluxei64_tum(vm, vd, rs1, rs2, vl);76}77 78// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(79// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {80// CHECK-RV64-NEXT: entry:81// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> [[VD]], ptr [[RS1]], <vscale x 4 x i64> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)82// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]83//84vbfloat16m1_t test_vluxei64_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd,85 const __bf16 *rs1, vuint64m4_t rs2,86 size_t vl) {87 return __riscv_vluxei64_tum(vm, vd, rs1, rs2, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(91// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> [[VD]], ptr [[RS1]], <vscale x 8 x i64> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)94// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]95//96vbfloat16m2_t test_vluxei64_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd,97 const __bf16 *rs1, vuint64m8_t rs2,98 size_t vl) {99 return __riscv_vluxei64_tum(vm, vd, rs1, rs2, vl);100}101 102// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tumu(103// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {104// CHECK-RV64-NEXT: entry:105// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> [[VD]], ptr [[RS1]], <vscale x 1 x i64> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)106// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]107//108vbfloat16mf4_t test_vluxei64_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd,109 const __bf16 *rs1, vuint64m1_t rs2,110 size_t vl) {111 return __riscv_vluxei64_tumu(vm, vd, rs1, rs2, vl);112}113 114// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tumu(115// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {116// CHECK-RV64-NEXT: entry:117// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> [[VD]], ptr [[RS1]], <vscale x 2 x i64> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)118// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]119//120vbfloat16mf2_t test_vluxei64_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd,121 const __bf16 *rs1, vuint64m2_t rs2,122 size_t vl) {123 return __riscv_vluxei64_tumu(vm, vd, rs1, rs2, vl);124}125 126// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tumu(127// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {128// CHECK-RV64-NEXT: entry:129// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> [[VD]], ptr [[RS1]], <vscale x 4 x i64> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)130// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]131//132vbfloat16m1_t test_vluxei64_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd,133 const __bf16 *rs1, vuint64m4_t rs2,134 size_t vl) {135 return __riscv_vluxei64_tumu(vm, vd, rs1, rs2, vl);136}137 138// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tumu(139// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {140// CHECK-RV64-NEXT: entry:141// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> [[VD]], ptr [[RS1]], <vscale x 8 x i64> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)142// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]143//144vbfloat16m2_t test_vluxei64_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd,145 const __bf16 *rs1, vuint64m8_t rs2,146 size_t vl) {147 return __riscv_vluxei64_tumu(vm, vd, rs1, rs2, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_mu(151// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: entry:153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> [[VD]], ptr [[RS1]], <vscale x 1 x i64> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)154// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]155//156vbfloat16mf4_t test_vluxei64_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd,157 const __bf16 *rs1, vuint64m1_t rs2,158 size_t vl) {159 return __riscv_vluxei64_mu(vm, vd, rs1, rs2, vl);160}161 162// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_mu(163// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {164// CHECK-RV64-NEXT: entry:165// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> [[VD]], ptr [[RS1]], <vscale x 2 x i64> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)166// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]167//168vbfloat16mf2_t test_vluxei64_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd,169 const __bf16 *rs1, vuint64m2_t rs2,170 size_t vl) {171 return __riscv_vluxei64_mu(vm, vd, rs1, rs2, vl);172}173 174// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_mu(175// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {176// CHECK-RV64-NEXT: entry:177// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> [[VD]], ptr [[RS1]], <vscale x 4 x i64> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)178// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]179//180vbfloat16m1_t test_vluxei64_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd,181 const __bf16 *rs1, vuint64m4_t rs2,182 size_t vl) {183 return __riscv_vluxei64_mu(vm, vd, rs1, rs2, vl);184}185 186// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_mu(187// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i64> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {188// CHECK-RV64-NEXT: entry:189// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> [[VD]], ptr [[RS1]], <vscale x 8 x i64> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)190// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]191//192vbfloat16m2_t test_vluxei64_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd,193 const __bf16 *rs1, vuint64m8_t rs2,194 size_t vl) {195 return __riscv_vluxei64_mu(vm, vd, rs1, rs2, vl);196}197