299 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(11// CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: [[ENTRY:.*:]]13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i16> [[VS1]], i64 [[VL]])14// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]15//16vbfloat16mf4_t test_vrgatherei16_vv_bf16mf4_tu(vbfloat16mf4_t vd,17 vbfloat16mf4_t vs2,18 vuint16mf4_t vs1, size_t vl) {19 return __riscv_vrgatherei16_tu(vd, vs2, vs1, vl);20}21 22// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(23// CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {24// CHECK-RV64-NEXT: [[ENTRY:.*:]]25// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i16> [[VS1]], i64 [[VL]])26// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]27//28vbfloat16mf2_t test_vrgatherei16_vv_bf16mf2_tu(vbfloat16mf2_t vd,29 vbfloat16mf2_t vs2,30 vuint16mf2_t vs1, size_t vl) {31 return __riscv_vrgatherei16_tu(vd, vs2, vs1, vl);32}33 34// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(35// CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {36// CHECK-RV64-NEXT: [[ENTRY:.*:]]37// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i16> [[VS1]], i64 [[VL]])38// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]39//40vbfloat16m1_t test_vrgatherei16_vv_bf16m1_tu(vbfloat16m1_t vd,41 vbfloat16m1_t vs2, vuint16m1_t vs1,42 size_t vl) {43 return __riscv_vrgatherei16_tu(vd, vs2, vs1, vl);44}45 46// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(47// CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {48// CHECK-RV64-NEXT: [[ENTRY:.*:]]49// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i16> [[VS1]], i64 [[VL]])50// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]51//52vbfloat16m2_t test_vrgatherei16_vv_bf16m2_tu(vbfloat16m2_t vd,53 vbfloat16m2_t vs2, vuint16m2_t vs1,54 size_t vl) {55 return __riscv_vrgatherei16_tu(vd, vs2, vs1, vl);56}57 58// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(59// CHECK-RV64-SAME: <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {60// CHECK-RV64-NEXT: [[ENTRY:.*:]]61// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i16> [[VS1]], i64 [[VL]])62// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]63//64vbfloat16m4_t test_vrgatherei16_vv_bf16m4_tu(vbfloat16m4_t vd,65 vbfloat16m4_t vs2, vuint16m4_t vs1,66 size_t vl) {67 return __riscv_vrgatherei16_tu(vd, vs2, vs1, vl);68}69 70// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(71// CHECK-RV64-SAME: <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: [[ENTRY:.*:]]73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS2]], <vscale x 32 x i16> [[VS1]], i64 [[VL]])74// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]75//76vbfloat16m8_t test_vrgatherei16_vv_bf16m8_tu(vbfloat16m8_t vd,77 vbfloat16m8_t vs2, vuint16m8_t vs1,78 size_t vl) {79 return __riscv_vrgatherei16_tu(vd, vs2, vs1, vl);80}81 82// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(83// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {84// CHECK-RV64-NEXT: [[ENTRY:.*:]]85// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)86// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]87//88vbfloat16mf4_t test_vrgatherei16_vv_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd,89 vbfloat16mf4_t vs2,90 vuint16mf4_t vs1, size_t vl) {91 return __riscv_vrgatherei16_tum(vm, vd, vs2, vs1, vl);92}93 94// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(95// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {96// CHECK-RV64-NEXT: [[ENTRY:.*:]]97// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)98// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]99//100vbfloat16mf2_t test_vrgatherei16_vv_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd,101 vbfloat16mf2_t vs2,102 vuint16mf2_t vs1, size_t vl) {103 return __riscv_vrgatherei16_tum(vm, vd, vs2, vs1, vl);104}105 106// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tum(107// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {108// CHECK-RV64-NEXT: [[ENTRY:.*:]]109// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv4bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)110// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]111//112vbfloat16m1_t test_vrgatherei16_vv_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd,113 vbfloat16m1_t vs2,114 vuint16m1_t vs1, size_t vl) {115 return __riscv_vrgatherei16_tum(vm, vd, vs2, vs1, vl);116}117 118// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tum(119// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {120// CHECK-RV64-NEXT: [[ENTRY:.*:]]121// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv8bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)122// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]123//124vbfloat16m2_t test_vrgatherei16_vv_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd,125 vbfloat16m2_t vs2,126 vuint16m2_t vs1, size_t vl) {127 return __riscv_vrgatherei16_tum(vm, vd, vs2, vs1, vl);128}129 130// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tum(131// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {132// CHECK-RV64-NEXT: [[ENTRY:.*:]]133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv16bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)134// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]135//136vbfloat16m4_t test_vrgatherei16_vv_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd,137 vbfloat16m4_t vs2,138 vuint16m4_t vs1, size_t vl) {139 return __riscv_vrgatherei16_tum(vm, vd, vs2, vs1, vl);140}141 142// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tum(143// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {144// CHECK-RV64-NEXT: [[ENTRY:.*:]]145// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv32bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS2]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)146// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]147//148vbfloat16m8_t test_vrgatherei16_vv_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd,149 vbfloat16m8_t vs2,150 vuint16m8_t vs1, size_t vl) {151 return __riscv_vrgatherei16_tum(vm, vd, vs2, vs1, vl);152}153 154// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tumu(155// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {156// CHECK-RV64-NEXT: [[ENTRY:.*:]]157// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)158// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]159//160vbfloat16mf4_t test_vrgatherei16_vv_bf16mf4_tumu(vbool64_t vm,161 vbfloat16mf4_t vd,162 vbfloat16mf4_t vs2,163 vuint16mf4_t vs1, size_t vl) {164 return __riscv_vrgatherei16_tumu(vm, vd, vs2, vs1, vl);165}166 167// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tumu(168// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {169// CHECK-RV64-NEXT: [[ENTRY:.*:]]170// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)171// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]172//173vbfloat16mf2_t test_vrgatherei16_vv_bf16mf2_tumu(vbool32_t vm,174 vbfloat16mf2_t vd,175 vbfloat16mf2_t vs2,176 vuint16mf2_t vs1, size_t vl) {177 return __riscv_vrgatherei16_tumu(vm, vd, vs2, vs1, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tumu(181// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: [[ENTRY:.*:]]183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv4bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)184// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]185//186vbfloat16m1_t test_vrgatherei16_vv_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd,187 vbfloat16m1_t vs2,188 vuint16m1_t vs1, size_t vl) {189 return __riscv_vrgatherei16_tumu(vm, vd, vs2, vs1, vl);190}191 192// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tumu(193// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {194// CHECK-RV64-NEXT: [[ENTRY:.*:]]195// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv8bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)196// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]197//198vbfloat16m2_t test_vrgatherei16_vv_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd,199 vbfloat16m2_t vs2,200 vuint16m2_t vs1, size_t vl) {201 return __riscv_vrgatherei16_tumu(vm, vd, vs2, vs1, vl);202}203 204// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tumu(205// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {206// CHECK-RV64-NEXT: [[ENTRY:.*:]]207// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv16bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)208// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]209//210vbfloat16m4_t test_vrgatherei16_vv_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd,211 vbfloat16m4_t vs2,212 vuint16m4_t vs1, size_t vl) {213 return __riscv_vrgatherei16_tumu(vm, vd, vs2, vs1, vl);214}215 216// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tumu(217// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {218// CHECK-RV64-NEXT: [[ENTRY:.*:]]219// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv32bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS2]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)220// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]221//222vbfloat16m8_t test_vrgatherei16_vv_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd,223 vbfloat16m8_t vs2,224 vuint16m8_t vs1, size_t vl) {225 return __riscv_vrgatherei16_tumu(vm, vd, vs2, vs1, vl);226}227 228// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_mu(229// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {230// CHECK-RV64-NEXT: [[ENTRY:.*:]]231// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)232// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]233//234vbfloat16mf4_t test_vrgatherei16_vv_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd,235 vbfloat16mf4_t vs2,236 vuint16mf4_t vs1, size_t vl) {237 return __riscv_vrgatherei16_mu(vm, vd, vs2, vs1, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_mu(241// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: [[ENTRY:.*:]]243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)244// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]245//246vbfloat16mf2_t test_vrgatherei16_vv_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd,247 vbfloat16mf2_t vs2,248 vuint16mf2_t vs1, size_t vl) {249 return __riscv_vrgatherei16_mu(vm, vd, vs2, vs1, vl);250}251 252// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_mu(253// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {254// CHECK-RV64-NEXT: [[ENTRY:.*:]]255// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv4bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)256// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]257//258vbfloat16m1_t test_vrgatherei16_vv_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd,259 vbfloat16m1_t vs2, vuint16m1_t vs1,260 size_t vl) {261 return __riscv_vrgatherei16_mu(vm, vd, vs2, vs1, vl);262}263 264// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_mu(265// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {266// CHECK-RV64-NEXT: [[ENTRY:.*:]]267// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv8bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)268// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]269//270vbfloat16m2_t test_vrgatherei16_vv_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd,271 vbfloat16m2_t vs2, vuint16m2_t vs1,272 size_t vl) {273 return __riscv_vrgatherei16_mu(vm, vd, vs2, vs1, vl);274}275 276// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_mu(277// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {278// CHECK-RV64-NEXT: [[ENTRY:.*:]]279// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv16bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)280// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]281//282vbfloat16m4_t test_vrgatherei16_vv_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd,283 vbfloat16m4_t vs2, vuint16m4_t vs1,284 size_t vl) {285 return __riscv_vrgatherei16_mu(vm, vd, vs2, vs1, vl);286}287 288// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_mu(289// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {290// CHECK-RV64-NEXT: [[ENTRY:.*:]]291// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv32bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS2]], <vscale x 32 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)292// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]293//294vbfloat16m8_t test_vrgatherei16_vv_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd,295 vbfloat16m8_t vs2, vuint16m8_t vs1,296 size_t vl) {297 return __riscv_vrgatherei16_mu(vm, vd, vs2, vs1, vl);298}299