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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfmin -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(11// CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: [[ENTRY:.*:]]13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], i64 [[RS1]], i64 [[VL]], i64 2)14// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]15//16vbfloat16mf4_t test_vslidedown_vx_bf16mf4_tu(vbfloat16mf4_t vd,17 vbfloat16mf4_t vs2, size_t rs1,18 size_t vl) {19 return __riscv_vslidedown_tu(vd, vs2, rs1, vl);20}21 22// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(23// CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {24// CHECK-RV64-NEXT: [[ENTRY:.*:]]25// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], i64 [[RS1]], i64 [[VL]], i64 2)26// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]27//28vbfloat16mf2_t test_vslidedown_vx_bf16mf2_tu(vbfloat16mf2_t vd,29 vbfloat16mf2_t vs2, size_t rs1,30 size_t vl) {31 return __riscv_vslidedown_tu(vd, vs2, rs1, vl);32}33 34// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(35// CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {36// CHECK-RV64-NEXT: [[ENTRY:.*:]]37// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], i64 [[RS1]], i64 [[VL]], i64 2)38// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]39//40vbfloat16m1_t test_vslidedown_vx_bf16m1_tu(vbfloat16m1_t vd, vbfloat16m1_t vs2,41 size_t rs1, size_t vl) {42 return __riscv_vslidedown_tu(vd, vs2, rs1, vl);43}44 45// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(46// CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {47// CHECK-RV64-NEXT: [[ENTRY:.*:]]48// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], i64 [[RS1]], i64 [[VL]], i64 2)49// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]50//51vbfloat16m2_t test_vslidedown_vx_bf16m2_tu(vbfloat16m2_t vd, vbfloat16m2_t vs2,52 size_t rs1, size_t vl) {53 return __riscv_vslidedown_tu(vd, vs2, rs1, vl);54}55 56// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(57// CHECK-RV64-SAME: <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {58// CHECK-RV64-NEXT: [[ENTRY:.*:]]59// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], i64 [[RS1]], i64 [[VL]], i64 2)60// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]61//62vbfloat16m4_t test_vslidedown_vx_bf16m4_tu(vbfloat16m4_t vd, vbfloat16m4_t vs2,63 size_t rs1, size_t vl) {64 return __riscv_vslidedown_tu(vd, vs2, rs1, vl);65}66 67// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(68// CHECK-RV64-SAME: <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {69// CHECK-RV64-NEXT: [[ENTRY:.*:]]70// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS2]], i64 [[RS1]], i64 [[VL]], i64 2)71// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]72//73vbfloat16m8_t test_vslidedown_vx_bf16m8_tu(vbfloat16m8_t vd, vbfloat16m8_t vs2,74 size_t rs1, size_t vl) {75 return __riscv_vslidedown_tu(vd, vs2, rs1, vl);76}77 78// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(79// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {80// CHECK-RV64-NEXT: [[ENTRY:.*:]]81// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)82// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]83//84vbfloat16mf4_t test_vslidedown_vx_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd,85 vbfloat16mf4_t vs2, size_t rs1,86 size_t vl) {87 return __riscv_vslidedown_tum(vm, vd, vs2, rs1, vl);88}89 90// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(91// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: [[ENTRY:.*:]]93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)94// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]95//96vbfloat16mf2_t test_vslidedown_vx_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd,97 vbfloat16mf2_t vs2, size_t rs1,98 size_t vl) {99 return __riscv_vslidedown_tum(vm, vd, vs2, rs1, vl);100}101 102// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tum(103// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {104// CHECK-RV64-NEXT: [[ENTRY:.*:]]105// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)106// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]107//108vbfloat16m1_t test_vslidedown_vx_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd,109 vbfloat16m1_t vs2, size_t rs1,110 size_t vl) {111 return __riscv_vslidedown_tum(vm, vd, vs2, rs1, vl);112}113 114// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tum(115// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {116// CHECK-RV64-NEXT: [[ENTRY:.*:]]117// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.mask.nxv8bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)118// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]119//120vbfloat16m2_t test_vslidedown_vx_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd,121 vbfloat16m2_t vs2, size_t rs1,122 size_t vl) {123 return __riscv_vslidedown_tum(vm, vd, vs2, rs1, vl);124}125 126// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tum(127// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {128// CHECK-RV64-NEXT: [[ENTRY:.*:]]129// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.mask.nxv16bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)130// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]131//132vbfloat16m4_t test_vslidedown_vx_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd,133 vbfloat16m4_t vs2, size_t rs1,134 size_t vl) {135 return __riscv_vslidedown_tum(vm, vd, vs2, rs1, vl);136}137 138// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tum(139// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {140// CHECK-RV64-NEXT: [[ENTRY:.*:]]141// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.mask.nxv32bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)142// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]143//144vbfloat16m8_t test_vslidedown_vx_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd,145 vbfloat16m8_t vs2, size_t rs1,146 size_t vl) {147 return __riscv_vslidedown_tum(vm, vd, vs2, rs1, vl);148}149 150// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tumu(151// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {152// CHECK-RV64-NEXT: [[ENTRY:.*:]]153// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)154// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]155//156vbfloat16mf4_t test_vslidedown_vx_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd,157 vbfloat16mf4_t vs2, size_t rs1,158 size_t vl) {159 return __riscv_vslidedown_tumu(vm, vd, vs2, rs1, vl);160}161 162// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tumu(163// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {164// CHECK-RV64-NEXT: [[ENTRY:.*:]]165// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)166// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]167//168vbfloat16mf2_t test_vslidedown_vx_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd,169 vbfloat16mf2_t vs2, size_t rs1,170 size_t vl) {171 return __riscv_vslidedown_tumu(vm, vd, vs2, rs1, vl);172}173 174// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tumu(175// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {176// CHECK-RV64-NEXT: [[ENTRY:.*:]]177// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)178// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]179//180vbfloat16m1_t test_vslidedown_vx_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd,181 vbfloat16m1_t vs2, size_t rs1,182 size_t vl) {183 return __riscv_vslidedown_tumu(vm, vd, vs2, rs1, vl);184}185 186// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tumu(187// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {188// CHECK-RV64-NEXT: [[ENTRY:.*:]]189// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.mask.nxv8bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)190// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]191//192vbfloat16m2_t test_vslidedown_vx_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd,193 vbfloat16m2_t vs2, size_t rs1,194 size_t vl) {195 return __riscv_vslidedown_tumu(vm, vd, vs2, rs1, vl);196}197 198// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tumu(199// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {200// CHECK-RV64-NEXT: [[ENTRY:.*:]]201// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.mask.nxv16bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)202// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]203//204vbfloat16m4_t test_vslidedown_vx_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd,205 vbfloat16m4_t vs2, size_t rs1,206 size_t vl) {207 return __riscv_vslidedown_tumu(vm, vd, vs2, rs1, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tumu(211// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: [[ENTRY:.*:]]213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.mask.nxv32bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)214// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]215//216vbfloat16m8_t test_vslidedown_vx_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd,217 vbfloat16m8_t vs2, size_t rs1,218 size_t vl) {219 return __riscv_vslidedown_tumu(vm, vd, vs2, rs1, vl);220}221 222// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_mu(223// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {224// CHECK-RV64-NEXT: [[ENTRY:.*:]]225// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)226// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]227//228vbfloat16mf4_t test_vslidedown_vx_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd,229 vbfloat16mf4_t vs2, size_t rs1,230 size_t vl) {231 return __riscv_vslidedown_mu(vm, vd, vs2, rs1, vl);232}233 234// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_mu(235// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {236// CHECK-RV64-NEXT: [[ENTRY:.*:]]237// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)238// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]239//240vbfloat16mf2_t test_vslidedown_vx_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd,241 vbfloat16mf2_t vs2, size_t rs1,242 size_t vl) {243 return __riscv_vslidedown_mu(vm, vd, vs2, rs1, vl);244}245 246// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_mu(247// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {248// CHECK-RV64-NEXT: [[ENTRY:.*:]]249// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)250// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]251//252vbfloat16m1_t test_vslidedown_vx_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd,253 vbfloat16m1_t vs2, size_t rs1,254 size_t vl) {255 return __riscv_vslidedown_mu(vm, vd, vs2, rs1, vl);256}257 258// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_mu(259// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {260// CHECK-RV64-NEXT: [[ENTRY:.*:]]261// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.mask.nxv8bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)262// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]263//264vbfloat16m2_t test_vslidedown_vx_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd,265 vbfloat16m2_t vs2, size_t rs1,266 size_t vl) {267 return __riscv_vslidedown_mu(vm, vd, vs2, rs1, vl);268}269 270// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_mu(271// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {272// CHECK-RV64-NEXT: [[ENTRY:.*:]]273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.mask.nxv16bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)274// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]275//276vbfloat16m4_t test_vslidedown_vx_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd,277 vbfloat16m4_t vs2, size_t rs1,278 size_t vl) {279 return __riscv_vslidedown_mu(vm, vd, vs2, rs1, vl);280}281 282// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_mu(283// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS2:%.*]], i64 noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {284// CHECK-RV64-NEXT: [[ENTRY:.*:]]285// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.mask.nxv32bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS2]], i64 [[RS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)286// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]287//288vbfloat16m8_t test_vslidedown_vx_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd,289 vbfloat16m8_t vs2, size_t rs1,290 size_t vl) {291 return __riscv_vslidedown_mu(vm, vd, vs2, rs1, vl);292}293