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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfwma -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(11// CHECK-RV64-SAME: <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 3)14// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]15//16vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2(vfloat32mf2_t vd, vbfloat16mf4_t vs1,17 vbfloat16mf4_t vs2, size_t vl) {18 return __riscv_vfwmaccbf16(vd, vs1, vs2, vl);19}20 21// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(22// CHECK-RV64-SAME: <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {23// CHECK-RV64-NEXT: entry:24// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 3)25// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]26//27vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2(vfloat32mf2_t vd, __bf16 vs1,28 vbfloat16mf4_t vs2, size_t vl) {29 return __riscv_vfwmaccbf16(vd, vs1, vs2, vl);30}31 32// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(33// CHECK-RV64-SAME: <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {34// CHECK-RV64-NEXT: entry:35// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 3)36// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]37//38vfloat32m1_t test_vfwmaccbf16_vv_f32m1(vfloat32m1_t vd, vbfloat16mf2_t vs1,39 vbfloat16mf2_t vs2, size_t vl) {40 return __riscv_vfwmaccbf16(vd, vs1, vs2, vl);41}42 43// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(44// CHECK-RV64-SAME: <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {45// CHECK-RV64-NEXT: entry:46// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 3)47// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]48//49vfloat32m1_t test_vfwmaccbf16_vf_f32m1(vfloat32m1_t vd, __bf16 vs1,50 vbfloat16mf2_t vs2, size_t vl) {51 return __riscv_vfwmaccbf16(vd, vs1, vs2, vl);52}53 54// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(55// CHECK-RV64-SAME: <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {56// CHECK-RV64-NEXT: entry:57// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 3)58// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]59//60vfloat32m2_t test_vfwmaccbf16_vv_f32m2(vfloat32m2_t vd, vbfloat16m1_t vs1,61 vbfloat16m1_t vs2, size_t vl) {62 return __riscv_vfwmaccbf16(vd, vs1, vs2, vl);63}64 65// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(66// CHECK-RV64-SAME: <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {67// CHECK-RV64-NEXT: entry:68// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 3)69// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]70//71vfloat32m2_t test_vfwmaccbf16_vf_f32m2(vfloat32m2_t vd, __bf16 vs1,72 vbfloat16m1_t vs2, size_t vl) {73 return __riscv_vfwmaccbf16(vd, vs1, vs2, vl);74}75 76// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(77// CHECK-RV64-SAME: <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {78// CHECK-RV64-NEXT: entry:79// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 3)80// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]81//82vfloat32m4_t test_vfwmaccbf16_vv_f32m4(vfloat32m4_t vd, vbfloat16m2_t vs1,83 vbfloat16m2_t vs2, size_t vl) {84 return __riscv_vfwmaccbf16(vd, vs1, vs2, vl);85}86 87// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(88// CHECK-RV64-SAME: <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {89// CHECK-RV64-NEXT: entry:90// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 3)91// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]92//93vfloat32m4_t test_vfwmaccbf16_vf_f32m4(vfloat32m4_t vd, __bf16 vs1,94 vbfloat16m2_t vs2, size_t vl) {95 return __riscv_vfwmaccbf16(vd, vs1, vs2, vl);96}97 98// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8(99// CHECK-RV64-SAME: <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {100// CHECK-RV64-NEXT: entry:101// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 3)102// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]103//104vfloat32m8_t test_vfwmaccbf16_vv_f32m8(vfloat32m8_t vd, vbfloat16m4_t vs1,105 vbfloat16m4_t vs2, size_t vl) {106 return __riscv_vfwmaccbf16(vd, vs1, vs2, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8(110// CHECK-RV64-SAME: <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 3)113// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]114//115vfloat32m8_t test_vfwmaccbf16_vf_f32m8(vfloat32m8_t vd, __bf16 vs1,116 vbfloat16m4_t vs2, size_t vl) {117 return __riscv_vfwmaccbf16(vd, vs1, vs2, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_m(121// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)124// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]125//126vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_m(vbool64_t vm, vfloat32mf2_t vd,127 vbfloat16mf4_t vs1,128 vbfloat16mf4_t vs2, size_t vl) {129 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, vl);130}131 132// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_m(133// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {134// CHECK-RV64-NEXT: entry:135// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)136// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]137//138vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_m(vbool64_t vm, vfloat32mf2_t vd,139 __bf16 vs1, vbfloat16mf4_t vs2,140 size_t vl) {141 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, vl);142}143 144// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_m(145// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {146// CHECK-RV64-NEXT: entry:147// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)148// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]149//150vfloat32m1_t test_vfwmaccbf16_vv_f32m1_m(vbool32_t vm, vfloat32m1_t vd,151 vbfloat16mf2_t vs1, vbfloat16mf2_t vs2,152 size_t vl) {153 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, vl);154}155 156// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_m(157// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {158// CHECK-RV64-NEXT: entry:159// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)160// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]161//162vfloat32m1_t test_vfwmaccbf16_vf_f32m1_m(vbool32_t vm, vfloat32m1_t vd,163 __bf16 vs1, vbfloat16mf2_t vs2,164 size_t vl) {165 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, vl);166}167 168// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_m(169// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {170// CHECK-RV64-NEXT: entry:171// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)172// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]173//174vfloat32m2_t test_vfwmaccbf16_vv_f32m2_m(vbool16_t vm, vfloat32m2_t vd,175 vbfloat16m1_t vs1, vbfloat16m1_t vs2,176 size_t vl) {177 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, vl);178}179 180// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_m(181// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {182// CHECK-RV64-NEXT: entry:183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)184// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]185//186vfloat32m2_t test_vfwmaccbf16_vf_f32m2_m(vbool16_t vm, vfloat32m2_t vd,187 __bf16 vs1, vbfloat16m1_t vs2,188 size_t vl) {189 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, vl);190}191 192// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_m(193// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {194// CHECK-RV64-NEXT: entry:195// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)196// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]197//198vfloat32m4_t test_vfwmaccbf16_vv_f32m4_m(vbool8_t vm, vfloat32m4_t vd,199 vbfloat16m2_t vs1, vbfloat16m2_t vs2,200 size_t vl) {201 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, vl);202}203 204// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_m(205// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {206// CHECK-RV64-NEXT: entry:207// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)208// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]209//210vfloat32m4_t test_vfwmaccbf16_vf_f32m4_m(vbool8_t vm, vfloat32m4_t vd,211 __bf16 vs1, vbfloat16m2_t vs2,212 size_t vl) {213 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, vl);214}215 216// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_m(217// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {218// CHECK-RV64-NEXT: entry:219// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)220// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]221//222vfloat32m8_t test_vfwmaccbf16_vv_f32m8_m(vbool4_t vm, vfloat32m8_t vd,223 vbfloat16m4_t vs1, vbfloat16m4_t vs2,224 size_t vl) {225 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, vl);226}227 228// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_m(229// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {230// CHECK-RV64-NEXT: entry:231// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 7, i64 [[VL]], i64 3)232// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]233//234vfloat32m8_t test_vfwmaccbf16_vf_f32m8_m(vbool4_t vm, vfloat32m8_t vd,235 __bf16 vs1, vbfloat16m4_t vs2,236 size_t vl) {237 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, vl);238}239 240// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_rm(241// CHECK-RV64-SAME: <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 3)244// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]245//246vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_rm(vfloat32mf2_t vd,247 vbfloat16mf4_t vs1,248 vbfloat16mf4_t vs2, size_t vl) {249 return __riscv_vfwmaccbf16(vd, vs1, vs2, __RISCV_FRM_RNE, vl);250}251 252// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_rm(253// CHECK-RV64-SAME: <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {254// CHECK-RV64-NEXT: entry:255// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 3)256// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]257//258vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_rm(vfloat32mf2_t vd, __bf16 vs1,259 vbfloat16mf4_t vs2, size_t vl) {260 return __riscv_vfwmaccbf16(vd, vs1, vs2, __RISCV_FRM_RNE, vl);261}262 263// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_rm(264// CHECK-RV64-SAME: <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {265// CHECK-RV64-NEXT: entry:266// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 3)267// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]268//269vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm(vfloat32m1_t vd, vbfloat16mf2_t vs1,270 vbfloat16mf2_t vs2, size_t vl) {271 return __riscv_vfwmaccbf16(vd, vs1, vs2, __RISCV_FRM_RNE, vl);272}273 274// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_rm(275// CHECK-RV64-SAME: <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {276// CHECK-RV64-NEXT: entry:277// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 3)278// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]279//280vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm(vfloat32m1_t vd, __bf16 vs1,281 vbfloat16mf2_t vs2, size_t vl) {282 return __riscv_vfwmaccbf16(vd, vs1, vs2, __RISCV_FRM_RNE, vl);283}284 285// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_rm(286// CHECK-RV64-SAME: <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {287// CHECK-RV64-NEXT: entry:288// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 3)289// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]290//291vfloat32m2_t test_vfwmaccbf16_vv_f32m2_rm(vfloat32m2_t vd, vbfloat16m1_t vs1,292 vbfloat16m1_t vs2, size_t vl) {293 return __riscv_vfwmaccbf16(vd, vs1, vs2, __RISCV_FRM_RNE, vl);294}295 296// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_rm(297// CHECK-RV64-SAME: <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {298// CHECK-RV64-NEXT: entry:299// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 3)300// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]301//302vfloat32m2_t test_vfwmaccbf16_vf_f32m2_rm(vfloat32m2_t vd, __bf16 vs1,303 vbfloat16m1_t vs2, size_t vl) {304 return __riscv_vfwmaccbf16(vd, vs1, vs2, __RISCV_FRM_RNE, vl);305}306 307// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_rm(308// CHECK-RV64-SAME: <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {309// CHECK-RV64-NEXT: entry:310// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 3)311// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]312//313vfloat32m4_t test_vfwmaccbf16_vv_f32m4_rm(vfloat32m4_t vd, vbfloat16m2_t vs1,314 vbfloat16m2_t vs2, size_t vl) {315 return __riscv_vfwmaccbf16(vd, vs1, vs2, __RISCV_FRM_RNE, vl);316}317 318// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_rm(319// CHECK-RV64-SAME: <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {320// CHECK-RV64-NEXT: entry:321// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 3)322// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]323//324vfloat32m4_t test_vfwmaccbf16_vf_f32m4_rm(vfloat32m4_t vd, __bf16 vs1,325 vbfloat16m2_t vs2, size_t vl) {326 return __riscv_vfwmaccbf16(vd, vs1, vs2, __RISCV_FRM_RNE, vl);327}328 329// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_rm(330// CHECK-RV64-SAME: <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {331// CHECK-RV64-NEXT: entry:332// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 3)333// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]334//335vfloat32m8_t test_vfwmaccbf16_vv_f32m8_rm(vfloat32m8_t vd, vbfloat16m4_t vs1,336 vbfloat16m4_t vs2, size_t vl) {337 return __riscv_vfwmaccbf16(vd, vs1, vs2, __RISCV_FRM_RNE, vl);338}339 340// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_rm(341// CHECK-RV64-SAME: <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {342// CHECK-RV64-NEXT: entry:343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 3)344// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]345//346vfloat32m8_t test_vfwmaccbf16_vf_f32m8_rm(vfloat32m8_t vd, __bf16 vs1,347 vbfloat16m4_t vs2, size_t vl) {348 return __riscv_vfwmaccbf16(vd, vs1, vs2, __RISCV_FRM_RNE, vl);349}350 351// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_rm_m(352// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {353// CHECK-RV64-NEXT: entry:354// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 0, i64 [[VL]], i64 3)355// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]356//357vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_rm_m(vbool64_t vm, vfloat32mf2_t vd,358 vbfloat16mf4_t vs1,359 vbfloat16mf4_t vs2, size_t vl) {360 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);361}362 363// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_rm_m(364// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {365// CHECK-RV64-NEXT: entry:366// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 0, i64 [[VL]], i64 3)367// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]368//369vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_rm_m(vbool64_t vm, vfloat32mf2_t vd,370 __bf16 vs1, vbfloat16mf4_t vs2,371 size_t vl) {372 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);373}374 375// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_rm_m(376// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {377// CHECK-RV64-NEXT: entry:378// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 0, i64 [[VL]], i64 3)379// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]380//381vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_m(vbool32_t vm, vfloat32m1_t vd,382 vbfloat16mf2_t vs1,383 vbfloat16mf2_t vs2, size_t vl) {384 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);385}386 387// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_rm_m(388// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {389// CHECK-RV64-NEXT: entry:390// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 0, i64 [[VL]], i64 3)391// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]392//393vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_m(vbool32_t vm, vfloat32m1_t vd,394 __bf16 vs1, vbfloat16mf2_t vs2,395 size_t vl) {396 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);397}398 399// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_rm_m(400// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {401// CHECK-RV64-NEXT: entry:402// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 0, i64 [[VL]], i64 3)403// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]404//405vfloat32m2_t test_vfwmaccbf16_vv_f32m2_rm_m(vbool16_t vm, vfloat32m2_t vd,406 vbfloat16m1_t vs1,407 vbfloat16m1_t vs2, size_t vl) {408 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);409}410 411// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_rm_m(412// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {413// CHECK-RV64-NEXT: entry:414// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 0, i64 [[VL]], i64 3)415// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]416//417vfloat32m2_t test_vfwmaccbf16_vf_f32m2_rm_m(vbool16_t vm, vfloat32m2_t vd,418 __bf16 vs1, vbfloat16m1_t vs2,419 size_t vl) {420 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);421}422 423// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_rm_m(424// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {425// CHECK-RV64-NEXT: entry:426// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 0, i64 [[VL]], i64 3)427// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]428//429vfloat32m4_t test_vfwmaccbf16_vv_f32m4_rm_m(vbool8_t vm, vfloat32m4_t vd,430 vbfloat16m2_t vs1,431 vbfloat16m2_t vs2, size_t vl) {432 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);433}434 435// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_rm_m(436// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {437// CHECK-RV64-NEXT: entry:438// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 0, i64 [[VL]], i64 3)439// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]440//441vfloat32m4_t test_vfwmaccbf16_vf_f32m4_rm_m(vbool8_t vm, vfloat32m4_t vd,442 __bf16 vs1, vbfloat16m2_t vs2,443 size_t vl) {444 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);445}446 447// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_rm_m(448// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {449// CHECK-RV64-NEXT: entry:450// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 0, i64 [[VL]], i64 3)451// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]452//453vfloat32m8_t test_vfwmaccbf16_vv_f32m8_rm_m(vbool4_t vm, vfloat32m8_t vd,454 vbfloat16m4_t vs1,455 vbfloat16m4_t vs2, size_t vl) {456 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);457}458 459// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_rm_m(460// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {461// CHECK-RV64-NEXT: entry:462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 0, i64 [[VL]], i64 3)463// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]464//465vfloat32m8_t test_vfwmaccbf16_vf_f32m8_rm_m(vbool4_t vm, vfloat32m8_t vd,466 __bf16 vs1, vbfloat16m4_t vs2,467 size_t vl) {468 return __riscv_vfwmaccbf16(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);469}470