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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \4// RUN: -target-feature +zvfbfwma -disable-O0-optnone \5// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \6// RUN: FileCheck --check-prefix=CHECK-RV64 %s7 8#include <riscv_vector.h>9 10// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(11// CHECK-RV64-SAME: <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 2)14// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]15//16vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_tu(vfloat32mf2_t vd,17 vbfloat16mf4_t vs1,18 vbfloat16mf4_t vs2, size_t vl) {19 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, vl);20}21 22// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(23// CHECK-RV64-SAME: <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {24// CHECK-RV64-NEXT: entry:25// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 2)26// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]27//28vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_tu(vfloat32mf2_t vd, __bf16 vs1,29 vbfloat16mf4_t vs2, size_t vl) {30 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, vl);31}32 33// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(34// CHECK-RV64-SAME: <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {35// CHECK-RV64-NEXT: entry:36// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 2)37// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]38//39vfloat32m1_t test_vfwmaccbf16_vv_f32m1_tu(vfloat32m1_t vd, vbfloat16mf2_t vs1,40 vbfloat16mf2_t vs2, size_t vl) {41 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, vl);42}43 44// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(45// CHECK-RV64-SAME: <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {46// CHECK-RV64-NEXT: entry:47// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 2)48// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]49//50vfloat32m1_t test_vfwmaccbf16_vf_f32m1_tu(vfloat32m1_t vd, __bf16 vs1,51 vbfloat16mf2_t vs2, size_t vl) {52 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, vl);53}54 55// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(56// CHECK-RV64-SAME: <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {57// CHECK-RV64-NEXT: entry:58// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 2)59// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]60//61vfloat32m2_t test_vfwmaccbf16_vv_f32m2_tu(vfloat32m2_t vd, vbfloat16m1_t vs1,62 vbfloat16m1_t vs2, size_t vl) {63 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, vl);64}65 66// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(67// CHECK-RV64-SAME: <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {68// CHECK-RV64-NEXT: entry:69// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 2)70// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]71//72vfloat32m2_t test_vfwmaccbf16_vf_f32m2_tu(vfloat32m2_t vd, __bf16 vs1,73 vbfloat16m1_t vs2, size_t vl) {74 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, vl);75}76 77// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(78// CHECK-RV64-SAME: <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {79// CHECK-RV64-NEXT: entry:80// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 2)81// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]82//83vfloat32m4_t test_vfwmaccbf16_vv_f32m4_tu(vfloat32m4_t vd, vbfloat16m2_t vs1,84 vbfloat16m2_t vs2, size_t vl) {85 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, vl);86}87 88// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(89// CHECK-RV64-SAME: <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {90// CHECK-RV64-NEXT: entry:91// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 2)92// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]93//94vfloat32m4_t test_vfwmaccbf16_vf_f32m4_tu(vfloat32m4_t vd, __bf16 vs1,95 vbfloat16m2_t vs2, size_t vl) {96 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, vl);97}98 99// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_tu(100// CHECK-RV64-SAME: <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 2)103// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]104//105vfloat32m8_t test_vfwmaccbf16_vv_f32m8_tu(vfloat32m8_t vd, vbfloat16m4_t vs1,106 vbfloat16m4_t vs2, size_t vl) {107 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, vl);108}109 110// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_tu(111// CHECK-RV64-SAME: <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {112// CHECK-RV64-NEXT: entry:113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], i64 7, i64 [[VL]], i64 2)114// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]115//116vfloat32m8_t test_vfwmaccbf16_vf_f32m8_tu(vfloat32m8_t vd, __bf16 vs1,117 vbfloat16m4_t vs2, size_t vl) {118 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, vl);119}120 121// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tum(122// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {123// CHECK-RV64-NEXT: entry:124// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 7, i64 [[VL]], i64 2)125// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]126//127vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_tum(vbool64_t vm, vfloat32mf2_t vd,128 vbfloat16mf4_t vs1,129 vbfloat16mf4_t vs2, size_t vl) {130 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, vl);131}132 133// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tum(134// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {135// CHECK-RV64-NEXT: entry:136// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 7, i64 [[VL]], i64 2)137// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]138//139vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_tum(vbool64_t vm, vfloat32mf2_t vd,140 __bf16 vs1, vbfloat16mf4_t vs2,141 size_t vl) {142 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, vl);143}144 145// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tum(146// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {147// CHECK-RV64-NEXT: entry:148// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 7, i64 [[VL]], i64 2)149// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]150//151vfloat32m1_t test_vfwmaccbf16_vv_f32m1_tum(vbool32_t vm, vfloat32m1_t vd,152 vbfloat16mf2_t vs1,153 vbfloat16mf2_t vs2, size_t vl) {154 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, vl);155}156 157// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tum(158// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {159// CHECK-RV64-NEXT: entry:160// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 7, i64 [[VL]], i64 2)161// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]162//163vfloat32m1_t test_vfwmaccbf16_vf_f32m1_tum(vbool32_t vm, vfloat32m1_t vd,164 __bf16 vs1, vbfloat16mf2_t vs2,165 size_t vl) {166 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, vl);167}168 169// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tum(170// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {171// CHECK-RV64-NEXT: entry:172// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 7, i64 [[VL]], i64 2)173// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]174//175vfloat32m2_t test_vfwmaccbf16_vv_f32m2_tum(vbool16_t vm, vfloat32m2_t vd,176 vbfloat16m1_t vs1, vbfloat16m1_t vs2,177 size_t vl) {178 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, vl);179}180 181// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tum(182// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {183// CHECK-RV64-NEXT: entry:184// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 7, i64 [[VL]], i64 2)185// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]186//187vfloat32m2_t test_vfwmaccbf16_vf_f32m2_tum(vbool16_t vm, vfloat32m2_t vd,188 __bf16 vs1, vbfloat16m1_t vs2,189 size_t vl) {190 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, vl);191}192 193// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tum(194// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {195// CHECK-RV64-NEXT: entry:196// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 7, i64 [[VL]], i64 2)197// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]198//199vfloat32m4_t test_vfwmaccbf16_vv_f32m4_tum(vbool8_t vm, vfloat32m4_t vd,200 vbfloat16m2_t vs1, vbfloat16m2_t vs2,201 size_t vl) {202 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, vl);203}204 205// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tum(206// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {207// CHECK-RV64-NEXT: entry:208// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 7, i64 [[VL]], i64 2)209// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]210//211vfloat32m4_t test_vfwmaccbf16_vf_f32m4_tum(vbool8_t vm, vfloat32m4_t vd,212 __bf16 vs1, vbfloat16m2_t vs2,213 size_t vl) {214 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, vl);215}216 217// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_tum(218// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {219// CHECK-RV64-NEXT: entry:220// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 7, i64 [[VL]], i64 2)221// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]222//223vfloat32m8_t test_vfwmaccbf16_vv_f32m8_tum(vbool4_t vm, vfloat32m8_t vd,224 vbfloat16m4_t vs1, vbfloat16m4_t vs2,225 size_t vl) {226 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, vl);227}228 229// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_tum(230// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {231// CHECK-RV64-NEXT: entry:232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 7, i64 [[VL]], i64 2)233// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]234//235vfloat32m8_t test_vfwmaccbf16_vf_f32m8_tum(vbool4_t vm, vfloat32m8_t vd,236 __bf16 vs1, vbfloat16m4_t vs2,237 size_t vl) {238 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, vl);239}240 241// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tumu(242// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {243// CHECK-RV64-NEXT: entry:244// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 7, i64 [[VL]], i64 0)245// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]246//247vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_tumu(vbool64_t vm, vfloat32mf2_t vd,248 vbfloat16mf4_t vs1,249 vbfloat16mf4_t vs2, size_t vl) {250 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, vl);251}252 253// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tumu(254// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {255// CHECK-RV64-NEXT: entry:256// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 7, i64 [[VL]], i64 0)257// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]258//259vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_tumu(vbool64_t vm, vfloat32mf2_t vd,260 __bf16 vs1, vbfloat16mf4_t vs2,261 size_t vl) {262 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, vl);263}264 265// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tumu(266// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {267// CHECK-RV64-NEXT: entry:268// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 7, i64 [[VL]], i64 0)269// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]270//271vfloat32m1_t test_vfwmaccbf16_vv_f32m1_tumu(vbool32_t vm, vfloat32m1_t vd,272 vbfloat16mf2_t vs1,273 vbfloat16mf2_t vs2, size_t vl) {274 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, vl);275}276 277// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tumu(278// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {279// CHECK-RV64-NEXT: entry:280// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 7, i64 [[VL]], i64 0)281// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]282//283vfloat32m1_t test_vfwmaccbf16_vf_f32m1_tumu(vbool32_t vm, vfloat32m1_t vd,284 __bf16 vs1, vbfloat16mf2_t vs2,285 size_t vl) {286 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, vl);287}288 289// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tumu(290// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {291// CHECK-RV64-NEXT: entry:292// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 7, i64 [[VL]], i64 0)293// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]294//295vfloat32m2_t test_vfwmaccbf16_vv_f32m2_tumu(vbool16_t vm, vfloat32m2_t vd,296 vbfloat16m1_t vs1,297 vbfloat16m1_t vs2, size_t vl) {298 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, vl);299}300 301// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tumu(302// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {303// CHECK-RV64-NEXT: entry:304// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 7, i64 [[VL]], i64 0)305// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]306//307vfloat32m2_t test_vfwmaccbf16_vf_f32m2_tumu(vbool16_t vm, vfloat32m2_t vd,308 __bf16 vs1, vbfloat16m1_t vs2,309 size_t vl) {310 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, vl);311}312 313// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tumu(314// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {315// CHECK-RV64-NEXT: entry:316// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 7, i64 [[VL]], i64 0)317// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]318//319vfloat32m4_t test_vfwmaccbf16_vv_f32m4_tumu(vbool8_t vm, vfloat32m4_t vd,320 vbfloat16m2_t vs1,321 vbfloat16m2_t vs2, size_t vl) {322 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, vl);323}324 325// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tumu(326// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {327// CHECK-RV64-NEXT: entry:328// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 7, i64 [[VL]], i64 0)329// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]330//331vfloat32m4_t test_vfwmaccbf16_vf_f32m4_tumu(vbool8_t vm, vfloat32m4_t vd,332 __bf16 vs1, vbfloat16m2_t vs2,333 size_t vl) {334 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, vl);335}336 337// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_tumu(338// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {339// CHECK-RV64-NEXT: entry:340// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 7, i64 [[VL]], i64 0)341// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]342//343vfloat32m8_t test_vfwmaccbf16_vv_f32m8_tumu(vbool4_t vm, vfloat32m8_t vd,344 vbfloat16m4_t vs1,345 vbfloat16m4_t vs2, size_t vl) {346 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, vl);347}348 349// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_tumu(350// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {351// CHECK-RV64-NEXT: entry:352// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 7, i64 [[VL]], i64 0)353// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]354//355vfloat32m8_t test_vfwmaccbf16_vf_f32m8_tumu(vbool4_t vm, vfloat32m8_t vd,356 __bf16 vs1, vbfloat16m4_t vs2,357 size_t vl) {358 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, vl);359}360 361// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_mu(362// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {363// CHECK-RV64-NEXT: entry:364// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 7, i64 [[VL]], i64 1)365// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]366//367vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_mu(vbool64_t vm, vfloat32mf2_t vd,368 vbfloat16mf4_t vs1,369 vbfloat16mf4_t vs2, size_t vl) {370 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, vl);371}372 373// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_mu(374// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {375// CHECK-RV64-NEXT: entry:376// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 7, i64 [[VL]], i64 1)377// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]378//379vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_mu(vbool64_t vm, vfloat32mf2_t vd,380 __bf16 vs1, vbfloat16mf4_t vs2,381 size_t vl) {382 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, vl);383}384 385// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_mu(386// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {387// CHECK-RV64-NEXT: entry:388// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 7, i64 [[VL]], i64 1)389// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]390//391vfloat32m1_t test_vfwmaccbf16_vv_f32m1_mu(vbool32_t vm, vfloat32m1_t vd,392 vbfloat16mf2_t vs1,393 vbfloat16mf2_t vs2, size_t vl) {394 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, vl);395}396 397// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_mu(398// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {399// CHECK-RV64-NEXT: entry:400// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 7, i64 [[VL]], i64 1)401// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]402//403vfloat32m1_t test_vfwmaccbf16_vf_f32m1_mu(vbool32_t vm, vfloat32m1_t vd,404 __bf16 vs1, vbfloat16mf2_t vs2,405 size_t vl) {406 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, vl);407}408 409// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_mu(410// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {411// CHECK-RV64-NEXT: entry:412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 7, i64 [[VL]], i64 1)413// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]414//415vfloat32m2_t test_vfwmaccbf16_vv_f32m2_mu(vbool16_t vm, vfloat32m2_t vd,416 vbfloat16m1_t vs1, vbfloat16m1_t vs2,417 size_t vl) {418 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, vl);419}420 421// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_mu(422// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {423// CHECK-RV64-NEXT: entry:424// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 7, i64 [[VL]], i64 1)425// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]426//427vfloat32m2_t test_vfwmaccbf16_vf_f32m2_mu(vbool16_t vm, vfloat32m2_t vd,428 __bf16 vs1, vbfloat16m1_t vs2,429 size_t vl) {430 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, vl);431}432 433// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_mu(434// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {435// CHECK-RV64-NEXT: entry:436// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 7, i64 [[VL]], i64 1)437// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]438//439vfloat32m4_t test_vfwmaccbf16_vv_f32m4_mu(vbool8_t vm, vfloat32m4_t vd,440 vbfloat16m2_t vs1, vbfloat16m2_t vs2,441 size_t vl) {442 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, vl);443}444 445// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_mu(446// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {447// CHECK-RV64-NEXT: entry:448// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 7, i64 [[VL]], i64 1)449// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]450//451vfloat32m4_t test_vfwmaccbf16_vf_f32m4_mu(vbool8_t vm, vfloat32m4_t vd,452 __bf16 vs1, vbfloat16m2_t vs2,453 size_t vl) {454 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, vl);455}456 457// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_mu(458// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {459// CHECK-RV64-NEXT: entry:460// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 7, i64 [[VL]], i64 1)461// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]462//463vfloat32m8_t test_vfwmaccbf16_vv_f32m8_mu(vbool4_t vm, vfloat32m8_t vd,464 vbfloat16m4_t vs1, vbfloat16m4_t vs2,465 size_t vl) {466 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, vl);467}468 469// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_mu(470// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {471// CHECK-RV64-NEXT: entry:472// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 7, i64 [[VL]], i64 1)473// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]474//475vfloat32m8_t test_vfwmaccbf16_vf_f32m8_mu(vbool4_t vm, vfloat32m8_t vd,476 __bf16 vs1, vbfloat16m4_t vs2,477 size_t vl) {478 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, vl);479}480 481// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_rm_tu(482// CHECK-RV64-SAME: <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {483// CHECK-RV64-NEXT: entry:484// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 2)485// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]486//487vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_rm_tu(vfloat32mf2_t vd,488 vbfloat16mf4_t vs1,489 vbfloat16mf4_t vs2, size_t vl) {490 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);491}492 493// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_rm_tu(494// CHECK-RV64-SAME: <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {495// CHECK-RV64-NEXT: entry:496// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 2)497// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]498//499vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_rm_tu(vfloat32mf2_t vd, __bf16 vs1,500 vbfloat16mf4_t vs2, size_t vl) {501 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);502}503 504// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_rm_tu(505// CHECK-RV64-SAME: <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {506// CHECK-RV64-NEXT: entry:507// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 2)508// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]509//510vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_tu(vfloat32m1_t vd,511 vbfloat16mf2_t vs1,512 vbfloat16mf2_t vs2, size_t vl) {513 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);514}515 516// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_rm_tu(517// CHECK-RV64-SAME: <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {518// CHECK-RV64-NEXT: entry:519// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 2)520// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]521//522vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_tu(vfloat32m1_t vd, __bf16 vs1,523 vbfloat16mf2_t vs2, size_t vl) {524 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);525}526 527// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_rm_tu(528// CHECK-RV64-SAME: <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {529// CHECK-RV64-NEXT: entry:530// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 2)531// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]532//533vfloat32m2_t test_vfwmaccbf16_vv_f32m2_rm_tu(vfloat32m2_t vd, vbfloat16m1_t vs1,534 vbfloat16m1_t vs2, size_t vl) {535 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);536}537 538// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_rm_tu(539// CHECK-RV64-SAME: <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {540// CHECK-RV64-NEXT: entry:541// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 2)542// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]543//544vfloat32m2_t test_vfwmaccbf16_vf_f32m2_rm_tu(vfloat32m2_t vd, __bf16 vs1,545 vbfloat16m1_t vs2, size_t vl) {546 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);547}548 549// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_rm_tu(550// CHECK-RV64-SAME: <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {551// CHECK-RV64-NEXT: entry:552// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 2)553// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]554//555vfloat32m4_t test_vfwmaccbf16_vv_f32m4_rm_tu(vfloat32m4_t vd, vbfloat16m2_t vs1,556 vbfloat16m2_t vs2, size_t vl) {557 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);558}559 560// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_rm_tu(561// CHECK-RV64-SAME: <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {562// CHECK-RV64-NEXT: entry:563// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 2)564// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]565//566vfloat32m4_t test_vfwmaccbf16_vf_f32m4_rm_tu(vfloat32m4_t vd, __bf16 vs1,567 vbfloat16m2_t vs2, size_t vl) {568 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);569}570 571// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_rm_tu(572// CHECK-RV64-SAME: <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {573// CHECK-RV64-NEXT: entry:574// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 2)575// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]576//577vfloat32m8_t test_vfwmaccbf16_vv_f32m8_rm_tu(vfloat32m8_t vd, vbfloat16m4_t vs1,578 vbfloat16m4_t vs2, size_t vl) {579 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);580}581 582// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_rm_tu(583// CHECK-RV64-SAME: <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {584// CHECK-RV64-NEXT: entry:585// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], i64 0, i64 [[VL]], i64 2)586// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]587//588vfloat32m8_t test_vfwmaccbf16_vf_f32m8_rm_tu(vfloat32m8_t vd, __bf16 vs1,589 vbfloat16m4_t vs2, size_t vl) {590 return __riscv_vfwmaccbf16_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);591}592 593// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_rm_tum(594// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {595// CHECK-RV64-NEXT: entry:596// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 0, i64 [[VL]], i64 2)597// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]598//599vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_rm_tum(vbool64_t vm, vfloat32mf2_t vd,600 vbfloat16mf4_t vs1,601 vbfloat16mf4_t vs2, size_t vl) {602 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);603}604 605// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_rm_tum(606// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {607// CHECK-RV64-NEXT: entry:608// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 0, i64 [[VL]], i64 2)609// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]610//611vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_rm_tum(vbool64_t vm, vfloat32mf2_t vd,612 __bf16 vs1, vbfloat16mf4_t vs2,613 size_t vl) {614 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);615}616 617// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_rm_tum(618// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {619// CHECK-RV64-NEXT: entry:620// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 0, i64 [[VL]], i64 2)621// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]622//623vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_tum(vbool32_t vm, vfloat32m1_t vd,624 vbfloat16mf2_t vs1,625 vbfloat16mf2_t vs2, size_t vl) {626 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);627}628 629// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_rm_tum(630// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {631// CHECK-RV64-NEXT: entry:632// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 0, i64 [[VL]], i64 2)633// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]634//635vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_tum(vbool32_t vm, vfloat32m1_t vd,636 __bf16 vs1, vbfloat16mf2_t vs2,637 size_t vl) {638 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);639}640 641// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_rm_tum(642// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {643// CHECK-RV64-NEXT: entry:644// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 0, i64 [[VL]], i64 2)645// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]646//647vfloat32m2_t test_vfwmaccbf16_vv_f32m2_rm_tum(vbool16_t vm, vfloat32m2_t vd,648 vbfloat16m1_t vs1,649 vbfloat16m1_t vs2, size_t vl) {650 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);651}652 653// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_rm_tum(654// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {655// CHECK-RV64-NEXT: entry:656// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 0, i64 [[VL]], i64 2)657// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]658//659vfloat32m2_t test_vfwmaccbf16_vf_f32m2_rm_tum(vbool16_t vm, vfloat32m2_t vd,660 __bf16 vs1, vbfloat16m1_t vs2,661 size_t vl) {662 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);663}664 665// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_rm_tum(666// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {667// CHECK-RV64-NEXT: entry:668// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 0, i64 [[VL]], i64 2)669// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]670//671vfloat32m4_t test_vfwmaccbf16_vv_f32m4_rm_tum(vbool8_t vm, vfloat32m4_t vd,672 vbfloat16m2_t vs1,673 vbfloat16m2_t vs2, size_t vl) {674 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);675}676 677// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_rm_tum(678// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {679// CHECK-RV64-NEXT: entry:680// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 0, i64 [[VL]], i64 2)681// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]682//683vfloat32m4_t test_vfwmaccbf16_vf_f32m4_rm_tum(vbool8_t vm, vfloat32m4_t vd,684 __bf16 vs1, vbfloat16m2_t vs2,685 size_t vl) {686 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);687}688 689// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_rm_tum(690// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {691// CHECK-RV64-NEXT: entry:692// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 0, i64 [[VL]], i64 2)693// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]694//695vfloat32m8_t test_vfwmaccbf16_vv_f32m8_rm_tum(vbool4_t vm, vfloat32m8_t vd,696 vbfloat16m4_t vs1,697 vbfloat16m4_t vs2, size_t vl) {698 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);699}700 701// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_rm_tum(702// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {703// CHECK-RV64-NEXT: entry:704// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 0, i64 [[VL]], i64 2)705// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]706//707vfloat32m8_t test_vfwmaccbf16_vf_f32m8_rm_tum(vbool4_t vm, vfloat32m8_t vd,708 __bf16 vs1, vbfloat16m4_t vs2,709 size_t vl) {710 return __riscv_vfwmaccbf16_tum(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);711}712 713// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_rm_tumu(714// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {715// CHECK-RV64-NEXT: entry:716// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 0, i64 [[VL]], i64 0)717// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]718//719vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_rm_tumu(vbool64_t vm, vfloat32mf2_t vd,720 vbfloat16mf4_t vs1,721 vbfloat16mf4_t vs2,722 size_t vl) {723 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);724}725 726// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_rm_tumu(727// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {728// CHECK-RV64-NEXT: entry:729// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 0, i64 [[VL]], i64 0)730// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]731//732vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_rm_tumu(vbool64_t vm, vfloat32mf2_t vd,733 __bf16 vs1, vbfloat16mf4_t vs2,734 size_t vl) {735 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);736}737 738// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_rm_tumu(739// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {740// CHECK-RV64-NEXT: entry:741// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 0, i64 [[VL]], i64 0)742// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]743//744vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_tumu(vbool32_t vm, vfloat32m1_t vd,745 vbfloat16mf2_t vs1,746 vbfloat16mf2_t vs2, size_t vl) {747 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);748}749 750// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_rm_tumu(751// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {752// CHECK-RV64-NEXT: entry:753// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 0, i64 [[VL]], i64 0)754// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]755//756vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_tumu(vbool32_t vm, vfloat32m1_t vd,757 __bf16 vs1, vbfloat16mf2_t vs2,758 size_t vl) {759 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);760}761 762// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_rm_tumu(763// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {764// CHECK-RV64-NEXT: entry:765// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 0, i64 [[VL]], i64 0)766// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]767//768vfloat32m2_t test_vfwmaccbf16_vv_f32m2_rm_tumu(vbool16_t vm, vfloat32m2_t vd,769 vbfloat16m1_t vs1,770 vbfloat16m1_t vs2, size_t vl) {771 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);772}773 774// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_rm_tumu(775// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {776// CHECK-RV64-NEXT: entry:777// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 0, i64 [[VL]], i64 0)778// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]779//780vfloat32m2_t test_vfwmaccbf16_vf_f32m2_rm_tumu(vbool16_t vm, vfloat32m2_t vd,781 __bf16 vs1, vbfloat16m1_t vs2,782 size_t vl) {783 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);784}785 786// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_rm_tumu(787// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {788// CHECK-RV64-NEXT: entry:789// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 0, i64 [[VL]], i64 0)790// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]791//792vfloat32m4_t test_vfwmaccbf16_vv_f32m4_rm_tumu(vbool8_t vm, vfloat32m4_t vd,793 vbfloat16m2_t vs1,794 vbfloat16m2_t vs2, size_t vl) {795 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);796}797 798// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_rm_tumu(799// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {800// CHECK-RV64-NEXT: entry:801// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 0, i64 [[VL]], i64 0)802// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]803//804vfloat32m4_t test_vfwmaccbf16_vf_f32m4_rm_tumu(vbool8_t vm, vfloat32m4_t vd,805 __bf16 vs1, vbfloat16m2_t vs2,806 size_t vl) {807 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);808}809 810// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_rm_tumu(811// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {812// CHECK-RV64-NEXT: entry:813// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 0, i64 [[VL]], i64 0)814// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]815//816vfloat32m8_t test_vfwmaccbf16_vv_f32m8_rm_tumu(vbool4_t vm, vfloat32m8_t vd,817 vbfloat16m4_t vs1,818 vbfloat16m4_t vs2, size_t vl) {819 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);820}821 822// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_rm_tumu(823// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {824// CHECK-RV64-NEXT: entry:825// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 0, i64 [[VL]], i64 0)826// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]827//828vfloat32m8_t test_vfwmaccbf16_vf_f32m8_rm_tumu(vbool4_t vm, vfloat32m8_t vd,829 __bf16 vs1, vbfloat16m4_t vs2,830 size_t vl) {831 return __riscv_vfwmaccbf16_tumu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);832}833 834// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_rm_mu(835// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {836// CHECK-RV64-NEXT: entry:837// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 0, i64 [[VL]], i64 1)838// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]839//840vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2_rm_mu(vbool64_t vm, vfloat32mf2_t vd,841 vbfloat16mf4_t vs1,842 vbfloat16mf4_t vs2, size_t vl) {843 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);844}845 846// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_rm_mu(847// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {848// CHECK-RV64-NEXT: entry:849// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> [[VD]], bfloat [[VS1]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x i1> [[VM]], i64 0, i64 [[VL]], i64 1)850// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]851//852vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2_rm_mu(vbool64_t vm, vfloat32mf2_t vd,853 __bf16 vs1, vbfloat16mf4_t vs2,854 size_t vl) {855 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);856}857 858// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_rm_mu(859// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {860// CHECK-RV64-NEXT: entry:861// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 0, i64 [[VL]], i64 1)862// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]863//864vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_mu(vbool32_t vm, vfloat32m1_t vd,865 vbfloat16mf2_t vs1,866 vbfloat16mf2_t vs2, size_t vl) {867 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);868}869 870// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_rm_mu(871// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {872// CHECK-RV64-NEXT: entry:873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> [[VD]], bfloat [[VS1]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x i1> [[VM]], i64 0, i64 [[VL]], i64 1)874// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]875//876vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_mu(vbool32_t vm, vfloat32m1_t vd,877 __bf16 vs1, vbfloat16mf2_t vs2,878 size_t vl) {879 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);880}881 882// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_rm_mu(883// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {884// CHECK-RV64-NEXT: entry:885// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 0, i64 [[VL]], i64 1)886// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]887//888vfloat32m2_t test_vfwmaccbf16_vv_f32m2_rm_mu(vbool16_t vm, vfloat32m2_t vd,889 vbfloat16m1_t vs1,890 vbfloat16m1_t vs2, size_t vl) {891 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);892}893 894// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_rm_mu(895// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {896// CHECK-RV64-NEXT: entry:897// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> [[VD]], bfloat [[VS1]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x i1> [[VM]], i64 0, i64 [[VL]], i64 1)898// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]899//900vfloat32m2_t test_vfwmaccbf16_vf_f32m2_rm_mu(vbool16_t vm, vfloat32m2_t vd,901 __bf16 vs1, vbfloat16m1_t vs2,902 size_t vl) {903 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);904}905 906// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_rm_mu(907// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {908// CHECK-RV64-NEXT: entry:909// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 0, i64 [[VL]], i64 1)910// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]911//912vfloat32m4_t test_vfwmaccbf16_vv_f32m4_rm_mu(vbool8_t vm, vfloat32m4_t vd,913 vbfloat16m2_t vs1,914 vbfloat16m2_t vs2, size_t vl) {915 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);916}917 918// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_rm_mu(919// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {920// CHECK-RV64-NEXT: entry:921// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.bf16.nxv8bf16.i64(<vscale x 8 x float> [[VD]], bfloat [[VS1]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x i1> [[VM]], i64 0, i64 [[VL]], i64 1)922// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]923//924vfloat32m4_t test_vfwmaccbf16_vf_f32m4_rm_mu(vbool8_t vm, vfloat32m4_t vd,925 __bf16 vs1, vbfloat16m2_t vs2,926 size_t vl) {927 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);928}929 930// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vv_f32m8_rm_mu(931// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {932// CHECK-RV64-NEXT: entry:933// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 0, i64 [[VL]], i64 1)934// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]935//936vfloat32m8_t test_vfwmaccbf16_vv_f32m8_rm_mu(vbool4_t vm, vfloat32m8_t vd,937 vbfloat16m4_t vs1,938 vbfloat16m4_t vs2, size_t vl) {939 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);940}941 942// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwmaccbf16_vf_f32m8_rm_mu(943// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], bfloat noundef [[VS1:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {944// CHECK-RV64-NEXT: entry:945// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.bf16.nxv16bf16.i64(<vscale x 16 x float> [[VD]], bfloat [[VS1]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x i1> [[VM]], i64 0, i64 [[VL]], i64 1)946// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]947//948vfloat32m8_t test_vfwmaccbf16_vf_f32m8_rm_mu(vbool4_t vm, vfloat32m8_t vd,949 __bf16 vs1, vbfloat16m4_t vs2,950 size_t vl) {951 return __riscv_vfwmaccbf16_mu(vm, vd, vs1, vs2, __RISCV_FRM_RNE, vl);952}953