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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <sifive_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2(10// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)13// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]14//15vuint32mf2_t test_vqdotu_vx_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2,16 uint32_t rs1, size_t vl) {17 return __riscv_vqdotu_vx_u32mf2(vd, vs2, rs1, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1(21// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)24// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]25//26vuint32m1_t test_vqdotu_vx_u32m1(vuint32m1_t vd, vuint8m1_t vs2, uint32_t rs1,27 size_t vl) {28 return __riscv_vqdotu_vx_u32m1(vd, vs2, rs1, vl);29}30 31// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2(32// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {33// CHECK-RV64-NEXT: entry:34// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)35// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]36//37vuint32m2_t test_vqdotu_vx_u32m2(vuint32m2_t vd, vuint8m2_t vs2, uint32_t rs1,38 size_t vl) {39 return __riscv_vqdotu_vx_u32m2(vd, vs2, rs1, vl);40}41 42// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4(43// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {44// CHECK-RV64-NEXT: entry:45// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)46// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]47//48vuint32m4_t test_vqdotu_vx_u32m4(vuint32m4_t vd, vuint8m4_t vs2, uint32_t rs1,49 size_t vl) {50 return __riscv_vqdotu_vx_u32m4(vd, vs2, rs1, vl);51}52 53// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8(54// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {55// CHECK-RV64-NEXT: entry:56// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3)57// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]58//59vuint32m8_t test_vqdotu_vx_u32m8(vuint32m8_t vd, vuint8m8_t vs2, uint32_t rs1,60 size_t vl) {61 return __riscv_vqdotu_vx_u32m8(vd, vs2, rs1, vl);62}63 64// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_m(65// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {66// CHECK-RV64-NEXT: entry:67// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)68// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]69//70vuint32mf2_t test_vqdotu_vx_u32mf2_m(vbool64_t vm, vuint32mf2_t vd,71 vuint8mf2_t vs2, uint32_t rs1, size_t vl) {72 return __riscv_vqdotu_vx_u32mf2_m(vm, vd, vs2, rs1, vl);73}74 75// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_m(76// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {77// CHECK-RV64-NEXT: entry:78// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)79// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]80//81vuint32m1_t test_vqdotu_vx_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint8m1_t vs2,82 uint32_t rs1, size_t vl) {83 return __riscv_vqdotu_vx_u32m1_m(vm, vd, vs2, rs1, vl);84}85 86// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_m(87// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {88// CHECK-RV64-NEXT: entry:89// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)90// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]91//92vuint32m2_t test_vqdotu_vx_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint8m2_t vs2,93 uint32_t rs1, size_t vl) {94 return __riscv_vqdotu_vx_u32m2_m(vm, vd, vs2, rs1, vl);95}96 97// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_m(98// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {99// CHECK-RV64-NEXT: entry:100// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)101// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]102//103vuint32m4_t test_vqdotu_vx_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,104 uint32_t rs1, size_t vl) {105 return __riscv_vqdotu_vx_u32m4_m(vm, vd, vs2, rs1, vl);106}107 108// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_m(109// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {110// CHECK-RV64-NEXT: entry:111// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)112// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]113//114vuint32m8_t test_vqdotu_vx_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,115 uint32_t rs1, size_t vl) {116 return __riscv_vqdotu_vx_u32m8_m(vm, vd, vs2, rs1, vl);117}118