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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <sifive_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_tu(10// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)13// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]14//15vint32mf2_t test_vqdotsu_vv_i32mf2_tu(vint32mf2_t vd, vint8mf2_t vs2,16 vuint8mf2_t vs1, size_t vl) {17 return __riscv_vqdotsu_vv_i32mf2_tu(vd, vs2, vs1, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_tu(21// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)24// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]25//26vint32m1_t test_vqdotsu_vv_i32m1_tu(vint32m1_t vd, vint8m1_t vs2,27 vuint8m1_t vs1, size_t vl) {28 return __riscv_vqdotsu_vv_i32m1_tu(vd, vs2, vs1, vl);29}30 31// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_tu(32// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {33// CHECK-RV64-NEXT: entry:34// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)35// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]36//37vint32m2_t test_vqdotsu_vv_i32m2_tu(vint32m2_t vd, vint8m2_t vs2,38 vuint8m2_t vs1, size_t vl) {39 return __riscv_vqdotsu_vv_i32m2_tu(vd, vs2, vs1, vl);40}41 42// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_tu(43// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {44// CHECK-RV64-NEXT: entry:45// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)46// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]47//48vint32m4_t test_vqdotsu_vv_i32m4_tu(vint32m4_t vd, vint8m4_t vs2,49 vuint8m4_t vs1, size_t vl) {50 return __riscv_vqdotsu_vv_i32m4_tu(vd, vs2, vs1, vl);51}52 53// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_tu(54// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {55// CHECK-RV64-NEXT: entry:56// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)57// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]58//59vint32m8_t test_vqdotsu_vv_i32m8_tu(vint32m8_t vd, vint8m8_t vs2,60 vuint8m8_t vs1, size_t vl) {61 return __riscv_vqdotsu_vv_i32m8_tu(vd, vs2, vs1, vl);62}63 64// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_tum(65// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {66// CHECK-RV64-NEXT: entry:67// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)68// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]69//70vint32mf2_t test_vqdotsu_vv_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,71 vint8mf2_t vs2, vuint8mf2_t vs1,72 size_t vl) {73 return __riscv_vqdotsu_vv_i32mf2_tum(vm, vd, vs2, vs1, vl);74}75 76// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_tum(77// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {78// CHECK-RV64-NEXT: entry:79// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)80// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]81//82vint32m1_t test_vqdotsu_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,83 vuint8m1_t vs1, size_t vl) {84 return __riscv_vqdotsu_vv_i32m1_tum(vm, vd, vs2, vs1, vl);85}86 87// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_tum(88// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {89// CHECK-RV64-NEXT: entry:90// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)91// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]92//93vint32m2_t test_vqdotsu_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,94 vuint8m2_t vs1, size_t vl) {95 return __riscv_vqdotsu_vv_i32m2_tum(vm, vd, vs2, vs1, vl);96}97 98// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_tum(99// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {100// CHECK-RV64-NEXT: entry:101// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)102// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]103//104vint32m4_t test_vqdotsu_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,105 vuint8m4_t vs1, size_t vl) {106 return __riscv_vqdotsu_vv_i32m4_tum(vm, vd, vs2, vs1, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_tum(110// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)113// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]114//115vint32m8_t test_vqdotsu_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,116 vuint8m8_t vs1, size_t vl) {117 return __riscv_vqdotsu_vv_i32m8_tum(vm, vd, vs2, vs1, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_tumu(121// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)124// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]125//126vint32mf2_t test_vqdotsu_vv_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,127 vint8mf2_t vs2, vuint8mf2_t vs1,128 size_t vl) {129 return __riscv_vqdotsu_vv_i32mf2_tumu(vm, vd, vs2, vs1, vl);130}131 132// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_tumu(133// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {134// CHECK-RV64-NEXT: entry:135// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)136// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]137//138vint32m1_t test_vqdotsu_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd,139 vint8m1_t vs2, vuint8m1_t vs1,140 size_t vl) {141 return __riscv_vqdotsu_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);142}143 144// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_tumu(145// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {146// CHECK-RV64-NEXT: entry:147// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)148// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]149//150vint32m2_t test_vqdotsu_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd,151 vint8m2_t vs2, vuint8m2_t vs1,152 size_t vl) {153 return __riscv_vqdotsu_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);154}155 156// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_tumu(157// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {158// CHECK-RV64-NEXT: entry:159// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)160// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]161//162vint32m4_t test_vqdotsu_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,163 vuint8m4_t vs1, size_t vl) {164 return __riscv_vqdotsu_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);165}166 167// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_tumu(168// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {169// CHECK-RV64-NEXT: entry:170// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)171// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]172//173vint32m8_t test_vqdotsu_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,174 vuint8m8_t vs1, size_t vl) {175 return __riscv_vqdotsu_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);176}177 178// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotsu_vv_i32mf2_mu(179// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {180// CHECK-RV64-NEXT: entry:181// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)182// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]183//184vint32mf2_t test_vqdotsu_vv_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,185 vint8mf2_t vs2, vuint8mf2_t vs1,186 size_t vl) {187 return __riscv_vqdotsu_vv_i32mf2_mu(vm, vd, vs2, vs1, vl);188}189 190// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotsu_vv_i32m1_mu(191// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {192// CHECK-RV64-NEXT: entry:193// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)194// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]195//196vint32m1_t test_vqdotsu_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2,197 vuint8m1_t vs1, size_t vl) {198 return __riscv_vqdotsu_vv_i32m1_mu(vm, vd, vs2, vs1, vl);199}200 201// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotsu_vv_i32m2_mu(202// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {203// CHECK-RV64-NEXT: entry:204// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)205// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]206//207vint32m2_t test_vqdotsu_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2,208 vuint8m2_t vs1, size_t vl) {209 return __riscv_vqdotsu_vv_i32m2_mu(vm, vd, vs2, vs1, vl);210}211 212// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotsu_vv_i32m4_mu(213// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {214// CHECK-RV64-NEXT: entry:215// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)216// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]217//218vint32m4_t test_vqdotsu_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2,219 vuint8m4_t vs1, size_t vl) {220 return __riscv_vqdotsu_vv_i32m4_mu(vm, vd, vs2, vs1, vl);221}222 223// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotsu_vv_i32m8_mu(224// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {225// CHECK-RV64-NEXT: entry:226// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)227// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]228//229vint32m8_t test_vqdotsu_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2,230 vuint8m8_t vs1, size_t vl) {231 return __riscv_vqdotsu_vv_i32m8_mu(vm, vd, vs2, vs1, vl);232}233