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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <sifive_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_tu(10// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 2)13// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]14//15vuint32mf2_t test_vqdotu_vv_u32mf2_tu(vuint32mf2_t vd, vuint8mf2_t vs2,16 vuint8mf2_t vs1, size_t vl) {17 return __riscv_vqdotu_tu(vd, vs2, vs1, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_tu(21// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 2)24// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]25//26vuint32m1_t test_vqdotu_vv_u32m1_tu(vuint32m1_t vd, vuint8m1_t vs2,27 vuint8m1_t vs1, size_t vl) {28 return __riscv_vqdotu_tu(vd, vs2, vs1, vl);29}30 31// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_tu(32// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {33// CHECK-RV64-NEXT: entry:34// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 2)35// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]36//37vuint32m2_t test_vqdotu_vv_u32m2_tu(vuint32m2_t vd, vuint8m2_t vs2,38 vuint8m2_t vs1, size_t vl) {39 return __riscv_vqdotu_tu(vd, vs2, vs1, vl);40}41 42// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_tu(43// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {44// CHECK-RV64-NEXT: entry:45// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 2)46// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]47//48vuint32m4_t test_vqdotu_vv_u32m4_tu(vuint32m4_t vd, vuint8m4_t vs2,49 vuint8m4_t vs1, size_t vl) {50 return __riscv_vqdotu_tu(vd, vs2, vs1, vl);51}52 53// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_tu(54// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {55// CHECK-RV64-NEXT: entry:56// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 2)57// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]58//59vuint32m8_t test_vqdotu_vv_u32m8_tu(vuint32m8_t vd, vuint8m8_t vs2,60 vuint8m8_t vs1, size_t vl) {61 return __riscv_vqdotu_tu(vd, vs2, vs1, vl);62}63 64// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_tum(65// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {66// CHECK-RV64-NEXT: entry:67// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)68// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]69//70vuint32mf2_t test_vqdotu_vv_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,71 vuint8mf2_t vs2, vuint8mf2_t vs1,72 size_t vl) {73 return __riscv_vqdotu_tum(vm, vd, vs2, vs1, vl);74}75 76// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_tum(77// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {78// CHECK-RV64-NEXT: entry:79// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)80// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]81//82vuint32m1_t test_vqdotu_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,83 vuint8m1_t vs2, vuint8m1_t vs1,84 size_t vl) {85 return __riscv_vqdotu_tum(vm, vd, vs2, vs1, vl);86}87 88// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_tum(89// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {90// CHECK-RV64-NEXT: entry:91// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)92// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]93//94vuint32m2_t test_vqdotu_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,95 vuint8m2_t vs2, vuint8m2_t vs1,96 size_t vl) {97 return __riscv_vqdotu_tum(vm, vd, vs2, vs1, vl);98}99 100// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_tum(101// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)104// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]105//106vuint32m4_t test_vqdotu_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,107 vuint8m4_t vs2, vuint8m4_t vs1,108 size_t vl) {109 return __riscv_vqdotu_tum(vm, vd, vs2, vs1, vl);110}111 112// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_tum(113// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {114// CHECK-RV64-NEXT: entry:115// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)116// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]117//118vuint32m8_t test_vqdotu_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd,119 vuint8m8_t vs2, vuint8m8_t vs1,120 size_t vl) {121 return __riscv_vqdotu_tum(vm, vd, vs2, vs1, vl);122}123 124// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_tumu(125// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {126// CHECK-RV64-NEXT: entry:127// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)128// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]129//130vuint32mf2_t test_vqdotu_vv_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,131 vuint8mf2_t vs2, vuint8mf2_t vs1,132 size_t vl) {133 return __riscv_vqdotu_tumu(vm, vd, vs2, vs1, vl);134}135 136// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_tumu(137// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {138// CHECK-RV64-NEXT: entry:139// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)140// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]141//142vuint32m1_t test_vqdotu_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,143 vuint8m1_t vs2, vuint8m1_t vs1,144 size_t vl) {145 return __riscv_vqdotu_tumu(vm, vd, vs2, vs1, vl);146}147 148// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_tumu(149// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {150// CHECK-RV64-NEXT: entry:151// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)152// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]153//154vuint32m2_t test_vqdotu_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,155 vuint8m2_t vs2, vuint8m2_t vs1,156 size_t vl) {157 return __riscv_vqdotu_tumu(vm, vd, vs2, vs1, vl);158}159 160// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_tumu(161// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {162// CHECK-RV64-NEXT: entry:163// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)164// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]165//166vuint32m4_t test_vqdotu_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,167 vuint8m4_t vs2, vuint8m4_t vs1,168 size_t vl) {169 return __riscv_vqdotu_tumu(vm, vd, vs2, vs1, vl);170}171 172// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_tumu(173// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {174// CHECK-RV64-NEXT: entry:175// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)176// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]177//178vuint32m8_t test_vqdotu_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,179 vuint8m8_t vs2, vuint8m8_t vs1,180 size_t vl) {181 return __riscv_vqdotu_tumu(vm, vd, vs2, vs1, vl);182}183 184// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_mu(185// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {186// CHECK-RV64-NEXT: entry:187// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)188// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]189//190vuint32mf2_t test_vqdotu_vv_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,191 vuint8mf2_t vs2, vuint8mf2_t vs1,192 size_t vl) {193 return __riscv_vqdotu_mu(vm, vd, vs2, vs1, vl);194}195 196// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_mu(197// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {198// CHECK-RV64-NEXT: entry:199// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)200// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]201//202vuint32m1_t test_vqdotu_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,203 vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {204 return __riscv_vqdotu_mu(vm, vd, vs2, vs1, vl);205}206 207// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_mu(208// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {209// CHECK-RV64-NEXT: entry:210// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)211// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]212//213vuint32m2_t test_vqdotu_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd,214 vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {215 return __riscv_vqdotu_mu(vm, vd, vs2, vs1, vl);216}217 218// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_mu(219// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {220// CHECK-RV64-NEXT: entry:221// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)222// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]223//224vuint32m4_t test_vqdotu_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,225 vuint8m4_t vs1, size_t vl) {226 return __riscv_vqdotu_mu(vm, vd, vs2, vs1, vl);227}228 229// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_mu(230// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {231// CHECK-RV64-NEXT: entry:232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)233// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]234//235vuint32m8_t test_vqdotu_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,236 vuint8m8_t vs1, size_t vl) {237 return __riscv_vqdotu_mu(vm, vd, vs2, vs1, vl);238}239