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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \4// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \5// RUN: FileCheck --check-prefix=CHECK-RV64 %s6 7#include <sifive_vector.h>8 9// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_tu(10// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)13// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]14//15vuint32mf2_t test_vqdotu_vx_u32mf2_tu(vuint32mf2_t vd, vuint8mf2_t vs2,16 uint32_t rs1, size_t vl) {17 return __riscv_vqdotu_tu(vd, vs2, rs1, vl);18}19 20// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_tu(21// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)24// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]25//26vuint32m1_t test_vqdotu_vx_u32m1_tu(vuint32m1_t vd, vuint8m1_t vs2,27 uint32_t rs1, size_t vl) {28 return __riscv_vqdotu_tu(vd, vs2, rs1, vl);29}30 31// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_tu(32// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {33// CHECK-RV64-NEXT: entry:34// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)35// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]36//37vuint32m2_t test_vqdotu_vx_u32m2_tu(vuint32m2_t vd, vuint8m2_t vs2,38 uint32_t rs1, size_t vl) {39 return __riscv_vqdotu_tu(vd, vs2, rs1, vl);40}41 42// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_tu(43// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {44// CHECK-RV64-NEXT: entry:45// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)46// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]47//48vuint32m4_t test_vqdotu_vx_u32m4_tu(vuint32m4_t vd, vuint8m4_t vs2,49 uint32_t rs1, size_t vl) {50 return __riscv_vqdotu_tu(vd, vs2, rs1, vl);51}52 53// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_tu(54// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {55// CHECK-RV64-NEXT: entry:56// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 2)57// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]58//59vuint32m8_t test_vqdotu_vx_u32m8_tu(vuint32m8_t vd, vuint8m8_t vs2,60 uint32_t rs1, size_t vl) {61 return __riscv_vqdotu_tu(vd, vs2, rs1, vl);62}63 64// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_tum(65// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {66// CHECK-RV64-NEXT: entry:67// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)68// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]69//70vuint32mf2_t test_vqdotu_vx_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,71 vuint8mf2_t vs2, uint32_t rs1,72 size_t vl) {73 return __riscv_vqdotu_tum(vm, vd, vs2, rs1, vl);74}75 76// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_tum(77// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {78// CHECK-RV64-NEXT: entry:79// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)80// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]81//82vuint32m1_t test_vqdotu_vx_u32m1_tum(vbool32_t vm, vuint32m1_t vd,83 vuint8m1_t vs2, uint32_t rs1, size_t vl) {84 return __riscv_vqdotu_tum(vm, vd, vs2, rs1, vl);85}86 87// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_tum(88// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {89// CHECK-RV64-NEXT: entry:90// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)91// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]92//93vuint32m2_t test_vqdotu_vx_u32m2_tum(vbool16_t vm, vuint32m2_t vd,94 vuint8m2_t vs2, uint32_t rs1, size_t vl) {95 return __riscv_vqdotu_tum(vm, vd, vs2, rs1, vl);96}97 98// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_tum(99// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {100// CHECK-RV64-NEXT: entry:101// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)102// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]103//104vuint32m4_t test_vqdotu_vx_u32m4_tum(vbool8_t vm, vuint32m4_t vd,105 vuint8m4_t vs2, uint32_t rs1, size_t vl) {106 return __riscv_vqdotu_tum(vm, vd, vs2, rs1, vl);107}108 109// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_tum(110// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)113// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]114//115vuint32m8_t test_vqdotu_vx_u32m8_tum(vbool4_t vm, vuint32m8_t vd,116 vuint8m8_t vs2, uint32_t rs1, size_t vl) {117 return __riscv_vqdotu_tum(vm, vd, vs2, rs1, vl);118}119 120// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_tumu(121// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {122// CHECK-RV64-NEXT: entry:123// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)124// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]125//126vuint32mf2_t test_vqdotu_vx_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,127 vuint8mf2_t vs2, uint32_t rs1,128 size_t vl) {129 return __riscv_vqdotu_tumu(vm, vd, vs2, rs1, vl);130}131 132// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_tumu(133// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {134// CHECK-RV64-NEXT: entry:135// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)136// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]137//138vuint32m1_t test_vqdotu_vx_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,139 vuint8m1_t vs2, uint32_t rs1, size_t vl) {140 return __riscv_vqdotu_tumu(vm, vd, vs2, rs1, vl);141}142 143// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_tumu(144// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {145// CHECK-RV64-NEXT: entry:146// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)147// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]148//149vuint32m2_t test_vqdotu_vx_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,150 vuint8m2_t vs2, uint32_t rs1, size_t vl) {151 return __riscv_vqdotu_tumu(vm, vd, vs2, rs1, vl);152}153 154// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_tumu(155// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {156// CHECK-RV64-NEXT: entry:157// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)158// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]159//160vuint32m4_t test_vqdotu_vx_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,161 vuint8m4_t vs2, uint32_t rs1, size_t vl) {162 return __riscv_vqdotu_tumu(vm, vd, vs2, rs1, vl);163}164 165// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_tumu(166// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {167// CHECK-RV64-NEXT: entry:168// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)169// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]170//171vuint32m8_t test_vqdotu_vx_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,172 vuint8m8_t vs2, uint32_t rs1, size_t vl) {173 return __riscv_vqdotu_tumu(vm, vd, vs2, rs1, vl);174}175 176// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2_mu(177// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {178// CHECK-RV64-NEXT: entry:179// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)180// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]181//182vuint32mf2_t test_vqdotu_vx_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,183 vuint8mf2_t vs2, uint32_t rs1,184 size_t vl) {185 return __riscv_vqdotu_mu(vm, vd, vs2, rs1, vl);186}187 188// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1_mu(189// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {190// CHECK-RV64-NEXT: entry:191// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)192// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]193//194vuint32m1_t test_vqdotu_vx_u32m1_mu(vbool32_t vm, vuint32m1_t vd,195 vuint8m1_t vs2, uint32_t rs1, size_t vl) {196 return __riscv_vqdotu_mu(vm, vd, vs2, rs1, vl);197}198 199// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2_mu(200// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {201// CHECK-RV64-NEXT: entry:202// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)203// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]204//205vuint32m2_t test_vqdotu_vx_u32m2_mu(vbool16_t vm, vuint32m2_t vd,206 vuint8m2_t vs2, uint32_t rs1, size_t vl) {207 return __riscv_vqdotu_mu(vm, vd, vs2, rs1, vl);208}209 210// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vx_u32m4_mu(211// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {212// CHECK-RV64-NEXT: entry:213// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)214// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]215//216vuint32m4_t test_vqdotu_vx_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2,217 uint32_t rs1, size_t vl) {218 return __riscv_vqdotu_mu(vm, vd, vs2, rs1, vl);219}220 221// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vx_u32m8_mu(222// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {223// CHECK-RV64-NEXT: entry:224// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], i32 [[RS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)225// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]226//227vuint32m8_t test_vqdotu_vx_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2,228 uint32_t rs1, size_t vl) {229 return __riscv_vqdotu_mu(vm, vd, vs2, rs1, vl);230}231