30 lines · cpp
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \4// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \5// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s6 7#include <riscv_vector.h>8 9// Use constexpr function to make sure we correctly evaluate it as a constant10// when emitting IR for the vget/vset builtins.11constexpr int foo() { return 1; }12 13// CHECK-RV64-LABEL: @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t14// CHECK-RV64-NEXT: entry:15// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 8)16// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]17//18vint8m1_t test_vget_v_i8m2_i8m1(vint8m2_t src) {19 return __riscv_vget_v_i8m2_i8m1(src, foo());20}21 22// CHECK-RV64-LABEL: @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t23// CHECK-RV64-NEXT: entry:24// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 8)25// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]26//27vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) {28 return __riscv_vset_v_i8m1_i8m2(dest, foo(), val);29}30