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1// REQUIRES: riscv-registered-target2// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \3// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \4// RUN: -fsyntax-only -verify %s5 6#include <riscv_vector.h>7 8vuint32m1_t test_vnclipu_wv_u32m1(vuint64m2_t op1, vuint32m1_t shift, size_t vl) {9 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}10 return __riscv_vnclipu_wv_u32m1(op1, shift, 5, vl);11}12 13vuint32m1_t test_vnclipu_wx_u32m1(vuint64m2_t op1, size_t shift, size_t vl) {14 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}15 return __riscv_vnclipu_wx_u32m1(op1, shift, 5, vl);16}17 18vuint32m1_t test_vnclipu_wv_u32m1_m(vbool32_t mask, vuint64m2_t op1, vuint32m1_t shift, size_t vl) {19 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}20 return __riscv_vnclipu_wv_u32m1_m(mask, op1, shift, 5, vl);21}22 23vuint32m1_t test_vnclipu_wx_u32m1_m(vbool32_t mask, vuint64m2_t op1, size_t shift, size_t vl) {24 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}25 return __riscv_vnclipu_wx_u32m1_m(mask, op1, shift, 5, vl);26}27 28vuint32m1_t test_vnclipu_wv_u32m1_tu(vuint32m1_t maskedoff, vuint64m2_t op1, vuint32m1_t shift, size_t vl) {29 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}30 return __riscv_vnclipu_wv_u32m1_tu(maskedoff, op1, shift, 5, vl);31}32 33vuint32m1_t test_vnclipu_wx_u32m1_tu(vuint32m1_t maskedoff, vuint64m2_t op1, size_t shift, size_t vl) {34 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}35 return __riscv_vnclipu_wx_u32m1_tu(maskedoff, op1, shift, 5, vl);36}37 38vuint32m1_t test_vnclipu_wv_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint64m2_t op1, vuint32m1_t shift, size_t vl) {39 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}40 return __riscv_vnclipu_wv_u32m1_tum(mask, maskedoff, op1, shift, 5, vl);41}42 43vuint32m1_t test_vnclipu_wx_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint64m2_t op1, size_t shift, size_t vl) {44 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}45 return __riscv_vnclipu_wx_u32m1_tum(mask, maskedoff, op1, shift, 5, vl);46}47 48vuint32m1_t test_vnclipu_wv_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint64m2_t op1, vuint32m1_t shift, size_t vl) {49 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}50 return __riscv_vnclipu_wv_u32m1_tumu(mask, maskedoff, op1, shift, 5, vl);51}52 53vuint32m1_t test_vnclipu_wx_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint64m2_t op1, size_t shift, size_t vl) {54 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}55 return __riscv_vnclipu_wx_u32m1_tumu(mask, maskedoff, op1, shift, 5, vl);56}57 58vuint32m1_t test_vnclipu_wv_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint64m2_t op1, vuint32m1_t shift, size_t vl) {59 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}60 return __riscv_vnclipu_wv_u32m1_mu(mask, maskedoff, op1, shift, 5, vl);61}62 63vuint32m1_t test_vnclipu_wx_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint64m2_t op1, size_t shift, size_t vl) {64 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}65 return __riscv_vnclipu_wx_u32m1_mu(mask, maskedoff, op1, shift, 5, vl);66}67