68 lines · c
1// REQUIRES: riscv-registered-target2// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \3// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \4// RUN: -fsyntax-only -verify %s5 6#include <riscv_vector.h>7 8vuint32m1_t test_vssrl_vv_u32m1(vuint32m1_t op1, vuint32m1_t op2, size_t vl) {9 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}10 return __riscv_vssrl_vv_u32m1(op1, op2, 5, vl);11}12 13vuint32m1_t test_vssrl_vx_u32m1(vuint32m1_t op1, uint32_t op2, size_t vl) {14 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}15 return __riscv_vssrl_vx_u32m1(op1, op2, 5, vl);16}17 18vuint32m1_t test_vssrl_vv_u32m1_m(vbool32_t mask, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {19 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}20 return __riscv_vssrl_vv_u32m1_m(mask, op1, op2, 5, vl);21}22 23vuint32m1_t test_vssrl_vx_u32m1_m(vbool32_t mask, vuint32m1_t op1, uint32_t op2, size_t vl) {24 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}25 return __riscv_vssrl_vx_u32m1_m(mask, op1, op2, 5, vl);26}27 28vuint32m1_t test_vssrl_vv_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {29 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}30 return __riscv_vssrl_vv_u32m1_tu(maskedoff, op1, op2, 5, vl);31}32 33vuint32m1_t test_vssrl_vx_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {34 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}35 return __riscv_vssrl_vx_u32m1_tu(maskedoff, op1, op2, 5, vl);36}37 38vuint32m1_t test_vssrl_vv_u32m1_tum(39 vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {40 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}41 return __riscv_vssrl_vv_u32m1_tum(mask, maskedoff, op1, op2, 5, vl);42}43 44vuint32m1_t test_vssrl_vx_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {45 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}46 return __riscv_vssrl_vx_u32m1_tum(mask, maskedoff, op1, op2, 5, vl);47}48 49vuint32m1_t test_vssrl_vv_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {50 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}51 return __riscv_vssrl_vv_u32m1_tumu(mask, maskedoff, op1, op2, 5, vl);52}53 54vuint32m1_t test_vssrl_vx_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {55 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}56 return __riscv_vssrl_vx_u32m1_tumu(mask, maskedoff, op1, op2, 5, vl);57}58 59vuint32m1_t test_vssrl_vv_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {60 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}61 return __riscv_vssrl_vv_u32m1_mu(mask, maskedoff, op1, op2, 5, vl);62}63 64vuint32m1_t test_vssrl_vx_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {65 // expected-error@+1 {{argument value 5 is outside the valid range [0, 3]}}66 return __riscv_vssrl_vx_u32m1_mu(mask, maskedoff, op1, op2, 5, vl);67}68