100 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \4// RUN: -target-feature +zve64x \5// RUN: -disable-O0-optnone -emit-llvm %s -o - | \6// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s7 8#include <sifive_vector.h>9 10// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e8w1(11// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 0, i64 1)14// CHECK-RV64-NEXT: ret i64 [[TMP0]]15//16size_t test_sf_vsettn_e8w1(size_t tn) {17 return __riscv_sf_vsettn_e8w1(tn);18}19 20// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e8w2(21// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 0, i64 2)24// CHECK-RV64-NEXT: ret i64 [[TMP0]]25//26size_t test_sf_vsettn_e8w2(size_t tn) {27 return __riscv_sf_vsettn_e8w2(tn);28}29 30// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e8w4(31// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 0, i64 3)34// CHECK-RV64-NEXT: ret i64 [[TMP0]]35//36size_t test_sf_vsettn_e8w4(size_t tn) {37 return __riscv_sf_vsettn_e8w4(tn);38}39 40// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e16w1(41// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 1, i64 1)44// CHECK-RV64-NEXT: ret i64 [[TMP0]]45//46size_t test_sf_vsettn_e16w1(size_t tn) {47 return __riscv_sf_vsettn_e16w1(tn);48}49 50// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e16w2(51// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 1, i64 2)54// CHECK-RV64-NEXT: ret i64 [[TMP0]]55//56size_t test_sf_vsettn_e16w2(size_t tn) {57 return __riscv_sf_vsettn_e16w2(tn);58}59 60// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e16w4(61// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 1, i64 3)64// CHECK-RV64-NEXT: ret i64 [[TMP0]]65//66size_t test_sf_vsettn_e16w4(size_t tn) {67 return __riscv_sf_vsettn_e16w4(tn);68}69 70// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e32w1(71// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 2, i64 1)74// CHECK-RV64-NEXT: ret i64 [[TMP0]]75//76size_t test_sf_vsettn_e32w1(size_t tn) {77 return __riscv_sf_vsettn_e32w1(tn);78}79 80// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e32w2(81// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 2, i64 2)84// CHECK-RV64-NEXT: ret i64 [[TMP0]]85//86size_t test_sf_vsettn_e32w2(size_t tn) {87 return __riscv_sf_vsettn_e32w2(tn);88}89 90// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e64w1(91// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 3, i64 1)94// CHECK-RV64-NEXT: ret i64 [[TMP0]]95//96size_t test_sf_vsettn_e64w1(size_t tn) {97 return __riscv_sf_vsettn_e64w1(tn);98}99 100