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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \4// RUN: -disable-O0-optnone -emit-llvm %s -o - | \5// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s6 7#include <sifive_vector.h>8 9// CHECK-RV64-LABEL: define dso_local void @test_sf_vste8_i8(10// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste8.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]])13// CHECK-RV64-NEXT: ret void14//15void test_sf_vste8_i8(size_t tss, int8_t *base, size_t vl) {16 return __riscv_sf_vste8_i8(tss, base, vl);17}18 19// CHECK-RV64-LABEL: define dso_local void @test_sf_vste8_u8(20// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste8.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]])23// CHECK-RV64-NEXT: ret void24//25void test_sf_vste8_u8(size_t tss, uint8_t *base, size_t vl) {26 return __riscv_sf_vste8_u8(tss, base, vl);27}28 29