100 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \4// RUN: -target-feature +zve64x \5// RUN: -disable-O0-optnone -emit-llvm %s -o - | \6// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s7 8#include <sifive_vector.h>9 10// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e8w1(11// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 3, i64 1)14// CHECK-RV64-NEXT: ret void15//16void test_sf_vtzero_t_e8w1(size_t tm, size_t tn) {17 return __riscv_sf_vtzero_t_e8w1(0, tm, tn);18}19 20// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e8w2(21// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 3, i64 2)24// CHECK-RV64-NEXT: ret void25//26void test_sf_vtzero_t_e8w2(size_t tm, size_t tn) {27 return __riscv_sf_vtzero_t_e8w2(0, tm, tn);28}29 30// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e8w4(31// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 3, i64 4)34// CHECK-RV64-NEXT: ret void35//36void test_sf_vtzero_t_e8w4(size_t tm, size_t tn) {37 return __riscv_sf_vtzero_t_e8w4(0, tm, tn);38}39 40// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e16w1(41// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 4, i64 1)44// CHECK-RV64-NEXT: ret void45//46void test_sf_vtzero_t_e16w1(size_t tm, size_t tn) {47 return __riscv_sf_vtzero_t_e16w1(0, tm, tn);48}49 50// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e16w2(51// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] {52// CHECK-RV64-NEXT: entry:53// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 4, i64 2)54// CHECK-RV64-NEXT: ret void55//56void test_sf_vtzero_t_e16w2(size_t tm, size_t tn) {57 return __riscv_sf_vtzero_t_e16w2(0, tm, tn);58}59 60// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e16w4(61// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] {62// CHECK-RV64-NEXT: entry:63// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 4, i64 4)64// CHECK-RV64-NEXT: ret void65//66void test_sf_vtzero_t_e16w4(size_t tm, size_t tn) {67 return __riscv_sf_vtzero_t_e16w4(0, tm, tn);68}69 70// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e32w1(71// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] {72// CHECK-RV64-NEXT: entry:73// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 5, i64 1)74// CHECK-RV64-NEXT: ret void75//76void test_sf_vtzero_t_e32w1(size_t tm, size_t tn) {77 return __riscv_sf_vtzero_t_e32w1(0, tm, tn);78}79 80// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e32w2(81// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] {82// CHECK-RV64-NEXT: entry:83// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 5, i64 2)84// CHECK-RV64-NEXT: ret void85//86void test_sf_vtzero_t_e32w2(size_t tm, size_t tn) {87 return __riscv_sf_vtzero_t_e32w2(0, tm, tn);88}89 90// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e64w1(91// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] {92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 6, i64 1)94// CHECK-RV64-NEXT: ret void95//96void test_sf_vtzero_t_e64w1(size_t tm, size_t tn) {97 return __riscv_sf_vtzero_t_e64w1(0, tm, tn);98}99 100