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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \4// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin \5// RUN: -disable-O0-optnone -emit-llvm %s -o - | \6// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s7 8#include <sifive_vector.h>9 10// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_bf16(11// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]])14// CHECK-RV64-NEXT: ret void15//16void test_sf_vste16_bf16(size_t tss, __bf16 *base, size_t vl) {17 return __riscv_sf_vste16(tss, base, vl);18}19 20// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_f16(21// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {22// CHECK-RV64-NEXT: entry:23// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]])24// CHECK-RV64-NEXT: ret void25//26void test_sf_vste16_f16(size_t tss, _Float16 *base, size_t vl) {27 return __riscv_sf_vste16(tss, base, vl);28}29 30// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_i16(31// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]])34// CHECK-RV64-NEXT: ret void35//36void test_sf_vste16_i16(size_t tss, int16_t *base, size_t vl) {37 return __riscv_sf_vste16(tss, base, vl);38}39 40// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_u16(41// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {42// CHECK-RV64-NEXT: entry:43// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]])44// CHECK-RV64-NEXT: ret void45//46void test_sf_vste16_u16(size_t tss, uint16_t *base, size_t vl) {47 return __riscv_sf_vste16(tss, base, vl);48}49 50