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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s4 5#include <sifive_vector.h>6 7#define p27_26 (0b11)8#define p24_20 (0b11111)9#define p11_7 (0b11111)10 11// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1(12// CHECK-RV64-NEXT: entry:13// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 0, i64 [[VL:%.*]])14// CHECK-RV64-NEXT: ret void15//16void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {17 __riscv_sf_vc_x_se_u64m1(p27_26, p24_20, p11_7, rs1, vl);18}19 20// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m2(21// CHECK-RV64-NEXT: entry:22// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 1, i64 [[VL:%.*]])23// CHECK-RV64-NEXT: ret void24//25void test_sf_vc_x_se_u64m2(uint64_t rs1, size_t vl) {26 __riscv_sf_vc_x_se_u64m2(p27_26, p24_20, p11_7, rs1, vl);27}28 29// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m4(30// CHECK-RV64-NEXT: entry:31// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 2, i64 [[VL:%.*]])32// CHECK-RV64-NEXT: ret void33//34void test_sf_vc_x_se_u64m4(uint64_t rs1, size_t vl) {35 __riscv_sf_vc_x_se_u64m4(p27_26, p24_20, p11_7, rs1, vl);36}37 38// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m8(39// CHECK-RV64-NEXT: entry:40// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 64, i64 3, i64 [[VL:%.*]])41// CHECK-RV64-NEXT: ret void42//43void test_sf_vc_x_se_u64m8(uint64_t rs1, size_t vl) {44 __riscv_sf_vc_x_se_u64m8(p27_26, p24_20, p11_7, rs1, vl);45}46 47// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m1(48// CHECK-RV64-NEXT: entry:49// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])50// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]51//52vuint64m1_t test_sf_vc_v_x_se_u64m1(uint64_t rs1, size_t vl) {53 return __riscv_sf_vc_v_x_se_u64m1(p27_26, p24_20, rs1, vl);54}55 56// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m2(57// CHECK-RV64-NEXT: entry:58// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])59// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]60//61vuint64m2_t test_sf_vc_v_x_se_u64m2(uint64_t rs1, size_t vl) {62 return __riscv_sf_vc_v_x_se_u64m2(p27_26, p24_20, rs1, vl);63}64 65// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m4(66// CHECK-RV64-NEXT: entry:67// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])68// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]69//70vuint64m4_t test_sf_vc_v_x_se_u64m4(uint64_t rs1, size_t vl) {71 return __riscv_sf_vc_v_x_se_u64m4(p27_26, p24_20, rs1, vl);72}73 74// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m8(75// CHECK-RV64-NEXT: entry:76// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])77// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]78//79vuint64m8_t test_sf_vc_v_x_se_u64m8(uint64_t rs1, size_t vl) {80 return __riscv_sf_vc_v_x_se_u64m8(p27_26, p24_20, rs1, vl);81}82 83// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m1(84// CHECK-RV64-NEXT: entry:85// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])86// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]87//88vuint64m1_t test_sf_vc_v_x_u64m1(uint64_t rs1, size_t vl) {89 return __riscv_sf_vc_v_x_u64m1(p27_26, p24_20, rs1, vl);90}91 92// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m2(93// CHECK-RV64-NEXT: entry:94// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])95// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]96//97vuint64m2_t test_sf_vc_v_x_u64m2(uint64_t rs1, size_t vl) {98 return __riscv_sf_vc_v_x_u64m2(p27_26, p24_20, rs1, vl);99}100 101// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m4(102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])104// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]105//106vuint64m4_t test_sf_vc_v_x_u64m4(uint64_t rs1, size_t vl) {107 return __riscv_sf_vc_v_x_u64m4(p27_26, p24_20, rs1, vl);108}109 110// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m8(111// CHECK-RV64-NEXT: entry:112// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])113// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]114//115vuint64m8_t test_sf_vc_v_x_u64m8(uint64_t rs1, size_t vl) {116 return __riscv_sf_vc_v_x_u64m8(p27_26, p24_20, rs1, vl);117}118