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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s4 5#include <sifive_vector.h>6 7#define p27_26 (0b11)8#define p11_7 (0b11111)9 10// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m1(11// CHECK-RV64-NEXT: entry:12// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])13// CHECK-RV64-NEXT: ret void14//15void test_sf_vc_xv_se_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {16 __riscv_sf_vc_xv_se_u64m1(p27_26, p11_7, vs2, rs1, vl);17}18 19// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m2(20// CHECK-RV64-NEXT: entry:21// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])22// CHECK-RV64-NEXT: ret void23//24void test_sf_vc_xv_se_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) {25 __riscv_sf_vc_xv_se_u64m2(p27_26, p11_7, vs2, rs1, vl);26}27 28// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m4(29// CHECK-RV64-NEXT: entry:30// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])31// CHECK-RV64-NEXT: ret void32//33void test_sf_vc_xv_se_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) {34 __riscv_sf_vc_xv_se_u64m4(p27_26, p11_7, vs2, rs1, vl);35}36 37// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m8(38// CHECK-RV64-NEXT: entry:39// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])40// CHECK-RV64-NEXT: ret void41//42void test_sf_vc_xv_se_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) {43 __riscv_sf_vc_xv_se_u64m8(p27_26, p11_7, vs2, rs1, vl);44}45 46// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m1(47// CHECK-RV64-NEXT: entry:48// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])49// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]50//51vuint64m1_t test_sf_vc_v_xv_se_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {52 return __riscv_sf_vc_v_xv_se_u64m1(p27_26, vs2, rs1, vl);53}54 55// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m2(56// CHECK-RV64-NEXT: entry:57// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])58// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]59//60vuint64m2_t test_sf_vc_v_xv_se_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) {61 return __riscv_sf_vc_v_xv_se_u64m2(p27_26, vs2, rs1, vl);62}63 64// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m4(65// CHECK-RV64-NEXT: entry:66// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])67// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]68//69vuint64m4_t test_sf_vc_v_xv_se_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) {70 return __riscv_sf_vc_v_xv_se_u64m4(p27_26, vs2, rs1, vl);71}72 73// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m8(74// CHECK-RV64-NEXT: entry:75// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])76// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]77//78vuint64m8_t test_sf_vc_v_xv_se_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) {79 return __riscv_sf_vc_v_xv_se_u64m8(p27_26, vs2, rs1, vl);80}81 82// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m1(83// CHECK-RV64-NEXT: entry:84// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])85// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]86//87vuint64m1_t test_sf_vc_v_xv_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {88 return __riscv_sf_vc_v_xv_u64m1(p27_26, vs2, rs1, vl);89}90 91// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m2(92// CHECK-RV64-NEXT: entry:93// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])94// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]95//96vuint64m2_t test_sf_vc_v_xv_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) {97 return __riscv_sf_vc_v_xv_u64m2(p27_26, vs2, rs1, vl);98}99 100// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m4(101// CHECK-RV64-NEXT: entry:102// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])103// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]104//105vuint64m4_t test_sf_vc_v_xv_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) {106 return __riscv_sf_vc_v_xv_u64m4(p27_26, vs2, rs1, vl);107}108 109// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m8(110// CHECK-RV64-NEXT: entry:111// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.nxv8i64.i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])112// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]113//114vuint64m8_t test_sf_vc_v_xv_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) {115 return __riscv_sf_vc_v_xv_u64m8(p27_26, vs2, rs1, vl);116}117