3246 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s4// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s5 6#include <sifive_vector.h>7 8#define p27_26 (0b11)9#define p26 (0b1)10#define p11_7 (0b11111)11#define simm5 (10)12 13// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8mf8(14// CHECK-RV32-NEXT: entry:15// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i32 [[VL:%.*]])16// CHECK-RV32-NEXT: ret void17//18// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8mf8(19// CHECK-RV64-NEXT: entry:20// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv1i8.nxv1i8.i64(i64 3, i64 31, <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 [[VL:%.*]])21// CHECK-RV64-NEXT: ret void22//23void test_sf_vc_vv_se_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {24 __riscv_sf_vc_vv_se_u8mf8(p27_26, p11_7, vs2, vs1, vl);25}26 27// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8mf4(28// CHECK-RV32-NEXT: entry:29// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i32 [[VL:%.*]])30// CHECK-RV32-NEXT: ret void31//32// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8mf4(33// CHECK-RV64-NEXT: entry:34// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv2i8.nxv2i8.i64(i64 3, i64 31, <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 [[VL:%.*]])35// CHECK-RV64-NEXT: ret void36//37void test_sf_vc_vv_se_u8mf4(vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) {38 __riscv_sf_vc_vv_se_u8mf4(p27_26, p11_7, vs2, vs1, vl);39}40 41// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8mf2(42// CHECK-RV32-NEXT: entry:43// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i32 [[VL:%.*]])44// CHECK-RV32-NEXT: ret void45//46// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8mf2(47// CHECK-RV64-NEXT: entry:48// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv4i8.nxv4i8.i64(i64 3, i64 31, <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 [[VL:%.*]])49// CHECK-RV64-NEXT: ret void50//51void test_sf_vc_vv_se_u8mf2(vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) {52 __riscv_sf_vc_vv_se_u8mf2(p27_26, p11_7, vs2, vs1, vl);53}54 55// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8m1(56// CHECK-RV32-NEXT: entry:57// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i32 [[VL:%.*]])58// CHECK-RV32-NEXT: ret void59//60// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8m1(61// CHECK-RV64-NEXT: entry:62// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv8i8.nxv8i8.i64(i64 3, i64 31, <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 [[VL:%.*]])63// CHECK-RV64-NEXT: ret void64//65void test_sf_vc_vv_se_u8m1(vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {66 __riscv_sf_vc_vv_se_u8m1(p27_26, p11_7, vs2, vs1, vl);67}68 69// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8m2(70// CHECK-RV32-NEXT: entry:71// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i32 [[VL:%.*]])72// CHECK-RV32-NEXT: ret void73//74// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8m2(75// CHECK-RV64-NEXT: entry:76// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv16i8.nxv16i8.i64(i64 3, i64 31, <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 [[VL:%.*]])77// CHECK-RV64-NEXT: ret void78//79void test_sf_vc_vv_se_u8m2(vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {80 __riscv_sf_vc_vv_se_u8m2(p27_26, p11_7, vs2, vs1, vl);81}82 83// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8m4(84// CHECK-RV32-NEXT: entry:85// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i32 [[VL:%.*]])86// CHECK-RV32-NEXT: ret void87//88// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8m4(89// CHECK-RV64-NEXT: entry:90// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv32i8.nxv32i8.i64(i64 3, i64 31, <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 [[VL:%.*]])91// CHECK-RV64-NEXT: ret void92//93void test_sf_vc_vv_se_u8m4(vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) {94 __riscv_sf_vc_vv_se_u8m4(p27_26, p11_7, vs2, vs1, vl);95}96 97// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8m8(98// CHECK-RV32-NEXT: entry:99// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i32 [[VL:%.*]])100// CHECK-RV32-NEXT: ret void101//102// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8m8(103// CHECK-RV64-NEXT: entry:104// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv64i8.nxv64i8.i64(i64 3, i64 31, <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 [[VL:%.*]])105// CHECK-RV64-NEXT: ret void106//107void test_sf_vc_vv_se_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {108 __riscv_sf_vc_vv_se_u8m8(p27_26, p11_7, vs2, vs1, vl);109}110 111// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16mf4(112// CHECK-RV32-NEXT: entry:113// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i32 [[VL:%.*]])114// CHECK-RV32-NEXT: ret void115//116// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16mf4(117// CHECK-RV64-NEXT: entry:118// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv1i16.nxv1i16.i64(i64 3, i64 31, <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 [[VL:%.*]])119// CHECK-RV64-NEXT: ret void120//121void test_sf_vc_vv_se_u16mf4(vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) {122 __riscv_sf_vc_vv_se_u16mf4(p27_26, p11_7, vs2, vs1, vl);123}124 125// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16mf2(126// CHECK-RV32-NEXT: entry:127// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i32 [[VL:%.*]])128// CHECK-RV32-NEXT: ret void129//130// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16mf2(131// CHECK-RV64-NEXT: entry:132// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv2i16.nxv2i16.i64(i64 3, i64 31, <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 [[VL:%.*]])133// CHECK-RV64-NEXT: ret void134//135void test_sf_vc_vv_se_u16mf2(vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) {136 __riscv_sf_vc_vv_se_u16mf2(p27_26, p11_7, vs2, vs1, vl);137}138 139// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16m1(140// CHECK-RV32-NEXT: entry:141// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i32 [[VL:%.*]])142// CHECK-RV32-NEXT: ret void143//144// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16m1(145// CHECK-RV64-NEXT: entry:146// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv4i16.nxv4i16.i64(i64 3, i64 31, <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 [[VL:%.*]])147// CHECK-RV64-NEXT: ret void148//149void test_sf_vc_vv_se_u16m1(vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) {150 __riscv_sf_vc_vv_se_u16m1(p27_26, p11_7, vs2, vs1, vl);151}152 153// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16m2(154// CHECK-RV32-NEXT: entry:155// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i32 [[VL:%.*]])156// CHECK-RV32-NEXT: ret void157//158// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16m2(159// CHECK-RV64-NEXT: entry:160// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv8i16.nxv8i16.i64(i64 3, i64 31, <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 [[VL:%.*]])161// CHECK-RV64-NEXT: ret void162//163void test_sf_vc_vv_se_u16m2(vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) {164 __riscv_sf_vc_vv_se_u16m2(p27_26, p11_7, vs2, vs1, vl);165}166 167// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16m4(168// CHECK-RV32-NEXT: entry:169// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i16.nxv16i16.i32(i32 3, i32 31, <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i32 [[VL:%.*]])170// CHECK-RV32-NEXT: ret void171//172// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16m4(173// CHECK-RV64-NEXT: entry:174// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv16i16.nxv16i16.i64(i64 3, i64 31, <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 [[VL:%.*]])175// CHECK-RV64-NEXT: ret void176//177void test_sf_vc_vv_se_u16m4(vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) {178 __riscv_sf_vc_vv_se_u16m4(p27_26, p11_7, vs2, vs1, vl);179}180 181// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16m8(182// CHECK-RV32-NEXT: entry:183// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i16.nxv32i16.i32(i32 3, i32 31, <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i32 [[VL:%.*]])184// CHECK-RV32-NEXT: ret void185//186// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16m8(187// CHECK-RV64-NEXT: entry:188// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv32i16.nxv32i16.i64(i64 3, i64 31, <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 [[VL:%.*]])189// CHECK-RV64-NEXT: ret void190//191void test_sf_vc_vv_se_u16m8(vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) {192 __riscv_sf_vc_vv_se_u16m8(p27_26, p11_7, vs2, vs1, vl);193}194 195// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u32mf2(196// CHECK-RV32-NEXT: entry:197// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i32.nxv1i32.i32(i32 3, i32 31, <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i32 [[VL:%.*]])198// CHECK-RV32-NEXT: ret void199//200// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u32mf2(201// CHECK-RV64-NEXT: entry:202// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv1i32.nxv1i32.i64(i64 3, i64 31, <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 [[VL:%.*]])203// CHECK-RV64-NEXT: ret void204//205void test_sf_vc_vv_se_u32mf2(vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {206 __riscv_sf_vc_vv_se_u32mf2(p27_26, p11_7, vs2, vs1, vl);207}208 209// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u32m1(210// CHECK-RV32-NEXT: entry:211// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i32.nxv2i32.i32(i32 3, i32 31, <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i32 [[VL:%.*]])212// CHECK-RV32-NEXT: ret void213//214// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u32m1(215// CHECK-RV64-NEXT: entry:216// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv2i32.nxv2i32.i64(i64 3, i64 31, <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 [[VL:%.*]])217// CHECK-RV64-NEXT: ret void218//219void test_sf_vc_vv_se_u32m1(vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {220 __riscv_sf_vc_vv_se_u32m1(p27_26, p11_7, vs2, vs1, vl);221}222 223// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u32m2(224// CHECK-RV32-NEXT: entry:225// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i32.nxv4i32.i32(i32 3, i32 31, <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i32 [[VL:%.*]])226// CHECK-RV32-NEXT: ret void227//228// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u32m2(229// CHECK-RV64-NEXT: entry:230// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv4i32.nxv4i32.i64(i64 3, i64 31, <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 [[VL:%.*]])231// CHECK-RV64-NEXT: ret void232//233void test_sf_vc_vv_se_u32m2(vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {234 __riscv_sf_vc_vv_se_u32m2(p27_26, p11_7, vs2, vs1, vl);235}236 237// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u32m4(238// CHECK-RV32-NEXT: entry:239// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i32.nxv8i32.i32(i32 3, i32 31, <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i32 [[VL:%.*]])240// CHECK-RV32-NEXT: ret void241//242// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u32m4(243// CHECK-RV64-NEXT: entry:244// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv8i32.nxv8i32.i64(i64 3, i64 31, <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 [[VL:%.*]])245// CHECK-RV64-NEXT: ret void246//247void test_sf_vc_vv_se_u32m4(vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {248 __riscv_sf_vc_vv_se_u32m4(p27_26, p11_7, vs2, vs1, vl);249}250 251// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u32m8(252// CHECK-RV32-NEXT: entry:253// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i32.nxv16i32.i32(i32 3, i32 31, <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i32 [[VL:%.*]])254// CHECK-RV32-NEXT: ret void255//256// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u32m8(257// CHECK-RV64-NEXT: entry:258// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv16i32.nxv16i32.i64(i64 3, i64 31, <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 [[VL:%.*]])259// CHECK-RV64-NEXT: ret void260//261void test_sf_vc_vv_se_u32m8(vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) {262 __riscv_sf_vc_vv_se_u32m8(p27_26, p11_7, vs2, vs1, vl);263}264 265// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u64m1(266// CHECK-RV32-NEXT: entry:267// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i64.nxv1i64.i32(i32 3, i32 31, <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i32 [[VL:%.*]])268// CHECK-RV32-NEXT: ret void269//270// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u64m1(271// CHECK-RV64-NEXT: entry:272// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv1i64.nxv1i64.i64(i64 3, i64 31, <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 [[VL:%.*]])273// CHECK-RV64-NEXT: ret void274//275void test_sf_vc_vv_se_u64m1(vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {276 __riscv_sf_vc_vv_se_u64m1(p27_26, p11_7, vs2, vs1, vl);277}278 279// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u64m2(280// CHECK-RV32-NEXT: entry:281// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i64.nxv2i64.i32(i32 3, i32 31, <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i32 [[VL:%.*]])282// CHECK-RV32-NEXT: ret void283//284// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u64m2(285// CHECK-RV64-NEXT: entry:286// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv2i64.nxv2i64.i64(i64 3, i64 31, <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 [[VL:%.*]])287// CHECK-RV64-NEXT: ret void288//289void test_sf_vc_vv_se_u64m2(vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {290 __riscv_sf_vc_vv_se_u64m2(p27_26, p11_7, vs2, vs1, vl);291}292 293// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u64m4(294// CHECK-RV32-NEXT: entry:295// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i64.nxv4i64.i32(i32 3, i32 31, <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i32 [[VL:%.*]])296// CHECK-RV32-NEXT: ret void297//298// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u64m4(299// CHECK-RV64-NEXT: entry:300// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv4i64.nxv4i64.i64(i64 3, i64 31, <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 [[VL:%.*]])301// CHECK-RV64-NEXT: ret void302//303void test_sf_vc_vv_se_u64m4(vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {304 __riscv_sf_vc_vv_se_u64m4(p27_26, p11_7, vs2, vs1, vl);305}306 307// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u64m8(308// CHECK-RV32-NEXT: entry:309// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i64.nxv8i64.i32(i32 3, i32 31, <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i32 [[VL:%.*]])310// CHECK-RV32-NEXT: ret void311//312// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u64m8(313// CHECK-RV64-NEXT: entry:314// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv8i64.nxv8i64.i64(i64 3, i64 31, <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 [[VL:%.*]])315// CHECK-RV64-NEXT: ret void316//317void test_sf_vc_vv_se_u64m8(vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {318 __riscv_sf_vc_vv_se_u64m8(p27_26, p11_7, vs2, vs1, vl);319}320 321// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8mf8(322// CHECK-RV32-NEXT: entry:323// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv1i8.i32.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i32 [[VL:%.*]])324// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]325//326// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8mf8(327// CHECK-RV64-NEXT: entry:328// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv1i8.i64.nxv1i8.nxv1i8.i64(i64 3, <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 [[VL:%.*]])329// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]330//331vuint8mf8_t test_sf_vc_v_vv_se_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {332 return __riscv_sf_vc_v_vv_se_u8mf8(p27_26, vs2, vs1, vl);333}334 335// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8mf4(336// CHECK-RV32-NEXT: entry:337// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv2i8.i32.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i32 [[VL:%.*]])338// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]339//340// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8mf4(341// CHECK-RV64-NEXT: entry:342// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv2i8.i64.nxv2i8.nxv2i8.i64(i64 3, <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 [[VL:%.*]])343// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]344//345vuint8mf4_t test_sf_vc_v_vv_se_u8mf4(vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) {346 return __riscv_sf_vc_v_vv_se_u8mf4(p27_26, vs2, vs1, vl);347}348 349// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8mf2(350// CHECK-RV32-NEXT: entry:351// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv4i8.i32.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i32 [[VL:%.*]])352// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]353//354// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8mf2(355// CHECK-RV64-NEXT: entry:356// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv4i8.i64.nxv4i8.nxv4i8.i64(i64 3, <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 [[VL:%.*]])357// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]358//359vuint8mf2_t test_sf_vc_v_vv_se_u8mf2(vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) {360 return __riscv_sf_vc_v_vv_se_u8mf2(p27_26, vs2, vs1, vl);361}362 363// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8m1(364// CHECK-RV32-NEXT: entry:365// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv8i8.i32.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i32 [[VL:%.*]])366// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]367//368// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8m1(369// CHECK-RV64-NEXT: entry:370// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv8i8.i64.nxv8i8.nxv8i8.i64(i64 3, <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 [[VL:%.*]])371// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]372//373vuint8m1_t test_sf_vc_v_vv_se_u8m1(vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {374 return __riscv_sf_vc_v_vv_se_u8m1(p27_26, vs2, vs1, vl);375}376 377// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8m2(378// CHECK-RV32-NEXT: entry:379// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv16i8.i32.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i32 [[VL:%.*]])380// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]381//382// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8m2(383// CHECK-RV64-NEXT: entry:384// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv16i8.i64.nxv16i8.nxv16i8.i64(i64 3, <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 [[VL:%.*]])385// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]386//387vuint8m2_t test_sf_vc_v_vv_se_u8m2(vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {388 return __riscv_sf_vc_v_vv_se_u8m2(p27_26, vs2, vs1, vl);389}390 391// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8m4(392// CHECK-RV32-NEXT: entry:393// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv32i8.i32.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i32 [[VL:%.*]])394// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]395//396// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8m4(397// CHECK-RV64-NEXT: entry:398// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv32i8.i64.nxv32i8.nxv32i8.i64(i64 3, <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 [[VL:%.*]])399// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]400//401vuint8m4_t test_sf_vc_v_vv_se_u8m4(vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) {402 return __riscv_sf_vc_v_vv_se_u8m4(p27_26, vs2, vs1, vl);403}404 405// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8m8(406// CHECK-RV32-NEXT: entry:407// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv64i8.i32.nxv64i8.nxv64i8.i32(i32 3, <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i32 [[VL:%.*]])408// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]409//410// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8m8(411// CHECK-RV64-NEXT: entry:412// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv64i8.i64.nxv64i8.nxv64i8.i64(i64 3, <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 [[VL:%.*]])413// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]414//415vuint8m8_t test_sf_vc_v_vv_se_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {416 return __riscv_sf_vc_v_vv_se_u8m8(p27_26, vs2, vs1, vl);417}418 419// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16mf4(420// CHECK-RV32-NEXT: entry:421// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv1i16.i32.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i32 [[VL:%.*]])422// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]423//424// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16mf4(425// CHECK-RV64-NEXT: entry:426// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv1i16.i64.nxv1i16.nxv1i16.i64(i64 3, <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 [[VL:%.*]])427// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]428//429vuint16mf4_t test_sf_vc_v_vv_se_u16mf4(vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) {430 return __riscv_sf_vc_v_vv_se_u16mf4(p27_26, vs2, vs1, vl);431}432 433// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16mf2(434// CHECK-RV32-NEXT: entry:435// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv2i16.i32.nxv2i16.nxv2i16.i32(i32 3, <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i32 [[VL:%.*]])436// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]437//438// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16mf2(439// CHECK-RV64-NEXT: entry:440// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv2i16.i64.nxv2i16.nxv2i16.i64(i64 3, <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 [[VL:%.*]])441// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]442//443vuint16mf2_t test_sf_vc_v_vv_se_u16mf2(vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) {444 return __riscv_sf_vc_v_vv_se_u16mf2(p27_26, vs2, vs1, vl);445}446 447// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16m1(448// CHECK-RV32-NEXT: entry:449// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv4i16.i32.nxv4i16.nxv4i16.i32(i32 3, <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i32 [[VL:%.*]])450// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]451//452// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16m1(453// CHECK-RV64-NEXT: entry:454// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv4i16.i64.nxv4i16.nxv4i16.i64(i64 3, <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 [[VL:%.*]])455// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]456//457vuint16m1_t test_sf_vc_v_vv_se_u16m1(vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) {458 return __riscv_sf_vc_v_vv_se_u16m1(p27_26, vs2, vs1, vl);459}460 461// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16m2(462// CHECK-RV32-NEXT: entry:463// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv8i16.i32.nxv8i16.nxv8i16.i32(i32 3, <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i32 [[VL:%.*]])464// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]465//466// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16m2(467// CHECK-RV64-NEXT: entry:468// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv8i16.i64.nxv8i16.nxv8i16.i64(i64 3, <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 [[VL:%.*]])469// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]470//471vuint16m2_t test_sf_vc_v_vv_se_u16m2(vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) {472 return __riscv_sf_vc_v_vv_se_u16m2(p27_26, vs2, vs1, vl);473}474 475// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16m4(476// CHECK-RV32-NEXT: entry:477// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv16i16.i32.nxv16i16.nxv16i16.i32(i32 3, <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i32 [[VL:%.*]])478// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]479//480// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16m4(481// CHECK-RV64-NEXT: entry:482// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv16i16.i64.nxv16i16.nxv16i16.i64(i64 3, <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 [[VL:%.*]])483// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]484//485vuint16m4_t test_sf_vc_v_vv_se_u16m4(vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) {486 return __riscv_sf_vc_v_vv_se_u16m4(p27_26, vs2, vs1, vl);487}488 489// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16m8(490// CHECK-RV32-NEXT: entry:491// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv32i16.i32.nxv32i16.nxv32i16.i32(i32 3, <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i32 [[VL:%.*]])492// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]493//494// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16m8(495// CHECK-RV64-NEXT: entry:496// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv32i16.i64.nxv32i16.nxv32i16.i64(i64 3, <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 [[VL:%.*]])497// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]498//499vuint16m8_t test_sf_vc_v_vv_se_u16m8(vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) {500 return __riscv_sf_vc_v_vv_se_u16m8(p27_26, vs2, vs1, vl);501}502 503// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u32mf2(504// CHECK-RV32-NEXT: entry:505// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv1i32.i32.nxv1i32.nxv1i32.i32(i32 3, <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i32 [[VL:%.*]])506// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]507//508// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u32mf2(509// CHECK-RV64-NEXT: entry:510// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv1i32.i64.nxv1i32.nxv1i32.i64(i64 3, <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 [[VL:%.*]])511// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]512//513vuint32mf2_t test_sf_vc_v_vv_se_u32mf2(vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {514 return __riscv_sf_vc_v_vv_se_u32mf2(p27_26, vs2, vs1, vl);515}516 517// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u32m1(518// CHECK-RV32-NEXT: entry:519// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv2i32.i32.nxv2i32.nxv2i32.i32(i32 3, <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i32 [[VL:%.*]])520// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]521//522// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u32m1(523// CHECK-RV64-NEXT: entry:524// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv2i32.i64.nxv2i32.nxv2i32.i64(i64 3, <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 [[VL:%.*]])525// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]526//527vuint32m1_t test_sf_vc_v_vv_se_u32m1(vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {528 return __riscv_sf_vc_v_vv_se_u32m1(p27_26, vs2, vs1, vl);529}530 531// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u32m2(532// CHECK-RV32-NEXT: entry:533// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv4i32.i32.nxv4i32.nxv4i32.i32(i32 3, <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i32 [[VL:%.*]])534// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]535//536// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u32m2(537// CHECK-RV64-NEXT: entry:538// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv4i32.i64.nxv4i32.nxv4i32.i64(i64 3, <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 [[VL:%.*]])539// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]540//541vuint32m2_t test_sf_vc_v_vv_se_u32m2(vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {542 return __riscv_sf_vc_v_vv_se_u32m2(p27_26, vs2, vs1, vl);543}544 545// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u32m4(546// CHECK-RV32-NEXT: entry:547// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv8i32.i32.nxv8i32.nxv8i32.i32(i32 3, <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i32 [[VL:%.*]])548// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]549//550// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u32m4(551// CHECK-RV64-NEXT: entry:552// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv8i32.i64.nxv8i32.nxv8i32.i64(i64 3, <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 [[VL:%.*]])553// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]554//555vuint32m4_t test_sf_vc_v_vv_se_u32m4(vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {556 return __riscv_sf_vc_v_vv_se_u32m4(p27_26, vs2, vs1, vl);557}558 559// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u32m8(560// CHECK-RV32-NEXT: entry:561// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv16i32.i32.nxv16i32.nxv16i32.i32(i32 3, <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i32 [[VL:%.*]])562// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]563//564// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u32m8(565// CHECK-RV64-NEXT: entry:566// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv16i32.i64.nxv16i32.nxv16i32.i64(i64 3, <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 [[VL:%.*]])567// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]568//569vuint32m8_t test_sf_vc_v_vv_se_u32m8(vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) {570 return __riscv_sf_vc_v_vv_se_u32m8(p27_26, vs2, vs1, vl);571}572 573// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u64m1(574// CHECK-RV32-NEXT: entry:575// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv1i64.i32.nxv1i64.nxv1i64.i32(i32 3, <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i32 [[VL:%.*]])576// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]577//578// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u64m1(579// CHECK-RV64-NEXT: entry:580// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64(i64 3, <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 [[VL:%.*]])581// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]582//583vuint64m1_t test_sf_vc_v_vv_se_u64m1(vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {584 return __riscv_sf_vc_v_vv_se_u64m1(p27_26, vs2, vs1, vl);585}586 587// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u64m2(588// CHECK-RV32-NEXT: entry:589// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv2i64.i32.nxv2i64.nxv2i64.i32(i32 3, <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i32 [[VL:%.*]])590// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]591//592// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u64m2(593// CHECK-RV64-NEXT: entry:594// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64(i64 3, <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 [[VL:%.*]])595// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]596//597vuint64m2_t test_sf_vc_v_vv_se_u64m2(vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {598 return __riscv_sf_vc_v_vv_se_u64m2(p27_26, vs2, vs1, vl);599}600 601// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u64m4(602// CHECK-RV32-NEXT: entry:603// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv4i64.i32.nxv4i64.nxv4i64.i32(i32 3, <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i32 [[VL:%.*]])604// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]605//606// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u64m4(607// CHECK-RV64-NEXT: entry:608// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64(i64 3, <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 [[VL:%.*]])609// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]610//611vuint64m4_t test_sf_vc_v_vv_se_u64m4(vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {612 return __riscv_sf_vc_v_vv_se_u64m4(p27_26, vs2, vs1, vl);613}614 615// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u64m8(616// CHECK-RV32-NEXT: entry:617// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv8i64.i32.nxv8i64.nxv8i64.i32(i32 3, <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i32 [[VL:%.*]])618// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]619//620// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u64m8(621// CHECK-RV64-NEXT: entry:622// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64(i64 3, <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 [[VL:%.*]])623// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]624//625vuint64m8_t test_sf_vc_v_vv_se_u64m8(vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {626 return __riscv_sf_vc_v_vv_se_u64m8(p27_26, vs2, vs1, vl);627}628 629// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8mf8(630// CHECK-RV32-NEXT: entry:631// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vv.nxv1i8.i32.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i32 [[VL:%.*]])632// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]633//634// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8mf8(635// CHECK-RV64-NEXT: entry:636// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vv.nxv1i8.i64.nxv1i8.nxv1i8.i64(i64 3, <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 [[VL:%.*]])637// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]638//639vuint8mf8_t test_sf_vc_v_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {640 return __riscv_sf_vc_v_vv_u8mf8(p27_26, vs2, vs1, vl);641}642 643// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8mf4(644// CHECK-RV32-NEXT: entry:645// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vv.nxv2i8.i32.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i32 [[VL:%.*]])646// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]647//648// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8mf4(649// CHECK-RV64-NEXT: entry:650// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vv.nxv2i8.i64.nxv2i8.nxv2i8.i64(i64 3, <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 [[VL:%.*]])651// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]652//653vuint8mf4_t test_sf_vc_v_vv_u8mf4(vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) {654 return __riscv_sf_vc_v_vv_u8mf4(p27_26, vs2, vs1, vl);655}656 657// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8mf2(658// CHECK-RV32-NEXT: entry:659// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vv.nxv4i8.i32.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i32 [[VL:%.*]])660// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]661//662// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8mf2(663// CHECK-RV64-NEXT: entry:664// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vv.nxv4i8.i64.nxv4i8.nxv4i8.i64(i64 3, <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 [[VL:%.*]])665// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]666//667vuint8mf2_t test_sf_vc_v_vv_u8mf2(vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) {668 return __riscv_sf_vc_v_vv_u8mf2(p27_26, vs2, vs1, vl);669}670 671// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8m1(672// CHECK-RV32-NEXT: entry:673// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vv.nxv8i8.i32.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i32 [[VL:%.*]])674// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]675//676// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8m1(677// CHECK-RV64-NEXT: entry:678// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vv.nxv8i8.i64.nxv8i8.nxv8i8.i64(i64 3, <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 [[VL:%.*]])679// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]680//681vuint8m1_t test_sf_vc_v_vv_u8m1(vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {682 return __riscv_sf_vc_v_vv_u8m1(p27_26, vs2, vs1, vl);683}684 685// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8m2(686// CHECK-RV32-NEXT: entry:687// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vv.nxv16i8.i32.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i32 [[VL:%.*]])688// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]689//690// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8m2(691// CHECK-RV64-NEXT: entry:692// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vv.nxv16i8.i64.nxv16i8.nxv16i8.i64(i64 3, <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 [[VL:%.*]])693// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]694//695vuint8m2_t test_sf_vc_v_vv_u8m2(vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {696 return __riscv_sf_vc_v_vv_u8m2(p27_26, vs2, vs1, vl);697}698 699// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8m4(700// CHECK-RV32-NEXT: entry:701// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vv.nxv32i8.i32.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i32 [[VL:%.*]])702// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]703//704// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8m4(705// CHECK-RV64-NEXT: entry:706// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vv.nxv32i8.i64.nxv32i8.nxv32i8.i64(i64 3, <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 [[VL:%.*]])707// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]708//709vuint8m4_t test_sf_vc_v_vv_u8m4(vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) {710 return __riscv_sf_vc_v_vv_u8m4(p27_26, vs2, vs1, vl);711}712 713// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8m8(714// CHECK-RV32-NEXT: entry:715// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vv.nxv64i8.i32.nxv64i8.nxv64i8.i32(i32 3, <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i32 [[VL:%.*]])716// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]717//718// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8m8(719// CHECK-RV64-NEXT: entry:720// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vv.nxv64i8.i64.nxv64i8.nxv64i8.i64(i64 3, <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 [[VL:%.*]])721// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]722//723vuint8m8_t test_sf_vc_v_vv_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {724 return __riscv_sf_vc_v_vv_u8m8(p27_26, vs2, vs1, vl);725}726 727// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16mf4(728// CHECK-RV32-NEXT: entry:729// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vv.nxv1i16.i32.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i32 [[VL:%.*]])730// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]731//732// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16mf4(733// CHECK-RV64-NEXT: entry:734// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vv.nxv1i16.i64.nxv1i16.nxv1i16.i64(i64 3, <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 [[VL:%.*]])735// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]736//737vuint16mf4_t test_sf_vc_v_vv_u16mf4(vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) {738 return __riscv_sf_vc_v_vv_u16mf4(p27_26, vs2, vs1, vl);739}740 741// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16mf2(742// CHECK-RV32-NEXT: entry:743// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vv.nxv2i16.i32.nxv2i16.nxv2i16.i32(i32 3, <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i32 [[VL:%.*]])744// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]745//746// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16mf2(747// CHECK-RV64-NEXT: entry:748// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vv.nxv2i16.i64.nxv2i16.nxv2i16.i64(i64 3, <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 [[VL:%.*]])749// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]750//751vuint16mf2_t test_sf_vc_v_vv_u16mf2(vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) {752 return __riscv_sf_vc_v_vv_u16mf2(p27_26, vs2, vs1, vl);753}754 755// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16m1(756// CHECK-RV32-NEXT: entry:757// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vv.nxv4i16.i32.nxv4i16.nxv4i16.i32(i32 3, <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i32 [[VL:%.*]])758// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]759//760// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16m1(761// CHECK-RV64-NEXT: entry:762// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vv.nxv4i16.i64.nxv4i16.nxv4i16.i64(i64 3, <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 [[VL:%.*]])763// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]764//765vuint16m1_t test_sf_vc_v_vv_u16m1(vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) {766 return __riscv_sf_vc_v_vv_u16m1(p27_26, vs2, vs1, vl);767}768 769// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16m2(770// CHECK-RV32-NEXT: entry:771// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vv.nxv8i16.i32.nxv8i16.nxv8i16.i32(i32 3, <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i32 [[VL:%.*]])772// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]773//774// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16m2(775// CHECK-RV64-NEXT: entry:776// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vv.nxv8i16.i64.nxv8i16.nxv8i16.i64(i64 3, <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 [[VL:%.*]])777// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]778//779vuint16m2_t test_sf_vc_v_vv_u16m2(vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) {780 return __riscv_sf_vc_v_vv_u16m2(p27_26, vs2, vs1, vl);781}782 783// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16m4(784// CHECK-RV32-NEXT: entry:785// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vv.nxv16i16.i32.nxv16i16.nxv16i16.i32(i32 3, <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i32 [[VL:%.*]])786// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]787//788// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16m4(789// CHECK-RV64-NEXT: entry:790// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vv.nxv16i16.i64.nxv16i16.nxv16i16.i64(i64 3, <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 [[VL:%.*]])791// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]792//793vuint16m4_t test_sf_vc_v_vv_u16m4(vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) {794 return __riscv_sf_vc_v_vv_u16m4(p27_26, vs2, vs1, vl);795}796 797// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16m8(798// CHECK-RV32-NEXT: entry:799// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vv.nxv32i16.i32.nxv32i16.nxv32i16.i32(i32 3, <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i32 [[VL:%.*]])800// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]801//802// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16m8(803// CHECK-RV64-NEXT: entry:804// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vv.nxv32i16.i64.nxv32i16.nxv32i16.i64(i64 3, <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 [[VL:%.*]])805// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]806//807vuint16m8_t test_sf_vc_v_vv_u16m8(vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) {808 return __riscv_sf_vc_v_vv_u16m8(p27_26, vs2, vs1, vl);809}810 811// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u32mf2(812// CHECK-RV32-NEXT: entry:813// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vv.nxv1i32.i32.nxv1i32.nxv1i32.i32(i32 3, <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i32 [[VL:%.*]])814// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]815//816// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u32mf2(817// CHECK-RV64-NEXT: entry:818// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vv.nxv1i32.i64.nxv1i32.nxv1i32.i64(i64 3, <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 [[VL:%.*]])819// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]820//821vuint32mf2_t test_sf_vc_v_vv_u32mf2(vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {822 return __riscv_sf_vc_v_vv_u32mf2(p27_26, vs2, vs1, vl);823}824 825// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u32m1(826// CHECK-RV32-NEXT: entry:827// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vv.nxv2i32.i32.nxv2i32.nxv2i32.i32(i32 3, <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i32 [[VL:%.*]])828// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]829//830// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u32m1(831// CHECK-RV64-NEXT: entry:832// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vv.nxv2i32.i64.nxv2i32.nxv2i32.i64(i64 3, <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 [[VL:%.*]])833// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]834//835vuint32m1_t test_sf_vc_v_vv_u32m1(vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {836 return __riscv_sf_vc_v_vv_u32m1(p27_26, vs2, vs1, vl);837}838 839// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u32m2(840// CHECK-RV32-NEXT: entry:841// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vv.nxv4i32.i32.nxv4i32.nxv4i32.i32(i32 3, <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i32 [[VL:%.*]])842// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]843//844// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u32m2(845// CHECK-RV64-NEXT: entry:846// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vv.nxv4i32.i64.nxv4i32.nxv4i32.i64(i64 3, <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 [[VL:%.*]])847// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]848//849vuint32m2_t test_sf_vc_v_vv_u32m2(vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {850 return __riscv_sf_vc_v_vv_u32m2(p27_26, vs2, vs1, vl);851}852 853// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u32m4(854// CHECK-RV32-NEXT: entry:855// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vv.nxv8i32.i32.nxv8i32.nxv8i32.i32(i32 3, <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i32 [[VL:%.*]])856// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]857//858// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u32m4(859// CHECK-RV64-NEXT: entry:860// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vv.nxv8i32.i64.nxv8i32.nxv8i32.i64(i64 3, <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 [[VL:%.*]])861// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]862//863vuint32m4_t test_sf_vc_v_vv_u32m4(vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {864 return __riscv_sf_vc_v_vv_u32m4(p27_26, vs2, vs1, vl);865}866 867// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u32m8(868// CHECK-RV32-NEXT: entry:869// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vv.nxv16i32.i32.nxv16i32.nxv16i32.i32(i32 3, <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i32 [[VL:%.*]])870// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]871//872// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u32m8(873// CHECK-RV64-NEXT: entry:874// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vv.nxv16i32.i64.nxv16i32.nxv16i32.i64(i64 3, <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 [[VL:%.*]])875// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]876//877vuint32m8_t test_sf_vc_v_vv_u32m8(vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) {878 return __riscv_sf_vc_v_vv_u32m8(p27_26, vs2, vs1, vl);879}880 881// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u64m1(882// CHECK-RV32-NEXT: entry:883// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vv.nxv1i64.i32.nxv1i64.nxv1i64.i32(i32 3, <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i32 [[VL:%.*]])884// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]885//886// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u64m1(887// CHECK-RV64-NEXT: entry:888// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vv.nxv1i64.i64.nxv1i64.nxv1i64.i64(i64 3, <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 [[VL:%.*]])889// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]890//891vuint64m1_t test_sf_vc_v_vv_u64m1(vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {892 return __riscv_sf_vc_v_vv_u64m1(p27_26, vs2, vs1, vl);893}894 895// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u64m2(896// CHECK-RV32-NEXT: entry:897// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vv.nxv2i64.i32.nxv2i64.nxv2i64.i32(i32 3, <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i32 [[VL:%.*]])898// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]899//900// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u64m2(901// CHECK-RV64-NEXT: entry:902// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vv.nxv2i64.i64.nxv2i64.nxv2i64.i64(i64 3, <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 [[VL:%.*]])903// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]904//905vuint64m2_t test_sf_vc_v_vv_u64m2(vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {906 return __riscv_sf_vc_v_vv_u64m2(p27_26, vs2, vs1, vl);907}908 909// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u64m4(910// CHECK-RV32-NEXT: entry:911// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vv.nxv4i64.i32.nxv4i64.nxv4i64.i32(i32 3, <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i32 [[VL:%.*]])912// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]913//914// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u64m4(915// CHECK-RV64-NEXT: entry:916// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vv.nxv4i64.i64.nxv4i64.nxv4i64.i64(i64 3, <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 [[VL:%.*]])917// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]918//919vuint64m4_t test_sf_vc_v_vv_u64m4(vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {920 return __riscv_sf_vc_v_vv_u64m4(p27_26, vs2, vs1, vl);921}922 923// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u64m8(924// CHECK-RV32-NEXT: entry:925// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vv.nxv8i64.i32.nxv8i64.nxv8i64.i32(i32 3, <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i32 [[VL:%.*]])926// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]927//928// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u64m8(929// CHECK-RV64-NEXT: entry:930// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vv.nxv8i64.i64.nxv8i64.nxv8i64.i64(i64 3, <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 [[VL:%.*]])931// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]932//933vuint64m8_t test_sf_vc_v_vv_u64m8(vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {934 return __riscv_sf_vc_v_vv_u64m8(p27_26, vs2, vs1, vl);935}936 937// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8mf8(938// CHECK-RV32-NEXT: entry:939// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv1i8.i8.i32(i32 3, i32 31, <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])940// CHECK-RV32-NEXT: ret void941//942// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8mf8(943// CHECK-RV64-NEXT: entry:944// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i8.i8.i64(i64 3, i64 31, <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])945// CHECK-RV64-NEXT: ret void946//947void test_sf_vc_xv_se_u8mf8(vuint8mf8_t vs2, uint8_t rs1, size_t vl) {948 __riscv_sf_vc_xv_se_u8mf8(p27_26, p11_7, vs2, rs1, vl);949}950 951// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8mf4(952// CHECK-RV32-NEXT: entry:953// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv2i8.i8.i32(i32 3, i32 31, <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])954// CHECK-RV32-NEXT: ret void955//956// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8mf4(957// CHECK-RV64-NEXT: entry:958// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i8.i8.i64(i64 3, i64 31, <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])959// CHECK-RV64-NEXT: ret void960//961void test_sf_vc_xv_se_u8mf4(vuint8mf4_t vs2, uint8_t rs1, size_t vl) {962 __riscv_sf_vc_xv_se_u8mf4(p27_26, p11_7, vs2, rs1, vl);963}964 965// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8mf2(966// CHECK-RV32-NEXT: entry:967// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv4i8.i8.i32(i32 3, i32 31, <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])968// CHECK-RV32-NEXT: ret void969//970// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8mf2(971// CHECK-RV64-NEXT: entry:972// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i8.i8.i64(i64 3, i64 31, <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])973// CHECK-RV64-NEXT: ret void974//975void test_sf_vc_xv_se_u8mf2(vuint8mf2_t vs2, uint8_t rs1, size_t vl) {976 __riscv_sf_vc_xv_se_u8mf2(p27_26, p11_7, vs2, rs1, vl);977}978 979// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8m1(980// CHECK-RV32-NEXT: entry:981// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv8i8.i8.i32(i32 3, i32 31, <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])982// CHECK-RV32-NEXT: ret void983//984// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8m1(985// CHECK-RV64-NEXT: entry:986// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i8.i8.i64(i64 3, i64 31, <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])987// CHECK-RV64-NEXT: ret void988//989void test_sf_vc_xv_se_u8m1(vuint8m1_t vs2, uint8_t rs1, size_t vl) {990 __riscv_sf_vc_xv_se_u8m1(p27_26, p11_7, vs2, rs1, vl);991}992 993// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8m2(994// CHECK-RV32-NEXT: entry:995// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv16i8.i8.i32(i32 3, i32 31, <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])996// CHECK-RV32-NEXT: ret void997//998// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8m2(999// CHECK-RV64-NEXT: entry:1000// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv16i8.i8.i64(i64 3, i64 31, <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1001// CHECK-RV64-NEXT: ret void1002//1003void test_sf_vc_xv_se_u8m2(vuint8m2_t vs2, uint8_t rs1, size_t vl) {1004 __riscv_sf_vc_xv_se_u8m2(p27_26, p11_7, vs2, rs1, vl);1005}1006 1007// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8m4(1008// CHECK-RV32-NEXT: entry:1009// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv32i8.i8.i32(i32 3, i32 31, <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1010// CHECK-RV32-NEXT: ret void1011//1012// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8m4(1013// CHECK-RV64-NEXT: entry:1014// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv32i8.i8.i64(i64 3, i64 31, <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1015// CHECK-RV64-NEXT: ret void1016//1017void test_sf_vc_xv_se_u8m4(vuint8m4_t vs2, uint8_t rs1, size_t vl) {1018 __riscv_sf_vc_xv_se_u8m4(p27_26, p11_7, vs2, rs1, vl);1019}1020 1021// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8m8(1022// CHECK-RV32-NEXT: entry:1023// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv64i8.i8.i32(i32 3, i32 31, <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1024// CHECK-RV32-NEXT: ret void1025//1026// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8m8(1027// CHECK-RV64-NEXT: entry:1028// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv64i8.i8.i64(i64 3, i64 31, <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1029// CHECK-RV64-NEXT: ret void1030//1031void test_sf_vc_xv_se_u8m8(vuint8m8_t vs2, uint8_t rs1, size_t vl) {1032 __riscv_sf_vc_xv_se_u8m8(p27_26, p11_7, vs2, rs1, vl);1033}1034 1035// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16mf4(1036// CHECK-RV32-NEXT: entry:1037// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv1i16.i16.i32(i32 3, i32 31, <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1038// CHECK-RV32-NEXT: ret void1039//1040// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16mf4(1041// CHECK-RV64-NEXT: entry:1042// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i16.i16.i64(i64 3, i64 31, <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1043// CHECK-RV64-NEXT: ret void1044//1045void test_sf_vc_xv_se_u16mf4(vuint16mf4_t vs2, uint16_t rs1, size_t vl) {1046 __riscv_sf_vc_xv_se_u16mf4(p27_26, p11_7, vs2, rs1, vl);1047}1048 1049// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16mf2(1050// CHECK-RV32-NEXT: entry:1051// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv2i16.i16.i32(i32 3, i32 31, <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1052// CHECK-RV32-NEXT: ret void1053//1054// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16mf2(1055// CHECK-RV64-NEXT: entry:1056// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i16.i16.i64(i64 3, i64 31, <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1057// CHECK-RV64-NEXT: ret void1058//1059void test_sf_vc_xv_se_u16mf2(vuint16mf2_t vs2, uint16_t rs1, size_t vl) {1060 __riscv_sf_vc_xv_se_u16mf2(p27_26, p11_7, vs2, rs1, vl);1061}1062 1063// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16m1(1064// CHECK-RV32-NEXT: entry:1065// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv4i16.i16.i32(i32 3, i32 31, <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1066// CHECK-RV32-NEXT: ret void1067//1068// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16m1(1069// CHECK-RV64-NEXT: entry:1070// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i16.i16.i64(i64 3, i64 31, <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1071// CHECK-RV64-NEXT: ret void1072//1073void test_sf_vc_xv_se_u16m1(vuint16m1_t vs2, uint16_t rs1, size_t vl) {1074 __riscv_sf_vc_xv_se_u16m1(p27_26, p11_7, vs2, rs1, vl);1075}1076 1077// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16m2(1078// CHECK-RV32-NEXT: entry:1079// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv8i16.i16.i32(i32 3, i32 31, <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1080// CHECK-RV32-NEXT: ret void1081//1082// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16m2(1083// CHECK-RV64-NEXT: entry:1084// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i16.i16.i64(i64 3, i64 31, <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1085// CHECK-RV64-NEXT: ret void1086//1087void test_sf_vc_xv_se_u16m2(vuint16m2_t vs2, uint16_t rs1, size_t vl) {1088 __riscv_sf_vc_xv_se_u16m2(p27_26, p11_7, vs2, rs1, vl);1089}1090 1091// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16m4(1092// CHECK-RV32-NEXT: entry:1093// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv16i16.i16.i32(i32 3, i32 31, <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1094// CHECK-RV32-NEXT: ret void1095//1096// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16m4(1097// CHECK-RV64-NEXT: entry:1098// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv16i16.i16.i64(i64 3, i64 31, <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1099// CHECK-RV64-NEXT: ret void1100//1101void test_sf_vc_xv_se_u16m4(vuint16m4_t vs2, uint16_t rs1, size_t vl) {1102 __riscv_sf_vc_xv_se_u16m4(p27_26, p11_7, vs2, rs1, vl);1103}1104 1105// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16m8(1106// CHECK-RV32-NEXT: entry:1107// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv32i16.i16.i32(i32 3, i32 31, <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1108// CHECK-RV32-NEXT: ret void1109//1110// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16m8(1111// CHECK-RV64-NEXT: entry:1112// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv32i16.i16.i64(i64 3, i64 31, <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1113// CHECK-RV64-NEXT: ret void1114//1115void test_sf_vc_xv_se_u16m8(vuint16m8_t vs2, uint16_t rs1, size_t vl) {1116 __riscv_sf_vc_xv_se_u16m8(p27_26, p11_7, vs2, rs1, vl);1117}1118 1119// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u32mf2(1120// CHECK-RV32-NEXT: entry:1121// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv1i32.i32.i32(i32 3, i32 31, <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1122// CHECK-RV32-NEXT: ret void1123//1124// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u32mf2(1125// CHECK-RV64-NEXT: entry:1126// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i32.i32.i64(i64 3, i64 31, <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1127// CHECK-RV64-NEXT: ret void1128//1129void test_sf_vc_xv_se_u32mf2(vuint32mf2_t vs2, uint32_t rs1, size_t vl) {1130 __riscv_sf_vc_xv_se_u32mf2(p27_26, p11_7, vs2, rs1, vl);1131}1132 1133// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u32m1(1134// CHECK-RV32-NEXT: entry:1135// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv2i32.i32.i32(i32 3, i32 31, <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1136// CHECK-RV32-NEXT: ret void1137//1138// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u32m1(1139// CHECK-RV64-NEXT: entry:1140// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i32.i32.i64(i64 3, i64 31, <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1141// CHECK-RV64-NEXT: ret void1142//1143void test_sf_vc_xv_se_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {1144 __riscv_sf_vc_xv_se_u32m1(p27_26, p11_7, vs2, rs1, vl);1145}1146 1147// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u32m2(1148// CHECK-RV32-NEXT: entry:1149// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv4i32.i32.i32(i32 3, i32 31, <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1150// CHECK-RV32-NEXT: ret void1151//1152// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u32m2(1153// CHECK-RV64-NEXT: entry:1154// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i32.i32.i64(i64 3, i64 31, <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1155// CHECK-RV64-NEXT: ret void1156//1157void test_sf_vc_xv_se_u32m2(vuint32m2_t vs2, uint32_t rs1, size_t vl) {1158 __riscv_sf_vc_xv_se_u32m2(p27_26, p11_7, vs2, rs1, vl);1159}1160 1161// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u32m4(1162// CHECK-RV32-NEXT: entry:1163// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv8i32.i32.i32(i32 3, i32 31, <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1164// CHECK-RV32-NEXT: ret void1165//1166// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u32m4(1167// CHECK-RV64-NEXT: entry:1168// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i32.i32.i64(i64 3, i64 31, <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1169// CHECK-RV64-NEXT: ret void1170//1171void test_sf_vc_xv_se_u32m4(vuint32m4_t vs2, uint32_t rs1, size_t vl) {1172 __riscv_sf_vc_xv_se_u32m4(p27_26, p11_7, vs2, rs1, vl);1173}1174 1175// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u32m8(1176// CHECK-RV32-NEXT: entry:1177// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv16i32.i32.i32(i32 3, i32 31, <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1178// CHECK-RV32-NEXT: ret void1179//1180// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u32m8(1181// CHECK-RV64-NEXT: entry:1182// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv16i32.i32.i64(i64 3, i64 31, <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1183// CHECK-RV64-NEXT: ret void1184//1185void test_sf_vc_xv_se_u32m8(vuint32m8_t vs2, uint32_t rs1, size_t vl) {1186 __riscv_sf_vc_xv_se_u32m8(p27_26, p11_7, vs2, rs1, vl);1187}1188 1189// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8mf8(1190// CHECK-RV32-NEXT: entry:1191// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv1i8.i32.nxv1i8.i8.i32(i32 3, <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1192// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]1193//1194// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8mf8(1195// CHECK-RV64-NEXT: entry:1196// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv1i8.i64.nxv1i8.i8.i64(i64 3, <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1197// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1198//1199vuint8mf8_t test_sf_vc_v_xv_se_u8mf8(vuint8mf8_t vs2, uint8_t rs1, size_t vl) {1200 return __riscv_sf_vc_v_xv_se_u8mf8(p27_26, vs2, rs1, vl);1201}1202 1203// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8mf4(1204// CHECK-RV32-NEXT: entry:1205// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv2i8.i32.nxv2i8.i8.i32(i32 3, <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1206// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]1207//1208// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8mf4(1209// CHECK-RV64-NEXT: entry:1210// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv2i8.i64.nxv2i8.i8.i64(i64 3, <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1211// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1212//1213vuint8mf4_t test_sf_vc_v_xv_se_u8mf4(vuint8mf4_t vs2, uint8_t rs1, size_t vl) {1214 return __riscv_sf_vc_v_xv_se_u8mf4(p27_26, vs2, rs1, vl);1215}1216 1217// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8mf2(1218// CHECK-RV32-NEXT: entry:1219// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv4i8.i32.nxv4i8.i8.i32(i32 3, <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1220// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]1221//1222// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8mf2(1223// CHECK-RV64-NEXT: entry:1224// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv4i8.i64.nxv4i8.i8.i64(i64 3, <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1225// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1226//1227vuint8mf2_t test_sf_vc_v_xv_se_u8mf2(vuint8mf2_t vs2, uint8_t rs1, size_t vl) {1228 return __riscv_sf_vc_v_xv_se_u8mf2(p27_26, vs2, rs1, vl);1229}1230 1231// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8m1(1232// CHECK-RV32-NEXT: entry:1233// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv8i8.i32.nxv8i8.i8.i32(i32 3, <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1234// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]1235//1236// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8m1(1237// CHECK-RV64-NEXT: entry:1238// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv8i8.i64.nxv8i8.i8.i64(i64 3, <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1239// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1240//1241vuint8m1_t test_sf_vc_v_xv_se_u8m1(vuint8m1_t vs2, uint8_t rs1, size_t vl) {1242 return __riscv_sf_vc_v_xv_se_u8m1(p27_26, vs2, rs1, vl);1243}1244 1245// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8m2(1246// CHECK-RV32-NEXT: entry:1247// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv16i8.i32.nxv16i8.i8.i32(i32 3, <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1248// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]1249//1250// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8m2(1251// CHECK-RV64-NEXT: entry:1252// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv16i8.i64.nxv16i8.i8.i64(i64 3, <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1253// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1254//1255vuint8m2_t test_sf_vc_v_xv_se_u8m2(vuint8m2_t vs2, uint8_t rs1, size_t vl) {1256 return __riscv_sf_vc_v_xv_se_u8m2(p27_26, vs2, rs1, vl);1257}1258 1259// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8m4(1260// CHECK-RV32-NEXT: entry:1261// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv32i8.i32.nxv32i8.i8.i32(i32 3, <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1262// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]1263//1264// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8m4(1265// CHECK-RV64-NEXT: entry:1266// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv32i8.i64.nxv32i8.i8.i64(i64 3, <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1267// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1268//1269vuint8m4_t test_sf_vc_v_xv_se_u8m4(vuint8m4_t vs2, uint8_t rs1, size_t vl) {1270 return __riscv_sf_vc_v_xv_se_u8m4(p27_26, vs2, rs1, vl);1271}1272 1273// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8m8(1274// CHECK-RV32-NEXT: entry:1275// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv64i8.i32.nxv64i8.i8.i32(i32 3, <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1276// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]1277//1278// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8m8(1279// CHECK-RV64-NEXT: entry:1280// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv64i8.i64.nxv64i8.i8.i64(i64 3, <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1281// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1282//1283vuint8m8_t test_sf_vc_v_xv_se_u8m8(vuint8m8_t vs2, uint8_t rs1, size_t vl) {1284 return __riscv_sf_vc_v_xv_se_u8m8(p27_26, vs2, rs1, vl);1285}1286 1287// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16mf4(1288// CHECK-RV32-NEXT: entry:1289// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv1i16.i32.nxv1i16.i16.i32(i32 3, <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1290// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]1291//1292// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16mf4(1293// CHECK-RV64-NEXT: entry:1294// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv1i16.i64.nxv1i16.i16.i64(i64 3, <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1295// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1296//1297vuint16mf4_t test_sf_vc_v_xv_se_u16mf4(vuint16mf4_t vs2, uint16_t rs1, size_t vl) {1298 return __riscv_sf_vc_v_xv_se_u16mf4(p27_26, vs2, rs1, vl);1299}1300 1301// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16mf2(1302// CHECK-RV32-NEXT: entry:1303// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv2i16.i32.nxv2i16.i16.i32(i32 3, <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1304// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]1305//1306// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16mf2(1307// CHECK-RV64-NEXT: entry:1308// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv2i16.i64.nxv2i16.i16.i64(i64 3, <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1309// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1310//1311vuint16mf2_t test_sf_vc_v_xv_se_u16mf2(vuint16mf2_t vs2, uint16_t rs1, size_t vl) {1312 return __riscv_sf_vc_v_xv_se_u16mf2(p27_26, vs2, rs1, vl);1313}1314 1315// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16m1(1316// CHECK-RV32-NEXT: entry:1317// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv4i16.i32.nxv4i16.i16.i32(i32 3, <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1318// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]1319//1320// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16m1(1321// CHECK-RV64-NEXT: entry:1322// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv4i16.i64.nxv4i16.i16.i64(i64 3, <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1323// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1324//1325vuint16m1_t test_sf_vc_v_xv_se_u16m1(vuint16m1_t vs2, uint16_t rs1, size_t vl) {1326 return __riscv_sf_vc_v_xv_se_u16m1(p27_26, vs2, rs1, vl);1327}1328 1329// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16m2(1330// CHECK-RV32-NEXT: entry:1331// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv8i16.i32.nxv8i16.i16.i32(i32 3, <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1332// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]1333//1334// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16m2(1335// CHECK-RV64-NEXT: entry:1336// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv8i16.i64.nxv8i16.i16.i64(i64 3, <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1337// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1338//1339vuint16m2_t test_sf_vc_v_xv_se_u16m2(vuint16m2_t vs2, uint16_t rs1, size_t vl) {1340 return __riscv_sf_vc_v_xv_se_u16m2(p27_26, vs2, rs1, vl);1341}1342 1343// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16m4(1344// CHECK-RV32-NEXT: entry:1345// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv16i16.i32.nxv16i16.i16.i32(i32 3, <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1346// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]1347//1348// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16m4(1349// CHECK-RV64-NEXT: entry:1350// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv16i16.i64.nxv16i16.i16.i64(i64 3, <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1351// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1352//1353vuint16m4_t test_sf_vc_v_xv_se_u16m4(vuint16m4_t vs2, uint16_t rs1, size_t vl) {1354 return __riscv_sf_vc_v_xv_se_u16m4(p27_26, vs2, rs1, vl);1355}1356 1357// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16m8(1358// CHECK-RV32-NEXT: entry:1359// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv32i16.i32.nxv32i16.i16.i32(i32 3, <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1360// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]1361//1362// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16m8(1363// CHECK-RV64-NEXT: entry:1364// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv32i16.i64.nxv32i16.i16.i64(i64 3, <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1365// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1366//1367vuint16m8_t test_sf_vc_v_xv_se_u16m8(vuint16m8_t vs2, uint16_t rs1, size_t vl) {1368 return __riscv_sf_vc_v_xv_se_u16m8(p27_26, vs2, rs1, vl);1369}1370 1371// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u32mf2(1372// CHECK-RV32-NEXT: entry:1373// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv1i32.i32.nxv1i32.i32.i32(i32 3, <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1374// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]1375//1376// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u32mf2(1377// CHECK-RV64-NEXT: entry:1378// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv1i32.i64.nxv1i32.i32.i64(i64 3, <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1379// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1380//1381vuint32mf2_t test_sf_vc_v_xv_se_u32mf2(vuint32mf2_t vs2, uint32_t rs1, size_t vl) {1382 return __riscv_sf_vc_v_xv_se_u32mf2(p27_26, vs2, rs1, vl);1383}1384 1385// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u32m1(1386// CHECK-RV32-NEXT: entry:1387// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv2i32.i32.nxv2i32.i32.i32(i32 3, <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1388// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]1389//1390// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u32m1(1391// CHECK-RV64-NEXT: entry:1392// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv2i32.i64.nxv2i32.i32.i64(i64 3, <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1393// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1394//1395vuint32m1_t test_sf_vc_v_xv_se_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {1396 return __riscv_sf_vc_v_xv_se_u32m1(p27_26, vs2, rs1, vl);1397}1398 1399// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u32m2(1400// CHECK-RV32-NEXT: entry:1401// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv4i32.i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1402// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]1403//1404// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u32m2(1405// CHECK-RV64-NEXT: entry:1406// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv4i32.i64.nxv4i32.i32.i64(i64 3, <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1407// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1408//1409vuint32m2_t test_sf_vc_v_xv_se_u32m2(vuint32m2_t vs2, uint32_t rs1, size_t vl) {1410 return __riscv_sf_vc_v_xv_se_u32m2(p27_26, vs2, rs1, vl);1411}1412 1413// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u32m4(1414// CHECK-RV32-NEXT: entry:1415// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv8i32.i32.nxv8i32.i32.i32(i32 3, <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1416// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]1417//1418// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u32m4(1419// CHECK-RV64-NEXT: entry:1420// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv8i32.i64.nxv8i32.i32.i64(i64 3, <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1421// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1422//1423vuint32m4_t test_sf_vc_v_xv_se_u32m4(vuint32m4_t vs2, uint32_t rs1, size_t vl) {1424 return __riscv_sf_vc_v_xv_se_u32m4(p27_26, vs2, rs1, vl);1425}1426 1427// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u32m8(1428// CHECK-RV32-NEXT: entry:1429// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv16i32.i32.nxv16i32.i32.i32(i32 3, <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1430// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]1431//1432// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u32m8(1433// CHECK-RV64-NEXT: entry:1434// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv16i32.i64.nxv16i32.i32.i64(i64 3, <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1435// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1436//1437vuint32m8_t test_sf_vc_v_xv_se_u32m8(vuint32m8_t vs2, uint32_t rs1, size_t vl) {1438 return __riscv_sf_vc_v_xv_se_u32m8(p27_26, vs2, rs1, vl);1439}1440 1441// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8mf8(1442// CHECK-RV32-NEXT: entry:1443// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xv.nxv1i8.i32.nxv1i8.i8.i32(i32 3, <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1444// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]1445//1446// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8mf8(1447// CHECK-RV64-NEXT: entry:1448// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xv.nxv1i8.i64.nxv1i8.i8.i64(i64 3, <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1449// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1450//1451vuint8mf8_t test_sf_vc_v_xv_u8mf8(vuint8mf8_t vs2, uint8_t rs1, size_t vl) {1452 return __riscv_sf_vc_v_xv_u8mf8(p27_26, vs2, rs1, vl);1453}1454 1455// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8mf4(1456// CHECK-RV32-NEXT: entry:1457// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xv.nxv2i8.i32.nxv2i8.i8.i32(i32 3, <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1458// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]1459//1460// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8mf4(1461// CHECK-RV64-NEXT: entry:1462// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xv.nxv2i8.i64.nxv2i8.i8.i64(i64 3, <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1463// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1464//1465vuint8mf4_t test_sf_vc_v_xv_u8mf4(vuint8mf4_t vs2, uint8_t rs1, size_t vl) {1466 return __riscv_sf_vc_v_xv_u8mf4(p27_26, vs2, rs1, vl);1467}1468 1469// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8mf2(1470// CHECK-RV32-NEXT: entry:1471// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xv.nxv4i8.i32.nxv4i8.i8.i32(i32 3, <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1472// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]1473//1474// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8mf2(1475// CHECK-RV64-NEXT: entry:1476// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xv.nxv4i8.i64.nxv4i8.i8.i64(i64 3, <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1477// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1478//1479vuint8mf2_t test_sf_vc_v_xv_u8mf2(vuint8mf2_t vs2, uint8_t rs1, size_t vl) {1480 return __riscv_sf_vc_v_xv_u8mf2(p27_26, vs2, rs1, vl);1481}1482 1483// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8m1(1484// CHECK-RV32-NEXT: entry:1485// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xv.nxv8i8.i32.nxv8i8.i8.i32(i32 3, <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1486// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]1487//1488// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8m1(1489// CHECK-RV64-NEXT: entry:1490// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xv.nxv8i8.i64.nxv8i8.i8.i64(i64 3, <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1491// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1492//1493vuint8m1_t test_sf_vc_v_xv_u8m1(vuint8m1_t vs2, uint8_t rs1, size_t vl) {1494 return __riscv_sf_vc_v_xv_u8m1(p27_26, vs2, rs1, vl);1495}1496 1497// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8m2(1498// CHECK-RV32-NEXT: entry:1499// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xv.nxv16i8.i32.nxv16i8.i8.i32(i32 3, <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1500// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]1501//1502// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8m2(1503// CHECK-RV64-NEXT: entry:1504// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xv.nxv16i8.i64.nxv16i8.i8.i64(i64 3, <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1505// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1506//1507vuint8m2_t test_sf_vc_v_xv_u8m2(vuint8m2_t vs2, uint8_t rs1, size_t vl) {1508 return __riscv_sf_vc_v_xv_u8m2(p27_26, vs2, rs1, vl);1509}1510 1511// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8m4(1512// CHECK-RV32-NEXT: entry:1513// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xv.nxv32i8.i32.nxv32i8.i8.i32(i32 3, <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1514// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]1515//1516// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8m4(1517// CHECK-RV64-NEXT: entry:1518// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xv.nxv32i8.i64.nxv32i8.i8.i64(i64 3, <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1519// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1520//1521vuint8m4_t test_sf_vc_v_xv_u8m4(vuint8m4_t vs2, uint8_t rs1, size_t vl) {1522 return __riscv_sf_vc_v_xv_u8m4(p27_26, vs2, rs1, vl);1523}1524 1525// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8m8(1526// CHECK-RV32-NEXT: entry:1527// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xv.nxv64i8.i32.nxv64i8.i8.i32(i32 3, <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1528// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]1529//1530// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8m8(1531// CHECK-RV64-NEXT: entry:1532// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xv.nxv64i8.i64.nxv64i8.i8.i64(i64 3, <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1533// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1534//1535vuint8m8_t test_sf_vc_v_xv_u8m8(vuint8m8_t vs2, uint8_t rs1, size_t vl) {1536 return __riscv_sf_vc_v_xv_u8m8(p27_26, vs2, rs1, vl);1537}1538 1539// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16mf4(1540// CHECK-RV32-NEXT: entry:1541// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xv.nxv1i16.i32.nxv1i16.i16.i32(i32 3, <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1542// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]1543//1544// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16mf4(1545// CHECK-RV64-NEXT: entry:1546// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xv.nxv1i16.i64.nxv1i16.i16.i64(i64 3, <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1547// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1548//1549vuint16mf4_t test_sf_vc_v_xv_u16mf4(vuint16mf4_t vs2, uint16_t rs1, size_t vl) {1550 return __riscv_sf_vc_v_xv_u16mf4(p27_26, vs2, rs1, vl);1551}1552 1553// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16mf2(1554// CHECK-RV32-NEXT: entry:1555// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xv.nxv2i16.i32.nxv2i16.i16.i32(i32 3, <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1556// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]1557//1558// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16mf2(1559// CHECK-RV64-NEXT: entry:1560// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xv.nxv2i16.i64.nxv2i16.i16.i64(i64 3, <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1561// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1562//1563vuint16mf2_t test_sf_vc_v_xv_u16mf2(vuint16mf2_t vs2, uint16_t rs1, size_t vl) {1564 return __riscv_sf_vc_v_xv_u16mf2(p27_26, vs2, rs1, vl);1565}1566 1567// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16m1(1568// CHECK-RV32-NEXT: entry:1569// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xv.nxv4i16.i32.nxv4i16.i16.i32(i32 3, <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1570// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]1571//1572// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16m1(1573// CHECK-RV64-NEXT: entry:1574// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xv.nxv4i16.i64.nxv4i16.i16.i64(i64 3, <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1575// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1576//1577vuint16m1_t test_sf_vc_v_xv_u16m1(vuint16m1_t vs2, uint16_t rs1, size_t vl) {1578 return __riscv_sf_vc_v_xv_u16m1(p27_26, vs2, rs1, vl);1579}1580 1581// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16m2(1582// CHECK-RV32-NEXT: entry:1583// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xv.nxv8i16.i32.nxv8i16.i16.i32(i32 3, <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1584// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]1585//1586// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16m2(1587// CHECK-RV64-NEXT: entry:1588// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xv.nxv8i16.i64.nxv8i16.i16.i64(i64 3, <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1589// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1590//1591vuint16m2_t test_sf_vc_v_xv_u16m2(vuint16m2_t vs2, uint16_t rs1, size_t vl) {1592 return __riscv_sf_vc_v_xv_u16m2(p27_26, vs2, rs1, vl);1593}1594 1595// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16m4(1596// CHECK-RV32-NEXT: entry:1597// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xv.nxv16i16.i32.nxv16i16.i16.i32(i32 3, <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1598// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]1599//1600// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16m4(1601// CHECK-RV64-NEXT: entry:1602// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xv.nxv16i16.i64.nxv16i16.i16.i64(i64 3, <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1603// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1604//1605vuint16m4_t test_sf_vc_v_xv_u16m4(vuint16m4_t vs2, uint16_t rs1, size_t vl) {1606 return __riscv_sf_vc_v_xv_u16m4(p27_26, vs2, rs1, vl);1607}1608 1609// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16m8(1610// CHECK-RV32-NEXT: entry:1611// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xv.nxv32i16.i32.nxv32i16.i16.i32(i32 3, <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1612// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]1613//1614// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16m8(1615// CHECK-RV64-NEXT: entry:1616// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xv.nxv32i16.i64.nxv32i16.i16.i64(i64 3, <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1617// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1618//1619vuint16m8_t test_sf_vc_v_xv_u16m8(vuint16m8_t vs2, uint16_t rs1, size_t vl) {1620 return __riscv_sf_vc_v_xv_u16m8(p27_26, vs2, rs1, vl);1621}1622 1623// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u32mf2(1624// CHECK-RV32-NEXT: entry:1625// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xv.nxv1i32.i32.nxv1i32.i32.i32(i32 3, <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1626// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]1627//1628// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u32mf2(1629// CHECK-RV64-NEXT: entry:1630// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xv.nxv1i32.i64.nxv1i32.i32.i64(i64 3, <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1631// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1632//1633vuint32mf2_t test_sf_vc_v_xv_u32mf2(vuint32mf2_t vs2, uint32_t rs1, size_t vl) {1634 return __riscv_sf_vc_v_xv_u32mf2(p27_26, vs2, rs1, vl);1635}1636 1637// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u32m1(1638// CHECK-RV32-NEXT: entry:1639// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xv.nxv2i32.i32.nxv2i32.i32.i32(i32 3, <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1640// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]1641//1642// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u32m1(1643// CHECK-RV64-NEXT: entry:1644// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xv.nxv2i32.i64.nxv2i32.i32.i64(i64 3, <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1645// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1646//1647vuint32m1_t test_sf_vc_v_xv_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {1648 return __riscv_sf_vc_v_xv_u32m1(p27_26, vs2, rs1, vl);1649}1650 1651// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u32m2(1652// CHECK-RV32-NEXT: entry:1653// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xv.nxv4i32.i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1654// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]1655//1656// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u32m2(1657// CHECK-RV64-NEXT: entry:1658// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xv.nxv4i32.i64.nxv4i32.i32.i64(i64 3, <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1659// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1660//1661vuint32m2_t test_sf_vc_v_xv_u32m2(vuint32m2_t vs2, uint32_t rs1, size_t vl) {1662 return __riscv_sf_vc_v_xv_u32m2(p27_26, vs2, rs1, vl);1663}1664 1665// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u32m4(1666// CHECK-RV32-NEXT: entry:1667// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xv.nxv8i32.i32.nxv8i32.i32.i32(i32 3, <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1668// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]1669//1670// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u32m4(1671// CHECK-RV64-NEXT: entry:1672// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xv.nxv8i32.i64.nxv8i32.i32.i64(i64 3, <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1673// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1674//1675vuint32m4_t test_sf_vc_v_xv_u32m4(vuint32m4_t vs2, uint32_t rs1, size_t vl) {1676 return __riscv_sf_vc_v_xv_u32m4(p27_26, vs2, rs1, vl);1677}1678 1679// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u32m8(1680// CHECK-RV32-NEXT: entry:1681// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xv.nxv16i32.i32.nxv16i32.i32.i32(i32 3, <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1682// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]1683//1684// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u32m8(1685// CHECK-RV64-NEXT: entry:1686// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xv.nxv16i32.i64.nxv16i32.i32.i64(i64 3, <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1687// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1688//1689vuint32m8_t test_sf_vc_v_xv_u32m8(vuint32m8_t vs2, uint32_t rs1, size_t vl) {1690 return __riscv_sf_vc_v_xv_u32m8(p27_26, vs2, rs1, vl);1691}1692 1693// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8mf8(1694// CHECK-RV32-NEXT: entry:1695// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv1i8.i32.i32(i32 3, i32 31, <vscale x 1 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1696// CHECK-RV32-NEXT: ret void1697//1698// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8mf8(1699// CHECK-RV64-NEXT: entry:1700// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv1i8.i64.i64(i64 3, i64 31, <vscale x 1 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1701// CHECK-RV64-NEXT: ret void1702//1703void test_sf_vc_iv_se_u8mf8(vuint8mf8_t vs2, size_t vl) {1704 __riscv_sf_vc_iv_se_u8mf8(p27_26, p11_7, vs2, simm5, vl);1705}1706 1707// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8mf4(1708// CHECK-RV32-NEXT: entry:1709// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv2i8.i32.i32(i32 3, i32 31, <vscale x 2 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1710// CHECK-RV32-NEXT: ret void1711//1712// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8mf4(1713// CHECK-RV64-NEXT: entry:1714// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv2i8.i64.i64(i64 3, i64 31, <vscale x 2 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1715// CHECK-RV64-NEXT: ret void1716//1717void test_sf_vc_iv_se_u8mf4(vuint8mf4_t vs2, size_t vl) {1718 __riscv_sf_vc_iv_se_u8mf4(p27_26, p11_7, vs2, simm5, vl);1719}1720 1721// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8mf2(1722// CHECK-RV32-NEXT: entry:1723// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv4i8.i32.i32(i32 3, i32 31, <vscale x 4 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1724// CHECK-RV32-NEXT: ret void1725//1726// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8mf2(1727// CHECK-RV64-NEXT: entry:1728// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv4i8.i64.i64(i64 3, i64 31, <vscale x 4 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1729// CHECK-RV64-NEXT: ret void1730//1731void test_sf_vc_iv_se_u8mf2(vuint8mf2_t vs2, size_t vl) {1732 __riscv_sf_vc_iv_se_u8mf2(p27_26, p11_7, vs2, simm5, vl);1733}1734 1735// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8m1(1736// CHECK-RV32-NEXT: entry:1737// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv8i8.i32.i32(i32 3, i32 31, <vscale x 8 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1738// CHECK-RV32-NEXT: ret void1739//1740// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8m1(1741// CHECK-RV64-NEXT: entry:1742// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv8i8.i64.i64(i64 3, i64 31, <vscale x 8 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1743// CHECK-RV64-NEXT: ret void1744//1745void test_sf_vc_iv_se_u8m1(vuint8m1_t vs2, size_t vl) {1746 __riscv_sf_vc_iv_se_u8m1(p27_26, p11_7, vs2, simm5, vl);1747}1748 1749// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8m2(1750// CHECK-RV32-NEXT: entry:1751// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv16i8.i32.i32(i32 3, i32 31, <vscale x 16 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1752// CHECK-RV32-NEXT: ret void1753//1754// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8m2(1755// CHECK-RV64-NEXT: entry:1756// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv16i8.i64.i64(i64 3, i64 31, <vscale x 16 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1757// CHECK-RV64-NEXT: ret void1758//1759void test_sf_vc_iv_se_u8m2(vuint8m2_t vs2, size_t vl) {1760 __riscv_sf_vc_iv_se_u8m2(p27_26, p11_7, vs2, simm5, vl);1761}1762 1763// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8m4(1764// CHECK-RV32-NEXT: entry:1765// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv32i8.i32.i32(i32 3, i32 31, <vscale x 32 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1766// CHECK-RV32-NEXT: ret void1767//1768// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8m4(1769// CHECK-RV64-NEXT: entry:1770// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv32i8.i64.i64(i64 3, i64 31, <vscale x 32 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1771// CHECK-RV64-NEXT: ret void1772//1773void test_sf_vc_iv_se_u8m4(vuint8m4_t vs2, size_t vl) {1774 __riscv_sf_vc_iv_se_u8m4(p27_26, p11_7, vs2, simm5, vl);1775}1776 1777// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8m8(1778// CHECK-RV32-NEXT: entry:1779// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv64i8.i32.i32(i32 3, i32 31, <vscale x 64 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1780// CHECK-RV32-NEXT: ret void1781//1782// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8m8(1783// CHECK-RV64-NEXT: entry:1784// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv64i8.i64.i64(i64 3, i64 31, <vscale x 64 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1785// CHECK-RV64-NEXT: ret void1786//1787void test_sf_vc_iv_se_u8m8(vuint8m8_t vs2, size_t vl) {1788 __riscv_sf_vc_iv_se_u8m8(p27_26, p11_7, vs2, simm5, vl);1789}1790 1791// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16mf4(1792// CHECK-RV32-NEXT: entry:1793// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv1i16.i32.i32(i32 3, i32 31, <vscale x 1 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1794// CHECK-RV32-NEXT: ret void1795//1796// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16mf4(1797// CHECK-RV64-NEXT: entry:1798// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv1i16.i64.i64(i64 3, i64 31, <vscale x 1 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1799// CHECK-RV64-NEXT: ret void1800//1801void test_sf_vc_iv_se_u16mf4(vuint16mf4_t vs2, size_t vl) {1802 __riscv_sf_vc_iv_se_u16mf4(p27_26, p11_7, vs2, simm5, vl);1803}1804 1805// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16mf2(1806// CHECK-RV32-NEXT: entry:1807// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv2i16.i32.i32(i32 3, i32 31, <vscale x 2 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1808// CHECK-RV32-NEXT: ret void1809//1810// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16mf2(1811// CHECK-RV64-NEXT: entry:1812// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv2i16.i64.i64(i64 3, i64 31, <vscale x 2 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1813// CHECK-RV64-NEXT: ret void1814//1815void test_sf_vc_iv_se_u16mf2(vuint16mf2_t vs2, size_t vl) {1816 __riscv_sf_vc_iv_se_u16mf2(p27_26, p11_7, vs2, simm5, vl);1817}1818 1819// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16m1(1820// CHECK-RV32-NEXT: entry:1821// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv4i16.i32.i32(i32 3, i32 31, <vscale x 4 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1822// CHECK-RV32-NEXT: ret void1823//1824// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16m1(1825// CHECK-RV64-NEXT: entry:1826// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv4i16.i64.i64(i64 3, i64 31, <vscale x 4 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1827// CHECK-RV64-NEXT: ret void1828//1829void test_sf_vc_iv_se_u16m1(vuint16m1_t vs2, size_t vl) {1830 __riscv_sf_vc_iv_se_u16m1(p27_26, p11_7, vs2, simm5, vl);1831}1832 1833// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16m2(1834// CHECK-RV32-NEXT: entry:1835// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv8i16.i32.i32(i32 3, i32 31, <vscale x 8 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1836// CHECK-RV32-NEXT: ret void1837//1838// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16m2(1839// CHECK-RV64-NEXT: entry:1840// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv8i16.i64.i64(i64 3, i64 31, <vscale x 8 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1841// CHECK-RV64-NEXT: ret void1842//1843void test_sf_vc_iv_se_u16m2(vuint16m2_t vs2, size_t vl) {1844 __riscv_sf_vc_iv_se_u16m2(p27_26, p11_7, vs2, simm5, vl);1845}1846 1847// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16m4(1848// CHECK-RV32-NEXT: entry:1849// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv16i16.i32.i32(i32 3, i32 31, <vscale x 16 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1850// CHECK-RV32-NEXT: ret void1851//1852// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16m4(1853// CHECK-RV64-NEXT: entry:1854// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv16i16.i64.i64(i64 3, i64 31, <vscale x 16 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1855// CHECK-RV64-NEXT: ret void1856//1857void test_sf_vc_iv_se_u16m4(vuint16m4_t vs2, size_t vl) {1858 __riscv_sf_vc_iv_se_u16m4(p27_26, p11_7, vs2, simm5, vl);1859}1860 1861// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16m8(1862// CHECK-RV32-NEXT: entry:1863// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv32i16.i32.i32(i32 3, i32 31, <vscale x 32 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1864// CHECK-RV32-NEXT: ret void1865//1866// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16m8(1867// CHECK-RV64-NEXT: entry:1868// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv32i16.i64.i64(i64 3, i64 31, <vscale x 32 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1869// CHECK-RV64-NEXT: ret void1870//1871void test_sf_vc_iv_se_u16m8(vuint16m8_t vs2, size_t vl) {1872 __riscv_sf_vc_iv_se_u16m8(p27_26, p11_7, vs2, simm5, vl);1873}1874 1875// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u32mf2(1876// CHECK-RV32-NEXT: entry:1877// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv1i32.i32.i32(i32 3, i32 31, <vscale x 1 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1878// CHECK-RV32-NEXT: ret void1879//1880// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u32mf2(1881// CHECK-RV64-NEXT: entry:1882// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv1i32.i64.i64(i64 3, i64 31, <vscale x 1 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1883// CHECK-RV64-NEXT: ret void1884//1885void test_sf_vc_iv_se_u32mf2(vuint32mf2_t vs2, size_t vl) {1886 __riscv_sf_vc_iv_se_u32mf2(p27_26, p11_7, vs2, simm5, vl);1887}1888 1889// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u32m1(1890// CHECK-RV32-NEXT: entry:1891// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv2i32.i32.i32(i32 3, i32 31, <vscale x 2 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1892// CHECK-RV32-NEXT: ret void1893//1894// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u32m1(1895// CHECK-RV64-NEXT: entry:1896// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv2i32.i64.i64(i64 3, i64 31, <vscale x 2 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1897// CHECK-RV64-NEXT: ret void1898//1899void test_sf_vc_iv_se_u32m1(vuint32m1_t vs2, size_t vl) {1900 __riscv_sf_vc_iv_se_u32m1(p27_26, p11_7, vs2, simm5, vl);1901}1902 1903// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u32m2(1904// CHECK-RV32-NEXT: entry:1905// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv4i32.i32.i32(i32 3, i32 31, <vscale x 4 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1906// CHECK-RV32-NEXT: ret void1907//1908// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u32m2(1909// CHECK-RV64-NEXT: entry:1910// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv4i32.i64.i64(i64 3, i64 31, <vscale x 4 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1911// CHECK-RV64-NEXT: ret void1912//1913void test_sf_vc_iv_se_u32m2(vuint32m2_t vs2, size_t vl) {1914 __riscv_sf_vc_iv_se_u32m2(p27_26, p11_7, vs2, simm5, vl);1915}1916 1917// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u32m4(1918// CHECK-RV32-NEXT: entry:1919// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv8i32.i32.i32(i32 3, i32 31, <vscale x 8 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1920// CHECK-RV32-NEXT: ret void1921//1922// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u32m4(1923// CHECK-RV64-NEXT: entry:1924// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv8i32.i64.i64(i64 3, i64 31, <vscale x 8 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1925// CHECK-RV64-NEXT: ret void1926//1927void test_sf_vc_iv_se_u32m4(vuint32m4_t vs2, size_t vl) {1928 __riscv_sf_vc_iv_se_u32m4(p27_26, p11_7, vs2, simm5, vl);1929}1930 1931// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u32m8(1932// CHECK-RV32-NEXT: entry:1933// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv16i32.i32.i32(i32 3, i32 31, <vscale x 16 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1934// CHECK-RV32-NEXT: ret void1935//1936// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u32m8(1937// CHECK-RV64-NEXT: entry:1938// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv16i32.i64.i64(i64 3, i64 31, <vscale x 16 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1939// CHECK-RV64-NEXT: ret void1940//1941void test_sf_vc_iv_se_u32m8(vuint32m8_t vs2, size_t vl) {1942 __riscv_sf_vc_iv_se_u32m8(p27_26, p11_7, vs2, simm5, vl);1943}1944 1945// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u64m1(1946// CHECK-RV32-NEXT: entry:1947// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv1i64.i32.i32(i32 3, i32 31, <vscale x 1 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1948// CHECK-RV32-NEXT: ret void1949//1950// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u64m1(1951// CHECK-RV64-NEXT: entry:1952// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, <vscale x 1 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1953// CHECK-RV64-NEXT: ret void1954//1955void test_sf_vc_iv_se_u64m1(vuint64m1_t vs2, size_t vl) {1956 __riscv_sf_vc_iv_se_u64m1(p27_26, p11_7, vs2, simm5, vl);1957}1958 1959// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u64m2(1960// CHECK-RV32-NEXT: entry:1961// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv2i64.i32.i32(i32 3, i32 31, <vscale x 2 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1962// CHECK-RV32-NEXT: ret void1963//1964// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u64m2(1965// CHECK-RV64-NEXT: entry:1966// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, <vscale x 2 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1967// CHECK-RV64-NEXT: ret void1968//1969void test_sf_vc_iv_se_u64m2(vuint64m2_t vs2, size_t vl) {1970 __riscv_sf_vc_iv_se_u64m2(p27_26, p11_7, vs2, simm5, vl);1971}1972 1973// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u64m4(1974// CHECK-RV32-NEXT: entry:1975// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv4i64.i32.i32(i32 3, i32 31, <vscale x 4 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1976// CHECK-RV32-NEXT: ret void1977//1978// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u64m4(1979// CHECK-RV64-NEXT: entry:1980// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, <vscale x 4 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1981// CHECK-RV64-NEXT: ret void1982//1983void test_sf_vc_iv_se_u64m4(vuint64m4_t vs2, size_t vl) {1984 __riscv_sf_vc_iv_se_u64m4(p27_26, p11_7, vs2, simm5, vl);1985}1986 1987// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u64m8(1988// CHECK-RV32-NEXT: entry:1989// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv8i64.i32.i32(i32 3, i32 31, <vscale x 8 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1990// CHECK-RV32-NEXT: ret void1991//1992// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u64m8(1993// CHECK-RV64-NEXT: entry:1994// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, <vscale x 8 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1995// CHECK-RV64-NEXT: ret void1996//1997void test_sf_vc_iv_se_u64m8(vuint64m8_t vs2, size_t vl) {1998 __riscv_sf_vc_iv_se_u64m8(p27_26, p11_7, vs2, simm5, vl);1999}2000 2001// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8mf8(2002// CHECK-RV32-NEXT: entry:2003// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv1i8.i32.nxv1i8.i32.i32(i32 3, <vscale x 1 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2004// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]2005//2006// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8mf8(2007// CHECK-RV64-NEXT: entry:2008// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv1i8.i64.nxv1i8.i64.i64(i64 3, <vscale x 1 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2009// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2010//2011vuint8mf8_t test_sf_vc_v_iv_se_u8mf8(vuint8mf8_t vs2, size_t vl) {2012 return __riscv_sf_vc_v_iv_se_u8mf8(p27_26, vs2, simm5, vl);2013}2014 2015// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8mf4(2016// CHECK-RV32-NEXT: entry:2017// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv2i8.i32.nxv2i8.i32.i32(i32 3, <vscale x 2 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2018// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]2019//2020// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8mf4(2021// CHECK-RV64-NEXT: entry:2022// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv2i8.i64.nxv2i8.i64.i64(i64 3, <vscale x 2 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2023// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2024//2025vuint8mf4_t test_sf_vc_v_iv_se_u8mf4(vuint8mf4_t vs2, size_t vl) {2026 return __riscv_sf_vc_v_iv_se_u8mf4(p27_26, vs2, simm5, vl);2027}2028 2029// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8mf2(2030// CHECK-RV32-NEXT: entry:2031// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv4i8.i32.nxv4i8.i32.i32(i32 3, <vscale x 4 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2032// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]2033//2034// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8mf2(2035// CHECK-RV64-NEXT: entry:2036// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv4i8.i64.nxv4i8.i64.i64(i64 3, <vscale x 4 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2037// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2038//2039vuint8mf2_t test_sf_vc_v_iv_se_u8mf2(vuint8mf2_t vs2, size_t vl) {2040 return __riscv_sf_vc_v_iv_se_u8mf2(p27_26, vs2, simm5, vl);2041}2042 2043// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8m1(2044// CHECK-RV32-NEXT: entry:2045// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv8i8.i32.nxv8i8.i32.i32(i32 3, <vscale x 8 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2046// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]2047//2048// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8m1(2049// CHECK-RV64-NEXT: entry:2050// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv8i8.i64.nxv8i8.i64.i64(i64 3, <vscale x 8 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2051// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2052//2053vuint8m1_t test_sf_vc_v_iv_se_u8m1(vuint8m1_t vs2, size_t vl) {2054 return __riscv_sf_vc_v_iv_se_u8m1(p27_26, vs2, simm5, vl);2055}2056 2057// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8m2(2058// CHECK-RV32-NEXT: entry:2059// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv16i8.i32.nxv16i8.i32.i32(i32 3, <vscale x 16 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2060// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]2061//2062// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8m2(2063// CHECK-RV64-NEXT: entry:2064// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv16i8.i64.nxv16i8.i64.i64(i64 3, <vscale x 16 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2065// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2066//2067vuint8m2_t test_sf_vc_v_iv_se_u8m2(vuint8m2_t vs2, size_t vl) {2068 return __riscv_sf_vc_v_iv_se_u8m2(p27_26, vs2, simm5, vl);2069}2070 2071// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8m4(2072// CHECK-RV32-NEXT: entry:2073// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv32i8.i32.nxv32i8.i32.i32(i32 3, <vscale x 32 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2074// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]2075//2076// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8m4(2077// CHECK-RV64-NEXT: entry:2078// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv32i8.i64.nxv32i8.i64.i64(i64 3, <vscale x 32 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2079// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2080//2081vuint8m4_t test_sf_vc_v_iv_se_u8m4(vuint8m4_t vs2, size_t vl) {2082 return __riscv_sf_vc_v_iv_se_u8m4(p27_26, vs2, simm5, vl);2083}2084 2085// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8m8(2086// CHECK-RV32-NEXT: entry:2087// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv64i8.i32.nxv64i8.i32.i32(i32 3, <vscale x 64 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2088// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]2089//2090// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8m8(2091// CHECK-RV64-NEXT: entry:2092// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv64i8.i64.nxv64i8.i64.i64(i64 3, <vscale x 64 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2093// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]2094//2095vuint8m8_t test_sf_vc_v_iv_se_u8m8(vuint8m8_t vs2, size_t vl) {2096 return __riscv_sf_vc_v_iv_se_u8m8(p27_26, vs2, simm5, vl);2097}2098 2099// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16mf4(2100// CHECK-RV32-NEXT: entry:2101// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv1i16.i32.nxv1i16.i32.i32(i32 3, <vscale x 1 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2102// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]2103//2104// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16mf4(2105// CHECK-RV64-NEXT: entry:2106// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv1i16.i64.nxv1i16.i64.i64(i64 3, <vscale x 1 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2107// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2108//2109vuint16mf4_t test_sf_vc_v_iv_se_u16mf4(vuint16mf4_t vs2, size_t vl) {2110 return __riscv_sf_vc_v_iv_se_u16mf4(p27_26, vs2, simm5, vl);2111}2112 2113// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16mf2(2114// CHECK-RV32-NEXT: entry:2115// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv2i16.i32.nxv2i16.i32.i32(i32 3, <vscale x 2 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2116// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]2117//2118// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16mf2(2119// CHECK-RV64-NEXT: entry:2120// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv2i16.i64.nxv2i16.i64.i64(i64 3, <vscale x 2 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2121// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2122//2123vuint16mf2_t test_sf_vc_v_iv_se_u16mf2(vuint16mf2_t vs2, size_t vl) {2124 return __riscv_sf_vc_v_iv_se_u16mf2(p27_26, vs2, simm5, vl);2125}2126 2127// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16m1(2128// CHECK-RV32-NEXT: entry:2129// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv4i16.i32.nxv4i16.i32.i32(i32 3, <vscale x 4 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2130// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]2131//2132// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16m1(2133// CHECK-RV64-NEXT: entry:2134// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv4i16.i64.nxv4i16.i64.i64(i64 3, <vscale x 4 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2135// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2136//2137vuint16m1_t test_sf_vc_v_iv_se_u16m1(vuint16m1_t vs2, size_t vl) {2138 return __riscv_sf_vc_v_iv_se_u16m1(p27_26, vs2, simm5, vl);2139}2140 2141// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16m2(2142// CHECK-RV32-NEXT: entry:2143// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv8i16.i32.nxv8i16.i32.i32(i32 3, <vscale x 8 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2144// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]2145//2146// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16m2(2147// CHECK-RV64-NEXT: entry:2148// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv8i16.i64.nxv8i16.i64.i64(i64 3, <vscale x 8 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2149// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2150//2151vuint16m2_t test_sf_vc_v_iv_se_u16m2(vuint16m2_t vs2, size_t vl) {2152 return __riscv_sf_vc_v_iv_se_u16m2(p27_26, vs2, simm5, vl);2153}2154 2155// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16m4(2156// CHECK-RV32-NEXT: entry:2157// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv16i16.i32.nxv16i16.i32.i32(i32 3, <vscale x 16 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2158// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]2159//2160// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16m4(2161// CHECK-RV64-NEXT: entry:2162// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv16i16.i64.nxv16i16.i64.i64(i64 3, <vscale x 16 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2163// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2164//2165vuint16m4_t test_sf_vc_v_iv_se_u16m4(vuint16m4_t vs2, size_t vl) {2166 return __riscv_sf_vc_v_iv_se_u16m4(p27_26, vs2, simm5, vl);2167}2168 2169// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16m8(2170// CHECK-RV32-NEXT: entry:2171// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv32i16.i32.nxv32i16.i32.i32(i32 3, <vscale x 32 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2172// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]2173//2174// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16m8(2175// CHECK-RV64-NEXT: entry:2176// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv32i16.i64.nxv32i16.i64.i64(i64 3, <vscale x 32 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2177// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2178//2179vuint16m8_t test_sf_vc_v_iv_se_u16m8(vuint16m8_t vs2, size_t vl) {2180 return __riscv_sf_vc_v_iv_se_u16m8(p27_26, vs2, simm5, vl);2181}2182 2183// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u32mf2(2184// CHECK-RV32-NEXT: entry:2185// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv1i32.i32.nxv1i32.i32.i32(i32 3, <vscale x 1 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2186// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]2187//2188// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u32mf2(2189// CHECK-RV64-NEXT: entry:2190// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv1i32.i64.nxv1i32.i64.i64(i64 3, <vscale x 1 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2191// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2192//2193vuint32mf2_t test_sf_vc_v_iv_se_u32mf2(vuint32mf2_t vs2, size_t vl) {2194 return __riscv_sf_vc_v_iv_se_u32mf2(p27_26, vs2, simm5, vl);2195}2196 2197// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u32m1(2198// CHECK-RV32-NEXT: entry:2199// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv2i32.i32.nxv2i32.i32.i32(i32 3, <vscale x 2 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2200// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]2201//2202// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u32m1(2203// CHECK-RV64-NEXT: entry:2204// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv2i32.i64.nxv2i32.i64.i64(i64 3, <vscale x 2 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2205// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2206//2207vuint32m1_t test_sf_vc_v_iv_se_u32m1(vuint32m1_t vs2, size_t vl) {2208 return __riscv_sf_vc_v_iv_se_u32m1(p27_26, vs2, simm5, vl);2209}2210 2211// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u32m2(2212// CHECK-RV32-NEXT: entry:2213// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2214// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]2215//2216// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u32m2(2217// CHECK-RV64-NEXT: entry:2218// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i64.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2219// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2220//2221vuint32m2_t test_sf_vc_v_iv_se_u32m2(vuint32m2_t vs2, size_t vl) {2222 return __riscv_sf_vc_v_iv_se_u32m2(p27_26, vs2, simm5, vl);2223}2224 2225// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u32m4(2226// CHECK-RV32-NEXT: entry:2227// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv8i32.i32.nxv8i32.i32.i32(i32 3, <vscale x 8 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2228// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]2229//2230// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u32m4(2231// CHECK-RV64-NEXT: entry:2232// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv8i32.i64.nxv8i32.i64.i64(i64 3, <vscale x 8 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2233// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2234//2235vuint32m4_t test_sf_vc_v_iv_se_u32m4(vuint32m4_t vs2, size_t vl) {2236 return __riscv_sf_vc_v_iv_se_u32m4(p27_26, vs2, simm5, vl);2237}2238 2239// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u32m8(2240// CHECK-RV32-NEXT: entry:2241// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv16i32.i32.nxv16i32.i32.i32(i32 3, <vscale x 16 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2242// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]2243//2244// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u32m8(2245// CHECK-RV64-NEXT: entry:2246// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv16i32.i64.nxv16i32.i64.i64(i64 3, <vscale x 16 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2247// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2248//2249vuint32m8_t test_sf_vc_v_iv_se_u32m8(vuint32m8_t vs2, size_t vl) {2250 return __riscv_sf_vc_v_iv_se_u32m8(p27_26, vs2, simm5, vl);2251}2252 2253// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u64m1(2254// CHECK-RV32-NEXT: entry:2255// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv1i64.i32.nxv1i64.i32.i32(i32 3, <vscale x 1 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2256// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]2257//2258// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u64m1(2259// CHECK-RV64-NEXT: entry:2260// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2261// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2262//2263vuint64m1_t test_sf_vc_v_iv_se_u64m1(vuint64m1_t vs2, size_t vl) {2264 return __riscv_sf_vc_v_iv_se_u64m1(p27_26, vs2, simm5, vl);2265}2266 2267// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u64m2(2268// CHECK-RV32-NEXT: entry:2269// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv2i64.i32.nxv2i64.i32.i32(i32 3, <vscale x 2 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2270// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]2271//2272// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u64m2(2273// CHECK-RV64-NEXT: entry:2274// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2275// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2276//2277vuint64m2_t test_sf_vc_v_iv_se_u64m2(vuint64m2_t vs2, size_t vl) {2278 return __riscv_sf_vc_v_iv_se_u64m2(p27_26, vs2, simm5, vl);2279}2280 2281// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u64m4(2282// CHECK-RV32-NEXT: entry:2283// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv4i64.i32.nxv4i64.i32.i32(i32 3, <vscale x 4 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2284// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]2285//2286// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u64m4(2287// CHECK-RV64-NEXT: entry:2288// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2289// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2290//2291vuint64m4_t test_sf_vc_v_iv_se_u64m4(vuint64m4_t vs2, size_t vl) {2292 return __riscv_sf_vc_v_iv_se_u64m4(p27_26, vs2, simm5, vl);2293}2294 2295// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u64m8(2296// CHECK-RV32-NEXT: entry:2297// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv8i64.i32.nxv8i64.i32.i32(i32 3, <vscale x 8 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2298// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]2299//2300// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u64m8(2301// CHECK-RV64-NEXT: entry:2302// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2303// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]2304//2305vuint64m8_t test_sf_vc_v_iv_se_u64m8(vuint64m8_t vs2, size_t vl) {2306 return __riscv_sf_vc_v_iv_se_u64m8(p27_26, vs2, simm5, vl);2307}2308 2309// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8mf8(2310// CHECK-RV32-NEXT: entry:2311// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.iv.nxv1i8.i32.nxv1i8.i32.i32(i32 3, <vscale x 1 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2312// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]2313//2314// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8mf8(2315// CHECK-RV64-NEXT: entry:2316// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.iv.nxv1i8.i64.nxv1i8.i64.i64(i64 3, <vscale x 1 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2317// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2318//2319vuint8mf8_t test_sf_vc_v_iv_u8mf8(vuint8mf8_t vs2, size_t vl) {2320 return __riscv_sf_vc_v_iv_u8mf8(p27_26, vs2, simm5, vl);2321}2322 2323// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8mf4(2324// CHECK-RV32-NEXT: entry:2325// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.iv.nxv2i8.i32.nxv2i8.i32.i32(i32 3, <vscale x 2 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2326// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]2327//2328// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8mf4(2329// CHECK-RV64-NEXT: entry:2330// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.iv.nxv2i8.i64.nxv2i8.i64.i64(i64 3, <vscale x 2 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2331// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2332//2333vuint8mf4_t test_sf_vc_v_iv_u8mf4(vuint8mf4_t vs2, size_t vl) {2334 return __riscv_sf_vc_v_iv_u8mf4(p27_26, vs2, simm5, vl);2335}2336 2337// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8mf2(2338// CHECK-RV32-NEXT: entry:2339// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.iv.nxv4i8.i32.nxv4i8.i32.i32(i32 3, <vscale x 4 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2340// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]2341//2342// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8mf2(2343// CHECK-RV64-NEXT: entry:2344// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.iv.nxv4i8.i64.nxv4i8.i64.i64(i64 3, <vscale x 4 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2345// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2346//2347vuint8mf2_t test_sf_vc_v_iv_u8mf2(vuint8mf2_t vs2, size_t vl) {2348 return __riscv_sf_vc_v_iv_u8mf2(p27_26, vs2, simm5, vl);2349}2350 2351// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8m1(2352// CHECK-RV32-NEXT: entry:2353// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.iv.nxv8i8.i32.nxv8i8.i32.i32(i32 3, <vscale x 8 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2354// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]2355//2356// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8m1(2357// CHECK-RV64-NEXT: entry:2358// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.iv.nxv8i8.i64.nxv8i8.i64.i64(i64 3, <vscale x 8 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2359// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2360//2361vuint8m1_t test_sf_vc_v_iv_u8m1(vuint8m1_t vs2, size_t vl) {2362 return __riscv_sf_vc_v_iv_u8m1(p27_26, vs2, simm5, vl);2363}2364 2365// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8m2(2366// CHECK-RV32-NEXT: entry:2367// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.iv.nxv16i8.i32.nxv16i8.i32.i32(i32 3, <vscale x 16 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2368// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]2369//2370// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8m2(2371// CHECK-RV64-NEXT: entry:2372// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.iv.nxv16i8.i64.nxv16i8.i64.i64(i64 3, <vscale x 16 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2373// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2374//2375vuint8m2_t test_sf_vc_v_iv_u8m2(vuint8m2_t vs2, size_t vl) {2376 return __riscv_sf_vc_v_iv_u8m2(p27_26, vs2, simm5, vl);2377}2378 2379// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8m4(2380// CHECK-RV32-NEXT: entry:2381// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.iv.nxv32i8.i32.nxv32i8.i32.i32(i32 3, <vscale x 32 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2382// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]2383//2384// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8m4(2385// CHECK-RV64-NEXT: entry:2386// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.iv.nxv32i8.i64.nxv32i8.i64.i64(i64 3, <vscale x 32 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2387// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2388//2389vuint8m4_t test_sf_vc_v_iv_u8m4(vuint8m4_t vs2, size_t vl) {2390 return __riscv_sf_vc_v_iv_u8m4(p27_26, vs2, simm5, vl);2391}2392 2393// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8m8(2394// CHECK-RV32-NEXT: entry:2395// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.iv.nxv64i8.i32.nxv64i8.i32.i32(i32 3, <vscale x 64 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2396// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]2397//2398// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8m8(2399// CHECK-RV64-NEXT: entry:2400// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.iv.nxv64i8.i64.nxv64i8.i64.i64(i64 3, <vscale x 64 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2401// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]2402//2403vuint8m8_t test_sf_vc_v_iv_u8m8(vuint8m8_t vs2, size_t vl) {2404 return __riscv_sf_vc_v_iv_u8m8(p27_26, vs2, simm5, vl);2405}2406 2407// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16mf4(2408// CHECK-RV32-NEXT: entry:2409// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.iv.nxv1i16.i32.nxv1i16.i32.i32(i32 3, <vscale x 1 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2410// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]2411//2412// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16mf4(2413// CHECK-RV64-NEXT: entry:2414// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.iv.nxv1i16.i64.nxv1i16.i64.i64(i64 3, <vscale x 1 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2415// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2416//2417vuint16mf4_t test_sf_vc_v_iv_u16mf4(vuint16mf4_t vs2, size_t vl) {2418 return __riscv_sf_vc_v_iv_u16mf4(p27_26, vs2, simm5, vl);2419}2420 2421// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16mf2(2422// CHECK-RV32-NEXT: entry:2423// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.iv.nxv2i16.i32.nxv2i16.i32.i32(i32 3, <vscale x 2 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2424// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]2425//2426// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16mf2(2427// CHECK-RV64-NEXT: entry:2428// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.iv.nxv2i16.i64.nxv2i16.i64.i64(i64 3, <vscale x 2 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2429// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2430//2431vuint16mf2_t test_sf_vc_v_iv_u16mf2(vuint16mf2_t vs2, size_t vl) {2432 return __riscv_sf_vc_v_iv_u16mf2(p27_26, vs2, simm5, vl);2433}2434 2435// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16m1(2436// CHECK-RV32-NEXT: entry:2437// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.iv.nxv4i16.i32.nxv4i16.i32.i32(i32 3, <vscale x 4 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2438// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]2439//2440// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16m1(2441// CHECK-RV64-NEXT: entry:2442// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.iv.nxv4i16.i64.nxv4i16.i64.i64(i64 3, <vscale x 4 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2443// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2444//2445vuint16m1_t test_sf_vc_v_iv_u16m1(vuint16m1_t vs2, size_t vl) {2446 return __riscv_sf_vc_v_iv_u16m1(p27_26, vs2, simm5, vl);2447}2448 2449// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16m2(2450// CHECK-RV32-NEXT: entry:2451// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.iv.nxv8i16.i32.nxv8i16.i32.i32(i32 3, <vscale x 8 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2452// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]2453//2454// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16m2(2455// CHECK-RV64-NEXT: entry:2456// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.iv.nxv8i16.i64.nxv8i16.i64.i64(i64 3, <vscale x 8 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2457// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2458//2459vuint16m2_t test_sf_vc_v_iv_u16m2(vuint16m2_t vs2, size_t vl) {2460 return __riscv_sf_vc_v_iv_u16m2(p27_26, vs2, simm5, vl);2461}2462 2463// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16m4(2464// CHECK-RV32-NEXT: entry:2465// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.iv.nxv16i16.i32.nxv16i16.i32.i32(i32 3, <vscale x 16 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2466// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]2467//2468// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16m4(2469// CHECK-RV64-NEXT: entry:2470// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.iv.nxv16i16.i64.nxv16i16.i64.i64(i64 3, <vscale x 16 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2471// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2472//2473vuint16m4_t test_sf_vc_v_iv_u16m4(vuint16m4_t vs2, size_t vl) {2474 return __riscv_sf_vc_v_iv_u16m4(p27_26, vs2, simm5, vl);2475}2476 2477// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16m8(2478// CHECK-RV32-NEXT: entry:2479// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.iv.nxv32i16.i32.nxv32i16.i32.i32(i32 3, <vscale x 32 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2480// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]2481//2482// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16m8(2483// CHECK-RV64-NEXT: entry:2484// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.iv.nxv32i16.i64.nxv32i16.i64.i64(i64 3, <vscale x 32 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2485// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2486//2487vuint16m8_t test_sf_vc_v_iv_u16m8(vuint16m8_t vs2, size_t vl) {2488 return __riscv_sf_vc_v_iv_u16m8(p27_26, vs2, simm5, vl);2489}2490 2491// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u32mf2(2492// CHECK-RV32-NEXT: entry:2493// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.iv.nxv1i32.i32.nxv1i32.i32.i32(i32 3, <vscale x 1 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2494// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]2495//2496// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u32mf2(2497// CHECK-RV64-NEXT: entry:2498// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.iv.nxv1i32.i64.nxv1i32.i64.i64(i64 3, <vscale x 1 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2499// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2500//2501vuint32mf2_t test_sf_vc_v_iv_u32mf2(vuint32mf2_t vs2, size_t vl) {2502 return __riscv_sf_vc_v_iv_u32mf2(p27_26, vs2, simm5, vl);2503}2504 2505// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u32m1(2506// CHECK-RV32-NEXT: entry:2507// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.iv.nxv2i32.i32.nxv2i32.i32.i32(i32 3, <vscale x 2 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2508// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]2509//2510// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u32m1(2511// CHECK-RV64-NEXT: entry:2512// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.iv.nxv2i32.i64.nxv2i32.i64.i64(i64 3, <vscale x 2 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2513// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2514//2515vuint32m1_t test_sf_vc_v_iv_u32m1(vuint32m1_t vs2, size_t vl) {2516 return __riscv_sf_vc_v_iv_u32m1(p27_26, vs2, simm5, vl);2517}2518 2519// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u32m2(2520// CHECK-RV32-NEXT: entry:2521// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.nxv4i32.i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2522// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]2523//2524// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u32m2(2525// CHECK-RV64-NEXT: entry:2526// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.nxv4i32.i64.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2527// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2528//2529vuint32m2_t test_sf_vc_v_iv_u32m2(vuint32m2_t vs2, size_t vl) {2530 return __riscv_sf_vc_v_iv_u32m2(p27_26, vs2, simm5, vl);2531}2532 2533// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u32m4(2534// CHECK-RV32-NEXT: entry:2535// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.iv.nxv8i32.i32.nxv8i32.i32.i32(i32 3, <vscale x 8 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2536// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]2537//2538// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u32m4(2539// CHECK-RV64-NEXT: entry:2540// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.iv.nxv8i32.i64.nxv8i32.i64.i64(i64 3, <vscale x 8 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2541// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2542//2543vuint32m4_t test_sf_vc_v_iv_u32m4(vuint32m4_t vs2, size_t vl) {2544 return __riscv_sf_vc_v_iv_u32m4(p27_26, vs2, simm5, vl);2545}2546 2547// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u32m8(2548// CHECK-RV32-NEXT: entry:2549// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.iv.nxv16i32.i32.nxv16i32.i32.i32(i32 3, <vscale x 16 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2550// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]2551//2552// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u32m8(2553// CHECK-RV64-NEXT: entry:2554// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.iv.nxv16i32.i64.nxv16i32.i64.i64(i64 3, <vscale x 16 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2555// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2556//2557vuint32m8_t test_sf_vc_v_iv_u32m8(vuint32m8_t vs2, size_t vl) {2558 return __riscv_sf_vc_v_iv_u32m8(p27_26, vs2, simm5, vl);2559}2560 2561// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u64m1(2562// CHECK-RV32-NEXT: entry:2563// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.iv.nxv1i64.i32.nxv1i64.i32.i32(i32 3, <vscale x 1 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2564// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]2565//2566// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u64m1(2567// CHECK-RV64-NEXT: entry:2568// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.iv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2569// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2570//2571vuint64m1_t test_sf_vc_v_iv_u64m1(vuint64m1_t vs2, size_t vl) {2572 return __riscv_sf_vc_v_iv_u64m1(p27_26, vs2, simm5, vl);2573}2574 2575// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u64m2(2576// CHECK-RV32-NEXT: entry:2577// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.iv.nxv2i64.i32.nxv2i64.i32.i32(i32 3, <vscale x 2 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2578// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]2579//2580// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u64m2(2581// CHECK-RV64-NEXT: entry:2582// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.iv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2583// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2584//2585vuint64m2_t test_sf_vc_v_iv_u64m2(vuint64m2_t vs2, size_t vl) {2586 return __riscv_sf_vc_v_iv_u64m2(p27_26, vs2, simm5, vl);2587}2588 2589// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u64m4(2590// CHECK-RV32-NEXT: entry:2591// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.iv.nxv4i64.i32.nxv4i64.i32.i32(i32 3, <vscale x 4 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2592// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]2593//2594// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u64m4(2595// CHECK-RV64-NEXT: entry:2596// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.iv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2597// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2598//2599vuint64m4_t test_sf_vc_v_iv_u64m4(vuint64m4_t vs2, size_t vl) {2600 return __riscv_sf_vc_v_iv_u64m4(p27_26, vs2, simm5, vl);2601}2602 2603// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u64m8(2604// CHECK-RV32-NEXT: entry:2605// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.iv.nxv8i64.i32.nxv8i64.i32.i32(i32 3, <vscale x 8 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2606// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]2607//2608// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u64m8(2609// CHECK-RV64-NEXT: entry:2610// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.iv.nxv8i64.i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2611// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]2612//2613vuint64m8_t test_sf_vc_v_iv_u64m8(vuint64m8_t vs2, size_t vl) {2614 return __riscv_sf_vc_v_iv_u64m8(p27_26, vs2, simm5, vl);2615}2616 2617// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16mf4(2618// CHECK-RV32-NEXT: entry:2619// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv1i16.f16.i32(i32 1, i32 31, <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2620// CHECK-RV32-NEXT: ret void2621//2622// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16mf4(2623// CHECK-RV64-NEXT: entry:2624// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv1i16.f16.i64(i64 1, i64 31, <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2625// CHECK-RV64-NEXT: ret void2626//2627void test_sf_vc_fv_se_u16mf4(vuint16mf4_t vs2, _Float16 fs1, size_t vl) {2628 __riscv_sf_vc_fv_se_u16mf4(p26, p11_7, vs2, fs1, vl);2629}2630 2631// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16mf2(2632// CHECK-RV32-NEXT: entry:2633// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv2i16.f16.i32(i32 1, i32 31, <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2634// CHECK-RV32-NEXT: ret void2635//2636// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16mf2(2637// CHECK-RV64-NEXT: entry:2638// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv2i16.f16.i64(i64 1, i64 31, <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2639// CHECK-RV64-NEXT: ret void2640//2641void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, _Float16 fs1, size_t vl) {2642 __riscv_sf_vc_fv_se_u16mf2(p26, p11_7, vs2, fs1, vl);2643}2644 2645// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16m1(2646// CHECK-RV32-NEXT: entry:2647// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv4i16.f16.i32(i32 1, i32 31, <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2648// CHECK-RV32-NEXT: ret void2649//2650// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16m1(2651// CHECK-RV64-NEXT: entry:2652// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv4i16.f16.i64(i64 1, i64 31, <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2653// CHECK-RV64-NEXT: ret void2654//2655void test_sf_vc_fv_se_u16m1(vuint16m1_t vs2, _Float16 fs1, size_t vl) {2656 __riscv_sf_vc_fv_se_u16m1(p26, p11_7, vs2, fs1, vl);2657}2658 2659// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16m2(2660// CHECK-RV32-NEXT: entry:2661// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv8i16.f16.i32(i32 1, i32 31, <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2662// CHECK-RV32-NEXT: ret void2663//2664// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16m2(2665// CHECK-RV64-NEXT: entry:2666// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv8i16.f16.i64(i64 1, i64 31, <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2667// CHECK-RV64-NEXT: ret void2668//2669void test_sf_vc_fv_se_u16m2(vuint16m2_t vs2, _Float16 fs1, size_t vl) {2670 __riscv_sf_vc_fv_se_u16m2(p26, p11_7, vs2, fs1, vl);2671}2672 2673// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16m4(2674// CHECK-RV32-NEXT: entry:2675// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv16i16.f16.i32(i32 1, i32 31, <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2676// CHECK-RV32-NEXT: ret void2677//2678// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16m4(2679// CHECK-RV64-NEXT: entry:2680// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv16i16.f16.i64(i64 1, i64 31, <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2681// CHECK-RV64-NEXT: ret void2682//2683void test_sf_vc_fv_se_u16m4(vuint16m4_t vs2, _Float16 fs1, size_t vl) {2684 __riscv_sf_vc_fv_se_u16m4(p26, p11_7, vs2, fs1, vl);2685}2686 2687// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16m8(2688// CHECK-RV32-NEXT: entry:2689// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv32i16.f16.i32(i32 1, i32 31, <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2690// CHECK-RV32-NEXT: ret void2691//2692// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16m8(2693// CHECK-RV64-NEXT: entry:2694// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv32i16.f16.i64(i64 1, i64 31, <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2695// CHECK-RV64-NEXT: ret void2696//2697void test_sf_vc_fv_se_u16m8(vuint16m8_t vs2, _Float16 fs1, size_t vl) {2698 __riscv_sf_vc_fv_se_u16m8(p26, p11_7, vs2, fs1, vl);2699}2700 2701// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u32mf2(2702// CHECK-RV32-NEXT: entry:2703// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv1i32.f32.i32(i32 1, i32 31, <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2704// CHECK-RV32-NEXT: ret void2705//2706// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u32mf2(2707// CHECK-RV64-NEXT: entry:2708// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv1i32.f32.i64(i64 1, i64 31, <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2709// CHECK-RV64-NEXT: ret void2710//2711void test_sf_vc_fv_se_u32mf2(vuint32mf2_t vs2, float fs1, size_t vl) {2712 __riscv_sf_vc_fv_se_u32mf2(p26, p11_7, vs2, fs1, vl);2713}2714 2715// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u32m1(2716// CHECK-RV32-NEXT: entry:2717// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv2i32.f32.i32(i32 1, i32 31, <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2718// CHECK-RV32-NEXT: ret void2719//2720// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u32m1(2721// CHECK-RV64-NEXT: entry:2722// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv2i32.f32.i64(i64 1, i64 31, <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2723// CHECK-RV64-NEXT: ret void2724//2725void test_sf_vc_fv_se_u32m1(vuint32m1_t vs2, float fs1, size_t vl) {2726 __riscv_sf_vc_fv_se_u32m1(p26, p11_7, vs2, fs1, vl);2727}2728 2729// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u32m2(2730// CHECK-RV32-NEXT: entry:2731// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv4i32.f32.i32(i32 1, i32 31, <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2732// CHECK-RV32-NEXT: ret void2733//2734// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u32m2(2735// CHECK-RV64-NEXT: entry:2736// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv4i32.f32.i64(i64 1, i64 31, <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2737// CHECK-RV64-NEXT: ret void2738//2739void test_sf_vc_fv_se_u32m2(vuint32m2_t vs2, float fs1, size_t vl) {2740 __riscv_sf_vc_fv_se_u32m2(p26, p11_7, vs2, fs1, vl);2741}2742 2743// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u32m4(2744// CHECK-RV32-NEXT: entry:2745// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv8i32.f32.i32(i32 1, i32 31, <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2746// CHECK-RV32-NEXT: ret void2747//2748// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u32m4(2749// CHECK-RV64-NEXT: entry:2750// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv8i32.f32.i64(i64 1, i64 31, <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2751// CHECK-RV64-NEXT: ret void2752//2753void test_sf_vc_fv_se_u32m4(vuint32m4_t vs2, float fs1, size_t vl) {2754 __riscv_sf_vc_fv_se_u32m4(p26, p11_7, vs2, fs1, vl);2755}2756 2757// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u32m8(2758// CHECK-RV32-NEXT: entry:2759// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv16i32.f32.i32(i32 1, i32 31, <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2760// CHECK-RV32-NEXT: ret void2761//2762// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u32m8(2763// CHECK-RV64-NEXT: entry:2764// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv16i32.f32.i64(i64 1, i64 31, <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2765// CHECK-RV64-NEXT: ret void2766//2767void test_sf_vc_fv_se_u32m8(vuint32m8_t vs2, float fs1, size_t vl) {2768 __riscv_sf_vc_fv_se_u32m8(p26, p11_7, vs2, fs1, vl);2769}2770 2771// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u64m1(2772// CHECK-RV32-NEXT: entry:2773// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv1i64.f64.i32(i32 1, i32 31, <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2774// CHECK-RV32-NEXT: ret void2775//2776// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u64m1(2777// CHECK-RV64-NEXT: entry:2778// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv1i64.f64.i64(i64 1, i64 31, <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])2779// CHECK-RV64-NEXT: ret void2780//2781void test_sf_vc_fv_se_u64m1(vuint64m1_t vs2, double fs1, size_t vl) {2782 __riscv_sf_vc_fv_se_u64m1(p26, p11_7, vs2, fs1, vl);2783}2784 2785// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u64m2(2786// CHECK-RV32-NEXT: entry:2787// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv2i64.f64.i32(i32 1, i32 31, <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2788// CHECK-RV32-NEXT: ret void2789//2790// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u64m2(2791// CHECK-RV64-NEXT: entry:2792// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv2i64.f64.i64(i64 1, i64 31, <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])2793// CHECK-RV64-NEXT: ret void2794//2795void test_sf_vc_fv_se_u64m2(vuint64m2_t vs2, double fs1, size_t vl) {2796 __riscv_sf_vc_fv_se_u64m2(p26, p11_7, vs2, fs1, vl);2797}2798 2799// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u64m4(2800// CHECK-RV32-NEXT: entry:2801// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv4i64.f64.i32(i32 1, i32 31, <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2802// CHECK-RV32-NEXT: ret void2803//2804// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u64m4(2805// CHECK-RV64-NEXT: entry:2806// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv4i64.f64.i64(i64 1, i64 31, <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])2807// CHECK-RV64-NEXT: ret void2808//2809void test_sf_vc_fv_se_u64m4(vuint64m4_t vs2, double fs1, size_t vl) {2810 __riscv_sf_vc_fv_se_u64m4(p26, p11_7, vs2, fs1, vl);2811}2812 2813// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u64m8(2814// CHECK-RV32-NEXT: entry:2815// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv8i64.f64.i32(i32 1, i32 31, <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2816// CHECK-RV32-NEXT: ret void2817//2818// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u64m8(2819// CHECK-RV64-NEXT: entry:2820// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv8i64.f64.i64(i64 1, i64 31, <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])2821// CHECK-RV64-NEXT: ret void2822//2823void test_sf_vc_fv_se_u64m8(vuint64m8_t vs2, double fs1, size_t vl) {2824 __riscv_sf_vc_fv_se_u64m8(p26, p11_7, vs2, fs1, vl);2825}2826 2827// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16mf4(2828// CHECK-RV32-NEXT: entry:2829// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv1i16.i32.nxv1i16.f16.i32(i32 1, <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2830// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]2831//2832// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16mf4(2833// CHECK-RV64-NEXT: entry:2834// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv1i16.i64.nxv1i16.f16.i64(i64 1, <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2835// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2836//2837vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, _Float16 fs1, size_t vl) {2838 return __riscv_sf_vc_v_fv_se_u16mf4(p26, vs2, fs1, vl);2839}2840 2841// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16mf2(2842// CHECK-RV32-NEXT: entry:2843// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv2i16.i32.nxv2i16.f16.i32(i32 1, <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2844// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]2845//2846// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16mf2(2847// CHECK-RV64-NEXT: entry:2848// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv2i16.i64.nxv2i16.f16.i64(i64 1, <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2849// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2850//2851vuint16mf2_t test_sf_vc_v_fv_se_u16mf2(vuint16mf2_t vs2, _Float16 fs1, size_t vl) {2852 return __riscv_sf_vc_v_fv_se_u16mf2(p26, vs2, fs1, vl);2853}2854 2855// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16m1(2856// CHECK-RV32-NEXT: entry:2857// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv4i16.i32.nxv4i16.f16.i32(i32 1, <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2858// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]2859//2860// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16m1(2861// CHECK-RV64-NEXT: entry:2862// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv4i16.i64.nxv4i16.f16.i64(i64 1, <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2863// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2864//2865vuint16m1_t test_sf_vc_v_fv_se_u16m1(vuint16m1_t vs2, _Float16 fs1, size_t vl) {2866 return __riscv_sf_vc_v_fv_se_u16m1(p26, vs2, fs1, vl);2867}2868 2869// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16m2(2870// CHECK-RV32-NEXT: entry:2871// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv8i16.i32.nxv8i16.f16.i32(i32 1, <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2872// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]2873//2874// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16m2(2875// CHECK-RV64-NEXT: entry:2876// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv8i16.i64.nxv8i16.f16.i64(i64 1, <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2877// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2878//2879vuint16m2_t test_sf_vc_v_fv_se_u16m2(vuint16m2_t vs2, _Float16 fs1, size_t vl) {2880 return __riscv_sf_vc_v_fv_se_u16m2(p26, vs2, fs1, vl);2881}2882 2883// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16m4(2884// CHECK-RV32-NEXT: entry:2885// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv16i16.i32.nxv16i16.f16.i32(i32 1, <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2886// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]2887//2888// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16m4(2889// CHECK-RV64-NEXT: entry:2890// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv16i16.i64.nxv16i16.f16.i64(i64 1, <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2891// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2892//2893vuint16m4_t test_sf_vc_v_fv_se_u16m4(vuint16m4_t vs2, _Float16 fs1, size_t vl) {2894 return __riscv_sf_vc_v_fv_se_u16m4(p26, vs2, fs1, vl);2895}2896 2897// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16m8(2898// CHECK-RV32-NEXT: entry:2899// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv32i16.i32.nxv32i16.f16.i32(i32 1, <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2900// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]2901//2902// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16m8(2903// CHECK-RV64-NEXT: entry:2904// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.fv.se.nxv32i16.i64.nxv32i16.f16.i64(i64 1, <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2905// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2906//2907vuint16m8_t test_sf_vc_v_fv_se_u16m8(vuint16m8_t vs2, _Float16 fs1, size_t vl) {2908 return __riscv_sf_vc_v_fv_se_u16m8(p26, vs2, fs1, vl);2909}2910 2911// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u32mf2(2912// CHECK-RV32-NEXT: entry:2913// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv1i32.i32.nxv1i32.f32.i32(i32 1, <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2914// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]2915//2916// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u32mf2(2917// CHECK-RV64-NEXT: entry:2918// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv1i32.i64.nxv1i32.f32.i64(i64 1, <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2919// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2920//2921vuint32mf2_t test_sf_vc_v_fv_se_u32mf2(vuint32mf2_t vs2, float fs1, size_t vl) {2922 return __riscv_sf_vc_v_fv_se_u32mf2(p26, vs2, fs1, vl);2923}2924 2925// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u32m1(2926// CHECK-RV32-NEXT: entry:2927// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv2i32.i32.nxv2i32.f32.i32(i32 1, <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2928// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]2929//2930// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u32m1(2931// CHECK-RV64-NEXT: entry:2932// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv2i32.i64.nxv2i32.f32.i64(i64 1, <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2933// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2934//2935vuint32m1_t test_sf_vc_v_fv_se_u32m1(vuint32m1_t vs2, float fs1, size_t vl) {2936 return __riscv_sf_vc_v_fv_se_u32m1(p26, vs2, fs1, vl);2937}2938 2939// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u32m2(2940// CHECK-RV32-NEXT: entry:2941// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv4i32.i32.nxv4i32.f32.i32(i32 1, <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2942// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]2943//2944// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u32m2(2945// CHECK-RV64-NEXT: entry:2946// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv4i32.i64.nxv4i32.f32.i64(i64 1, <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2947// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2948//2949vuint32m2_t test_sf_vc_v_fv_se_u32m2(vuint32m2_t vs2, float fs1, size_t vl) {2950 return __riscv_sf_vc_v_fv_se_u32m2(p26, vs2, fs1, vl);2951}2952 2953// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u32m4(2954// CHECK-RV32-NEXT: entry:2955// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv8i32.i32.nxv8i32.f32.i32(i32 1, <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2956// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]2957//2958// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u32m4(2959// CHECK-RV64-NEXT: entry:2960// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv8i32.i64.nxv8i32.f32.i64(i64 1, <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2961// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2962//2963vuint32m4_t test_sf_vc_v_fv_se_u32m4(vuint32m4_t vs2, float fs1, size_t vl) {2964 return __riscv_sf_vc_v_fv_se_u32m4(p26, vs2, fs1, vl);2965}2966 2967// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u32m8(2968// CHECK-RV32-NEXT: entry:2969// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv16i32.i32.nxv16i32.f32.i32(i32 1, <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2970// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]2971//2972// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u32m8(2973// CHECK-RV64-NEXT: entry:2974// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv16i32.i64.nxv16i32.f32.i64(i64 1, <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2975// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2976//2977vuint32m8_t test_sf_vc_v_fv_se_u32m8(vuint32m8_t vs2, float fs1, size_t vl) {2978 return __riscv_sf_vc_v_fv_se_u32m8(p26, vs2, fs1, vl);2979}2980 2981// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u64m1(2982// CHECK-RV32-NEXT: entry:2983// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.fv.se.nxv1i64.i32.nxv1i64.f64.i32(i32 1, <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2984// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]2985//2986// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u64m1(2987// CHECK-RV64-NEXT: entry:2988// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.fv.se.nxv1i64.i64.nxv1i64.f64.i64(i64 1, <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])2989// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2990//2991vuint64m1_t test_sf_vc_v_fv_se_u64m1(vuint64m1_t vs2, double fs1, size_t vl) {2992 return __riscv_sf_vc_v_fv_se_u64m1(p26, vs2, fs1, vl);2993}2994 2995// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u64m2(2996// CHECK-RV32-NEXT: entry:2997// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.fv.se.nxv2i64.i32.nxv2i64.f64.i32(i32 1, <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2998// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]2999//3000// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u64m2(3001// CHECK-RV64-NEXT: entry:3002// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.fv.se.nxv2i64.i64.nxv2i64.f64.i64(i64 1, <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3003// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]3004//3005vuint64m2_t test_sf_vc_v_fv_se_u64m2(vuint64m2_t vs2, double fs1, size_t vl) {3006 return __riscv_sf_vc_v_fv_se_u64m2(p26, vs2, fs1, vl);3007}3008 3009// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u64m4(3010// CHECK-RV32-NEXT: entry:3011// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.fv.se.nxv4i64.i32.nxv4i64.f64.i32(i32 1, <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3012// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]3013//3014// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u64m4(3015// CHECK-RV64-NEXT: entry:3016// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.fv.se.nxv4i64.i64.nxv4i64.f64.i64(i64 1, <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3017// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]3018//3019vuint64m4_t test_sf_vc_v_fv_se_u64m4(vuint64m4_t vs2, double fs1, size_t vl) {3020 return __riscv_sf_vc_v_fv_se_u64m4(p26, vs2, fs1, vl);3021}3022 3023// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u64m8(3024// CHECK-RV32-NEXT: entry:3025// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.fv.se.nxv8i64.i32.nxv8i64.f64.i32(i32 1, <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3026// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]3027//3028// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u64m8(3029// CHECK-RV64-NEXT: entry:3030// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.fv.se.nxv8i64.i64.nxv8i64.f64.i64(i64 1, <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3031// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]3032//3033vuint64m8_t test_sf_vc_v_fv_se_u64m8(vuint64m8_t vs2, double fs1, size_t vl) {3034 return __riscv_sf_vc_v_fv_se_u64m8(p26, vs2, fs1, vl);3035}3036 3037// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16mf4(3038// CHECK-RV32-NEXT: entry:3039// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.fv.nxv1i16.i32.nxv1i16.f16.i32(i32 1, <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3040// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]3041//3042// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16mf4(3043// CHECK-RV64-NEXT: entry:3044// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.fv.nxv1i16.i64.nxv1i16.f16.i64(i64 1, <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3045// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]3046//3047vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, _Float16 fs1, size_t vl) {3048 return __riscv_sf_vc_v_fv_u16mf4(p26, vs2, fs1, vl);3049}3050 3051// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16mf2(3052// CHECK-RV32-NEXT: entry:3053// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.fv.nxv2i16.i32.nxv2i16.f16.i32(i32 1, <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3054// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]3055//3056// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16mf2(3057// CHECK-RV64-NEXT: entry:3058// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.fv.nxv2i16.i64.nxv2i16.f16.i64(i64 1, <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3059// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]3060//3061vuint16mf2_t test_sf_vc_v_fv_u16mf2(vuint16mf2_t vs2, _Float16 fs1, size_t vl) {3062 return __riscv_sf_vc_v_fv_u16mf2(p26, vs2, fs1, vl);3063}3064 3065// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16m1(3066// CHECK-RV32-NEXT: entry:3067// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.fv.nxv4i16.i32.nxv4i16.f16.i32(i32 1, <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3068// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]3069//3070// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16m1(3071// CHECK-RV64-NEXT: entry:3072// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.fv.nxv4i16.i64.nxv4i16.f16.i64(i64 1, <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3073// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]3074//3075vuint16m1_t test_sf_vc_v_fv_u16m1(vuint16m1_t vs2, _Float16 fs1, size_t vl) {3076 return __riscv_sf_vc_v_fv_u16m1(p26, vs2, fs1, vl);3077}3078 3079// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16m2(3080// CHECK-RV32-NEXT: entry:3081// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.fv.nxv8i16.i32.nxv8i16.f16.i32(i32 1, <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3082// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]3083//3084// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16m2(3085// CHECK-RV64-NEXT: entry:3086// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.fv.nxv8i16.i64.nxv8i16.f16.i64(i64 1, <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3087// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]3088//3089vuint16m2_t test_sf_vc_v_fv_u16m2(vuint16m2_t vs2, _Float16 fs1, size_t vl) {3090 return __riscv_sf_vc_v_fv_u16m2(p26, vs2, fs1, vl);3091}3092 3093// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16m4(3094// CHECK-RV32-NEXT: entry:3095// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.fv.nxv16i16.i32.nxv16i16.f16.i32(i32 1, <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3096// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]3097//3098// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16m4(3099// CHECK-RV64-NEXT: entry:3100// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.fv.nxv16i16.i64.nxv16i16.f16.i64(i64 1, <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3101// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]3102//3103vuint16m4_t test_sf_vc_v_fv_u16m4(vuint16m4_t vs2, _Float16 fs1, size_t vl) {3104 return __riscv_sf_vc_v_fv_u16m4(p26, vs2, fs1, vl);3105}3106 3107// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16m8(3108// CHECK-RV32-NEXT: entry:3109// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.fv.nxv32i16.i32.nxv32i16.f16.i32(i32 1, <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3110// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]3111//3112// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16m8(3113// CHECK-RV64-NEXT: entry:3114// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.fv.nxv32i16.i64.nxv32i16.f16.i64(i64 1, <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3115// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]3116//3117vuint16m8_t test_sf_vc_v_fv_u16m8(vuint16m8_t vs2, _Float16 fs1, size_t vl) {3118 return __riscv_sf_vc_v_fv_u16m8(p26, vs2, fs1, vl);3119}3120 3121// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u32mf2(3122// CHECK-RV32-NEXT: entry:3123// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.fv.nxv1i32.i32.nxv1i32.f32.i32(i32 1, <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])3124// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]3125//3126// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u32mf2(3127// CHECK-RV64-NEXT: entry:3128// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.fv.nxv1i32.i64.nxv1i32.f32.i64(i64 1, <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])3129// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]3130//3131vuint32mf2_t test_sf_vc_v_fv_u32mf2(vuint32mf2_t vs2, float fs1, size_t vl) {3132 return __riscv_sf_vc_v_fv_u32mf2(p26, vs2, fs1, vl);3133}3134 3135// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u32m1(3136// CHECK-RV32-NEXT: entry:3137// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.fv.nxv2i32.i32.nxv2i32.f32.i32(i32 1, <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])3138// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]3139//3140// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u32m1(3141// CHECK-RV64-NEXT: entry:3142// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.fv.nxv2i32.i64.nxv2i32.f32.i64(i64 1, <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])3143// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]3144//3145vuint32m1_t test_sf_vc_v_fv_u32m1(vuint32m1_t vs2, float fs1, size_t vl) {3146 return __riscv_sf_vc_v_fv_u32m1(p26, vs2, fs1, vl);3147}3148 3149// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u32m2(3150// CHECK-RV32-NEXT: entry:3151// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fv.nxv4i32.i32.nxv4i32.f32.i32(i32 1, <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])3152// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]3153//3154// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u32m2(3155// CHECK-RV64-NEXT: entry:3156// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fv.nxv4i32.i64.nxv4i32.f32.i64(i64 1, <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])3157// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]3158//3159vuint32m2_t test_sf_vc_v_fv_u32m2(vuint32m2_t vs2, float fs1, size_t vl) {3160 return __riscv_sf_vc_v_fv_u32m2(p26, vs2, fs1, vl);3161}3162 3163// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u32m4(3164// CHECK-RV32-NEXT: entry:3165// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.fv.nxv8i32.i32.nxv8i32.f32.i32(i32 1, <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])3166// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]3167//3168// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u32m4(3169// CHECK-RV64-NEXT: entry:3170// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.fv.nxv8i32.i64.nxv8i32.f32.i64(i64 1, <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])3171// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]3172//3173vuint32m4_t test_sf_vc_v_fv_u32m4(vuint32m4_t vs2, float fs1, size_t vl) {3174 return __riscv_sf_vc_v_fv_u32m4(p26, vs2, fs1, vl);3175}3176 3177// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u32m8(3178// CHECK-RV32-NEXT: entry:3179// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.fv.nxv16i32.i32.nxv16i32.f32.i32(i32 1, <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])3180// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]3181//3182// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u32m8(3183// CHECK-RV64-NEXT: entry:3184// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.fv.nxv16i32.i64.nxv16i32.f32.i64(i64 1, <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])3185// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]3186//3187vuint32m8_t test_sf_vc_v_fv_u32m8(vuint32m8_t vs2, float fs1, size_t vl) {3188 return __riscv_sf_vc_v_fv_u32m8(p26, vs2, fs1, vl);3189}3190 3191// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u64m1(3192// CHECK-RV32-NEXT: entry:3193// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.fv.nxv1i64.i32.nxv1i64.f64.i32(i32 1, <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3194// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]3195//3196// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u64m1(3197// CHECK-RV64-NEXT: entry:3198// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.fv.nxv1i64.i64.nxv1i64.f64.i64(i64 1, <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3199// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]3200//3201vuint64m1_t test_sf_vc_v_fv_u64m1(vuint64m1_t vs2, double fs1, size_t vl) {3202 return __riscv_sf_vc_v_fv_u64m1(p26, vs2, fs1, vl);3203}3204 3205// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u64m2(3206// CHECK-RV32-NEXT: entry:3207// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.fv.nxv2i64.i32.nxv2i64.f64.i32(i32 1, <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3208// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]3209//3210// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u64m2(3211// CHECK-RV64-NEXT: entry:3212// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.fv.nxv2i64.i64.nxv2i64.f64.i64(i64 1, <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3213// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]3214//3215vuint64m2_t test_sf_vc_v_fv_u64m2(vuint64m2_t vs2, double fs1, size_t vl) {3216 return __riscv_sf_vc_v_fv_u64m2(p26, vs2, fs1, vl);3217}3218 3219// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u64m4(3220// CHECK-RV32-NEXT: entry:3221// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.fv.nxv4i64.i32.nxv4i64.f64.i32(i32 1, <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3222// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]3223//3224// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u64m4(3225// CHECK-RV64-NEXT: entry:3226// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.fv.nxv4i64.i64.nxv4i64.f64.i64(i64 1, <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3227// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]3228//3229vuint64m4_t test_sf_vc_v_fv_u64m4(vuint64m4_t vs2, double fs1, size_t vl) {3230 return __riscv_sf_vc_v_fv_u64m4(p26, vs2, fs1, vl);3231}3232 3233// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u64m8(3234// CHECK-RV32-NEXT: entry:3235// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.fv.nxv8i64.i32.nxv8i64.f64.i32(i32 1, <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3236// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]3237//3238// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u64m8(3239// CHECK-RV64-NEXT: entry:3240// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.fv.nxv8i64.i64.nxv8i64.f64.i64(i64 1, <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3241// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]3242//3243vuint64m8_t test_sf_vc_v_fv_u64m8(vuint64m8_t vs2, double fs1, size_t vl) {3244 return __riscv_sf_vc_v_fv_u64m8(p26, vs2, fs1, vl);3245}3246