3245 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// REQUIRES: riscv-registered-target3// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s4// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s5 6#include <sifive_vector.h>7 8#define p27_26 (0b11)9#define p26 (0b1)10#define simm5 (10)11 12// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8mf8(13// CHECK-RV32-NEXT: entry:14// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i32 [[VL:%.*]])15// CHECK-RV32-NEXT: ret void16//17// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8mf8(18// CHECK-RV64-NEXT: entry:19// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv1i8.nxv1i8.nxv1i8.i64(i64 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 [[VL:%.*]])20// CHECK-RV64-NEXT: ret void21//22void test_sf_vc_vvv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {23 __riscv_sf_vc_vvv_se_u8mf8(p27_26, vd, vs2, vs1, vl);24}25 26// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8mf4(27// CHECK-RV32-NEXT: entry:28// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i32 [[VL:%.*]])29// CHECK-RV32-NEXT: ret void30//31// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8mf4(32// CHECK-RV64-NEXT: entry:33// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv2i8.nxv2i8.nxv2i8.i64(i64 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 [[VL:%.*]])34// CHECK-RV64-NEXT: ret void35//36void test_sf_vc_vvv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) {37 __riscv_sf_vc_vvv_se_u8mf4(p27_26, vd, vs2, vs1, vl);38}39 40// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8mf2(41// CHECK-RV32-NEXT: entry:42// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i32 [[VL:%.*]])43// CHECK-RV32-NEXT: ret void44//45// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8mf2(46// CHECK-RV64-NEXT: entry:47// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv4i8.nxv4i8.nxv4i8.i64(i64 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 [[VL:%.*]])48// CHECK-RV64-NEXT: ret void49//50void test_sf_vc_vvv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) {51 __riscv_sf_vc_vvv_se_u8mf2(p27_26, vd, vs2, vs1, vl);52}53 54// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8m1(55// CHECK-RV32-NEXT: entry:56// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i32 [[VL:%.*]])57// CHECK-RV32-NEXT: ret void58//59// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8m1(60// CHECK-RV64-NEXT: entry:61// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv8i8.nxv8i8.nxv8i8.i64(i64 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 [[VL:%.*]])62// CHECK-RV64-NEXT: ret void63//64void test_sf_vc_vvv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {65 __riscv_sf_vc_vvv_se_u8m1(p27_26, vd, vs2, vs1, vl);66}67 68// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8m2(69// CHECK-RV32-NEXT: entry:70// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i32 [[VL:%.*]])71// CHECK-RV32-NEXT: ret void72//73// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8m2(74// CHECK-RV64-NEXT: entry:75// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv16i8.nxv16i8.nxv16i8.i64(i64 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 [[VL:%.*]])76// CHECK-RV64-NEXT: ret void77//78void test_sf_vc_vvv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {79 __riscv_sf_vc_vvv_se_u8m2(p27_26, vd, vs2, vs1, vl);80}81 82// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8m4(83// CHECK-RV32-NEXT: entry:84// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i32 [[VL:%.*]])85// CHECK-RV32-NEXT: ret void86//87// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8m4(88// CHECK-RV64-NEXT: entry:89// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv32i8.nxv32i8.nxv32i8.i64(i64 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 [[VL:%.*]])90// CHECK-RV64-NEXT: ret void91//92void test_sf_vc_vvv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) {93 __riscv_sf_vc_vvv_se_u8m4(p27_26, vd, vs2, vs1, vl);94}95 96// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8m8(97// CHECK-RV32-NEXT: entry:98// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i32 [[VL:%.*]])99// CHECK-RV32-NEXT: ret void100//101// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8m8(102// CHECK-RV64-NEXT: entry:103// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv64i8.nxv64i8.nxv64i8.i64(i64 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 [[VL:%.*]])104// CHECK-RV64-NEXT: ret void105//106void test_sf_vc_vvv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {107 __riscv_sf_vc_vvv_se_u8m8(p27_26, vd, vs2, vs1, vl);108}109 110// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16mf4(111// CHECK-RV32-NEXT: entry:112// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i32 [[VL:%.*]])113// CHECK-RV32-NEXT: ret void114//115// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16mf4(116// CHECK-RV64-NEXT: entry:117// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv1i16.nxv1i16.nxv1i16.i64(i64 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 [[VL:%.*]])118// CHECK-RV64-NEXT: ret void119//120void test_sf_vc_vvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) {121 __riscv_sf_vc_vvv_se_u16mf4(p27_26, vd, vs2, vs1, vl);122}123 124// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16mf2(125// CHECK-RV32-NEXT: entry:126// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.nxv2i16.i32(i32 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i32 [[VL:%.*]])127// CHECK-RV32-NEXT: ret void128//129// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16mf2(130// CHECK-RV64-NEXT: entry:131// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv2i16.nxv2i16.nxv2i16.i64(i64 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 [[VL:%.*]])132// CHECK-RV64-NEXT: ret void133//134void test_sf_vc_vvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) {135 __riscv_sf_vc_vvv_se_u16mf2(p27_26, vd, vs2, vs1, vl);136}137 138// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16m1(139// CHECK-RV32-NEXT: entry:140// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i16.nxv4i16.nxv4i16.i32(i32 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i32 [[VL:%.*]])141// CHECK-RV32-NEXT: ret void142//143// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16m1(144// CHECK-RV64-NEXT: entry:145// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv4i16.nxv4i16.nxv4i16.i64(i64 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 [[VL:%.*]])146// CHECK-RV64-NEXT: ret void147//148void test_sf_vc_vvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) {149 __riscv_sf_vc_vvv_se_u16m1(p27_26, vd, vs2, vs1, vl);150}151 152// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16m2(153// CHECK-RV32-NEXT: entry:154// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i16.nxv8i16.nxv8i16.i32(i32 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i32 [[VL:%.*]])155// CHECK-RV32-NEXT: ret void156//157// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16m2(158// CHECK-RV64-NEXT: entry:159// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv8i16.nxv8i16.nxv8i16.i64(i64 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 [[VL:%.*]])160// CHECK-RV64-NEXT: ret void161//162void test_sf_vc_vvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) {163 __riscv_sf_vc_vvv_se_u16m2(p27_26, vd, vs2, vs1, vl);164}165 166// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16m4(167// CHECK-RV32-NEXT: entry:168// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i16.nxv16i16.nxv16i16.i32(i32 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i32 [[VL:%.*]])169// CHECK-RV32-NEXT: ret void170//171// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16m4(172// CHECK-RV64-NEXT: entry:173// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv16i16.nxv16i16.nxv16i16.i64(i64 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 [[VL:%.*]])174// CHECK-RV64-NEXT: ret void175//176void test_sf_vc_vvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) {177 __riscv_sf_vc_vvv_se_u16m4(p27_26, vd, vs2, vs1, vl);178}179 180// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16m8(181// CHECK-RV32-NEXT: entry:182// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i16.nxv32i16.nxv32i16.i32(i32 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i32 [[VL:%.*]])183// CHECK-RV32-NEXT: ret void184//185// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16m8(186// CHECK-RV64-NEXT: entry:187// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv32i16.nxv32i16.nxv32i16.i64(i64 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 [[VL:%.*]])188// CHECK-RV64-NEXT: ret void189//190void test_sf_vc_vvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) {191 __riscv_sf_vc_vvv_se_u16m8(p27_26, vd, vs2, vs1, vl);192}193 194// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u32mf2(195// CHECK-RV32-NEXT: entry:196// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i32.nxv1i32.nxv1i32.i32(i32 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i32 [[VL:%.*]])197// CHECK-RV32-NEXT: ret void198//199// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u32mf2(200// CHECK-RV64-NEXT: entry:201// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv1i32.nxv1i32.nxv1i32.i64(i64 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 [[VL:%.*]])202// CHECK-RV64-NEXT: ret void203//204void test_sf_vc_vvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {205 __riscv_sf_vc_vvv_se_u32mf2(p27_26, vd, vs2, vs1, vl);206}207 208// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u32m1(209// CHECK-RV32-NEXT: entry:210// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i32.nxv2i32.nxv2i32.i32(i32 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i32 [[VL:%.*]])211// CHECK-RV32-NEXT: ret void212//213// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u32m1(214// CHECK-RV64-NEXT: entry:215// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv2i32.nxv2i32.nxv2i32.i64(i64 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 [[VL:%.*]])216// CHECK-RV64-NEXT: ret void217//218void test_sf_vc_vvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {219 __riscv_sf_vc_vvv_se_u32m1(p27_26, vd, vs2, vs1, vl);220}221 222// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u32m2(223// CHECK-RV32-NEXT: entry:224// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i32.nxv4i32.nxv4i32.i32(i32 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i32 [[VL:%.*]])225// CHECK-RV32-NEXT: ret void226//227// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u32m2(228// CHECK-RV64-NEXT: entry:229// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv4i32.nxv4i32.nxv4i32.i64(i64 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 [[VL:%.*]])230// CHECK-RV64-NEXT: ret void231//232void test_sf_vc_vvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {233 __riscv_sf_vc_vvv_se_u32m2(p27_26, vd, vs2, vs1, vl);234}235 236// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u32m4(237// CHECK-RV32-NEXT: entry:238// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i32.nxv8i32.nxv8i32.i32(i32 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i32 [[VL:%.*]])239// CHECK-RV32-NEXT: ret void240//241// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u32m4(242// CHECK-RV64-NEXT: entry:243// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv8i32.nxv8i32.nxv8i32.i64(i64 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 [[VL:%.*]])244// CHECK-RV64-NEXT: ret void245//246void test_sf_vc_vvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {247 __riscv_sf_vc_vvv_se_u32m4(p27_26, vd, vs2, vs1, vl);248}249 250// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u32m8(251// CHECK-RV32-NEXT: entry:252// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i32.nxv16i32.nxv16i32.i32(i32 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i32 [[VL:%.*]])253// CHECK-RV32-NEXT: ret void254//255// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u32m8(256// CHECK-RV64-NEXT: entry:257// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv16i32.nxv16i32.nxv16i32.i64(i64 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 [[VL:%.*]])258// CHECK-RV64-NEXT: ret void259//260void test_sf_vc_vvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) {261 __riscv_sf_vc_vvv_se_u32m8(p27_26, vd, vs2, vs1, vl);262}263 264// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u64m1(265// CHECK-RV32-NEXT: entry:266// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i64.nxv1i64.nxv1i64.i32(i32 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i32 [[VL:%.*]])267// CHECK-RV32-NEXT: ret void268//269// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u64m1(270// CHECK-RV64-NEXT: entry:271// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv1i64.nxv1i64.nxv1i64.i64(i64 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 [[VL:%.*]])272// CHECK-RV64-NEXT: ret void273//274void test_sf_vc_vvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {275 __riscv_sf_vc_vvv_se_u64m1(p27_26, vd, vs2, vs1, vl);276}277 278// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u64m2(279// CHECK-RV32-NEXT: entry:280// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i64.nxv2i64.nxv2i64.i32(i32 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i32 [[VL:%.*]])281// CHECK-RV32-NEXT: ret void282//283// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u64m2(284// CHECK-RV64-NEXT: entry:285// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv2i64.nxv2i64.nxv2i64.i64(i64 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 [[VL:%.*]])286// CHECK-RV64-NEXT: ret void287//288void test_sf_vc_vvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {289 __riscv_sf_vc_vvv_se_u64m2(p27_26, vd, vs2, vs1, vl);290}291 292// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u64m4(293// CHECK-RV32-NEXT: entry:294// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i64.nxv4i64.nxv4i64.i32(i32 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i32 [[VL:%.*]])295// CHECK-RV32-NEXT: ret void296//297// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u64m4(298// CHECK-RV64-NEXT: entry:299// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv4i64.nxv4i64.nxv4i64.i64(i64 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 [[VL:%.*]])300// CHECK-RV64-NEXT: ret void301//302void test_sf_vc_vvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {303 __riscv_sf_vc_vvv_se_u64m4(p27_26, vd, vs2, vs1, vl);304}305 306// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u64m8(307// CHECK-RV32-NEXT: entry:308// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i64.nxv8i64.nxv8i64.i32(i32 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i32 [[VL:%.*]])309// CHECK-RV32-NEXT: ret void310//311// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u64m8(312// CHECK-RV64-NEXT: entry:313// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv8i64.nxv8i64.nxv8i64.i64(i64 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 [[VL:%.*]])314// CHECK-RV64-NEXT: ret void315//316void test_sf_vc_vvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {317 __riscv_sf_vc_vvv_se_u64m8(p27_26, vd, vs2, vs1, vl);318}319 320// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8mf8(321// CHECK-RV32-NEXT: entry:322// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv1i8.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i32 [[VL:%.*]])323// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]324//325// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8mf8(326// CHECK-RV64-NEXT: entry:327// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv1i8.i64.nxv1i8.nxv1i8.nxv1i8.i64(i64 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 [[VL:%.*]])328// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]329//330vuint8mf8_t test_sf_vc_v_vvv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {331 return __riscv_sf_vc_v_vvv_se_u8mf8(p27_26, vd, vs2, vs1, vl);332}333 334// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8mf4(335// CHECK-RV32-NEXT: entry:336// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv2i8.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i32 [[VL:%.*]])337// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]338//339// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8mf4(340// CHECK-RV64-NEXT: entry:341// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv2i8.i64.nxv2i8.nxv2i8.nxv2i8.i64(i64 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 [[VL:%.*]])342// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]343//344vuint8mf4_t test_sf_vc_v_vvv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) {345 return __riscv_sf_vc_v_vvv_se_u8mf4(p27_26, vd, vs2, vs1, vl);346}347 348// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8mf2(349// CHECK-RV32-NEXT: entry:350// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv4i8.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i32 [[VL:%.*]])351// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]352//353// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8mf2(354// CHECK-RV64-NEXT: entry:355// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv4i8.i64.nxv4i8.nxv4i8.nxv4i8.i64(i64 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 [[VL:%.*]])356// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]357//358vuint8mf2_t test_sf_vc_v_vvv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) {359 return __riscv_sf_vc_v_vvv_se_u8mf2(p27_26, vd, vs2, vs1, vl);360}361 362// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8m1(363// CHECK-RV32-NEXT: entry:364// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv8i8.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i32 [[VL:%.*]])365// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]366//367// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8m1(368// CHECK-RV64-NEXT: entry:369// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv8i8.i64.nxv8i8.nxv8i8.nxv8i8.i64(i64 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 [[VL:%.*]])370// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]371//372vuint8m1_t test_sf_vc_v_vvv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {373 return __riscv_sf_vc_v_vvv_se_u8m1(p27_26, vd, vs2, vs1, vl);374}375 376// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8m2(377// CHECK-RV32-NEXT: entry:378// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv16i8.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i32 [[VL:%.*]])379// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]380//381// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8m2(382// CHECK-RV64-NEXT: entry:383// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv16i8.i64.nxv16i8.nxv16i8.nxv16i8.i64(i64 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 [[VL:%.*]])384// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]385//386vuint8m2_t test_sf_vc_v_vvv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {387 return __riscv_sf_vc_v_vvv_se_u8m2(p27_26, vd, vs2, vs1, vl);388}389 390// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8m4(391// CHECK-RV32-NEXT: entry:392// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv32i8.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i32 [[VL:%.*]])393// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]394//395// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8m4(396// CHECK-RV64-NEXT: entry:397// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv32i8.i64.nxv32i8.nxv32i8.nxv32i8.i64(i64 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 [[VL:%.*]])398// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]399//400vuint8m4_t test_sf_vc_v_vvv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) {401 return __riscv_sf_vc_v_vvv_se_u8m4(p27_26, vd, vs2, vs1, vl);402}403 404// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8m8(405// CHECK-RV32-NEXT: entry:406// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv64i8.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i32 [[VL:%.*]])407// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]408//409// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8m8(410// CHECK-RV64-NEXT: entry:411// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv64i8.i64.nxv64i8.nxv64i8.nxv64i8.i64(i64 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 [[VL:%.*]])412// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]413//414vuint8m8_t test_sf_vc_v_vvv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {415 return __riscv_sf_vc_v_vvv_se_u8m8(p27_26, vd, vs2, vs1, vl);416}417 418// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16mf4(419// CHECK-RV32-NEXT: entry:420// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv1i16.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i32 [[VL:%.*]])421// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]422//423// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16mf4(424// CHECK-RV64-NEXT: entry:425// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv1i16.i64.nxv1i16.nxv1i16.nxv1i16.i64(i64 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 [[VL:%.*]])426// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]427//428vuint16mf4_t test_sf_vc_v_vvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) {429 return __riscv_sf_vc_v_vvv_se_u16mf4(p27_26, vd, vs2, vs1, vl);430}431 432// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16mf2(433// CHECK-RV32-NEXT: entry:434// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv2i16.i32.nxv2i16.nxv2i16.nxv2i16.i32(i32 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i32 [[VL:%.*]])435// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]436//437// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16mf2(438// CHECK-RV64-NEXT: entry:439// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv2i16.i64.nxv2i16.nxv2i16.nxv2i16.i64(i64 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 [[VL:%.*]])440// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]441//442vuint16mf2_t test_sf_vc_v_vvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) {443 return __riscv_sf_vc_v_vvv_se_u16mf2(p27_26, vd, vs2, vs1, vl);444}445 446// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16m1(447// CHECK-RV32-NEXT: entry:448// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv4i16.i32.nxv4i16.nxv4i16.nxv4i16.i32(i32 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i32 [[VL:%.*]])449// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]450//451// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16m1(452// CHECK-RV64-NEXT: entry:453// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv4i16.i64.nxv4i16.nxv4i16.nxv4i16.i64(i64 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 [[VL:%.*]])454// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]455//456vuint16m1_t test_sf_vc_v_vvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) {457 return __riscv_sf_vc_v_vvv_se_u16m1(p27_26, vd, vs2, vs1, vl);458}459 460// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16m2(461// CHECK-RV32-NEXT: entry:462// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv8i16.i32.nxv8i16.nxv8i16.nxv8i16.i32(i32 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i32 [[VL:%.*]])463// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]464//465// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16m2(466// CHECK-RV64-NEXT: entry:467// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv8i16.i64.nxv8i16.nxv8i16.nxv8i16.i64(i64 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 [[VL:%.*]])468// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]469//470vuint16m2_t test_sf_vc_v_vvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) {471 return __riscv_sf_vc_v_vvv_se_u16m2(p27_26, vd, vs2, vs1, vl);472}473 474// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16m4(475// CHECK-RV32-NEXT: entry:476// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv16i16.i32.nxv16i16.nxv16i16.nxv16i16.i32(i32 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i32 [[VL:%.*]])477// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]478//479// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16m4(480// CHECK-RV64-NEXT: entry:481// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv16i16.i64.nxv16i16.nxv16i16.nxv16i16.i64(i64 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 [[VL:%.*]])482// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]483//484vuint16m4_t test_sf_vc_v_vvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) {485 return __riscv_sf_vc_v_vvv_se_u16m4(p27_26, vd, vs2, vs1, vl);486}487 488// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16m8(489// CHECK-RV32-NEXT: entry:490// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv32i16.i32.nxv32i16.nxv32i16.nxv32i16.i32(i32 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i32 [[VL:%.*]])491// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]492//493// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16m8(494// CHECK-RV64-NEXT: entry:495// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv32i16.i64.nxv32i16.nxv32i16.nxv32i16.i64(i64 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 [[VL:%.*]])496// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]497//498vuint16m8_t test_sf_vc_v_vvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) {499 return __riscv_sf_vc_v_vvv_se_u16m8(p27_26, vd, vs2, vs1, vl);500}501 502// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u32mf2(503// CHECK-RV32-NEXT: entry:504// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv1i32.i32.nxv1i32.nxv1i32.nxv1i32.i32(i32 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i32 [[VL:%.*]])505// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]506//507// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u32mf2(508// CHECK-RV64-NEXT: entry:509// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv1i32.i64.nxv1i32.nxv1i32.nxv1i32.i64(i64 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 [[VL:%.*]])510// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]511//512vuint32mf2_t test_sf_vc_v_vvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {513 return __riscv_sf_vc_v_vvv_se_u32mf2(p27_26, vd, vs2, vs1, vl);514}515 516// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u32m1(517// CHECK-RV32-NEXT: entry:518// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv2i32.i32.nxv2i32.nxv2i32.nxv2i32.i32(i32 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i32 [[VL:%.*]])519// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]520//521// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u32m1(522// CHECK-RV64-NEXT: entry:523// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv2i32.i64.nxv2i32.nxv2i32.nxv2i32.i64(i64 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 [[VL:%.*]])524// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]525//526vuint32m1_t test_sf_vc_v_vvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {527 return __riscv_sf_vc_v_vvv_se_u32m1(p27_26, vd, vs2, vs1, vl);528}529 530// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u32m2(531// CHECK-RV32-NEXT: entry:532// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv4i32.i32.nxv4i32.nxv4i32.nxv4i32.i32(i32 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i32 [[VL:%.*]])533// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]534//535// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u32m2(536// CHECK-RV64-NEXT: entry:537// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv4i32.i64.nxv4i32.nxv4i32.nxv4i32.i64(i64 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 [[VL:%.*]])538// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]539//540vuint32m2_t test_sf_vc_v_vvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {541 return __riscv_sf_vc_v_vvv_se_u32m2(p27_26, vd, vs2, vs1, vl);542}543 544// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u32m4(545// CHECK-RV32-NEXT: entry:546// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv8i32.i32.nxv8i32.nxv8i32.nxv8i32.i32(i32 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i32 [[VL:%.*]])547// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]548//549// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u32m4(550// CHECK-RV64-NEXT: entry:551// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv8i32.i64.nxv8i32.nxv8i32.nxv8i32.i64(i64 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 [[VL:%.*]])552// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]553//554vuint32m4_t test_sf_vc_v_vvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {555 return __riscv_sf_vc_v_vvv_se_u32m4(p27_26, vd, vs2, vs1, vl);556}557 558// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u32m8(559// CHECK-RV32-NEXT: entry:560// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv16i32.i32.nxv16i32.nxv16i32.nxv16i32.i32(i32 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i32 [[VL:%.*]])561// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]562//563// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u32m8(564// CHECK-RV64-NEXT: entry:565// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv16i32.i64.nxv16i32.nxv16i32.nxv16i32.i64(i64 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 [[VL:%.*]])566// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]567//568vuint32m8_t test_sf_vc_v_vvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) {569 return __riscv_sf_vc_v_vvv_se_u32m8(p27_26, vd, vs2, vs1, vl);570}571 572// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u64m1(573// CHECK-RV32-NEXT: entry:574// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv1i64.i32.nxv1i64.nxv1i64.nxv1i64.i32(i32 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i32 [[VL:%.*]])575// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]576//577// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u64m1(578// CHECK-RV64-NEXT: entry:579// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv1i64.i64.nxv1i64.nxv1i64.nxv1i64.i64(i64 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 [[VL:%.*]])580// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]581//582vuint64m1_t test_sf_vc_v_vvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {583 return __riscv_sf_vc_v_vvv_se_u64m1(p27_26, vd, vs2, vs1, vl);584}585 586// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u64m2(587// CHECK-RV32-NEXT: entry:588// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv2i64.i32.nxv2i64.nxv2i64.nxv2i64.i32(i32 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i32 [[VL:%.*]])589// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]590//591// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u64m2(592// CHECK-RV64-NEXT: entry:593// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv2i64.i64.nxv2i64.nxv2i64.nxv2i64.i64(i64 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 [[VL:%.*]])594// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]595//596vuint64m2_t test_sf_vc_v_vvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {597 return __riscv_sf_vc_v_vvv_se_u64m2(p27_26, vd, vs2, vs1, vl);598}599 600// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u64m4(601// CHECK-RV32-NEXT: entry:602// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv4i64.i32.nxv4i64.nxv4i64.nxv4i64.i32(i32 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i32 [[VL:%.*]])603// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]604//605// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u64m4(606// CHECK-RV64-NEXT: entry:607// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv4i64.i64.nxv4i64.nxv4i64.nxv4i64.i64(i64 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 [[VL:%.*]])608// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]609//610vuint64m4_t test_sf_vc_v_vvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {611 return __riscv_sf_vc_v_vvv_se_u64m4(p27_26, vd, vs2, vs1, vl);612}613 614// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u64m8(615// CHECK-RV32-NEXT: entry:616// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv8i64.i32.nxv8i64.nxv8i64.nxv8i64.i32(i32 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i32 [[VL:%.*]])617// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]618//619// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u64m8(620// CHECK-RV64-NEXT: entry:621// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv8i64.i64.nxv8i64.nxv8i64.nxv8i64.i64(i64 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 [[VL:%.*]])622// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]623//624vuint64m8_t test_sf_vc_v_vvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {625 return __riscv_sf_vc_v_vvv_se_u64m8(p27_26, vd, vs2, vs1, vl);626}627 628// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8mf8(629// CHECK-RV32-NEXT: entry:630// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vvv.nxv1i8.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i32 [[VL:%.*]])631// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]632//633// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8mf8(634// CHECK-RV64-NEXT: entry:635// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vvv.nxv1i8.i64.nxv1i8.nxv1i8.nxv1i8.i64(i64 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 [[VL:%.*]])636// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]637//638vuint8mf8_t test_sf_vc_v_vvv_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {639 return __riscv_sf_vc_v_vvv_u8mf8(p27_26, vd, vs2, vs1, vl);640}641 642// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8mf4(643// CHECK-RV32-NEXT: entry:644// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vvv.nxv2i8.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i32 [[VL:%.*]])645// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]646//647// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8mf4(648// CHECK-RV64-NEXT: entry:649// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vvv.nxv2i8.i64.nxv2i8.nxv2i8.nxv2i8.i64(i64 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 [[VL:%.*]])650// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]651//652vuint8mf4_t test_sf_vc_v_vvv_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) {653 return __riscv_sf_vc_v_vvv_u8mf4(p27_26, vd, vs2, vs1, vl);654}655 656// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8mf2(657// CHECK-RV32-NEXT: entry:658// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vvv.nxv4i8.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i32 [[VL:%.*]])659// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]660//661// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8mf2(662// CHECK-RV64-NEXT: entry:663// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vvv.nxv4i8.i64.nxv4i8.nxv4i8.nxv4i8.i64(i64 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 [[VL:%.*]])664// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]665//666vuint8mf2_t test_sf_vc_v_vvv_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) {667 return __riscv_sf_vc_v_vvv_u8mf2(p27_26, vd, vs2, vs1, vl);668}669 670// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8m1(671// CHECK-RV32-NEXT: entry:672// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vvv.nxv8i8.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i32 [[VL:%.*]])673// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]674//675// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8m1(676// CHECK-RV64-NEXT: entry:677// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vvv.nxv8i8.i64.nxv8i8.nxv8i8.nxv8i8.i64(i64 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 [[VL:%.*]])678// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]679//680vuint8m1_t test_sf_vc_v_vvv_u8m1(vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) {681 return __riscv_sf_vc_v_vvv_u8m1(p27_26, vd, vs2, vs1, vl);682}683 684// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8m2(685// CHECK-RV32-NEXT: entry:686// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vvv.nxv16i8.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i32 [[VL:%.*]])687// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]688//689// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8m2(690// CHECK-RV64-NEXT: entry:691// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vvv.nxv16i8.i64.nxv16i8.nxv16i8.nxv16i8.i64(i64 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 [[VL:%.*]])692// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]693//694vuint8m2_t test_sf_vc_v_vvv_u8m2(vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) {695 return __riscv_sf_vc_v_vvv_u8m2(p27_26, vd, vs2, vs1, vl);696}697 698// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8m4(699// CHECK-RV32-NEXT: entry:700// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vvv.nxv32i8.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i32 [[VL:%.*]])701// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]702//703// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8m4(704// CHECK-RV64-NEXT: entry:705// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vvv.nxv32i8.i64.nxv32i8.nxv32i8.nxv32i8.i64(i64 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 [[VL:%.*]])706// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]707//708vuint8m4_t test_sf_vc_v_vvv_u8m4(vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) {709 return __riscv_sf_vc_v_vvv_u8m4(p27_26, vd, vs2, vs1, vl);710}711 712// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8m8(713// CHECK-RV32-NEXT: entry:714// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vvv.nxv64i8.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i32 [[VL:%.*]])715// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]716//717// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8m8(718// CHECK-RV64-NEXT: entry:719// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vvv.nxv64i8.i64.nxv64i8.nxv64i8.nxv64i8.i64(i64 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 [[VL:%.*]])720// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]721//722vuint8m8_t test_sf_vc_v_vvv_u8m8(vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {723 return __riscv_sf_vc_v_vvv_u8m8(p27_26, vd, vs2, vs1, vl);724}725 726// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16mf4(727// CHECK-RV32-NEXT: entry:728// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vvv.nxv1i16.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i32 [[VL:%.*]])729// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]730//731// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16mf4(732// CHECK-RV64-NEXT: entry:733// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vvv.nxv1i16.i64.nxv1i16.nxv1i16.nxv1i16.i64(i64 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 [[VL:%.*]])734// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]735//736vuint16mf4_t test_sf_vc_v_vvv_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) {737 return __riscv_sf_vc_v_vvv_u16mf4(p27_26, vd, vs2, vs1, vl);738}739 740// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16mf2(741// CHECK-RV32-NEXT: entry:742// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vvv.nxv2i16.i32.nxv2i16.nxv2i16.nxv2i16.i32(i32 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i32 [[VL:%.*]])743// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]744//745// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16mf2(746// CHECK-RV64-NEXT: entry:747// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vvv.nxv2i16.i64.nxv2i16.nxv2i16.nxv2i16.i64(i64 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 [[VL:%.*]])748// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]749//750vuint16mf2_t test_sf_vc_v_vvv_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) {751 return __riscv_sf_vc_v_vvv_u16mf2(p27_26, vd, vs2, vs1, vl);752}753 754// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16m1(755// CHECK-RV32-NEXT: entry:756// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vvv.nxv4i16.i32.nxv4i16.nxv4i16.nxv4i16.i32(i32 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i32 [[VL:%.*]])757// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]758//759// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16m1(760// CHECK-RV64-NEXT: entry:761// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vvv.nxv4i16.i64.nxv4i16.nxv4i16.nxv4i16.i64(i64 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 [[VL:%.*]])762// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]763//764vuint16m1_t test_sf_vc_v_vvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) {765 return __riscv_sf_vc_v_vvv_u16m1(p27_26, vd, vs2, vs1, vl);766}767 768// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16m2(769// CHECK-RV32-NEXT: entry:770// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vvv.nxv8i16.i32.nxv8i16.nxv8i16.nxv8i16.i32(i32 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i32 [[VL:%.*]])771// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]772//773// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16m2(774// CHECK-RV64-NEXT: entry:775// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vvv.nxv8i16.i64.nxv8i16.nxv8i16.nxv8i16.i64(i64 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 [[VL:%.*]])776// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]777//778vuint16m2_t test_sf_vc_v_vvv_u16m2(vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) {779 return __riscv_sf_vc_v_vvv_u16m2(p27_26, vd, vs2, vs1, vl);780}781 782// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16m4(783// CHECK-RV32-NEXT: entry:784// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vvv.nxv16i16.i32.nxv16i16.nxv16i16.nxv16i16.i32(i32 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i32 [[VL:%.*]])785// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]786//787// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16m4(788// CHECK-RV64-NEXT: entry:789// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vvv.nxv16i16.i64.nxv16i16.nxv16i16.nxv16i16.i64(i64 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 [[VL:%.*]])790// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]791//792vuint16m4_t test_sf_vc_v_vvv_u16m4(vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) {793 return __riscv_sf_vc_v_vvv_u16m4(p27_26, vd, vs2, vs1, vl);794}795 796// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16m8(797// CHECK-RV32-NEXT: entry:798// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vvv.nxv32i16.i32.nxv32i16.nxv32i16.nxv32i16.i32(i32 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i32 [[VL:%.*]])799// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]800//801// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16m8(802// CHECK-RV64-NEXT: entry:803// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vvv.nxv32i16.i64.nxv32i16.nxv32i16.nxv32i16.i64(i64 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 [[VL:%.*]])804// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]805//806vuint16m8_t test_sf_vc_v_vvv_u16m8(vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) {807 return __riscv_sf_vc_v_vvv_u16m8(p27_26, vd, vs2, vs1, vl);808}809 810// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u32mf2(811// CHECK-RV32-NEXT: entry:812// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vvv.nxv1i32.i32.nxv1i32.nxv1i32.nxv1i32.i32(i32 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i32 [[VL:%.*]])813// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]814//815// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u32mf2(816// CHECK-RV64-NEXT: entry:817// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vvv.nxv1i32.i64.nxv1i32.nxv1i32.nxv1i32.i64(i64 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 [[VL:%.*]])818// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]819//820vuint32mf2_t test_sf_vc_v_vvv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) {821 return __riscv_sf_vc_v_vvv_u32mf2(p27_26, vd, vs2, vs1, vl);822}823 824// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u32m1(825// CHECK-RV32-NEXT: entry:826// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vvv.nxv2i32.i32.nxv2i32.nxv2i32.nxv2i32.i32(i32 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i32 [[VL:%.*]])827// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]828//829// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u32m1(830// CHECK-RV64-NEXT: entry:831// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vvv.nxv2i32.i64.nxv2i32.nxv2i32.nxv2i32.i64(i64 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 [[VL:%.*]])832// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]833//834vuint32m1_t test_sf_vc_v_vvv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {835 return __riscv_sf_vc_v_vvv_u32m1(p27_26, vd, vs2, vs1, vl);836}837 838// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u32m2(839// CHECK-RV32-NEXT: entry:840// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vvv.nxv4i32.i32.nxv4i32.nxv4i32.nxv4i32.i32(i32 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i32 [[VL:%.*]])841// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]842//843// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u32m2(844// CHECK-RV64-NEXT: entry:845// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vvv.nxv4i32.i64.nxv4i32.nxv4i32.nxv4i32.i64(i64 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 [[VL:%.*]])846// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]847//848vuint32m2_t test_sf_vc_v_vvv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) {849 return __riscv_sf_vc_v_vvv_u32m2(p27_26, vd, vs2, vs1, vl);850}851 852// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u32m4(853// CHECK-RV32-NEXT: entry:854// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vvv.nxv8i32.i32.nxv8i32.nxv8i32.nxv8i32.i32(i32 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i32 [[VL:%.*]])855// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]856//857// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u32m4(858// CHECK-RV64-NEXT: entry:859// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vvv.nxv8i32.i64.nxv8i32.nxv8i32.nxv8i32.i64(i64 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 [[VL:%.*]])860// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]861//862vuint32m4_t test_sf_vc_v_vvv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {863 return __riscv_sf_vc_v_vvv_u32m4(p27_26, vd, vs2, vs1, vl);864}865 866// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u32m8(867// CHECK-RV32-NEXT: entry:868// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vvv.nxv16i32.i32.nxv16i32.nxv16i32.nxv16i32.i32(i32 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i32 [[VL:%.*]])869// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]870//871// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u32m8(872// CHECK-RV64-NEXT: entry:873// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vvv.nxv16i32.i64.nxv16i32.nxv16i32.nxv16i32.i64(i64 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 [[VL:%.*]])874// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]875//876vuint32m8_t test_sf_vc_v_vvv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) {877 return __riscv_sf_vc_v_vvv_u32m8(p27_26, vd, vs2, vs1, vl);878}879 880// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u64m1(881// CHECK-RV32-NEXT: entry:882// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vvv.nxv1i64.i32.nxv1i64.nxv1i64.nxv1i64.i32(i32 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i32 [[VL:%.*]])883// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]884//885// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u64m1(886// CHECK-RV64-NEXT: entry:887// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vvv.nxv1i64.i64.nxv1i64.nxv1i64.nxv1i64.i64(i64 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 [[VL:%.*]])888// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]889//890vuint64m1_t test_sf_vc_v_vvv_u64m1(vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) {891 return __riscv_sf_vc_v_vvv_u64m1(p27_26, vd, vs2, vs1, vl);892}893 894// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u64m2(895// CHECK-RV32-NEXT: entry:896// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vvv.nxv2i64.i32.nxv2i64.nxv2i64.nxv2i64.i32(i32 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i32 [[VL:%.*]])897// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]898//899// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u64m2(900// CHECK-RV64-NEXT: entry:901// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vvv.nxv2i64.i64.nxv2i64.nxv2i64.nxv2i64.i64(i64 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 [[VL:%.*]])902// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]903//904vuint64m2_t test_sf_vc_v_vvv_u64m2(vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) {905 return __riscv_sf_vc_v_vvv_u64m2(p27_26, vd, vs2, vs1, vl);906}907 908// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u64m4(909// CHECK-RV32-NEXT: entry:910// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vvv.nxv4i64.i32.nxv4i64.nxv4i64.nxv4i64.i32(i32 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i32 [[VL:%.*]])911// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]912//913// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u64m4(914// CHECK-RV64-NEXT: entry:915// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vvv.nxv4i64.i64.nxv4i64.nxv4i64.nxv4i64.i64(i64 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 [[VL:%.*]])916// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]917//918vuint64m4_t test_sf_vc_v_vvv_u64m4(vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {919 return __riscv_sf_vc_v_vvv_u64m4(p27_26, vd, vs2, vs1, vl);920}921 922// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u64m8(923// CHECK-RV32-NEXT: entry:924// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vvv.nxv8i64.i32.nxv8i64.nxv8i64.nxv8i64.i32(i32 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i32 [[VL:%.*]])925// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]926//927// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u64m8(928// CHECK-RV64-NEXT: entry:929// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vvv.nxv8i64.i64.nxv8i64.nxv8i64.nxv8i64.i64(i64 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], <vscale x 8 x i64> [[VS1:%.*]], i64 [[VL:%.*]])930// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]931//932vuint64m8_t test_sf_vc_v_vvv_u64m8(vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) {933 return __riscv_sf_vc_v_vvv_u64m8(p27_26, vd, vs2, vs1, vl);934}935 936// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8mf8(937// CHECK-RV32-NEXT: entry:938// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv1i8.nxv1i8.i8.i32(i32 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])939// CHECK-RV32-NEXT: ret void940//941// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8mf8(942// CHECK-RV64-NEXT: entry:943// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i8.nxv1i8.i8.i64(i64 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])944// CHECK-RV64-NEXT: ret void945//946void test_sf_vc_xvv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {947 __riscv_sf_vc_xvv_se_u8mf8(p27_26, vd, vs2, rs1, vl);948}949 950// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8mf4(951// CHECK-RV32-NEXT: entry:952// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv2i8.nxv2i8.i8.i32(i32 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])953// CHECK-RV32-NEXT: ret void954//955// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8mf4(956// CHECK-RV64-NEXT: entry:957// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i8.nxv2i8.i8.i64(i64 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])958// CHECK-RV64-NEXT: ret void959//960void test_sf_vc_xvv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, uint8_t rs1, size_t vl) {961 __riscv_sf_vc_xvv_se_u8mf4(p27_26, vd, vs2, rs1, vl);962}963 964// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8mf2(965// CHECK-RV32-NEXT: entry:966// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv4i8.nxv4i8.i8.i32(i32 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])967// CHECK-RV32-NEXT: ret void968//969// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8mf2(970// CHECK-RV64-NEXT: entry:971// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i8.nxv4i8.i8.i64(i64 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])972// CHECK-RV64-NEXT: ret void973//974void test_sf_vc_xvv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, uint8_t rs1, size_t vl) {975 __riscv_sf_vc_xvv_se_u8mf2(p27_26, vd, vs2, rs1, vl);976}977 978// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8m1(979// CHECK-RV32-NEXT: entry:980// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv8i8.nxv8i8.i8.i32(i32 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])981// CHECK-RV32-NEXT: ret void982//983// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8m1(984// CHECK-RV64-NEXT: entry:985// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i8.nxv8i8.i8.i64(i64 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])986// CHECK-RV64-NEXT: ret void987//988void test_sf_vc_xvv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, uint8_t rs1, size_t vl) {989 __riscv_sf_vc_xvv_se_u8m1(p27_26, vd, vs2, rs1, vl);990}991 992// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8m2(993// CHECK-RV32-NEXT: entry:994// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv16i8.nxv16i8.i8.i32(i32 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])995// CHECK-RV32-NEXT: ret void996//997// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8m2(998// CHECK-RV64-NEXT: entry:999// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv16i8.nxv16i8.i8.i64(i64 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1000// CHECK-RV64-NEXT: ret void1001//1002void test_sf_vc_xvv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, uint8_t rs1, size_t vl) {1003 __riscv_sf_vc_xvv_se_u8m2(p27_26, vd, vs2, rs1, vl);1004}1005 1006// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8m4(1007// CHECK-RV32-NEXT: entry:1008// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv32i8.nxv32i8.i8.i32(i32 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1009// CHECK-RV32-NEXT: ret void1010//1011// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8m4(1012// CHECK-RV64-NEXT: entry:1013// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv32i8.nxv32i8.i8.i64(i64 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1014// CHECK-RV64-NEXT: ret void1015//1016void test_sf_vc_xvv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, uint8_t rs1, size_t vl) {1017 __riscv_sf_vc_xvv_se_u8m4(p27_26, vd, vs2, rs1, vl);1018}1019 1020// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8m8(1021// CHECK-RV32-NEXT: entry:1022// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv64i8.nxv64i8.i8.i32(i32 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1023// CHECK-RV32-NEXT: ret void1024//1025// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8m8(1026// CHECK-RV64-NEXT: entry:1027// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv64i8.nxv64i8.i8.i64(i64 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1028// CHECK-RV64-NEXT: ret void1029//1030void test_sf_vc_xvv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, uint8_t rs1, size_t vl) {1031 __riscv_sf_vc_xvv_se_u8m8(p27_26, vd, vs2, rs1, vl);1032}1033 1034// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16mf4(1035// CHECK-RV32-NEXT: entry:1036// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv1i16.nxv1i16.i16.i32(i32 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1037// CHECK-RV32-NEXT: ret void1038//1039// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16mf4(1040// CHECK-RV64-NEXT: entry:1041// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i16.nxv1i16.i16.i64(i64 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1042// CHECK-RV64-NEXT: ret void1043//1044void test_sf_vc_xvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, uint16_t rs1, size_t vl) {1045 __riscv_sf_vc_xvv_se_u16mf4(p27_26, vd, vs2, rs1, vl);1046}1047 1048// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16mf2(1049// CHECK-RV32-NEXT: entry:1050// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv2i16.nxv2i16.i16.i32(i32 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1051// CHECK-RV32-NEXT: ret void1052//1053// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16mf2(1054// CHECK-RV64-NEXT: entry:1055// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i16.nxv2i16.i16.i64(i64 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1056// CHECK-RV64-NEXT: ret void1057//1058void test_sf_vc_xvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, uint16_t rs1, size_t vl) {1059 __riscv_sf_vc_xvv_se_u16mf2(p27_26, vd, vs2, rs1, vl);1060}1061 1062// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16m1(1063// CHECK-RV32-NEXT: entry:1064// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv4i16.nxv4i16.i16.i32(i32 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1065// CHECK-RV32-NEXT: ret void1066//1067// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16m1(1068// CHECK-RV64-NEXT: entry:1069// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i16.nxv4i16.i16.i64(i64 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1070// CHECK-RV64-NEXT: ret void1071//1072void test_sf_vc_xvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t rs1, size_t vl) {1073 __riscv_sf_vc_xvv_se_u16m1(p27_26, vd, vs2, rs1, vl);1074}1075 1076// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16m2(1077// CHECK-RV32-NEXT: entry:1078// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv8i16.nxv8i16.i16.i32(i32 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1079// CHECK-RV32-NEXT: ret void1080//1081// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16m2(1082// CHECK-RV64-NEXT: entry:1083// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i16.nxv8i16.i16.i64(i64 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1084// CHECK-RV64-NEXT: ret void1085//1086void test_sf_vc_xvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, uint16_t rs1, size_t vl) {1087 __riscv_sf_vc_xvv_se_u16m2(p27_26, vd, vs2, rs1, vl);1088}1089 1090// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16m4(1091// CHECK-RV32-NEXT: entry:1092// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv16i16.nxv16i16.i16.i32(i32 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1093// CHECK-RV32-NEXT: ret void1094//1095// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16m4(1096// CHECK-RV64-NEXT: entry:1097// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv16i16.nxv16i16.i16.i64(i64 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1098// CHECK-RV64-NEXT: ret void1099//1100void test_sf_vc_xvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, uint16_t rs1, size_t vl) {1101 __riscv_sf_vc_xvv_se_u16m4(p27_26, vd, vs2, rs1, vl);1102}1103 1104// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16m8(1105// CHECK-RV32-NEXT: entry:1106// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv32i16.nxv32i16.i16.i32(i32 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1107// CHECK-RV32-NEXT: ret void1108//1109// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16m8(1110// CHECK-RV64-NEXT: entry:1111// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv32i16.nxv32i16.i16.i64(i64 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1112// CHECK-RV64-NEXT: ret void1113//1114void test_sf_vc_xvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, uint16_t rs1, size_t vl) {1115 __riscv_sf_vc_xvv_se_u16m8(p27_26, vd, vs2, rs1, vl);1116}1117 1118// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u32mf2(1119// CHECK-RV32-NEXT: entry:1120// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv1i32.nxv1i32.i32.i32(i32 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1121// CHECK-RV32-NEXT: ret void1122//1123// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u32mf2(1124// CHECK-RV64-NEXT: entry:1125// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i32.nxv1i32.i32.i64(i64 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1126// CHECK-RV64-NEXT: ret void1127//1128void test_sf_vc_xvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) {1129 __riscv_sf_vc_xvv_se_u32mf2(p27_26, vd, vs2, rs1, vl);1130}1131 1132// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u32m1(1133// CHECK-RV32-NEXT: entry:1134// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv2i32.nxv2i32.i32.i32(i32 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1135// CHECK-RV32-NEXT: ret void1136//1137// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u32m1(1138// CHECK-RV64-NEXT: entry:1139// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i32.nxv2i32.i32.i64(i64 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1140// CHECK-RV64-NEXT: ret void1141//1142void test_sf_vc_xvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) {1143 __riscv_sf_vc_xvv_se_u32m1(p27_26, vd, vs2, rs1, vl);1144}1145 1146// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u32m2(1147// CHECK-RV32-NEXT: entry:1148// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv4i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1149// CHECK-RV32-NEXT: ret void1150//1151// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u32m2(1152// CHECK-RV64-NEXT: entry:1153// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i32.nxv4i32.i32.i64(i64 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1154// CHECK-RV64-NEXT: ret void1155//1156void test_sf_vc_xvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) {1157 __riscv_sf_vc_xvv_se_u32m2(p27_26, vd, vs2, rs1, vl);1158}1159 1160// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u32m4(1161// CHECK-RV32-NEXT: entry:1162// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv8i32.nxv8i32.i32.i32(i32 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1163// CHECK-RV32-NEXT: ret void1164//1165// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u32m4(1166// CHECK-RV64-NEXT: entry:1167// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i32.nxv8i32.i32.i64(i64 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1168// CHECK-RV64-NEXT: ret void1169//1170void test_sf_vc_xvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) {1171 __riscv_sf_vc_xvv_se_u32m4(p27_26, vd, vs2, rs1, vl);1172}1173 1174// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u32m8(1175// CHECK-RV32-NEXT: entry:1176// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv16i32.nxv16i32.i32.i32(i32 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1177// CHECK-RV32-NEXT: ret void1178//1179// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u32m8(1180// CHECK-RV64-NEXT: entry:1181// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv16i32.nxv16i32.i32.i64(i64 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1182// CHECK-RV64-NEXT: ret void1183//1184void test_sf_vc_xvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1, size_t vl) {1185 __riscv_sf_vc_xvv_se_u32m8(p27_26, vd, vs2, rs1, vl);1186}1187 1188// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8mf8(1189// CHECK-RV32-NEXT: entry:1190// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv1i8.i32.nxv1i8.nxv1i8.i8.i32(i32 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1191// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]1192//1193// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8mf8(1194// CHECK-RV64-NEXT: entry:1195// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv1i8.i64.nxv1i8.nxv1i8.i8.i64(i64 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1196// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1197//1198vuint8mf8_t test_sf_vc_v_xvv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {1199 return __riscv_sf_vc_v_xvv_se_u8mf8(p27_26, vd, vs2, rs1, vl);1200}1201 1202// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8mf4(1203// CHECK-RV32-NEXT: entry:1204// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv2i8.i32.nxv2i8.nxv2i8.i8.i32(i32 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1205// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]1206//1207// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8mf4(1208// CHECK-RV64-NEXT: entry:1209// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv2i8.i64.nxv2i8.nxv2i8.i8.i64(i64 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1210// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1211//1212vuint8mf4_t test_sf_vc_v_xvv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, uint8_t rs1, size_t vl) {1213 return __riscv_sf_vc_v_xvv_se_u8mf4(p27_26, vd, vs2, rs1, vl);1214}1215 1216// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8mf2(1217// CHECK-RV32-NEXT: entry:1218// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv4i8.i32.nxv4i8.nxv4i8.i8.i32(i32 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1219// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]1220//1221// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8mf2(1222// CHECK-RV64-NEXT: entry:1223// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv4i8.i64.nxv4i8.nxv4i8.i8.i64(i64 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1224// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1225//1226vuint8mf2_t test_sf_vc_v_xvv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, uint8_t rs1, size_t vl) {1227 return __riscv_sf_vc_v_xvv_se_u8mf2(p27_26, vd, vs2, rs1, vl);1228}1229 1230// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8m1(1231// CHECK-RV32-NEXT: entry:1232// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv8i8.i32.nxv8i8.nxv8i8.i8.i32(i32 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1233// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]1234//1235// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8m1(1236// CHECK-RV64-NEXT: entry:1237// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv8i8.i64.nxv8i8.nxv8i8.i8.i64(i64 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1238// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1239//1240vuint8m1_t test_sf_vc_v_xvv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, uint8_t rs1, size_t vl) {1241 return __riscv_sf_vc_v_xvv_se_u8m1(p27_26, vd, vs2, rs1, vl);1242}1243 1244// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8m2(1245// CHECK-RV32-NEXT: entry:1246// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv16i8.i32.nxv16i8.nxv16i8.i8.i32(i32 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1247// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]1248//1249// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8m2(1250// CHECK-RV64-NEXT: entry:1251// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv16i8.i64.nxv16i8.nxv16i8.i8.i64(i64 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1252// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1253//1254vuint8m2_t test_sf_vc_v_xvv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, uint8_t rs1, size_t vl) {1255 return __riscv_sf_vc_v_xvv_se_u8m2(p27_26, vd, vs2, rs1, vl);1256}1257 1258// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8m4(1259// CHECK-RV32-NEXT: entry:1260// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv32i8.i32.nxv32i8.nxv32i8.i8.i32(i32 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1261// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]1262//1263// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8m4(1264// CHECK-RV64-NEXT: entry:1265// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv32i8.i64.nxv32i8.nxv32i8.i8.i64(i64 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1266// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1267//1268vuint8m4_t test_sf_vc_v_xvv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, uint8_t rs1, size_t vl) {1269 return __riscv_sf_vc_v_xvv_se_u8m4(p27_26, vd, vs2, rs1, vl);1270}1271 1272// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8m8(1273// CHECK-RV32-NEXT: entry:1274// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv64i8.i32.nxv64i8.nxv64i8.i8.i32(i32 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1275// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]1276//1277// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8m8(1278// CHECK-RV64-NEXT: entry:1279// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv64i8.i64.nxv64i8.nxv64i8.i8.i64(i64 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1280// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1281//1282vuint8m8_t test_sf_vc_v_xvv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, uint8_t rs1, size_t vl) {1283 return __riscv_sf_vc_v_xvv_se_u8m8(p27_26, vd, vs2, rs1, vl);1284}1285 1286// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16mf4(1287// CHECK-RV32-NEXT: entry:1288// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv1i16.i32.nxv1i16.nxv1i16.i16.i32(i32 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1289// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]1290//1291// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16mf4(1292// CHECK-RV64-NEXT: entry:1293// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv1i16.i64.nxv1i16.nxv1i16.i16.i64(i64 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1294// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1295//1296vuint16mf4_t test_sf_vc_v_xvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, uint16_t rs1, size_t vl) {1297 return __riscv_sf_vc_v_xvv_se_u16mf4(p27_26, vd, vs2, rs1, vl);1298}1299 1300// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16mf2(1301// CHECK-RV32-NEXT: entry:1302// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv2i16.i32.nxv2i16.nxv2i16.i16.i32(i32 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1303// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]1304//1305// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16mf2(1306// CHECK-RV64-NEXT: entry:1307// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv2i16.i64.nxv2i16.nxv2i16.i16.i64(i64 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1308// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1309//1310vuint16mf2_t test_sf_vc_v_xvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, uint16_t rs1, size_t vl) {1311 return __riscv_sf_vc_v_xvv_se_u16mf2(p27_26, vd, vs2, rs1, vl);1312}1313 1314// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16m1(1315// CHECK-RV32-NEXT: entry:1316// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv4i16.i32.nxv4i16.nxv4i16.i16.i32(i32 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1317// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]1318//1319// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16m1(1320// CHECK-RV64-NEXT: entry:1321// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv4i16.i64.nxv4i16.nxv4i16.i16.i64(i64 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1322// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1323//1324vuint16m1_t test_sf_vc_v_xvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t rs1, size_t vl) {1325 return __riscv_sf_vc_v_xvv_se_u16m1(p27_26, vd, vs2, rs1, vl);1326}1327 1328// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16m2(1329// CHECK-RV32-NEXT: entry:1330// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv8i16.i32.nxv8i16.nxv8i16.i16.i32(i32 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1331// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]1332//1333// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16m2(1334// CHECK-RV64-NEXT: entry:1335// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv8i16.i64.nxv8i16.nxv8i16.i16.i64(i64 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1336// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1337//1338vuint16m2_t test_sf_vc_v_xvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, uint16_t rs1, size_t vl) {1339 return __riscv_sf_vc_v_xvv_se_u16m2(p27_26, vd, vs2, rs1, vl);1340}1341 1342// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16m4(1343// CHECK-RV32-NEXT: entry:1344// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv16i16.i32.nxv16i16.nxv16i16.i16.i32(i32 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1345// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]1346//1347// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16m4(1348// CHECK-RV64-NEXT: entry:1349// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv16i16.i64.nxv16i16.nxv16i16.i16.i64(i64 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1350// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1351//1352vuint16m4_t test_sf_vc_v_xvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, uint16_t rs1, size_t vl) {1353 return __riscv_sf_vc_v_xvv_se_u16m4(p27_26, vd, vs2, rs1, vl);1354}1355 1356// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16m8(1357// CHECK-RV32-NEXT: entry:1358// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv32i16.i32.nxv32i16.nxv32i16.i16.i32(i32 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1359// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]1360//1361// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16m8(1362// CHECK-RV64-NEXT: entry:1363// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv32i16.i64.nxv32i16.nxv32i16.i16.i64(i64 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1364// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1365//1366vuint16m8_t test_sf_vc_v_xvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, uint16_t rs1, size_t vl) {1367 return __riscv_sf_vc_v_xvv_se_u16m8(p27_26, vd, vs2, rs1, vl);1368}1369 1370// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u32mf2(1371// CHECK-RV32-NEXT: entry:1372// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv1i32.i32.nxv1i32.nxv1i32.i32.i32(i32 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1373// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]1374//1375// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u32mf2(1376// CHECK-RV64-NEXT: entry:1377// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv1i32.i64.nxv1i32.nxv1i32.i32.i64(i64 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1378// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1379//1380vuint32mf2_t test_sf_vc_v_xvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) {1381 return __riscv_sf_vc_v_xvv_se_u32mf2(p27_26, vd, vs2, rs1, vl);1382}1383 1384// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u32m1(1385// CHECK-RV32-NEXT: entry:1386// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv2i32.i32.nxv2i32.nxv2i32.i32.i32(i32 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1387// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]1388//1389// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u32m1(1390// CHECK-RV64-NEXT: entry:1391// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv2i32.i64.nxv2i32.nxv2i32.i32.i64(i64 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1392// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1393//1394vuint32m1_t test_sf_vc_v_xvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) {1395 return __riscv_sf_vc_v_xvv_se_u32m1(p27_26, vd, vs2, rs1, vl);1396}1397 1398// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u32m2(1399// CHECK-RV32-NEXT: entry:1400// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv4i32.i32.nxv4i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1401// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]1402//1403// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u32m2(1404// CHECK-RV64-NEXT: entry:1405// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv4i32.i64.nxv4i32.nxv4i32.i32.i64(i64 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1406// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1407//1408vuint32m2_t test_sf_vc_v_xvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) {1409 return __riscv_sf_vc_v_xvv_se_u32m2(p27_26, vd, vs2, rs1, vl);1410}1411 1412// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u32m4(1413// CHECK-RV32-NEXT: entry:1414// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv8i32.i32.nxv8i32.nxv8i32.i32.i32(i32 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1415// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]1416//1417// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u32m4(1418// CHECK-RV64-NEXT: entry:1419// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv8i32.i64.nxv8i32.nxv8i32.i32.i64(i64 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1420// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1421//1422vuint32m4_t test_sf_vc_v_xvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) {1423 return __riscv_sf_vc_v_xvv_se_u32m4(p27_26, vd, vs2, rs1, vl);1424}1425 1426// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u32m8(1427// CHECK-RV32-NEXT: entry:1428// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv16i32.i32.nxv16i32.nxv16i32.i32.i32(i32 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1429// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]1430//1431// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u32m8(1432// CHECK-RV64-NEXT: entry:1433// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv16i32.i64.nxv16i32.nxv16i32.i32.i64(i64 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1434// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1435//1436vuint32m8_t test_sf_vc_v_xvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1, size_t vl) {1437 return __riscv_sf_vc_v_xvv_se_u32m8(p27_26, vd, vs2, rs1, vl);1438}1439 1440// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8mf8(1441// CHECK-RV32-NEXT: entry:1442// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xvv.nxv1i8.i32.nxv1i8.nxv1i8.i8.i32(i32 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1443// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]1444//1445// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8mf8(1446// CHECK-RV64-NEXT: entry:1447// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xvv.nxv1i8.i64.nxv1i8.nxv1i8.i8.i64(i64 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1448// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]1449//1450vuint8mf8_t test_sf_vc_v_xvv_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {1451 return __riscv_sf_vc_v_xvv_u8mf8(p27_26, vd, vs2, rs1, vl);1452}1453 1454// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8mf4(1455// CHECK-RV32-NEXT: entry:1456// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xvv.nxv2i8.i32.nxv2i8.nxv2i8.i8.i32(i32 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1457// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]1458//1459// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8mf4(1460// CHECK-RV64-NEXT: entry:1461// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xvv.nxv2i8.i64.nxv2i8.nxv2i8.i8.i64(i64 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1462// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]1463//1464vuint8mf4_t test_sf_vc_v_xvv_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, uint8_t rs1, size_t vl) {1465 return __riscv_sf_vc_v_xvv_u8mf4(p27_26, vd, vs2, rs1, vl);1466}1467 1468// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8mf2(1469// CHECK-RV32-NEXT: entry:1470// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xvv.nxv4i8.i32.nxv4i8.nxv4i8.i8.i32(i32 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1471// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]1472//1473// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8mf2(1474// CHECK-RV64-NEXT: entry:1475// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xvv.nxv4i8.i64.nxv4i8.nxv4i8.i8.i64(i64 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1476// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]1477//1478vuint8mf2_t test_sf_vc_v_xvv_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, uint8_t rs1, size_t vl) {1479 return __riscv_sf_vc_v_xvv_u8mf2(p27_26, vd, vs2, rs1, vl);1480}1481 1482// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8m1(1483// CHECK-RV32-NEXT: entry:1484// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xvv.nxv8i8.i32.nxv8i8.nxv8i8.i8.i32(i32 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1485// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]1486//1487// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8m1(1488// CHECK-RV64-NEXT: entry:1489// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xvv.nxv8i8.i64.nxv8i8.nxv8i8.i8.i64(i64 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1490// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]1491//1492vuint8m1_t test_sf_vc_v_xvv_u8m1(vuint8m1_t vd, vuint8m1_t vs2, uint8_t rs1, size_t vl) {1493 return __riscv_sf_vc_v_xvv_u8m1(p27_26, vd, vs2, rs1, vl);1494}1495 1496// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8m2(1497// CHECK-RV32-NEXT: entry:1498// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xvv.nxv16i8.i32.nxv16i8.nxv16i8.i8.i32(i32 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1499// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]1500//1501// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8m2(1502// CHECK-RV64-NEXT: entry:1503// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xvv.nxv16i8.i64.nxv16i8.nxv16i8.i8.i64(i64 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1504// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]1505//1506vuint8m2_t test_sf_vc_v_xvv_u8m2(vuint8m2_t vd, vuint8m2_t vs2, uint8_t rs1, size_t vl) {1507 return __riscv_sf_vc_v_xvv_u8m2(p27_26, vd, vs2, rs1, vl);1508}1509 1510// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8m4(1511// CHECK-RV32-NEXT: entry:1512// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xvv.nxv32i8.i32.nxv32i8.nxv32i8.i8.i32(i32 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1513// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]1514//1515// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8m4(1516// CHECK-RV64-NEXT: entry:1517// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xvv.nxv32i8.i64.nxv32i8.nxv32i8.i8.i64(i64 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1518// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]1519//1520vuint8m4_t test_sf_vc_v_xvv_u8m4(vuint8m4_t vd, vuint8m4_t vs2, uint8_t rs1, size_t vl) {1521 return __riscv_sf_vc_v_xvv_u8m4(p27_26, vd, vs2, rs1, vl);1522}1523 1524// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8m8(1525// CHECK-RV32-NEXT: entry:1526// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xvv.nxv64i8.i32.nxv64i8.nxv64i8.i8.i32(i32 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]])1527// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]1528//1529// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8m8(1530// CHECK-RV64-NEXT: entry:1531// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xvv.nxv64i8.i64.nxv64i8.nxv64i8.i8.i64(i64 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]])1532// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]1533//1534vuint8m8_t test_sf_vc_v_xvv_u8m8(vuint8m8_t vd, vuint8m8_t vs2, uint8_t rs1, size_t vl) {1535 return __riscv_sf_vc_v_xvv_u8m8(p27_26, vd, vs2, rs1, vl);1536}1537 1538// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16mf4(1539// CHECK-RV32-NEXT: entry:1540// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xvv.nxv1i16.i32.nxv1i16.nxv1i16.i16.i32(i32 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1541// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]1542//1543// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16mf4(1544// CHECK-RV64-NEXT: entry:1545// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xvv.nxv1i16.i64.nxv1i16.nxv1i16.i16.i64(i64 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1546// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]1547//1548vuint16mf4_t test_sf_vc_v_xvv_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, uint16_t rs1, size_t vl) {1549 return __riscv_sf_vc_v_xvv_u16mf4(p27_26, vd, vs2, rs1, vl);1550}1551 1552// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16mf2(1553// CHECK-RV32-NEXT: entry:1554// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xvv.nxv2i16.i32.nxv2i16.nxv2i16.i16.i32(i32 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1555// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]1556//1557// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16mf2(1558// CHECK-RV64-NEXT: entry:1559// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xvv.nxv2i16.i64.nxv2i16.nxv2i16.i16.i64(i64 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1560// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]1561//1562vuint16mf2_t test_sf_vc_v_xvv_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, uint16_t rs1, size_t vl) {1563 return __riscv_sf_vc_v_xvv_u16mf2(p27_26, vd, vs2, rs1, vl);1564}1565 1566// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16m1(1567// CHECK-RV32-NEXT: entry:1568// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xvv.nxv4i16.i32.nxv4i16.nxv4i16.i16.i32(i32 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1569// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]1570//1571// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16m1(1572// CHECK-RV64-NEXT: entry:1573// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xvv.nxv4i16.i64.nxv4i16.nxv4i16.i16.i64(i64 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1574// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]1575//1576vuint16m1_t test_sf_vc_v_xvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t rs1, size_t vl) {1577 return __riscv_sf_vc_v_xvv_u16m1(p27_26, vd, vs2, rs1, vl);1578}1579 1580// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16m2(1581// CHECK-RV32-NEXT: entry:1582// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xvv.nxv8i16.i32.nxv8i16.nxv8i16.i16.i32(i32 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1583// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]1584//1585// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16m2(1586// CHECK-RV64-NEXT: entry:1587// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xvv.nxv8i16.i64.nxv8i16.nxv8i16.i16.i64(i64 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1588// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]1589//1590vuint16m2_t test_sf_vc_v_xvv_u16m2(vuint16m2_t vd, vuint16m2_t vs2, uint16_t rs1, size_t vl) {1591 return __riscv_sf_vc_v_xvv_u16m2(p27_26, vd, vs2, rs1, vl);1592}1593 1594// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16m4(1595// CHECK-RV32-NEXT: entry:1596// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xvv.nxv16i16.i32.nxv16i16.nxv16i16.i16.i32(i32 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1597// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]1598//1599// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16m4(1600// CHECK-RV64-NEXT: entry:1601// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xvv.nxv16i16.i64.nxv16i16.nxv16i16.i16.i64(i64 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1602// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]1603//1604vuint16m4_t test_sf_vc_v_xvv_u16m4(vuint16m4_t vd, vuint16m4_t vs2, uint16_t rs1, size_t vl) {1605 return __riscv_sf_vc_v_xvv_u16m4(p27_26, vd, vs2, rs1, vl);1606}1607 1608// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16m8(1609// CHECK-RV32-NEXT: entry:1610// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xvv.nxv32i16.i32.nxv32i16.nxv32i16.i16.i32(i32 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]])1611// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]1612//1613// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16m8(1614// CHECK-RV64-NEXT: entry:1615// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xvv.nxv32i16.i64.nxv32i16.nxv32i16.i16.i64(i64 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]])1616// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]1617//1618vuint16m8_t test_sf_vc_v_xvv_u16m8(vuint16m8_t vd, vuint16m8_t vs2, uint16_t rs1, size_t vl) {1619 return __riscv_sf_vc_v_xvv_u16m8(p27_26, vd, vs2, rs1, vl);1620}1621 1622// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u32mf2(1623// CHECK-RV32-NEXT: entry:1624// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xvv.nxv1i32.i32.nxv1i32.nxv1i32.i32.i32(i32 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1625// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]1626//1627// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u32mf2(1628// CHECK-RV64-NEXT: entry:1629// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xvv.nxv1i32.i64.nxv1i32.nxv1i32.i32.i64(i64 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1630// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]1631//1632vuint32mf2_t test_sf_vc_v_xvv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) {1633 return __riscv_sf_vc_v_xvv_u32mf2(p27_26, vd, vs2, rs1, vl);1634}1635 1636// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u32m1(1637// CHECK-RV32-NEXT: entry:1638// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xvv.nxv2i32.i32.nxv2i32.nxv2i32.i32.i32(i32 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1639// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]1640//1641// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u32m1(1642// CHECK-RV64-NEXT: entry:1643// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xvv.nxv2i32.i64.nxv2i32.nxv2i32.i32.i64(i64 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1644// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]1645//1646vuint32m1_t test_sf_vc_v_xvv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) {1647 return __riscv_sf_vc_v_xvv_u32m1(p27_26, vd, vs2, rs1, vl);1648}1649 1650// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u32m2(1651// CHECK-RV32-NEXT: entry:1652// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xvv.nxv4i32.i32.nxv4i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1653// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]1654//1655// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u32m2(1656// CHECK-RV64-NEXT: entry:1657// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xvv.nxv4i32.i64.nxv4i32.nxv4i32.i32.i64(i64 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1658// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]1659//1660vuint32m2_t test_sf_vc_v_xvv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) {1661 return __riscv_sf_vc_v_xvv_u32m2(p27_26, vd, vs2, rs1, vl);1662}1663 1664// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u32m4(1665// CHECK-RV32-NEXT: entry:1666// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xvv.nxv8i32.i32.nxv8i32.nxv8i32.i32.i32(i32 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1667// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]1668//1669// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u32m4(1670// CHECK-RV64-NEXT: entry:1671// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xvv.nxv8i32.i64.nxv8i32.nxv8i32.i32.i64(i64 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1672// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]1673//1674vuint32m4_t test_sf_vc_v_xvv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) {1675 return __riscv_sf_vc_v_xvv_u32m4(p27_26, vd, vs2, rs1, vl);1676}1677 1678// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u32m8(1679// CHECK-RV32-NEXT: entry:1680// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xvv.nxv16i32.i32.nxv16i32.nxv16i32.i32.i32(i32 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]])1681// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]1682//1683// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u32m8(1684// CHECK-RV64-NEXT: entry:1685// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xvv.nxv16i32.i64.nxv16i32.nxv16i32.i32.i64(i64 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]])1686// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]1687//1688vuint32m8_t test_sf_vc_v_xvv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1, size_t vl) {1689 return __riscv_sf_vc_v_xvv_u32m8(p27_26, vd, vs2, rs1, vl);1690}1691 1692// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8mf8(1693// CHECK-RV32-NEXT: entry:1694// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv1i8.nxv1i8.i32.i32(i32 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1695// CHECK-RV32-NEXT: ret void1696//1697// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8mf8(1698// CHECK-RV64-NEXT: entry:1699// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv1i8.nxv1i8.i64.i64(i64 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1700// CHECK-RV64-NEXT: ret void1701//1702void test_sf_vc_ivv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) {1703 __riscv_sf_vc_ivv_se_u8mf8(p27_26, vd, vs2, simm5, vl);1704}1705 1706// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8mf4(1707// CHECK-RV32-NEXT: entry:1708// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv2i8.nxv2i8.i32.i32(i32 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1709// CHECK-RV32-NEXT: ret void1710//1711// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8mf4(1712// CHECK-RV64-NEXT: entry:1713// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv2i8.nxv2i8.i64.i64(i64 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1714// CHECK-RV64-NEXT: ret void1715//1716void test_sf_vc_ivv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, size_t vl) {1717 __riscv_sf_vc_ivv_se_u8mf4(p27_26, vd, vs2, simm5, vl);1718}1719 1720// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8mf2(1721// CHECK-RV32-NEXT: entry:1722// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv4i8.nxv4i8.i32.i32(i32 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1723// CHECK-RV32-NEXT: ret void1724//1725// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8mf2(1726// CHECK-RV64-NEXT: entry:1727// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv4i8.nxv4i8.i64.i64(i64 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1728// CHECK-RV64-NEXT: ret void1729//1730void test_sf_vc_ivv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, size_t vl) {1731 __riscv_sf_vc_ivv_se_u8mf2(p27_26, vd, vs2, simm5, vl);1732}1733 1734// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8m1(1735// CHECK-RV32-NEXT: entry:1736// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv8i8.nxv8i8.i32.i32(i32 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1737// CHECK-RV32-NEXT: ret void1738//1739// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8m1(1740// CHECK-RV64-NEXT: entry:1741// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv8i8.nxv8i8.i64.i64(i64 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1742// CHECK-RV64-NEXT: ret void1743//1744void test_sf_vc_ivv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, size_t vl) {1745 __riscv_sf_vc_ivv_se_u8m1(p27_26, vd, vs2, simm5, vl);1746}1747 1748// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8m2(1749// CHECK-RV32-NEXT: entry:1750// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv16i8.nxv16i8.i32.i32(i32 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1751// CHECK-RV32-NEXT: ret void1752//1753// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8m2(1754// CHECK-RV64-NEXT: entry:1755// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv16i8.nxv16i8.i64.i64(i64 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1756// CHECK-RV64-NEXT: ret void1757//1758void test_sf_vc_ivv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, size_t vl) {1759 __riscv_sf_vc_ivv_se_u8m2(p27_26, vd, vs2, simm5, vl);1760}1761 1762// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8m4(1763// CHECK-RV32-NEXT: entry:1764// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv32i8.nxv32i8.i32.i32(i32 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1765// CHECK-RV32-NEXT: ret void1766//1767// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8m4(1768// CHECK-RV64-NEXT: entry:1769// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv32i8.nxv32i8.i64.i64(i64 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1770// CHECK-RV64-NEXT: ret void1771//1772void test_sf_vc_ivv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, size_t vl) {1773 __riscv_sf_vc_ivv_se_u8m4(p27_26, vd, vs2, simm5, vl);1774}1775 1776// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8m8(1777// CHECK-RV32-NEXT: entry:1778// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv64i8.nxv64i8.i32.i32(i32 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1779// CHECK-RV32-NEXT: ret void1780//1781// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8m8(1782// CHECK-RV64-NEXT: entry:1783// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv64i8.nxv64i8.i64.i64(i64 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1784// CHECK-RV64-NEXT: ret void1785//1786void test_sf_vc_ivv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) {1787 __riscv_sf_vc_ivv_se_u8m8(p27_26, vd, vs2, simm5, vl);1788}1789 1790// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16mf4(1791// CHECK-RV32-NEXT: entry:1792// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv1i16.nxv1i16.i32.i32(i32 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1793// CHECK-RV32-NEXT: ret void1794//1795// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16mf4(1796// CHECK-RV64-NEXT: entry:1797// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv1i16.nxv1i16.i64.i64(i64 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1798// CHECK-RV64-NEXT: ret void1799//1800void test_sf_vc_ivv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, size_t vl) {1801 __riscv_sf_vc_ivv_se_u16mf4(p27_26, vd, vs2, simm5, vl);1802}1803 1804// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16mf2(1805// CHECK-RV32-NEXT: entry:1806// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv2i16.nxv2i16.i32.i32(i32 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1807// CHECK-RV32-NEXT: ret void1808//1809// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16mf2(1810// CHECK-RV64-NEXT: entry:1811// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv2i16.nxv2i16.i64.i64(i64 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1812// CHECK-RV64-NEXT: ret void1813//1814void test_sf_vc_ivv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, size_t vl) {1815 __riscv_sf_vc_ivv_se_u16mf2(p27_26, vd, vs2, simm5, vl);1816}1817 1818// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16m1(1819// CHECK-RV32-NEXT: entry:1820// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv4i16.nxv4i16.i32.i32(i32 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1821// CHECK-RV32-NEXT: ret void1822//1823// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16m1(1824// CHECK-RV64-NEXT: entry:1825// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv4i16.nxv4i16.i64.i64(i64 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1826// CHECK-RV64-NEXT: ret void1827//1828void test_sf_vc_ivv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, size_t vl) {1829 __riscv_sf_vc_ivv_se_u16m1(p27_26, vd, vs2, simm5, vl);1830}1831 1832// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16m2(1833// CHECK-RV32-NEXT: entry:1834// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv8i16.nxv8i16.i32.i32(i32 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1835// CHECK-RV32-NEXT: ret void1836//1837// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16m2(1838// CHECK-RV64-NEXT: entry:1839// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv8i16.nxv8i16.i64.i64(i64 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1840// CHECK-RV64-NEXT: ret void1841//1842void test_sf_vc_ivv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, size_t vl) {1843 __riscv_sf_vc_ivv_se_u16m2(p27_26, vd, vs2, simm5, vl);1844}1845 1846// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16m4(1847// CHECK-RV32-NEXT: entry:1848// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv16i16.nxv16i16.i32.i32(i32 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1849// CHECK-RV32-NEXT: ret void1850//1851// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16m4(1852// CHECK-RV64-NEXT: entry:1853// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv16i16.nxv16i16.i64.i64(i64 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1854// CHECK-RV64-NEXT: ret void1855//1856void test_sf_vc_ivv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, size_t vl) {1857 __riscv_sf_vc_ivv_se_u16m4(p27_26, vd, vs2, simm5, vl);1858}1859 1860// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16m8(1861// CHECK-RV32-NEXT: entry:1862// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv32i16.nxv32i16.i32.i32(i32 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1863// CHECK-RV32-NEXT: ret void1864//1865// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16m8(1866// CHECK-RV64-NEXT: entry:1867// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv32i16.nxv32i16.i64.i64(i64 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1868// CHECK-RV64-NEXT: ret void1869//1870void test_sf_vc_ivv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, size_t vl) {1871 __riscv_sf_vc_ivv_se_u16m8(p27_26, vd, vs2, simm5, vl);1872}1873 1874// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u32mf2(1875// CHECK-RV32-NEXT: entry:1876// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv1i32.nxv1i32.i32.i32(i32 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1877// CHECK-RV32-NEXT: ret void1878//1879// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u32mf2(1880// CHECK-RV64-NEXT: entry:1881// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv1i32.nxv1i32.i64.i64(i64 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1882// CHECK-RV64-NEXT: ret void1883//1884void test_sf_vc_ivv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) {1885 __riscv_sf_vc_ivv_se_u32mf2(p27_26, vd, vs2, simm5, vl);1886}1887 1888// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u32m1(1889// CHECK-RV32-NEXT: entry:1890// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv2i32.nxv2i32.i32.i32(i32 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1891// CHECK-RV32-NEXT: ret void1892//1893// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u32m1(1894// CHECK-RV64-NEXT: entry:1895// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv2i32.nxv2i32.i64.i64(i64 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1896// CHECK-RV64-NEXT: ret void1897//1898void test_sf_vc_ivv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) {1899 __riscv_sf_vc_ivv_se_u32m1(p27_26, vd, vs2, simm5, vl);1900}1901 1902// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u32m2(1903// CHECK-RV32-NEXT: entry:1904// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv4i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1905// CHECK-RV32-NEXT: ret void1906//1907// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u32m2(1908// CHECK-RV64-NEXT: entry:1909// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv4i32.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1910// CHECK-RV64-NEXT: ret void1911//1912void test_sf_vc_ivv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) {1913 __riscv_sf_vc_ivv_se_u32m2(p27_26, vd, vs2, simm5, vl);1914}1915 1916// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u32m4(1917// CHECK-RV32-NEXT: entry:1918// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv8i32.nxv8i32.i32.i32(i32 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1919// CHECK-RV32-NEXT: ret void1920//1921// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u32m4(1922// CHECK-RV64-NEXT: entry:1923// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv8i32.nxv8i32.i64.i64(i64 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1924// CHECK-RV64-NEXT: ret void1925//1926void test_sf_vc_ivv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) {1927 __riscv_sf_vc_ivv_se_u32m4(p27_26, vd, vs2, simm5, vl);1928}1929 1930// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u32m8(1931// CHECK-RV32-NEXT: entry:1932// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv16i32.nxv16i32.i32.i32(i32 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1933// CHECK-RV32-NEXT: ret void1934//1935// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u32m8(1936// CHECK-RV64-NEXT: entry:1937// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv16i32.nxv16i32.i64.i64(i64 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1938// CHECK-RV64-NEXT: ret void1939//1940void test_sf_vc_ivv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) {1941 __riscv_sf_vc_ivv_se_u32m8(p27_26, vd, vs2, simm5, vl);1942}1943 1944// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u64m1(1945// CHECK-RV32-NEXT: entry:1946// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv1i64.nxv1i64.i32.i32(i32 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1947// CHECK-RV32-NEXT: ret void1948//1949// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u64m1(1950// CHECK-RV64-NEXT: entry:1951// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1952// CHECK-RV64-NEXT: ret void1953//1954void test_sf_vc_ivv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, size_t vl) {1955 __riscv_sf_vc_ivv_se_u64m1(p27_26, vd, vs2, simm5, vl);1956}1957 1958// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u64m2(1959// CHECK-RV32-NEXT: entry:1960// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv2i64.nxv2i64.i32.i32(i32 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1961// CHECK-RV32-NEXT: ret void1962//1963// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u64m2(1964// CHECK-RV64-NEXT: entry:1965// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1966// CHECK-RV64-NEXT: ret void1967//1968void test_sf_vc_ivv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, size_t vl) {1969 __riscv_sf_vc_ivv_se_u64m2(p27_26, vd, vs2, simm5, vl);1970}1971 1972// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u64m4(1973// CHECK-RV32-NEXT: entry:1974// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv4i64.nxv4i64.i32.i32(i32 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1975// CHECK-RV32-NEXT: ret void1976//1977// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u64m4(1978// CHECK-RV64-NEXT: entry:1979// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1980// CHECK-RV64-NEXT: ret void1981//1982void test_sf_vc_ivv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, size_t vl) {1983 __riscv_sf_vc_ivv_se_u64m4(p27_26, vd, vs2, simm5, vl);1984}1985 1986// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u64m8(1987// CHECK-RV32-NEXT: entry:1988// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv8i64.nxv8i64.i32.i32(i32 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])1989// CHECK-RV32-NEXT: ret void1990//1991// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u64m8(1992// CHECK-RV64-NEXT: entry:1993// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])1994// CHECK-RV64-NEXT: ret void1995//1996void test_sf_vc_ivv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, size_t vl) {1997 __riscv_sf_vc_ivv_se_u64m8(p27_26, vd, vs2, simm5, vl);1998}1999 2000// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8mf8(2001// CHECK-RV32-NEXT: entry:2002// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv1i8.i32.nxv1i8.nxv1i8.i32.i32(i32 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2003// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]2004//2005// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8mf8(2006// CHECK-RV64-NEXT: entry:2007// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv1i8.i64.nxv1i8.nxv1i8.i64.i64(i64 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2008// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2009//2010vuint8mf8_t test_sf_vc_v_ivv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) {2011 return __riscv_sf_vc_v_ivv_se_u8mf8(p27_26, vd, vs2, simm5, vl);2012}2013 2014// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8mf4(2015// CHECK-RV32-NEXT: entry:2016// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv2i8.i32.nxv2i8.nxv2i8.i32.i32(i32 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2017// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]2018//2019// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8mf4(2020// CHECK-RV64-NEXT: entry:2021// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv2i8.i64.nxv2i8.nxv2i8.i64.i64(i64 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2022// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2023//2024vuint8mf4_t test_sf_vc_v_ivv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, size_t vl) {2025 return __riscv_sf_vc_v_ivv_se_u8mf4(p27_26, vd, vs2, simm5, vl);2026}2027 2028// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8mf2(2029// CHECK-RV32-NEXT: entry:2030// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv4i8.i32.nxv4i8.nxv4i8.i32.i32(i32 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2031// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]2032//2033// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8mf2(2034// CHECK-RV64-NEXT: entry:2035// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv4i8.i64.nxv4i8.nxv4i8.i64.i64(i64 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2036// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2037//2038vuint8mf2_t test_sf_vc_v_ivv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, size_t vl) {2039 return __riscv_sf_vc_v_ivv_se_u8mf2(p27_26, vd, vs2, simm5, vl);2040}2041 2042// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8m1(2043// CHECK-RV32-NEXT: entry:2044// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv8i8.i32.nxv8i8.nxv8i8.i32.i32(i32 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2045// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]2046//2047// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8m1(2048// CHECK-RV64-NEXT: entry:2049// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv8i8.i64.nxv8i8.nxv8i8.i64.i64(i64 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2050// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2051//2052vuint8m1_t test_sf_vc_v_ivv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, size_t vl) {2053 return __riscv_sf_vc_v_ivv_se_u8m1(p27_26, vd, vs2, simm5, vl);2054}2055 2056// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8m2(2057// CHECK-RV32-NEXT: entry:2058// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv16i8.i32.nxv16i8.nxv16i8.i32.i32(i32 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2059// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]2060//2061// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8m2(2062// CHECK-RV64-NEXT: entry:2063// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv16i8.i64.nxv16i8.nxv16i8.i64.i64(i64 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2064// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2065//2066vuint8m2_t test_sf_vc_v_ivv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, size_t vl) {2067 return __riscv_sf_vc_v_ivv_se_u8m2(p27_26, vd, vs2, simm5, vl);2068}2069 2070// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8m4(2071// CHECK-RV32-NEXT: entry:2072// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv32i8.i32.nxv32i8.nxv32i8.i32.i32(i32 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2073// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]2074//2075// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8m4(2076// CHECK-RV64-NEXT: entry:2077// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv32i8.i64.nxv32i8.nxv32i8.i64.i64(i64 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2078// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2079//2080vuint8m4_t test_sf_vc_v_ivv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, size_t vl) {2081 return __riscv_sf_vc_v_ivv_se_u8m4(p27_26, vd, vs2, simm5, vl);2082}2083 2084// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8m8(2085// CHECK-RV32-NEXT: entry:2086// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv64i8.i32.nxv64i8.nxv64i8.i32.i32(i32 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2087// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]2088//2089// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8m8(2090// CHECK-RV64-NEXT: entry:2091// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv64i8.i64.nxv64i8.nxv64i8.i64.i64(i64 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2092// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]2093//2094vuint8m8_t test_sf_vc_v_ivv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) {2095 return __riscv_sf_vc_v_ivv_se_u8m8(p27_26, vd, vs2, simm5, vl);2096}2097 2098// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16mf4(2099// CHECK-RV32-NEXT: entry:2100// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv1i16.i32.nxv1i16.nxv1i16.i32.i32(i32 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2101// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]2102//2103// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16mf4(2104// CHECK-RV64-NEXT: entry:2105// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv1i16.i64.nxv1i16.nxv1i16.i64.i64(i64 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2106// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2107//2108vuint16mf4_t test_sf_vc_v_ivv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, size_t vl) {2109 return __riscv_sf_vc_v_ivv_se_u16mf4(p27_26, vd, vs2, simm5, vl);2110}2111 2112// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16mf2(2113// CHECK-RV32-NEXT: entry:2114// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv2i16.i32.nxv2i16.nxv2i16.i32.i32(i32 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2115// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]2116//2117// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16mf2(2118// CHECK-RV64-NEXT: entry:2119// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv2i16.i64.nxv2i16.nxv2i16.i64.i64(i64 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2120// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2121//2122vuint16mf2_t test_sf_vc_v_ivv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, size_t vl) {2123 return __riscv_sf_vc_v_ivv_se_u16mf2(p27_26, vd, vs2, simm5, vl);2124}2125 2126// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16m1(2127// CHECK-RV32-NEXT: entry:2128// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv4i16.i32.nxv4i16.nxv4i16.i32.i32(i32 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2129// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]2130//2131// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16m1(2132// CHECK-RV64-NEXT: entry:2133// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv4i16.i64.nxv4i16.nxv4i16.i64.i64(i64 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2134// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2135//2136vuint16m1_t test_sf_vc_v_ivv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, size_t vl) {2137 return __riscv_sf_vc_v_ivv_se_u16m1(p27_26, vd, vs2, simm5, vl);2138}2139 2140// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16m2(2141// CHECK-RV32-NEXT: entry:2142// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv8i16.i32.nxv8i16.nxv8i16.i32.i32(i32 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2143// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]2144//2145// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16m2(2146// CHECK-RV64-NEXT: entry:2147// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv8i16.i64.nxv8i16.nxv8i16.i64.i64(i64 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2148// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2149//2150vuint16m2_t test_sf_vc_v_ivv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, size_t vl) {2151 return __riscv_sf_vc_v_ivv_se_u16m2(p27_26, vd, vs2, simm5, vl);2152}2153 2154// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16m4(2155// CHECK-RV32-NEXT: entry:2156// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv16i16.i32.nxv16i16.nxv16i16.i32.i32(i32 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2157// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]2158//2159// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16m4(2160// CHECK-RV64-NEXT: entry:2161// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv16i16.i64.nxv16i16.nxv16i16.i64.i64(i64 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2162// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2163//2164vuint16m4_t test_sf_vc_v_ivv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, size_t vl) {2165 return __riscv_sf_vc_v_ivv_se_u16m4(p27_26, vd, vs2, simm5, vl);2166}2167 2168// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16m8(2169// CHECK-RV32-NEXT: entry:2170// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv32i16.i32.nxv32i16.nxv32i16.i32.i32(i32 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2171// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]2172//2173// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16m8(2174// CHECK-RV64-NEXT: entry:2175// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv32i16.i64.nxv32i16.nxv32i16.i64.i64(i64 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2176// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2177//2178vuint16m8_t test_sf_vc_v_ivv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, size_t vl) {2179 return __riscv_sf_vc_v_ivv_se_u16m8(p27_26, vd, vs2, simm5, vl);2180}2181 2182// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u32mf2(2183// CHECK-RV32-NEXT: entry:2184// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv1i32.i32.nxv1i32.nxv1i32.i32.i32(i32 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2185// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]2186//2187// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u32mf2(2188// CHECK-RV64-NEXT: entry:2189// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv1i32.i64.nxv1i32.nxv1i32.i64.i64(i64 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2190// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2191//2192vuint32mf2_t test_sf_vc_v_ivv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) {2193 return __riscv_sf_vc_v_ivv_se_u32mf2(p27_26, vd, vs2, simm5, vl);2194}2195 2196// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u32m1(2197// CHECK-RV32-NEXT: entry:2198// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv2i32.i32.nxv2i32.nxv2i32.i32.i32(i32 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2199// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]2200//2201// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u32m1(2202// CHECK-RV64-NEXT: entry:2203// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv2i32.i64.nxv2i32.nxv2i32.i64.i64(i64 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2204// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2205//2206vuint32m1_t test_sf_vc_v_ivv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) {2207 return __riscv_sf_vc_v_ivv_se_u32m1(p27_26, vd, vs2, simm5, vl);2208}2209 2210// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u32m2(2211// CHECK-RV32-NEXT: entry:2212// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv4i32.i32.nxv4i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2213// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]2214//2215// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u32m2(2216// CHECK-RV64-NEXT: entry:2217// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv4i32.i64.nxv4i32.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2218// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2219//2220vuint32m2_t test_sf_vc_v_ivv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) {2221 return __riscv_sf_vc_v_ivv_se_u32m2(p27_26, vd, vs2, simm5, vl);2222}2223 2224// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u32m4(2225// CHECK-RV32-NEXT: entry:2226// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv8i32.i32.nxv8i32.nxv8i32.i32.i32(i32 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2227// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]2228//2229// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u32m4(2230// CHECK-RV64-NEXT: entry:2231// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv8i32.i64.nxv8i32.nxv8i32.i64.i64(i64 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2232// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2233//2234vuint32m4_t test_sf_vc_v_ivv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) {2235 return __riscv_sf_vc_v_ivv_se_u32m4(p27_26, vd, vs2, simm5, vl);2236}2237 2238// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u32m8(2239// CHECK-RV32-NEXT: entry:2240// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv16i32.i32.nxv16i32.nxv16i32.i32.i32(i32 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2241// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]2242//2243// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u32m8(2244// CHECK-RV64-NEXT: entry:2245// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv16i32.i64.nxv16i32.nxv16i32.i64.i64(i64 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2246// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2247//2248vuint32m8_t test_sf_vc_v_ivv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) {2249 return __riscv_sf_vc_v_ivv_se_u32m8(p27_26, vd, vs2, simm5, vl);2250}2251 2252// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u64m1(2253// CHECK-RV32-NEXT: entry:2254// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv1i64.i32.nxv1i64.nxv1i64.i32.i32(i32 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2255// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]2256//2257// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u64m1(2258// CHECK-RV64-NEXT: entry:2259// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2260// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2261//2262vuint64m1_t test_sf_vc_v_ivv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, size_t vl) {2263 return __riscv_sf_vc_v_ivv_se_u64m1(p27_26, vd, vs2, simm5, vl);2264}2265 2266// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u64m2(2267// CHECK-RV32-NEXT: entry:2268// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv2i64.i32.nxv2i64.nxv2i64.i32.i32(i32 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2269// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]2270//2271// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u64m2(2272// CHECK-RV64-NEXT: entry:2273// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2274// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2275//2276vuint64m2_t test_sf_vc_v_ivv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, size_t vl) {2277 return __riscv_sf_vc_v_ivv_se_u64m2(p27_26, vd, vs2, simm5, vl);2278}2279 2280// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u64m4(2281// CHECK-RV32-NEXT: entry:2282// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv4i64.i32.nxv4i64.nxv4i64.i32.i32(i32 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2283// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]2284//2285// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u64m4(2286// CHECK-RV64-NEXT: entry:2287// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2288// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2289//2290vuint64m4_t test_sf_vc_v_ivv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, size_t vl) {2291 return __riscv_sf_vc_v_ivv_se_u64m4(p27_26, vd, vs2, simm5, vl);2292}2293 2294// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u64m8(2295// CHECK-RV32-NEXT: entry:2296// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv8i64.i32.nxv8i64.nxv8i64.i32.i32(i32 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2297// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]2298//2299// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u64m8(2300// CHECK-RV64-NEXT: entry:2301// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2302// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]2303//2304vuint64m8_t test_sf_vc_v_ivv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, size_t vl) {2305 return __riscv_sf_vc_v_ivv_se_u64m8(p27_26, vd, vs2, simm5, vl);2306}2307 2308// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8mf8(2309// CHECK-RV32-NEXT: entry:2310// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.ivv.nxv1i8.i32.nxv1i8.nxv1i8.i32.i32(i32 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2311// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]2312//2313// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8mf8(2314// CHECK-RV64-NEXT: entry:2315// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.ivv.nxv1i8.i64.nxv1i8.nxv1i8.i64.i64(i64 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2316// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]2317//2318vuint8mf8_t test_sf_vc_v_ivv_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) {2319 return __riscv_sf_vc_v_ivv_u8mf8(p27_26, vd, vs2, simm5, vl);2320}2321 2322// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8mf4(2323// CHECK-RV32-NEXT: entry:2324// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.ivv.nxv2i8.i32.nxv2i8.nxv2i8.i32.i32(i32 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2325// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]2326//2327// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8mf4(2328// CHECK-RV64-NEXT: entry:2329// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.ivv.nxv2i8.i64.nxv2i8.nxv2i8.i64.i64(i64 3, <vscale x 2 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2330// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]2331//2332vuint8mf4_t test_sf_vc_v_ivv_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, size_t vl) {2333 return __riscv_sf_vc_v_ivv_u8mf4(p27_26, vd, vs2, simm5, vl);2334}2335 2336// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8mf2(2337// CHECK-RV32-NEXT: entry:2338// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.ivv.nxv4i8.i32.nxv4i8.nxv4i8.i32.i32(i32 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2339// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]2340//2341// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8mf2(2342// CHECK-RV64-NEXT: entry:2343// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.ivv.nxv4i8.i64.nxv4i8.nxv4i8.i64.i64(i64 3, <vscale x 4 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2344// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]2345//2346vuint8mf2_t test_sf_vc_v_ivv_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, size_t vl) {2347 return __riscv_sf_vc_v_ivv_u8mf2(p27_26, vd, vs2, simm5, vl);2348}2349 2350// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8m1(2351// CHECK-RV32-NEXT: entry:2352// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.ivv.nxv8i8.i32.nxv8i8.nxv8i8.i32.i32(i32 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2353// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]2354//2355// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8m1(2356// CHECK-RV64-NEXT: entry:2357// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.ivv.nxv8i8.i64.nxv8i8.nxv8i8.i64.i64(i64 3, <vscale x 8 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2358// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]2359//2360vuint8m1_t test_sf_vc_v_ivv_u8m1(vuint8m1_t vd, vuint8m1_t vs2, size_t vl) {2361 return __riscv_sf_vc_v_ivv_u8m1(p27_26, vd, vs2, simm5, vl);2362}2363 2364// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8m2(2365// CHECK-RV32-NEXT: entry:2366// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.ivv.nxv16i8.i32.nxv16i8.nxv16i8.i32.i32(i32 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2367// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]2368//2369// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8m2(2370// CHECK-RV64-NEXT: entry:2371// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.ivv.nxv16i8.i64.nxv16i8.nxv16i8.i64.i64(i64 3, <vscale x 16 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2372// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]2373//2374vuint8m2_t test_sf_vc_v_ivv_u8m2(vuint8m2_t vd, vuint8m2_t vs2, size_t vl) {2375 return __riscv_sf_vc_v_ivv_u8m2(p27_26, vd, vs2, simm5, vl);2376}2377 2378// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8m4(2379// CHECK-RV32-NEXT: entry:2380// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.ivv.nxv32i8.i32.nxv32i8.nxv32i8.i32.i32(i32 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2381// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]2382//2383// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8m4(2384// CHECK-RV64-NEXT: entry:2385// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.ivv.nxv32i8.i64.nxv32i8.nxv32i8.i64.i64(i64 3, <vscale x 32 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2386// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]2387//2388vuint8m4_t test_sf_vc_v_ivv_u8m4(vuint8m4_t vd, vuint8m4_t vs2, size_t vl) {2389 return __riscv_sf_vc_v_ivv_u8m4(p27_26, vd, vs2, simm5, vl);2390}2391 2392// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8m8(2393// CHECK-RV32-NEXT: entry:2394// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.ivv.nxv64i8.i32.nxv64i8.nxv64i8.i32.i32(i32 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2395// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]2396//2397// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8m8(2398// CHECK-RV64-NEXT: entry:2399// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.ivv.nxv64i8.i64.nxv64i8.nxv64i8.i64.i64(i64 3, <vscale x 64 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2400// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]2401//2402vuint8m8_t test_sf_vc_v_ivv_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) {2403 return __riscv_sf_vc_v_ivv_u8m8(p27_26, vd, vs2, simm5, vl);2404}2405 2406// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16mf4(2407// CHECK-RV32-NEXT: entry:2408// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.ivv.nxv1i16.i32.nxv1i16.nxv1i16.i32.i32(i32 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2409// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]2410//2411// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16mf4(2412// CHECK-RV64-NEXT: entry:2413// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.ivv.nxv1i16.i64.nxv1i16.nxv1i16.i64.i64(i64 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2414// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2415//2416vuint16mf4_t test_sf_vc_v_ivv_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, size_t vl) {2417 return __riscv_sf_vc_v_ivv_u16mf4(p27_26, vd, vs2, simm5, vl);2418}2419 2420// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16mf2(2421// CHECK-RV32-NEXT: entry:2422// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.ivv.nxv2i16.i32.nxv2i16.nxv2i16.i32.i32(i32 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2423// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]2424//2425// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16mf2(2426// CHECK-RV64-NEXT: entry:2427// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.ivv.nxv2i16.i64.nxv2i16.nxv2i16.i64.i64(i64 3, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2428// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2429//2430vuint16mf2_t test_sf_vc_v_ivv_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, size_t vl) {2431 return __riscv_sf_vc_v_ivv_u16mf2(p27_26, vd, vs2, simm5, vl);2432}2433 2434// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16m1(2435// CHECK-RV32-NEXT: entry:2436// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.ivv.nxv4i16.i32.nxv4i16.nxv4i16.i32.i32(i32 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2437// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]2438//2439// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16m1(2440// CHECK-RV64-NEXT: entry:2441// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.ivv.nxv4i16.i64.nxv4i16.nxv4i16.i64.i64(i64 3, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2442// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2443//2444vuint16m1_t test_sf_vc_v_ivv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, size_t vl) {2445 return __riscv_sf_vc_v_ivv_u16m1(p27_26, vd, vs2, simm5, vl);2446}2447 2448// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16m2(2449// CHECK-RV32-NEXT: entry:2450// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.ivv.nxv8i16.i32.nxv8i16.nxv8i16.i32.i32(i32 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2451// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]2452//2453// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16m2(2454// CHECK-RV64-NEXT: entry:2455// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.ivv.nxv8i16.i64.nxv8i16.nxv8i16.i64.i64(i64 3, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2456// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2457//2458vuint16m2_t test_sf_vc_v_ivv_u16m2(vuint16m2_t vd, vuint16m2_t vs2, size_t vl) {2459 return __riscv_sf_vc_v_ivv_u16m2(p27_26, vd, vs2, simm5, vl);2460}2461 2462// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16m4(2463// CHECK-RV32-NEXT: entry:2464// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.ivv.nxv16i16.i32.nxv16i16.nxv16i16.i32.i32(i32 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2465// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]2466//2467// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16m4(2468// CHECK-RV64-NEXT: entry:2469// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.ivv.nxv16i16.i64.nxv16i16.nxv16i16.i64.i64(i64 3, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2470// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2471//2472vuint16m4_t test_sf_vc_v_ivv_u16m4(vuint16m4_t vd, vuint16m4_t vs2, size_t vl) {2473 return __riscv_sf_vc_v_ivv_u16m4(p27_26, vd, vs2, simm5, vl);2474}2475 2476// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16m8(2477// CHECK-RV32-NEXT: entry:2478// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.ivv.nxv32i16.i32.nxv32i16.nxv32i16.i32.i32(i32 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2479// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]2480//2481// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16m8(2482// CHECK-RV64-NEXT: entry:2483// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.ivv.nxv32i16.i64.nxv32i16.nxv32i16.i64.i64(i64 3, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2484// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2485//2486vuint16m8_t test_sf_vc_v_ivv_u16m8(vuint16m8_t vd, vuint16m8_t vs2, size_t vl) {2487 return __riscv_sf_vc_v_ivv_u16m8(p27_26, vd, vs2, simm5, vl);2488}2489 2490// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u32mf2(2491// CHECK-RV32-NEXT: entry:2492// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.ivv.nxv1i32.i32.nxv1i32.nxv1i32.i32.i32(i32 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2493// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]2494//2495// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u32mf2(2496// CHECK-RV64-NEXT: entry:2497// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.ivv.nxv1i32.i64.nxv1i32.nxv1i32.i64.i64(i64 3, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2498// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2499//2500vuint32mf2_t test_sf_vc_v_ivv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) {2501 return __riscv_sf_vc_v_ivv_u32mf2(p27_26, vd, vs2, simm5, vl);2502}2503 2504// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u32m1(2505// CHECK-RV32-NEXT: entry:2506// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.ivv.nxv2i32.i32.nxv2i32.nxv2i32.i32.i32(i32 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2507// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]2508//2509// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u32m1(2510// CHECK-RV64-NEXT: entry:2511// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.ivv.nxv2i32.i64.nxv2i32.nxv2i32.i64.i64(i64 3, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2512// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2513//2514vuint32m1_t test_sf_vc_v_ivv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) {2515 return __riscv_sf_vc_v_ivv_u32m1(p27_26, vd, vs2, simm5, vl);2516}2517 2518// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u32m2(2519// CHECK-RV32-NEXT: entry:2520// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.ivv.nxv4i32.i32.nxv4i32.nxv4i32.i32.i32(i32 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2521// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]2522//2523// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u32m2(2524// CHECK-RV64-NEXT: entry:2525// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.ivv.nxv4i32.i64.nxv4i32.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2526// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2527//2528vuint32m2_t test_sf_vc_v_ivv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) {2529 return __riscv_sf_vc_v_ivv_u32m2(p27_26, vd, vs2, simm5, vl);2530}2531 2532// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u32m4(2533// CHECK-RV32-NEXT: entry:2534// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.ivv.nxv8i32.i32.nxv8i32.nxv8i32.i32.i32(i32 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2535// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]2536//2537// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u32m4(2538// CHECK-RV64-NEXT: entry:2539// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.ivv.nxv8i32.i64.nxv8i32.nxv8i32.i64.i64(i64 3, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2540// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2541//2542vuint32m4_t test_sf_vc_v_ivv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) {2543 return __riscv_sf_vc_v_ivv_u32m4(p27_26, vd, vs2, simm5, vl);2544}2545 2546// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u32m8(2547// CHECK-RV32-NEXT: entry:2548// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.ivv.nxv16i32.i32.nxv16i32.nxv16i32.i32.i32(i32 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2549// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]2550//2551// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u32m8(2552// CHECK-RV64-NEXT: entry:2553// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.ivv.nxv16i32.i64.nxv16i32.nxv16i32.i64.i64(i64 3, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2554// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2555//2556vuint32m8_t test_sf_vc_v_ivv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) {2557 return __riscv_sf_vc_v_ivv_u32m8(p27_26, vd, vs2, simm5, vl);2558}2559 2560// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u64m1(2561// CHECK-RV32-NEXT: entry:2562// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.ivv.nxv1i64.i32.nxv1i64.nxv1i64.i32.i32(i32 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2563// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]2564//2565// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u64m1(2566// CHECK-RV64-NEXT: entry:2567// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.ivv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2568// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2569//2570vuint64m1_t test_sf_vc_v_ivv_u64m1(vuint64m1_t vd, vuint64m1_t vs2, size_t vl) {2571 return __riscv_sf_vc_v_ivv_u64m1(p27_26, vd, vs2, simm5, vl);2572}2573 2574// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u64m2(2575// CHECK-RV32-NEXT: entry:2576// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.ivv.nxv2i64.i32.nxv2i64.nxv2i64.i32.i32(i32 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2577// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]2578//2579// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u64m2(2580// CHECK-RV64-NEXT: entry:2581// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.ivv.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2582// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]2583//2584vuint64m2_t test_sf_vc_v_ivv_u64m2(vuint64m2_t vd, vuint64m2_t vs2, size_t vl) {2585 return __riscv_sf_vc_v_ivv_u64m2(p27_26, vd, vs2, simm5, vl);2586}2587 2588// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u64m4(2589// CHECK-RV32-NEXT: entry:2590// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.ivv.nxv4i64.i32.nxv4i64.nxv4i64.i32.i32(i32 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2591// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]2592//2593// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u64m4(2594// CHECK-RV64-NEXT: entry:2595// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.ivv.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2596// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]2597//2598vuint64m4_t test_sf_vc_v_ivv_u64m4(vuint64m4_t vd, vuint64m4_t vs2, size_t vl) {2599 return __riscv_sf_vc_v_ivv_u64m4(p27_26, vd, vs2, simm5, vl);2600}2601 2602// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u64m8(2603// CHECK-RV32-NEXT: entry:2604// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.ivv.nxv8i64.i32.nxv8i64.nxv8i64.i32.i32(i32 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i32 10, i32 [[VL:%.*]])2605// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]2606//2607// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u64m8(2608// CHECK-RV64-NEXT: entry:2609// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.ivv.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 10, i64 [[VL:%.*]])2610// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]2611//2612vuint64m8_t test_sf_vc_v_ivv_u64m8(vuint64m8_t vd, vuint64m8_t vs2, size_t vl) {2613 return __riscv_sf_vc_v_ivv_u64m8(p27_26, vd, vs2, simm5, vl);2614}2615 2616// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16mf4(2617// CHECK-RV32-NEXT: entry:2618// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv1i16.nxv1i16.f16.i32(i32 1, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2619// CHECK-RV32-NEXT: ret void2620//2621// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16mf4(2622// CHECK-RV64-NEXT: entry:2623// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv1i16.nxv1i16.f16.i64(i64 1, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2624// CHECK-RV64-NEXT: ret void2625//2626void test_sf_vc_fvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) {2627 __riscv_sf_vc_fvv_se_u16mf4(p26, vd, vs2, fs1, vl);2628}2629 2630// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16mf2(2631// CHECK-RV32-NEXT: entry:2632// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv2i16.nxv2i16.f16.i32(i32 1, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2633// CHECK-RV32-NEXT: ret void2634//2635// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16mf2(2636// CHECK-RV64-NEXT: entry:2637// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv2i16.nxv2i16.f16.i64(i64 1, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2638// CHECK-RV64-NEXT: ret void2639//2640void test_sf_vc_fvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, _Float16 fs1, size_t vl) {2641 __riscv_sf_vc_fvv_se_u16mf2(p26, vd, vs2, fs1, vl);2642}2643 2644// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16m1(2645// CHECK-RV32-NEXT: entry:2646// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv4i16.nxv4i16.f16.i32(i32 1, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2647// CHECK-RV32-NEXT: ret void2648//2649// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16m1(2650// CHECK-RV64-NEXT: entry:2651// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv4i16.nxv4i16.f16.i64(i64 1, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2652// CHECK-RV64-NEXT: ret void2653//2654void test_sf_vc_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, _Float16 fs1, size_t vl) {2655 __riscv_sf_vc_fvv_se_u16m1(p26, vd, vs2, fs1, vl);2656}2657 2658// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16m2(2659// CHECK-RV32-NEXT: entry:2660// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv8i16.nxv8i16.f16.i32(i32 1, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2661// CHECK-RV32-NEXT: ret void2662//2663// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16m2(2664// CHECK-RV64-NEXT: entry:2665// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv8i16.nxv8i16.f16.i64(i64 1, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2666// CHECK-RV64-NEXT: ret void2667//2668void test_sf_vc_fvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, _Float16 fs1, size_t vl) {2669 __riscv_sf_vc_fvv_se_u16m2(p26, vd, vs2, fs1, vl);2670}2671 2672// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16m4(2673// CHECK-RV32-NEXT: entry:2674// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv16i16.nxv16i16.f16.i32(i32 1, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2675// CHECK-RV32-NEXT: ret void2676//2677// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16m4(2678// CHECK-RV64-NEXT: entry:2679// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv16i16.nxv16i16.f16.i64(i64 1, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2680// CHECK-RV64-NEXT: ret void2681//2682void test_sf_vc_fvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, _Float16 fs1, size_t vl) {2683 __riscv_sf_vc_fvv_se_u16m4(p26, vd, vs2, fs1, vl);2684}2685 2686// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16m8(2687// CHECK-RV32-NEXT: entry:2688// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv32i16.nxv32i16.f16.i32(i32 1, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2689// CHECK-RV32-NEXT: ret void2690//2691// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16m8(2692// CHECK-RV64-NEXT: entry:2693// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv32i16.nxv32i16.f16.i64(i64 1, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2694// CHECK-RV64-NEXT: ret void2695//2696void test_sf_vc_fvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, _Float16 fs1, size_t vl) {2697 __riscv_sf_vc_fvv_se_u16m8(p26, vd, vs2, fs1, vl);2698}2699 2700// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u32mf2(2701// CHECK-RV32-NEXT: entry:2702// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv1i32.nxv1i32.f32.i32(i32 1, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2703// CHECK-RV32-NEXT: ret void2704//2705// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u32mf2(2706// CHECK-RV64-NEXT: entry:2707// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv1i32.nxv1i32.f32.i64(i64 1, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2708// CHECK-RV64-NEXT: ret void2709//2710void test_sf_vc_fvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, float fs1, size_t vl) {2711 __riscv_sf_vc_fvv_se_u32mf2(p26, vd, vs2, fs1, vl);2712}2713 2714// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u32m1(2715// CHECK-RV32-NEXT: entry:2716// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv2i32.nxv2i32.f32.i32(i32 1, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2717// CHECK-RV32-NEXT: ret void2718//2719// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u32m1(2720// CHECK-RV64-NEXT: entry:2721// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv2i32.nxv2i32.f32.i64(i64 1, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2722// CHECK-RV64-NEXT: ret void2723//2724void test_sf_vc_fvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, float fs1, size_t vl) {2725 __riscv_sf_vc_fvv_se_u32m1(p26, vd, vs2, fs1, vl);2726}2727 2728// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u32m2(2729// CHECK-RV32-NEXT: entry:2730// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv4i32.nxv4i32.f32.i32(i32 1, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2731// CHECK-RV32-NEXT: ret void2732//2733// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u32m2(2734// CHECK-RV64-NEXT: entry:2735// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv4i32.nxv4i32.f32.i64(i64 1, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2736// CHECK-RV64-NEXT: ret void2737//2738void test_sf_vc_fvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, float fs1, size_t vl) {2739 __riscv_sf_vc_fvv_se_u32m2(p26, vd, vs2, fs1, vl);2740}2741 2742// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u32m4(2743// CHECK-RV32-NEXT: entry:2744// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv8i32.nxv8i32.f32.i32(i32 1, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2745// CHECK-RV32-NEXT: ret void2746//2747// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u32m4(2748// CHECK-RV64-NEXT: entry:2749// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv8i32.nxv8i32.f32.i64(i64 1, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2750// CHECK-RV64-NEXT: ret void2751//2752void test_sf_vc_fvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, float fs1, size_t vl) {2753 __riscv_sf_vc_fvv_se_u32m4(p26, vd, vs2, fs1, vl);2754}2755 2756// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u32m8(2757// CHECK-RV32-NEXT: entry:2758// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv16i32.nxv16i32.f32.i32(i32 1, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2759// CHECK-RV32-NEXT: ret void2760//2761// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u32m8(2762// CHECK-RV64-NEXT: entry:2763// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv16i32.nxv16i32.f32.i64(i64 1, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2764// CHECK-RV64-NEXT: ret void2765//2766void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float fs1, size_t vl) {2767 __riscv_sf_vc_fvv_se_u32m8(p26, vd, vs2, fs1, vl);2768}2769 2770// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u64m1(2771// CHECK-RV32-NEXT: entry:2772// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv1i64.nxv1i64.f64.i32(i32 1, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2773// CHECK-RV32-NEXT: ret void2774//2775// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u64m1(2776// CHECK-RV64-NEXT: entry:2777// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv1i64.nxv1i64.f64.i64(i64 1, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])2778// CHECK-RV64-NEXT: ret void2779//2780void test_sf_vc_fvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, double fs1, size_t vl) {2781 __riscv_sf_vc_fvv_se_u64m1(p26, vd, vs2, fs1, vl);2782}2783 2784// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u64m2(2785// CHECK-RV32-NEXT: entry:2786// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv2i64.nxv2i64.f64.i32(i32 1, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2787// CHECK-RV32-NEXT: ret void2788//2789// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u64m2(2790// CHECK-RV64-NEXT: entry:2791// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv2i64.nxv2i64.f64.i64(i64 1, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])2792// CHECK-RV64-NEXT: ret void2793//2794void test_sf_vc_fvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, double fs1, size_t vl) {2795 __riscv_sf_vc_fvv_se_u64m2(p26, vd, vs2, fs1, vl);2796}2797 2798// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u64m4(2799// CHECK-RV32-NEXT: entry:2800// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv4i64.nxv4i64.f64.i32(i32 1, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2801// CHECK-RV32-NEXT: ret void2802//2803// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u64m4(2804// CHECK-RV64-NEXT: entry:2805// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv4i64.nxv4i64.f64.i64(i64 1, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])2806// CHECK-RV64-NEXT: ret void2807//2808void test_sf_vc_fvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, double fs1, size_t vl) {2809 __riscv_sf_vc_fvv_se_u64m4(p26, vd, vs2, fs1, vl);2810}2811 2812// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u64m8(2813// CHECK-RV32-NEXT: entry:2814// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv8i64.nxv8i64.f64.i32(i32 1, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2815// CHECK-RV32-NEXT: ret void2816//2817// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u64m8(2818// CHECK-RV64-NEXT: entry:2819// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv8i64.nxv8i64.f64.i64(i64 1, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])2820// CHECK-RV64-NEXT: ret void2821//2822void test_sf_vc_fvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, double fs1, size_t vl) {2823 __riscv_sf_vc_fvv_se_u64m8(p26, vd, vs2, fs1, vl);2824}2825 2826// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16mf4(2827// CHECK-RV32-NEXT: entry:2828// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv1i16.i32.nxv1i16.nxv1i16.f16.i32(i32 1, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2829// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]2830//2831// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16mf4(2832// CHECK-RV64-NEXT: entry:2833// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv1i16.i64.nxv1i16.nxv1i16.f16.i64(i64 1, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2834// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]2835//2836vuint16mf4_t test_sf_vc_v_fvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) {2837 return __riscv_sf_vc_v_fvv_se_u16mf4(p26, vd, vs2, fs1, vl);2838}2839 2840// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16mf2(2841// CHECK-RV32-NEXT: entry:2842// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv2i16.i32.nxv2i16.nxv2i16.f16.i32(i32 1, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2843// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]2844//2845// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16mf2(2846// CHECK-RV64-NEXT: entry:2847// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv2i16.i64.nxv2i16.nxv2i16.f16.i64(i64 1, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2848// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]2849//2850vuint16mf2_t test_sf_vc_v_fvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, _Float16 fs1, size_t vl) {2851 return __riscv_sf_vc_v_fvv_se_u16mf2(p26, vd, vs2, fs1, vl);2852}2853 2854// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16m1(2855// CHECK-RV32-NEXT: entry:2856// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv4i16.i32.nxv4i16.nxv4i16.f16.i32(i32 1, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2857// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]2858//2859// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16m1(2860// CHECK-RV64-NEXT: entry:2861// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv4i16.i64.nxv4i16.nxv4i16.f16.i64(i64 1, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2862// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]2863//2864vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, _Float16 fs1, size_t vl) {2865 return __riscv_sf_vc_v_fvv_se_u16m1(p26, vd, vs2, fs1, vl);2866}2867 2868// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16m2(2869// CHECK-RV32-NEXT: entry:2870// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv8i16.i32.nxv8i16.nxv8i16.f16.i32(i32 1, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2871// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]2872//2873// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16m2(2874// CHECK-RV64-NEXT: entry:2875// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv8i16.i64.nxv8i16.nxv8i16.f16.i64(i64 1, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2876// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]2877//2878vuint16m2_t test_sf_vc_v_fvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, _Float16 fs1, size_t vl) {2879 return __riscv_sf_vc_v_fvv_se_u16m2(p26, vd, vs2, fs1, vl);2880}2881 2882// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16m4(2883// CHECK-RV32-NEXT: entry:2884// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv16i16.i32.nxv16i16.nxv16i16.f16.i32(i32 1, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2885// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]2886//2887// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16m4(2888// CHECK-RV64-NEXT: entry:2889// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv16i16.i64.nxv16i16.nxv16i16.f16.i64(i64 1, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2890// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]2891//2892vuint16m4_t test_sf_vc_v_fvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, _Float16 fs1, size_t vl) {2893 return __riscv_sf_vc_v_fvv_se_u16m4(p26, vd, vs2, fs1, vl);2894}2895 2896// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16m8(2897// CHECK-RV32-NEXT: entry:2898// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv32i16.i32.nxv32i16.nxv32i16.f16.i32(i32 1, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])2899// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]2900//2901// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16m8(2902// CHECK-RV64-NEXT: entry:2903// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.fvv.se.nxv32i16.i64.nxv32i16.nxv32i16.f16.i64(i64 1, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])2904// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]2905//2906vuint16m8_t test_sf_vc_v_fvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, _Float16 fs1, size_t vl) {2907 return __riscv_sf_vc_v_fvv_se_u16m8(p26, vd, vs2, fs1, vl);2908}2909 2910// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u32mf2(2911// CHECK-RV32-NEXT: entry:2912// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.fvv.se.nxv1i32.i32.nxv1i32.nxv1i32.f32.i32(i32 1, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2913// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]2914//2915// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u32mf2(2916// CHECK-RV64-NEXT: entry:2917// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.fvv.se.nxv1i32.i64.nxv1i32.nxv1i32.f32.i64(i64 1, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2918// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]2919//2920vuint32mf2_t test_sf_vc_v_fvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, float fs1, size_t vl) {2921 return __riscv_sf_vc_v_fvv_se_u32mf2(p26, vd, vs2, fs1, vl);2922}2923 2924// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u32m1(2925// CHECK-RV32-NEXT: entry:2926// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.fvv.se.nxv2i32.i32.nxv2i32.nxv2i32.f32.i32(i32 1, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2927// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]2928//2929// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u32m1(2930// CHECK-RV64-NEXT: entry:2931// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.fvv.se.nxv2i32.i64.nxv2i32.nxv2i32.f32.i64(i64 1, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2932// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]2933//2934vuint32m1_t test_sf_vc_v_fvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, float fs1, size_t vl) {2935 return __riscv_sf_vc_v_fvv_se_u32m1(p26, vd, vs2, fs1, vl);2936}2937 2938// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u32m2(2939// CHECK-RV32-NEXT: entry:2940// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fvv.se.nxv4i32.i32.nxv4i32.nxv4i32.f32.i32(i32 1, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2941// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]2942//2943// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u32m2(2944// CHECK-RV64-NEXT: entry:2945// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fvv.se.nxv4i32.i64.nxv4i32.nxv4i32.f32.i64(i64 1, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2946// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]2947//2948vuint32m2_t test_sf_vc_v_fvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, float fs1, size_t vl) {2949 return __riscv_sf_vc_v_fvv_se_u32m2(p26, vd, vs2, fs1, vl);2950}2951 2952// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u32m4(2953// CHECK-RV32-NEXT: entry:2954// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.fvv.se.nxv8i32.i32.nxv8i32.nxv8i32.f32.i32(i32 1, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2955// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]2956//2957// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u32m4(2958// CHECK-RV64-NEXT: entry:2959// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.fvv.se.nxv8i32.i64.nxv8i32.nxv8i32.f32.i64(i64 1, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2960// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]2961//2962vuint32m4_t test_sf_vc_v_fvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, float fs1, size_t vl) {2963 return __riscv_sf_vc_v_fvv_se_u32m4(p26, vd, vs2, fs1, vl);2964}2965 2966// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u32m8(2967// CHECK-RV32-NEXT: entry:2968// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.fvv.se.nxv16i32.i32.nxv16i32.nxv16i32.f32.i32(i32 1, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])2969// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]2970//2971// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u32m8(2972// CHECK-RV64-NEXT: entry:2973// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.fvv.se.nxv16i32.i64.nxv16i32.nxv16i32.f32.i64(i64 1, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])2974// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]2975//2976vuint32m8_t test_sf_vc_v_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float fs1, size_t vl) {2977 return __riscv_sf_vc_v_fvv_se_u32m8(p26, vd, vs2, fs1, vl);2978}2979 2980// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u64m1(2981// CHECK-RV32-NEXT: entry:2982// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.fvv.se.nxv1i64.i32.nxv1i64.nxv1i64.f64.i32(i32 1, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2983// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]2984//2985// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u64m1(2986// CHECK-RV64-NEXT: entry:2987// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.fvv.se.nxv1i64.i64.nxv1i64.nxv1i64.f64.i64(i64 1, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])2988// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]2989//2990vuint64m1_t test_sf_vc_v_fvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, double fs1, size_t vl) {2991 return __riscv_sf_vc_v_fvv_se_u64m1(p26, vd, vs2, fs1, vl);2992}2993 2994// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u64m2(2995// CHECK-RV32-NEXT: entry:2996// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.fvv.se.nxv2i64.i32.nxv2i64.nxv2i64.f64.i32(i32 1, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])2997// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]2998//2999// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u64m2(3000// CHECK-RV64-NEXT: entry:3001// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.fvv.se.nxv2i64.i64.nxv2i64.nxv2i64.f64.i64(i64 1, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3002// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]3003//3004vuint64m2_t test_sf_vc_v_fvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, double fs1, size_t vl) {3005 return __riscv_sf_vc_v_fvv_se_u64m2(p26, vd, vs2, fs1, vl);3006}3007 3008// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u64m4(3009// CHECK-RV32-NEXT: entry:3010// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.fvv.se.nxv4i64.i32.nxv4i64.nxv4i64.f64.i32(i32 1, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3011// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]3012//3013// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u64m4(3014// CHECK-RV64-NEXT: entry:3015// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.fvv.se.nxv4i64.i64.nxv4i64.nxv4i64.f64.i64(i64 1, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3016// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]3017//3018vuint64m4_t test_sf_vc_v_fvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, double fs1, size_t vl) {3019 return __riscv_sf_vc_v_fvv_se_u64m4(p26, vd, vs2, fs1, vl);3020}3021 3022// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u64m8(3023// CHECK-RV32-NEXT: entry:3024// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.fvv.se.nxv8i64.i32.nxv8i64.nxv8i64.f64.i32(i32 1, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3025// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]3026//3027// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u64m8(3028// CHECK-RV64-NEXT: entry:3029// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.fvv.se.nxv8i64.i64.nxv8i64.nxv8i64.f64.i64(i64 1, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3030// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]3031//3032vuint64m8_t test_sf_vc_v_fvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, double fs1, size_t vl) {3033 return __riscv_sf_vc_v_fvv_se_u64m8(p26, vd, vs2, fs1, vl);3034}3035 3036// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16mf4(3037// CHECK-RV32-NEXT: entry:3038// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.fvv.nxv1i16.i32.nxv1i16.nxv1i16.f16.i32(i32 1, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3039// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]3040//3041// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16mf4(3042// CHECK-RV64-NEXT: entry:3043// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.fvv.nxv1i16.i64.nxv1i16.nxv1i16.f16.i64(i64 1, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3044// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]3045//3046vuint16mf4_t test_sf_vc_v_fvv_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) {3047 return __riscv_sf_vc_v_fvv_u16mf4(p26, vd, vs2, fs1, vl);3048}3049 3050// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16mf2(3051// CHECK-RV32-NEXT: entry:3052// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.fvv.nxv2i16.i32.nxv2i16.nxv2i16.f16.i32(i32 1, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3053// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]3054//3055// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16mf2(3056// CHECK-RV64-NEXT: entry:3057// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.fvv.nxv2i16.i64.nxv2i16.nxv2i16.f16.i64(i64 1, <vscale x 2 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3058// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]3059//3060vuint16mf2_t test_sf_vc_v_fvv_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, _Float16 fs1, size_t vl) {3061 return __riscv_sf_vc_v_fvv_u16mf2(p26, vd, vs2, fs1, vl);3062}3063 3064// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16m1(3065// CHECK-RV32-NEXT: entry:3066// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.fvv.nxv4i16.i32.nxv4i16.nxv4i16.f16.i32(i32 1, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3067// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]3068//3069// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16m1(3070// CHECK-RV64-NEXT: entry:3071// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.fvv.nxv4i16.i64.nxv4i16.nxv4i16.f16.i64(i64 1, <vscale x 4 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3072// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]3073//3074vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, _Float16 fs1, size_t vl) {3075 return __riscv_sf_vc_v_fvv_u16m1(p26, vd, vs2, fs1, vl);3076}3077 3078// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16m2(3079// CHECK-RV32-NEXT: entry:3080// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.fvv.nxv8i16.i32.nxv8i16.nxv8i16.f16.i32(i32 1, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3081// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]3082//3083// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16m2(3084// CHECK-RV64-NEXT: entry:3085// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.fvv.nxv8i16.i64.nxv8i16.nxv8i16.f16.i64(i64 1, <vscale x 8 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3086// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]3087//3088vuint16m2_t test_sf_vc_v_fvv_u16m2(vuint16m2_t vd, vuint16m2_t vs2, _Float16 fs1, size_t vl) {3089 return __riscv_sf_vc_v_fvv_u16m2(p26, vd, vs2, fs1, vl);3090}3091 3092// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16m4(3093// CHECK-RV32-NEXT: entry:3094// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.fvv.nxv16i16.i32.nxv16i16.nxv16i16.f16.i32(i32 1, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3095// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]3096//3097// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16m4(3098// CHECK-RV64-NEXT: entry:3099// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.fvv.nxv16i16.i64.nxv16i16.nxv16i16.f16.i64(i64 1, <vscale x 16 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3100// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]3101//3102vuint16m4_t test_sf_vc_v_fvv_u16m4(vuint16m4_t vd, vuint16m4_t vs2, _Float16 fs1, size_t vl) {3103 return __riscv_sf_vc_v_fvv_u16m4(p26, vd, vs2, fs1, vl);3104}3105 3106// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16m8(3107// CHECK-RV32-NEXT: entry:3108// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.fvv.nxv32i16.i32.nxv32i16.nxv32i16.f16.i32(i32 1, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]])3109// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]3110//3111// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16m8(3112// CHECK-RV64-NEXT: entry:3113// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.fvv.nxv32i16.i64.nxv32i16.nxv32i16.f16.i64(i64 1, <vscale x 32 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]])3114// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]3115//3116vuint16m8_t test_sf_vc_v_fvv_u16m8(vuint16m8_t vd, vuint16m8_t vs2, _Float16 fs1, size_t vl) {3117 return __riscv_sf_vc_v_fvv_u16m8(p26, vd, vs2, fs1, vl);3118}3119 3120// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u32mf2(3121// CHECK-RV32-NEXT: entry:3122// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.fvv.nxv1i32.i32.nxv1i32.nxv1i32.f32.i32(i32 1, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])3123// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]3124//3125// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u32mf2(3126// CHECK-RV64-NEXT: entry:3127// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.fvv.nxv1i32.i64.nxv1i32.nxv1i32.f32.i64(i64 1, <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])3128// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]3129//3130vuint32mf2_t test_sf_vc_v_fvv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, float fs1, size_t vl) {3131 return __riscv_sf_vc_v_fvv_u32mf2(p26, vd, vs2, fs1, vl);3132}3133 3134// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u32m1(3135// CHECK-RV32-NEXT: entry:3136// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.fvv.nxv2i32.i32.nxv2i32.nxv2i32.f32.i32(i32 1, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])3137// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]3138//3139// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u32m1(3140// CHECK-RV64-NEXT: entry:3141// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.fvv.nxv2i32.i64.nxv2i32.nxv2i32.f32.i64(i64 1, <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])3142// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]3143//3144vuint32m1_t test_sf_vc_v_fvv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, float fs1, size_t vl) {3145 return __riscv_sf_vc_v_fvv_u32m1(p26, vd, vs2, fs1, vl);3146}3147 3148// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u32m2(3149// CHECK-RV32-NEXT: entry:3150// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fvv.nxv4i32.i32.nxv4i32.nxv4i32.f32.i32(i32 1, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])3151// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]3152//3153// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u32m2(3154// CHECK-RV64-NEXT: entry:3155// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fvv.nxv4i32.i64.nxv4i32.nxv4i32.f32.i64(i64 1, <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])3156// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]3157//3158vuint32m2_t test_sf_vc_v_fvv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, float fs1, size_t vl) {3159 return __riscv_sf_vc_v_fvv_u32m2(p26, vd, vs2, fs1, vl);3160}3161 3162// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u32m4(3163// CHECK-RV32-NEXT: entry:3164// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.fvv.nxv8i32.i32.nxv8i32.nxv8i32.f32.i32(i32 1, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])3165// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]3166//3167// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u32m4(3168// CHECK-RV64-NEXT: entry:3169// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.fvv.nxv8i32.i64.nxv8i32.nxv8i32.f32.i64(i64 1, <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])3170// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]3171//3172vuint32m4_t test_sf_vc_v_fvv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, float fs1, size_t vl) {3173 return __riscv_sf_vc_v_fvv_u32m4(p26, vd, vs2, fs1, vl);3174}3175 3176// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u32m8(3177// CHECK-RV32-NEXT: entry:3178// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.fvv.nxv16i32.i32.nxv16i32.nxv16i32.f32.i32(i32 1, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]])3179// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]3180//3181// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u32m8(3182// CHECK-RV64-NEXT: entry:3183// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.fvv.nxv16i32.i64.nxv16i32.nxv16i32.f32.i64(i64 1, <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]])3184// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]3185//3186vuint32m8_t test_sf_vc_v_fvv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float fs1, size_t vl) {3187 return __riscv_sf_vc_v_fvv_u32m8(p26, vd, vs2, fs1, vl);3188}3189 3190// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u64m1(3191// CHECK-RV32-NEXT: entry:3192// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.fvv.nxv1i64.i32.nxv1i64.nxv1i64.f64.i32(i32 1, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3193// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]3194//3195// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u64m1(3196// CHECK-RV64-NEXT: entry:3197// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.fvv.nxv1i64.i64.nxv1i64.nxv1i64.f64.i64(i64 1, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3198// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]3199//3200vuint64m1_t test_sf_vc_v_fvv_u64m1(vuint64m1_t vd, vuint64m1_t vs2, double fs1, size_t vl) {3201 return __riscv_sf_vc_v_fvv_u64m1(p26, vd, vs2, fs1, vl);3202}3203 3204// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u64m2(3205// CHECK-RV32-NEXT: entry:3206// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.fvv.nxv2i64.i32.nxv2i64.nxv2i64.f64.i32(i32 1, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3207// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]3208//3209// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u64m2(3210// CHECK-RV64-NEXT: entry:3211// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.fvv.nxv2i64.i64.nxv2i64.nxv2i64.f64.i64(i64 1, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3212// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]3213//3214vuint64m2_t test_sf_vc_v_fvv_u64m2(vuint64m2_t vd, vuint64m2_t vs2, double fs1, size_t vl) {3215 return __riscv_sf_vc_v_fvv_u64m2(p26, vd, vs2, fs1, vl);3216}3217 3218// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u64m4(3219// CHECK-RV32-NEXT: entry:3220// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.fvv.nxv4i64.i32.nxv4i64.nxv4i64.f64.i32(i32 1, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3221// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]3222//3223// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u64m4(3224// CHECK-RV64-NEXT: entry:3225// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.fvv.nxv4i64.i64.nxv4i64.nxv4i64.f64.i64(i64 1, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3226// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]3227//3228vuint64m4_t test_sf_vc_v_fvv_u64m4(vuint64m4_t vd, vuint64m4_t vs2, double fs1, size_t vl) {3229 return __riscv_sf_vc_v_fvv_u64m4(p26, vd, vs2, fs1, vl);3230}3231 3232// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u64m8(3233// CHECK-RV32-NEXT: entry:3234// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.fvv.nxv8i64.i32.nxv8i64.nxv8i64.f64.i32(i32 1, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]])3235// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]3236//3237// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u64m8(3238// CHECK-RV64-NEXT: entry:3239// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.fvv.nxv8i64.i64.nxv8i64.nxv8i64.f64.i64(i64 1, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]])3240// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]3241//3242vuint64m8_t test_sf_vc_v_fvv_u64m8(vuint64m8_t vd, vuint64m8_t vs2, double fs1, size_t vl) {3243 return __riscv_sf_vc_v_fvv_u64m8(p26, vd, vs2, fs1, vl);3244}3245