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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple s390x-linux-gnu -O1 -emit-llvm %s -o - | FileCheck %s3//4// Test GNU atomic builtins for int16_t.5 6#include <stdatomic.h>7#include <stdint.h>8 9// CHECK-LABEL: @f1(10// CHECK-NEXT: entry:11// CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[PTR:%.*]] seq_cst, align 212// CHECK-NEXT: ret i16 [[TMP0]]13//14int16_t f1(int16_t *Ptr) {15 return __atomic_load_n(Ptr, memory_order_seq_cst);16}17 18// CHECK-LABEL: @f2(19// CHECK-NEXT: entry:20// CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[PTR:%.*]] seq_cst, align 221// CHECK-NEXT: store i16 [[TMP0]], ptr [[RET:%.*]], align 222// CHECK-NEXT: ret i16 [[TMP0]]23//24int16_t f2(int16_t *Ptr, int16_t *Ret) {25 __atomic_load(Ptr, Ret, memory_order_seq_cst);26 return *Ret;27}28 29// CHECK-LABEL: @f3(30// CHECK-NEXT: entry:31// CHECK-NEXT: store atomic i16 [[VAL:%.*]], ptr [[PTR:%.*]] seq_cst, align 232// CHECK-NEXT: ret void33//34void f3(int16_t *Ptr, int16_t Val) {35 __atomic_store_n(Ptr, Val, memory_order_seq_cst);36}37 38// CHECK-LABEL: @f4(39// CHECK-NEXT: entry:40// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[VAL:%.*]], align 241// CHECK-NEXT: store atomic i16 [[TMP0]], ptr [[PTR:%.*]] seq_cst, align 242// CHECK-NEXT: ret void43//44void f4(int16_t *Ptr, int16_t *Val) {45 __atomic_store(Ptr, Val, memory_order_seq_cst);46}47 48// CHECK-LABEL: @f5(49// CHECK-NEXT: entry:50// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 251// CHECK-NEXT: ret i16 [[TMP0]]52//53int16_t f5(int16_t *Ptr, int16_t Val) {54 return __atomic_exchange_n(Ptr, Val, memory_order_seq_cst);55}56 57// CHECK-LABEL: @f6(58// CHECK-NEXT: entry:59// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[VAL:%.*]], align 260// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i16 [[TMP0]] seq_cst, align 261// CHECK-NEXT: store i16 [[TMP1]], ptr [[RET:%.*]], align 262// CHECK-NEXT: ret i16 [[TMP1]]63//64int16_t f6(int16_t *Ptr, int16_t *Val, int16_t *Ret) {65 __atomic_exchange(Ptr, Val, Ret, memory_order_seq_cst);66 return *Ret;67}68 69// CHECK-LABEL: @f7(70// CHECK-NEXT: entry:71// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[EXP:%.*]], align 272// CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[PTR:%.*]], i16 [[TMP0]], i16 [[DES:%.*]] seq_cst seq_cst, align 273// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i16, i1 } [[TMP1]], 174// CHECK-NEXT: br i1 [[TMP2]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]]75// CHECK: cmpxchg.store_expected:76// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i16, i1 } [[TMP1]], 077// CHECK-NEXT: store i16 [[TMP3]], ptr [[EXP]], align 278// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]]79// CHECK: cmpxchg.continue:80// CHECK-NEXT: ret i1 [[TMP2]]81//82_Bool f7(int16_t *Ptr, int16_t *Exp, int16_t Des) {83 return __atomic_compare_exchange_n(Ptr, Exp, Des, 0,84 memory_order_seq_cst, memory_order_seq_cst);85}86 87// CHECK-LABEL: @f8(88// CHECK-NEXT: entry:89// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[EXP:%.*]], align 290// CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[DES:%.*]], align 291// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[PTR:%.*]], i16 [[TMP0]], i16 [[TMP1]] seq_cst seq_cst, align 292// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i16, i1 } [[TMP2]], 193// CHECK-NEXT: br i1 [[TMP3]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]]94// CHECK: cmpxchg.store_expected:95// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i16, i1 } [[TMP2]], 096// CHECK-NEXT: store i16 [[TMP4]], ptr [[EXP]], align 297// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]]98// CHECK: cmpxchg.continue:99// CHECK-NEXT: ret i1 [[TMP3]]100//101_Bool f8(int16_t *Ptr, int16_t *Exp, int16_t *Des) {102 return __atomic_compare_exchange(Ptr, Exp, Des, 0,103 memory_order_seq_cst, memory_order_seq_cst);104}105 106// CHECK-LABEL: @f9(107// CHECK-NEXT: entry:108// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2109// CHECK-NEXT: [[TMP1:%.*]] = add i16 [[TMP0]], [[VAL]]110// CHECK-NEXT: ret i16 [[TMP1]]111//112int16_t f9(int16_t *Ptr, int16_t Val) {113 return __atomic_add_fetch(Ptr, Val, memory_order_seq_cst);114}115 116// CHECK-LABEL: @f10(117// CHECK-NEXT: entry:118// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw sub ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2119// CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[TMP0]], [[VAL]]120// CHECK-NEXT: ret i16 [[TMP1]]121//122int16_t f10(int16_t *Ptr, int16_t Val) {123 return __atomic_sub_fetch(Ptr, Val, memory_order_seq_cst);124}125 126// CHECK-LABEL: @f11(127// CHECK-NEXT: entry:128// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw and ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2129// CHECK-NEXT: [[TMP1:%.*]] = and i16 [[TMP0]], [[VAL]]130// CHECK-NEXT: ret i16 [[TMP1]]131//132int16_t f11(int16_t *Ptr, int16_t Val) {133 return __atomic_and_fetch(Ptr, Val, memory_order_seq_cst);134}135 136// CHECK-LABEL: @f12(137// CHECK-NEXT: entry:138// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xor ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2139// CHECK-NEXT: [[TMP1:%.*]] = xor i16 [[TMP0]], [[VAL]]140// CHECK-NEXT: ret i16 [[TMP1]]141//142int16_t f12(int16_t *Ptr, int16_t Val) {143 return __atomic_xor_fetch(Ptr, Val, memory_order_seq_cst);144}145 146// CHECK-LABEL: @f13(147// CHECK-NEXT: entry:148// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw or ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2149// CHECK-NEXT: [[TMP1:%.*]] = or i16 [[TMP0]], [[VAL]]150// CHECK-NEXT: ret i16 [[TMP1]]151//152int16_t f13(int16_t *Ptr, int16_t Val) {153 return __atomic_or_fetch(Ptr, Val, memory_order_seq_cst);154}155 156// CHECK-LABEL: @f14(157// CHECK-NEXT: entry:158// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw nand ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2159// CHECK-NEXT: [[TMP1:%.*]] = and i16 [[TMP0]], [[VAL]]160// CHECK-NEXT: [[TMP2:%.*]] = xor i16 [[TMP1]], -1161// CHECK-NEXT: ret i16 [[TMP2]]162//163int16_t f14(int16_t *Ptr, int16_t Val) {164 return __atomic_nand_fetch(Ptr, Val, memory_order_seq_cst);165}166 167// CHECK-LABEL: @f15(168// CHECK-NEXT: entry:169// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2170// CHECK-NEXT: ret i16 [[TMP0]]171//172int16_t f15(int16_t *Ptr, int16_t Val) {173 return __atomic_fetch_add(Ptr, Val, memory_order_seq_cst);174}175 176// CHECK-LABEL: @f16(177// CHECK-NEXT: entry:178// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw sub ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2179// CHECK-NEXT: ret i16 [[TMP0]]180//181int16_t f16(int16_t *Ptr, int16_t Val) {182 return __atomic_fetch_sub(Ptr, Val, memory_order_seq_cst);183}184 185// CHECK-LABEL: @f17(186// CHECK-NEXT: entry:187// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw and ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2188// CHECK-NEXT: ret i16 [[TMP0]]189//190int16_t f17(int16_t *Ptr, int16_t Val) {191 return __atomic_fetch_and(Ptr, Val, memory_order_seq_cst);192}193 194// CHECK-LABEL: @f18(195// CHECK-NEXT: entry:196// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xor ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2197// CHECK-NEXT: ret i16 [[TMP0]]198//199int16_t f18(int16_t *Ptr, int16_t Val) {200 return __atomic_fetch_xor(Ptr, Val, memory_order_seq_cst);201}202 203// CHECK-LABEL: @f19(204// CHECK-NEXT: entry:205// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw or ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2206// CHECK-NEXT: ret i16 [[TMP0]]207//208int16_t f19(int16_t *Ptr, int16_t Val) {209 return __atomic_fetch_or(Ptr, Val, memory_order_seq_cst);210}211 212// CHECK-LABEL: @f20(213// CHECK-NEXT: entry:214// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw nand ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2215// CHECK-NEXT: ret i16 [[TMP0]]216//217int16_t f20(int16_t *Ptr, int16_t Val) {218 return __atomic_fetch_nand(Ptr, Val, memory_order_seq_cst);219}220