4243 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 -fzvector \3// RUN: -emit-llvm -o - -W -Wall -Werror \4// RUN: %s | opt -S -passes=mem2reg | FileCheck %s5 6volatile vector signed char sc, sc2;7volatile vector unsigned char uc, uc2;8volatile vector bool char bc, bc2;9 10volatile vector signed short ss, ss2;11volatile vector unsigned short us, us2;12volatile vector bool short bs, bs2;13 14volatile vector signed int si, si2;15volatile vector unsigned int ui, ui2;16volatile vector bool int bi, bi2;17 18volatile vector signed long long sl, sl2;19volatile vector unsigned long long ul, ul2;20volatile vector bool long long bl, bl2;21 22volatile vector signed __int128 slll, slll2;23volatile vector unsigned __int128 ulll, ulll2;24volatile vector bool __int128 blll, blll2;25 26volatile vector double fd, fd2;27 28volatile int cnt;29 30// CHECK-LABEL: define dso_local void @test_assign(31// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {32// CHECK-NEXT: [[ENTRY:.*:]]33// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 834// CHECK-NEXT: store volatile <16 x i8> [[TMP0]], ptr @sc, align 835// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 836// CHECK-NEXT: store volatile <16 x i8> [[TMP1]], ptr @uc, align 837// CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 838// CHECK-NEXT: store volatile <8 x i16> [[TMP2]], ptr @ss, align 839// CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 840// CHECK-NEXT: store volatile <8 x i16> [[TMP3]], ptr @us, align 841// CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 842// CHECK-NEXT: store volatile <4 x i32> [[TMP4]], ptr @si, align 843// CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 844// CHECK-NEXT: store volatile <4 x i32> [[TMP5]], ptr @ui, align 845// CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 846// CHECK-NEXT: store volatile <2 x i64> [[TMP6]], ptr @sl, align 847// CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 848// CHECK-NEXT: store volatile <2 x i64> [[TMP7]], ptr @ul, align 849// CHECK-NEXT: [[TMP8:%.*]] = load volatile <1 x i128>, ptr @slll2, align 850// CHECK-NEXT: store volatile <1 x i128> [[TMP8]], ptr @slll, align 851// CHECK-NEXT: [[TMP9:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 852// CHECK-NEXT: store volatile <1 x i128> [[TMP9]], ptr @ulll, align 853// CHECK-NEXT: [[TMP10:%.*]] = load volatile <2 x double>, ptr @fd2, align 854// CHECK-NEXT: store volatile <2 x double> [[TMP10]], ptr @fd, align 855// CHECK-NEXT: ret void56//57void test_assign(void) {58 59 sc = sc2;60 uc = uc2;61 62 ss = ss2;63 us = us2;64 65 si = si2;66 ui = ui2;67 68 sl = sl2;69 ul = ul2;70 71 slll = slll2;72 ulll = ulll2;73 74 fd = fd2;75}76 77// CHECK-LABEL: define dso_local void @test_pos(78// CHECK-SAME: ) #[[ATTR0]] {79// CHECK-NEXT: [[ENTRY:.*:]]80// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 881// CHECK-NEXT: store volatile <16 x i8> [[TMP0]], ptr @sc, align 882// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 883// CHECK-NEXT: store volatile <16 x i8> [[TMP1]], ptr @uc, align 884// CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 885// CHECK-NEXT: store volatile <8 x i16> [[TMP2]], ptr @ss, align 886// CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 887// CHECK-NEXT: store volatile <8 x i16> [[TMP3]], ptr @us, align 888// CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 889// CHECK-NEXT: store volatile <4 x i32> [[TMP4]], ptr @si, align 890// CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 891// CHECK-NEXT: store volatile <4 x i32> [[TMP5]], ptr @ui, align 892// CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 893// CHECK-NEXT: store volatile <2 x i64> [[TMP6]], ptr @sl, align 894// CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 895// CHECK-NEXT: store volatile <2 x i64> [[TMP7]], ptr @ul, align 896// CHECK-NEXT: [[TMP8:%.*]] = load volatile <1 x i128>, ptr @slll2, align 897// CHECK-NEXT: store volatile <1 x i128> [[TMP8]], ptr @slll, align 898// CHECK-NEXT: [[TMP9:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 899// CHECK-NEXT: store volatile <1 x i128> [[TMP9]], ptr @ulll, align 8100// CHECK-NEXT: [[TMP10:%.*]] = load volatile <2 x double>, ptr @fd2, align 8101// CHECK-NEXT: store volatile <2 x double> [[TMP10]], ptr @fd, align 8102// CHECK-NEXT: ret void103//104void test_pos(void) {105 106 sc = +sc2;107 uc = +uc2;108 109 ss = +ss2;110 us = +us2;111 112 si = +si2;113 ui = +ui2;114 115 sl = +sl2;116 ul = +ul2;117 118 slll = +slll2;119 ulll = +ulll2;120 121 fd = +fd2;122}123 124// CHECK-LABEL: define dso_local void @test_neg(125// CHECK-SAME: ) #[[ATTR0]] {126// CHECK-NEXT: [[ENTRY:.*:]]127// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8128// CHECK-NEXT: [[SUB:%.*]] = sub <16 x i8> zeroinitializer, [[TMP0]]129// CHECK-NEXT: store volatile <16 x i8> [[SUB]], ptr @sc, align 8130// CHECK-NEXT: [[TMP1:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8131// CHECK-NEXT: [[SUB1:%.*]] = sub <8 x i16> zeroinitializer, [[TMP1]]132// CHECK-NEXT: store volatile <8 x i16> [[SUB1]], ptr @ss, align 8133// CHECK-NEXT: [[TMP2:%.*]] = load volatile <4 x i32>, ptr @si2, align 8134// CHECK-NEXT: [[SUB2:%.*]] = sub <4 x i32> zeroinitializer, [[TMP2]]135// CHECK-NEXT: store volatile <4 x i32> [[SUB2]], ptr @si, align 8136// CHECK-NEXT: [[TMP3:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8137// CHECK-NEXT: [[SUB3:%.*]] = sub <2 x i64> zeroinitializer, [[TMP3]]138// CHECK-NEXT: store volatile <2 x i64> [[SUB3]], ptr @sl, align 8139// CHECK-NEXT: [[TMP4:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8140// CHECK-NEXT: [[SUB4:%.*]] = sub <1 x i128> zeroinitializer, [[TMP4]]141// CHECK-NEXT: store volatile <1 x i128> [[SUB4]], ptr @slll, align 8142// CHECK-NEXT: [[TMP5:%.*]] = load volatile <2 x double>, ptr @fd2, align 8143// CHECK-NEXT: [[FNEG:%.*]] = fneg <2 x double> [[TMP5]]144// CHECK-NEXT: store volatile <2 x double> [[FNEG]], ptr @fd, align 8145// CHECK-NEXT: ret void146//147void test_neg(void) {148 149 sc = -sc2;150 ss = -ss2;151 si = -si2;152 sl = -sl2;153 slll = -slll2;154 fd = -fd2;155}156 157// CHECK-LABEL: define dso_local void @test_preinc(158// CHECK-SAME: ) #[[ATTR0]] {159// CHECK-NEXT: [[ENTRY:.*:]]160// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8161// CHECK-NEXT: [[INC:%.*]] = add <16 x i8> [[TMP0]], splat (i8 1)162// CHECK-NEXT: store volatile <16 x i8> [[INC]], ptr @sc2, align 8163// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8164// CHECK-NEXT: [[INC1:%.*]] = add <16 x i8> [[TMP1]], splat (i8 1)165// CHECK-NEXT: store volatile <16 x i8> [[INC1]], ptr @uc2, align 8166// CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8167// CHECK-NEXT: [[INC2:%.*]] = add <8 x i16> [[TMP2]], splat (i16 1)168// CHECK-NEXT: store volatile <8 x i16> [[INC2]], ptr @ss2, align 8169// CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 8170// CHECK-NEXT: [[INC3:%.*]] = add <8 x i16> [[TMP3]], splat (i16 1)171// CHECK-NEXT: store volatile <8 x i16> [[INC3]], ptr @us2, align 8172// CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 8173// CHECK-NEXT: [[INC4:%.*]] = add <4 x i32> [[TMP4]], splat (i32 1)174// CHECK-NEXT: store volatile <4 x i32> [[INC4]], ptr @si2, align 8175// CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8176// CHECK-NEXT: [[INC5:%.*]] = add <4 x i32> [[TMP5]], splat (i32 1)177// CHECK-NEXT: store volatile <4 x i32> [[INC5]], ptr @ui2, align 8178// CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8179// CHECK-NEXT: [[INC6:%.*]] = add <2 x i64> [[TMP6]], splat (i64 1)180// CHECK-NEXT: store volatile <2 x i64> [[INC6]], ptr @sl2, align 8181// CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8182// CHECK-NEXT: [[INC7:%.*]] = add <2 x i64> [[TMP7]], splat (i64 1)183// CHECK-NEXT: store volatile <2 x i64> [[INC7]], ptr @ul2, align 8184// CHECK-NEXT: [[TMP8:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8185// CHECK-NEXT: [[INC8:%.*]] = add <1 x i128> [[TMP8]], splat (i128 1)186// CHECK-NEXT: store volatile <1 x i128> [[INC8]], ptr @slll2, align 8187// CHECK-NEXT: [[TMP9:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 8188// CHECK-NEXT: [[INC9:%.*]] = add <1 x i128> [[TMP9]], splat (i128 1)189// CHECK-NEXT: store volatile <1 x i128> [[INC9]], ptr @ulll2, align 8190// CHECK-NEXT: [[TMP10:%.*]] = load volatile <2 x double>, ptr @fd2, align 8191// CHECK-NEXT: [[INC10:%.*]] = fadd <2 x double> [[TMP10]], splat (double 1.000000e+00)192// CHECK-NEXT: store volatile <2 x double> [[INC10]], ptr @fd2, align 8193// CHECK-NEXT: ret void194//195void test_preinc(void) {196 197 ++sc2;198 ++uc2;199 200 ++ss2;201 ++us2;202 203 ++si2;204 ++ui2;205 206 ++sl2;207 ++ul2;208 209 ++slll2;210 ++ulll2;211 212 ++fd2;213}214 215// CHECK-LABEL: define dso_local void @test_postinc(216// CHECK-SAME: ) #[[ATTR0]] {217// CHECK-NEXT: [[ENTRY:.*:]]218// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8219// CHECK-NEXT: [[INC:%.*]] = add <16 x i8> [[TMP0]], splat (i8 1)220// CHECK-NEXT: store volatile <16 x i8> [[INC]], ptr @sc2, align 8221// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8222// CHECK-NEXT: [[INC1:%.*]] = add <16 x i8> [[TMP1]], splat (i8 1)223// CHECK-NEXT: store volatile <16 x i8> [[INC1]], ptr @uc2, align 8224// CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8225// CHECK-NEXT: [[INC2:%.*]] = add <8 x i16> [[TMP2]], splat (i16 1)226// CHECK-NEXT: store volatile <8 x i16> [[INC2]], ptr @ss2, align 8227// CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 8228// CHECK-NEXT: [[INC3:%.*]] = add <8 x i16> [[TMP3]], splat (i16 1)229// CHECK-NEXT: store volatile <8 x i16> [[INC3]], ptr @us2, align 8230// CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 8231// CHECK-NEXT: [[INC4:%.*]] = add <4 x i32> [[TMP4]], splat (i32 1)232// CHECK-NEXT: store volatile <4 x i32> [[INC4]], ptr @si2, align 8233// CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8234// CHECK-NEXT: [[INC5:%.*]] = add <4 x i32> [[TMP5]], splat (i32 1)235// CHECK-NEXT: store volatile <4 x i32> [[INC5]], ptr @ui2, align 8236// CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8237// CHECK-NEXT: [[INC6:%.*]] = add <2 x i64> [[TMP6]], splat (i64 1)238// CHECK-NEXT: store volatile <2 x i64> [[INC6]], ptr @sl2, align 8239// CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8240// CHECK-NEXT: [[INC7:%.*]] = add <2 x i64> [[TMP7]], splat (i64 1)241// CHECK-NEXT: store volatile <2 x i64> [[INC7]], ptr @ul2, align 8242// CHECK-NEXT: [[TMP8:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8243// CHECK-NEXT: [[INC8:%.*]] = add <1 x i128> [[TMP8]], splat (i128 1)244// CHECK-NEXT: store volatile <1 x i128> [[INC8]], ptr @slll2, align 8245// CHECK-NEXT: [[TMP9:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 8246// CHECK-NEXT: [[INC9:%.*]] = add <1 x i128> [[TMP9]], splat (i128 1)247// CHECK-NEXT: store volatile <1 x i128> [[INC9]], ptr @ulll2, align 8248// CHECK-NEXT: [[TMP10:%.*]] = load volatile <2 x double>, ptr @fd2, align 8249// CHECK-NEXT: [[INC10:%.*]] = fadd <2 x double> [[TMP10]], splat (double 1.000000e+00)250// CHECK-NEXT: store volatile <2 x double> [[INC10]], ptr @fd2, align 8251// CHECK-NEXT: ret void252//253void test_postinc(void) {254 255 sc2++;256 uc2++;257 258 ss2++;259 us2++;260 261 si2++;262 ui2++;263 264 sl2++;265 ul2++;266 267 slll2++;268 ulll2++;269 270 fd2++;271}272 273// CHECK-LABEL: define dso_local void @test_predec(274// CHECK-SAME: ) #[[ATTR0]] {275// CHECK-NEXT: [[ENTRY:.*:]]276// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8277// CHECK-NEXT: [[DEC:%.*]] = add <16 x i8> [[TMP0]], splat (i8 -1)278// CHECK-NEXT: store volatile <16 x i8> [[DEC]], ptr @sc2, align 8279// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8280// CHECK-NEXT: [[DEC1:%.*]] = add <16 x i8> [[TMP1]], splat (i8 -1)281// CHECK-NEXT: store volatile <16 x i8> [[DEC1]], ptr @uc2, align 8282// CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8283// CHECK-NEXT: [[DEC2:%.*]] = add <8 x i16> [[TMP2]], splat (i16 -1)284// CHECK-NEXT: store volatile <8 x i16> [[DEC2]], ptr @ss2, align 8285// CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 8286// CHECK-NEXT: [[DEC3:%.*]] = add <8 x i16> [[TMP3]], splat (i16 -1)287// CHECK-NEXT: store volatile <8 x i16> [[DEC3]], ptr @us2, align 8288// CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 8289// CHECK-NEXT: [[DEC4:%.*]] = add <4 x i32> [[TMP4]], splat (i32 -1)290// CHECK-NEXT: store volatile <4 x i32> [[DEC4]], ptr @si2, align 8291// CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8292// CHECK-NEXT: [[DEC5:%.*]] = add <4 x i32> [[TMP5]], splat (i32 -1)293// CHECK-NEXT: store volatile <4 x i32> [[DEC5]], ptr @ui2, align 8294// CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8295// CHECK-NEXT: [[DEC6:%.*]] = add <2 x i64> [[TMP6]], splat (i64 -1)296// CHECK-NEXT: store volatile <2 x i64> [[DEC6]], ptr @sl2, align 8297// CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8298// CHECK-NEXT: [[DEC7:%.*]] = add <2 x i64> [[TMP7]], splat (i64 -1)299// CHECK-NEXT: store volatile <2 x i64> [[DEC7]], ptr @ul2, align 8300// CHECK-NEXT: [[TMP8:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8301// CHECK-NEXT: [[DEC8:%.*]] = add <1 x i128> [[TMP8]], splat (i128 18446744073709551615)302// CHECK-NEXT: store volatile <1 x i128> [[DEC8]], ptr @slll2, align 8303// CHECK-NEXT: [[TMP9:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 8304// CHECK-NEXT: [[DEC9:%.*]] = add <1 x i128> [[TMP9]], splat (i128 18446744073709551615)305// CHECK-NEXT: store volatile <1 x i128> [[DEC9]], ptr @ulll2, align 8306// CHECK-NEXT: [[TMP10:%.*]] = load volatile <2 x double>, ptr @fd2, align 8307// CHECK-NEXT: [[DEC10:%.*]] = fadd <2 x double> [[TMP10]], splat (double -1.000000e+00)308// CHECK-NEXT: store volatile <2 x double> [[DEC10]], ptr @fd2, align 8309// CHECK-NEXT: ret void310//311void test_predec(void) {312 313 --sc2;314 --uc2;315 316 --ss2;317 --us2;318 319 --si2;320 --ui2;321 322 --sl2;323 --ul2;324 325 --slll2;326 --ulll2;327 328 --fd2;329}330 331// CHECK-LABEL: define dso_local void @test_postdec(332// CHECK-SAME: ) #[[ATTR0]] {333// CHECK-NEXT: [[ENTRY:.*:]]334// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8335// CHECK-NEXT: [[DEC:%.*]] = add <16 x i8> [[TMP0]], splat (i8 -1)336// CHECK-NEXT: store volatile <16 x i8> [[DEC]], ptr @sc2, align 8337// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8338// CHECK-NEXT: [[DEC1:%.*]] = add <16 x i8> [[TMP1]], splat (i8 -1)339// CHECK-NEXT: store volatile <16 x i8> [[DEC1]], ptr @uc2, align 8340// CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8341// CHECK-NEXT: [[DEC2:%.*]] = add <8 x i16> [[TMP2]], splat (i16 -1)342// CHECK-NEXT: store volatile <8 x i16> [[DEC2]], ptr @ss2, align 8343// CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 8344// CHECK-NEXT: [[DEC3:%.*]] = add <8 x i16> [[TMP3]], splat (i16 -1)345// CHECK-NEXT: store volatile <8 x i16> [[DEC3]], ptr @us2, align 8346// CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 8347// CHECK-NEXT: [[DEC4:%.*]] = add <4 x i32> [[TMP4]], splat (i32 -1)348// CHECK-NEXT: store volatile <4 x i32> [[DEC4]], ptr @si2, align 8349// CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8350// CHECK-NEXT: [[DEC5:%.*]] = add <4 x i32> [[TMP5]], splat (i32 -1)351// CHECK-NEXT: store volatile <4 x i32> [[DEC5]], ptr @ui2, align 8352// CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8353// CHECK-NEXT: [[DEC6:%.*]] = add <2 x i64> [[TMP6]], splat (i64 -1)354// CHECK-NEXT: store volatile <2 x i64> [[DEC6]], ptr @sl2, align 8355// CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8356// CHECK-NEXT: [[DEC7:%.*]] = add <2 x i64> [[TMP7]], splat (i64 -1)357// CHECK-NEXT: store volatile <2 x i64> [[DEC7]], ptr @ul2, align 8358// CHECK-NEXT: [[TMP8:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8359// CHECK-NEXT: [[DEC8:%.*]] = add <1 x i128> [[TMP8]], splat (i128 18446744073709551615)360// CHECK-NEXT: store volatile <1 x i128> [[DEC8]], ptr @slll2, align 8361// CHECK-NEXT: [[TMP9:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 8362// CHECK-NEXT: [[DEC9:%.*]] = add <1 x i128> [[TMP9]], splat (i128 18446744073709551615)363// CHECK-NEXT: store volatile <1 x i128> [[DEC9]], ptr @ulll2, align 8364// CHECK-NEXT: [[TMP10:%.*]] = load volatile <2 x double>, ptr @fd2, align 8365// CHECK-NEXT: [[DEC10:%.*]] = fadd <2 x double> [[TMP10]], splat (double -1.000000e+00)366// CHECK-NEXT: store volatile <2 x double> [[DEC10]], ptr @fd2, align 8367// CHECK-NEXT: ret void368//369void test_postdec(void) {370 371 sc2--;372 uc2--;373 374 ss2--;375 us2--;376 377 si2--;378 ui2--;379 380 sl2--;381 ul2--;382 383 slll2--;384 ulll2--;385 386 fd2--;387}388 389// CHECK-LABEL: define dso_local void @test_add(390// CHECK-SAME: ) #[[ATTR0]] {391// CHECK-NEXT: [[ENTRY:.*:]]392// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8393// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8394// CHECK-NEXT: [[ADD:%.*]] = add <16 x i8> [[TMP0]], [[TMP1]]395// CHECK-NEXT: store volatile <16 x i8> [[ADD]], ptr @sc, align 8396// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8397// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8398// CHECK-NEXT: [[ADD1:%.*]] = add <16 x i8> [[TMP2]], [[TMP3]]399// CHECK-NEXT: store volatile <16 x i8> [[ADD1]], ptr @sc, align 8400// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8401// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8402// CHECK-NEXT: [[ADD2:%.*]] = add <16 x i8> [[TMP4]], [[TMP5]]403// CHECK-NEXT: store volatile <16 x i8> [[ADD2]], ptr @sc, align 8404// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 8405// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8406// CHECK-NEXT: [[ADD3:%.*]] = add <16 x i8> [[TMP6]], [[TMP7]]407// CHECK-NEXT: store volatile <16 x i8> [[ADD3]], ptr @uc, align 8408// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8409// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8410// CHECK-NEXT: [[ADD4:%.*]] = add <16 x i8> [[TMP8]], [[TMP9]]411// CHECK-NEXT: store volatile <16 x i8> [[ADD4]], ptr @uc, align 8412// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 8413// CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8414// CHECK-NEXT: [[ADD5:%.*]] = add <16 x i8> [[TMP10]], [[TMP11]]415// CHECK-NEXT: store volatile <16 x i8> [[ADD5]], ptr @uc, align 8416// CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @ss, align 8417// CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8418// CHECK-NEXT: [[ADD6:%.*]] = add <8 x i16> [[TMP12]], [[TMP13]]419// CHECK-NEXT: store volatile <8 x i16> [[ADD6]], ptr @ss, align 8420// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8421// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8422// CHECK-NEXT: [[ADD7:%.*]] = add <8 x i16> [[TMP14]], [[TMP15]]423// CHECK-NEXT: store volatile <8 x i16> [[ADD7]], ptr @ss, align 8424// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @bs, align 8425// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8426// CHECK-NEXT: [[ADD8:%.*]] = add <8 x i16> [[TMP16]], [[TMP17]]427// CHECK-NEXT: store volatile <8 x i16> [[ADD8]], ptr @ss, align 8428// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @us, align 8429// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @us2, align 8430// CHECK-NEXT: [[ADD9:%.*]] = add <8 x i16> [[TMP18]], [[TMP19]]431// CHECK-NEXT: store volatile <8 x i16> [[ADD9]], ptr @us, align 8432// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 8433// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8434// CHECK-NEXT: [[ADD10:%.*]] = add <8 x i16> [[TMP20]], [[TMP21]]435// CHECK-NEXT: store volatile <8 x i16> [[ADD10]], ptr @us, align 8436// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @bs, align 8437// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us2, align 8438// CHECK-NEXT: [[ADD11:%.*]] = add <8 x i16> [[TMP22]], [[TMP23]]439// CHECK-NEXT: store volatile <8 x i16> [[ADD11]], ptr @us, align 8440// CHECK-NEXT: [[TMP24:%.*]] = load volatile <4 x i32>, ptr @si, align 8441// CHECK-NEXT: [[TMP25:%.*]] = load volatile <4 x i32>, ptr @si2, align 8442// CHECK-NEXT: [[ADD12:%.*]] = add <4 x i32> [[TMP24]], [[TMP25]]443// CHECK-NEXT: store volatile <4 x i32> [[ADD12]], ptr @si, align 8444// CHECK-NEXT: [[TMP26:%.*]] = load volatile <4 x i32>, ptr @si, align 8445// CHECK-NEXT: [[TMP27:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8446// CHECK-NEXT: [[ADD13:%.*]] = add <4 x i32> [[TMP26]], [[TMP27]]447// CHECK-NEXT: store volatile <4 x i32> [[ADD13]], ptr @si, align 8448// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @bi, align 8449// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8450// CHECK-NEXT: [[ADD14:%.*]] = add <4 x i32> [[TMP28]], [[TMP29]]451// CHECK-NEXT: store volatile <4 x i32> [[ADD14]], ptr @si, align 8452// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @ui, align 8453// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8454// CHECK-NEXT: [[ADD15:%.*]] = add <4 x i32> [[TMP30]], [[TMP31]]455// CHECK-NEXT: store volatile <4 x i32> [[ADD15]], ptr @ui, align 8456// CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @ui, align 8457// CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8458// CHECK-NEXT: [[ADD16:%.*]] = add <4 x i32> [[TMP32]], [[TMP33]]459// CHECK-NEXT: store volatile <4 x i32> [[ADD16]], ptr @ui, align 8460// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @bi, align 8461// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8462// CHECK-NEXT: [[ADD17:%.*]] = add <4 x i32> [[TMP34]], [[TMP35]]463// CHECK-NEXT: store volatile <4 x i32> [[ADD17]], ptr @ui, align 8464// CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @sl, align 8465// CHECK-NEXT: [[TMP37:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8466// CHECK-NEXT: [[ADD18:%.*]] = add <2 x i64> [[TMP36]], [[TMP37]]467// CHECK-NEXT: store volatile <2 x i64> [[ADD18]], ptr @sl, align 8468// CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @sl, align 8469// CHECK-NEXT: [[TMP39:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8470// CHECK-NEXT: [[ADD19:%.*]] = add <2 x i64> [[TMP38]], [[TMP39]]471// CHECK-NEXT: store volatile <2 x i64> [[ADD19]], ptr @sl, align 8472// CHECK-NEXT: [[TMP40:%.*]] = load volatile <2 x i64>, ptr @bl, align 8473// CHECK-NEXT: [[TMP41:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8474// CHECK-NEXT: [[ADD20:%.*]] = add <2 x i64> [[TMP40]], [[TMP41]]475// CHECK-NEXT: store volatile <2 x i64> [[ADD20]], ptr @sl, align 8476// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @ul, align 8477// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8478// CHECK-NEXT: [[ADD21:%.*]] = add <2 x i64> [[TMP42]], [[TMP43]]479// CHECK-NEXT: store volatile <2 x i64> [[ADD21]], ptr @ul, align 8480// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @ul, align 8481// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8482// CHECK-NEXT: [[ADD22:%.*]] = add <2 x i64> [[TMP44]], [[TMP45]]483// CHECK-NEXT: store volatile <2 x i64> [[ADD22]], ptr @ul, align 8484// CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 8485// CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8486// CHECK-NEXT: [[ADD23:%.*]] = add <2 x i64> [[TMP46]], [[TMP47]]487// CHECK-NEXT: store volatile <2 x i64> [[ADD23]], ptr @ul, align 8488// CHECK-NEXT: [[TMP48:%.*]] = load volatile <1 x i128>, ptr @slll, align 8489// CHECK-NEXT: [[TMP49:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8490// CHECK-NEXT: [[ADD24:%.*]] = add <1 x i128> [[TMP48]], [[TMP49]]491// CHECK-NEXT: store volatile <1 x i128> [[ADD24]], ptr @slll, align 8492// CHECK-NEXT: [[TMP50:%.*]] = load volatile <1 x i128>, ptr @slll, align 8493// CHECK-NEXT: [[TMP51:%.*]] = load volatile <1 x i128>, ptr @blll2, align 8494// CHECK-NEXT: [[ADD25:%.*]] = add <1 x i128> [[TMP50]], [[TMP51]]495// CHECK-NEXT: store volatile <1 x i128> [[ADD25]], ptr @slll, align 8496// CHECK-NEXT: [[TMP52:%.*]] = load volatile <1 x i128>, ptr @blll, align 8497// CHECK-NEXT: [[TMP53:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8498// CHECK-NEXT: [[ADD26:%.*]] = add <1 x i128> [[TMP52]], [[TMP53]]499// CHECK-NEXT: store volatile <1 x i128> [[ADD26]], ptr @slll, align 8500// CHECK-NEXT: [[TMP54:%.*]] = load volatile <1 x i128>, ptr @ulll, align 8501// CHECK-NEXT: [[TMP55:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 8502// CHECK-NEXT: [[ADD27:%.*]] = add <1 x i128> [[TMP54]], [[TMP55]]503// CHECK-NEXT: store volatile <1 x i128> [[ADD27]], ptr @ulll, align 8504// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @ulll, align 8505// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @blll2, align 8506// CHECK-NEXT: [[ADD28:%.*]] = add <1 x i128> [[TMP56]], [[TMP57]]507// CHECK-NEXT: store volatile <1 x i128> [[ADD28]], ptr @ulll, align 8508// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @blll, align 8509// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 8510// CHECK-NEXT: [[ADD29:%.*]] = add <1 x i128> [[TMP58]], [[TMP59]]511// CHECK-NEXT: store volatile <1 x i128> [[ADD29]], ptr @ulll, align 8512// CHECK-NEXT: [[TMP60:%.*]] = load volatile <2 x double>, ptr @fd, align 8513// CHECK-NEXT: [[TMP61:%.*]] = load volatile <2 x double>, ptr @fd2, align 8514// CHECK-NEXT: [[ADD30:%.*]] = fadd <2 x double> [[TMP60]], [[TMP61]]515// CHECK-NEXT: store volatile <2 x double> [[ADD30]], ptr @fd, align 8516// CHECK-NEXT: ret void517//518void test_add(void) {519 520 sc = sc + sc2;521 sc = sc + bc2;522 sc = bc + sc2;523 uc = uc + uc2;524 uc = uc + bc2;525 uc = bc + uc2;526 527 ss = ss + ss2;528 ss = ss + bs2;529 ss = bs + ss2;530 us = us + us2;531 us = us + bs2;532 us = bs + us2;533 534 si = si + si2;535 si = si + bi2;536 si = bi + si2;537 ui = ui + ui2;538 ui = ui + bi2;539 ui = bi + ui2;540 541 sl = sl + sl2;542 sl = sl + bl2;543 sl = bl + sl2;544 ul = ul + ul2;545 ul = ul + bl2;546 ul = bl + ul2;547 548 slll = slll + slll2;549 slll = slll + blll2;550 slll = blll + slll2;551 ulll = ulll + ulll2;552 ulll = ulll + blll2;553 ulll = blll + ulll2;554 555 fd = fd + fd2;556}557 558// CHECK-LABEL: define dso_local void @test_add_assign(559// CHECK-SAME: ) #[[ATTR0]] {560// CHECK-NEXT: [[ENTRY:.*:]]561// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8562// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8563// CHECK-NEXT: [[ADD:%.*]] = add <16 x i8> [[TMP1]], [[TMP0]]564// CHECK-NEXT: store volatile <16 x i8> [[ADD]], ptr @sc, align 8565// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8566// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 8567// CHECK-NEXT: [[ADD1:%.*]] = add <16 x i8> [[TMP3]], [[TMP2]]568// CHECK-NEXT: store volatile <16 x i8> [[ADD1]], ptr @sc, align 8569// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8570// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @uc, align 8571// CHECK-NEXT: [[ADD2:%.*]] = add <16 x i8> [[TMP5]], [[TMP4]]572// CHECK-NEXT: store volatile <16 x i8> [[ADD2]], ptr @uc, align 8573// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8574// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 8575// CHECK-NEXT: [[ADD3:%.*]] = add <16 x i8> [[TMP7]], [[TMP6]]576// CHECK-NEXT: store volatile <16 x i8> [[ADD3]], ptr @uc, align 8577// CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8578// CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @ss, align 8579// CHECK-NEXT: [[ADD4:%.*]] = add <8 x i16> [[TMP9]], [[TMP8]]580// CHECK-NEXT: store volatile <8 x i16> [[ADD4]], ptr @ss, align 8581// CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8582// CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @ss, align 8583// CHECK-NEXT: [[ADD5:%.*]] = add <8 x i16> [[TMP11]], [[TMP10]]584// CHECK-NEXT: store volatile <8 x i16> [[ADD5]], ptr @ss, align 8585// CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @us2, align 8586// CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @us, align 8587// CHECK-NEXT: [[ADD6:%.*]] = add <8 x i16> [[TMP13]], [[TMP12]]588// CHECK-NEXT: store volatile <8 x i16> [[ADD6]], ptr @us, align 8589// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8590// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @us, align 8591// CHECK-NEXT: [[ADD7:%.*]] = add <8 x i16> [[TMP15]], [[TMP14]]592// CHECK-NEXT: store volatile <8 x i16> [[ADD7]], ptr @us, align 8593// CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @si2, align 8594// CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @si, align 8595// CHECK-NEXT: [[ADD8:%.*]] = add <4 x i32> [[TMP17]], [[TMP16]]596// CHECK-NEXT: store volatile <4 x i32> [[ADD8]], ptr @si, align 8597// CHECK-NEXT: [[TMP18:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8598// CHECK-NEXT: [[TMP19:%.*]] = load volatile <4 x i32>, ptr @si, align 8599// CHECK-NEXT: [[ADD9:%.*]] = add <4 x i32> [[TMP19]], [[TMP18]]600// CHECK-NEXT: store volatile <4 x i32> [[ADD9]], ptr @si, align 8601// CHECK-NEXT: [[TMP20:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8602// CHECK-NEXT: [[TMP21:%.*]] = load volatile <4 x i32>, ptr @ui, align 8603// CHECK-NEXT: [[ADD10:%.*]] = add <4 x i32> [[TMP21]], [[TMP20]]604// CHECK-NEXT: store volatile <4 x i32> [[ADD10]], ptr @ui, align 8605// CHECK-NEXT: [[TMP22:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8606// CHECK-NEXT: [[TMP23:%.*]] = load volatile <4 x i32>, ptr @ui, align 8607// CHECK-NEXT: [[ADD11:%.*]] = add <4 x i32> [[TMP23]], [[TMP22]]608// CHECK-NEXT: store volatile <4 x i32> [[ADD11]], ptr @ui, align 8609// CHECK-NEXT: [[TMP24:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8610// CHECK-NEXT: [[TMP25:%.*]] = load volatile <2 x i64>, ptr @sl, align 8611// CHECK-NEXT: [[ADD12:%.*]] = add <2 x i64> [[TMP25]], [[TMP24]]612// CHECK-NEXT: store volatile <2 x i64> [[ADD12]], ptr @sl, align 8613// CHECK-NEXT: [[TMP26:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8614// CHECK-NEXT: [[TMP27:%.*]] = load volatile <2 x i64>, ptr @sl, align 8615// CHECK-NEXT: [[ADD13:%.*]] = add <2 x i64> [[TMP27]], [[TMP26]]616// CHECK-NEXT: store volatile <2 x i64> [[ADD13]], ptr @sl, align 8617// CHECK-NEXT: [[TMP28:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8618// CHECK-NEXT: [[TMP29:%.*]] = load volatile <2 x i64>, ptr @ul, align 8619// CHECK-NEXT: [[ADD14:%.*]] = add <2 x i64> [[TMP29]], [[TMP28]]620// CHECK-NEXT: store volatile <2 x i64> [[ADD14]], ptr @ul, align 8621// CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8622// CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @ul, align 8623// CHECK-NEXT: [[ADD15:%.*]] = add <2 x i64> [[TMP31]], [[TMP30]]624// CHECK-NEXT: store volatile <2 x i64> [[ADD15]], ptr @ul, align 8625// CHECK-NEXT: [[TMP32:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8626// CHECK-NEXT: [[TMP33:%.*]] = load volatile <1 x i128>, ptr @slll, align 8627// CHECK-NEXT: [[ADD16:%.*]] = add <1 x i128> [[TMP33]], [[TMP32]]628// CHECK-NEXT: store volatile <1 x i128> [[ADD16]], ptr @slll, align 8629// CHECK-NEXT: [[TMP34:%.*]] = load volatile <1 x i128>, ptr @blll2, align 8630// CHECK-NEXT: [[TMP35:%.*]] = load volatile <1 x i128>, ptr @slll, align 8631// CHECK-NEXT: [[ADD17:%.*]] = add <1 x i128> [[TMP35]], [[TMP34]]632// CHECK-NEXT: store volatile <1 x i128> [[ADD17]], ptr @slll, align 8633// CHECK-NEXT: [[TMP36:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 8634// CHECK-NEXT: [[TMP37:%.*]] = load volatile <1 x i128>, ptr @ulll, align 8635// CHECK-NEXT: [[ADD18:%.*]] = add <1 x i128> [[TMP37]], [[TMP36]]636// CHECK-NEXT: store volatile <1 x i128> [[ADD18]], ptr @ulll, align 8637// CHECK-NEXT: [[TMP38:%.*]] = load volatile <1 x i128>, ptr @blll2, align 8638// CHECK-NEXT: [[TMP39:%.*]] = load volatile <1 x i128>, ptr @ulll, align 8639// CHECK-NEXT: [[ADD19:%.*]] = add <1 x i128> [[TMP39]], [[TMP38]]640// CHECK-NEXT: store volatile <1 x i128> [[ADD19]], ptr @ulll, align 8641// CHECK-NEXT: [[TMP40:%.*]] = load volatile <2 x double>, ptr @fd2, align 8642// CHECK-NEXT: [[TMP41:%.*]] = load volatile <2 x double>, ptr @fd, align 8643// CHECK-NEXT: [[ADD20:%.*]] = fadd <2 x double> [[TMP41]], [[TMP40]]644// CHECK-NEXT: store volatile <2 x double> [[ADD20]], ptr @fd, align 8645// CHECK-NEXT: ret void646//647void test_add_assign(void) {648 649 sc += sc2;650 sc += bc2;651 uc += uc2;652 uc += bc2;653 654 ss += ss2;655 ss += bs2;656 us += us2;657 us += bs2;658 659 si += si2;660 si += bi2;661 ui += ui2;662 ui += bi2;663 664 sl += sl2;665 sl += bl2;666 ul += ul2;667 ul += bl2;668 669 slll += slll2;670 slll += blll2;671 ulll += ulll2;672 ulll += blll2;673 674 fd += fd2;675}676 677// CHECK-LABEL: define dso_local void @test_sub(678// CHECK-SAME: ) #[[ATTR0]] {679// CHECK-NEXT: [[ENTRY:.*:]]680// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8681// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8682// CHECK-NEXT: [[SUB:%.*]] = sub <16 x i8> [[TMP0]], [[TMP1]]683// CHECK-NEXT: store volatile <16 x i8> [[SUB]], ptr @sc, align 8684// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8685// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8686// CHECK-NEXT: [[SUB1:%.*]] = sub <16 x i8> [[TMP2]], [[TMP3]]687// CHECK-NEXT: store volatile <16 x i8> [[SUB1]], ptr @sc, align 8688// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8689// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8690// CHECK-NEXT: [[SUB2:%.*]] = sub <16 x i8> [[TMP4]], [[TMP5]]691// CHECK-NEXT: store volatile <16 x i8> [[SUB2]], ptr @sc, align 8692// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 8693// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8694// CHECK-NEXT: [[SUB3:%.*]] = sub <16 x i8> [[TMP6]], [[TMP7]]695// CHECK-NEXT: store volatile <16 x i8> [[SUB3]], ptr @uc, align 8696// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8697// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8698// CHECK-NEXT: [[SUB4:%.*]] = sub <16 x i8> [[TMP8]], [[TMP9]]699// CHECK-NEXT: store volatile <16 x i8> [[SUB4]], ptr @uc, align 8700// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 8701// CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8702// CHECK-NEXT: [[SUB5:%.*]] = sub <16 x i8> [[TMP10]], [[TMP11]]703// CHECK-NEXT: store volatile <16 x i8> [[SUB5]], ptr @uc, align 8704// CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @ss, align 8705// CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8706// CHECK-NEXT: [[SUB6:%.*]] = sub <8 x i16> [[TMP12]], [[TMP13]]707// CHECK-NEXT: store volatile <8 x i16> [[SUB6]], ptr @ss, align 8708// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8709// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8710// CHECK-NEXT: [[SUB7:%.*]] = sub <8 x i16> [[TMP14]], [[TMP15]]711// CHECK-NEXT: store volatile <8 x i16> [[SUB7]], ptr @ss, align 8712// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @bs, align 8713// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8714// CHECK-NEXT: [[SUB8:%.*]] = sub <8 x i16> [[TMP16]], [[TMP17]]715// CHECK-NEXT: store volatile <8 x i16> [[SUB8]], ptr @ss, align 8716// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @us, align 8717// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @us2, align 8718// CHECK-NEXT: [[SUB9:%.*]] = sub <8 x i16> [[TMP18]], [[TMP19]]719// CHECK-NEXT: store volatile <8 x i16> [[SUB9]], ptr @us, align 8720// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 8721// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8722// CHECK-NEXT: [[SUB10:%.*]] = sub <8 x i16> [[TMP20]], [[TMP21]]723// CHECK-NEXT: store volatile <8 x i16> [[SUB10]], ptr @us, align 8724// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @bs, align 8725// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us2, align 8726// CHECK-NEXT: [[SUB11:%.*]] = sub <8 x i16> [[TMP22]], [[TMP23]]727// CHECK-NEXT: store volatile <8 x i16> [[SUB11]], ptr @us, align 8728// CHECK-NEXT: [[TMP24:%.*]] = load volatile <4 x i32>, ptr @si, align 8729// CHECK-NEXT: [[TMP25:%.*]] = load volatile <4 x i32>, ptr @si2, align 8730// CHECK-NEXT: [[SUB12:%.*]] = sub <4 x i32> [[TMP24]], [[TMP25]]731// CHECK-NEXT: store volatile <4 x i32> [[SUB12]], ptr @si, align 8732// CHECK-NEXT: [[TMP26:%.*]] = load volatile <4 x i32>, ptr @si, align 8733// CHECK-NEXT: [[TMP27:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8734// CHECK-NEXT: [[SUB13:%.*]] = sub <4 x i32> [[TMP26]], [[TMP27]]735// CHECK-NEXT: store volatile <4 x i32> [[SUB13]], ptr @si, align 8736// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @bi, align 8737// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8738// CHECK-NEXT: [[SUB14:%.*]] = sub <4 x i32> [[TMP28]], [[TMP29]]739// CHECK-NEXT: store volatile <4 x i32> [[SUB14]], ptr @si, align 8740// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @ui, align 8741// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8742// CHECK-NEXT: [[SUB15:%.*]] = sub <4 x i32> [[TMP30]], [[TMP31]]743// CHECK-NEXT: store volatile <4 x i32> [[SUB15]], ptr @ui, align 8744// CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @ui, align 8745// CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8746// CHECK-NEXT: [[SUB16:%.*]] = sub <4 x i32> [[TMP32]], [[TMP33]]747// CHECK-NEXT: store volatile <4 x i32> [[SUB16]], ptr @ui, align 8748// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @bi, align 8749// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8750// CHECK-NEXT: [[SUB17:%.*]] = sub <4 x i32> [[TMP34]], [[TMP35]]751// CHECK-NEXT: store volatile <4 x i32> [[SUB17]], ptr @ui, align 8752// CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @sl, align 8753// CHECK-NEXT: [[TMP37:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8754// CHECK-NEXT: [[SUB18:%.*]] = sub <2 x i64> [[TMP36]], [[TMP37]]755// CHECK-NEXT: store volatile <2 x i64> [[SUB18]], ptr @sl, align 8756// CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @sl, align 8757// CHECK-NEXT: [[TMP39:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8758// CHECK-NEXT: [[SUB19:%.*]] = sub <2 x i64> [[TMP38]], [[TMP39]]759// CHECK-NEXT: store volatile <2 x i64> [[SUB19]], ptr @sl, align 8760// CHECK-NEXT: [[TMP40:%.*]] = load volatile <2 x i64>, ptr @bl, align 8761// CHECK-NEXT: [[TMP41:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8762// CHECK-NEXT: [[SUB20:%.*]] = sub <2 x i64> [[TMP40]], [[TMP41]]763// CHECK-NEXT: store volatile <2 x i64> [[SUB20]], ptr @sl, align 8764// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @ul, align 8765// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8766// CHECK-NEXT: [[SUB21:%.*]] = sub <2 x i64> [[TMP42]], [[TMP43]]767// CHECK-NEXT: store volatile <2 x i64> [[SUB21]], ptr @ul, align 8768// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @ul, align 8769// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8770// CHECK-NEXT: [[SUB22:%.*]] = sub <2 x i64> [[TMP44]], [[TMP45]]771// CHECK-NEXT: store volatile <2 x i64> [[SUB22]], ptr @ul, align 8772// CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 8773// CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8774// CHECK-NEXT: [[SUB23:%.*]] = sub <2 x i64> [[TMP46]], [[TMP47]]775// CHECK-NEXT: store volatile <2 x i64> [[SUB23]], ptr @ul, align 8776// CHECK-NEXT: [[TMP48:%.*]] = load volatile <1 x i128>, ptr @slll, align 8777// CHECK-NEXT: [[TMP49:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8778// CHECK-NEXT: [[SUB24:%.*]] = sub <1 x i128> [[TMP48]], [[TMP49]]779// CHECK-NEXT: store volatile <1 x i128> [[SUB24]], ptr @slll, align 8780// CHECK-NEXT: [[TMP50:%.*]] = load volatile <1 x i128>, ptr @slll, align 8781// CHECK-NEXT: [[TMP51:%.*]] = load volatile <1 x i128>, ptr @blll2, align 8782// CHECK-NEXT: [[SUB25:%.*]] = sub <1 x i128> [[TMP50]], [[TMP51]]783// CHECK-NEXT: store volatile <1 x i128> [[SUB25]], ptr @slll, align 8784// CHECK-NEXT: [[TMP52:%.*]] = load volatile <1 x i128>, ptr @blll, align 8785// CHECK-NEXT: [[TMP53:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8786// CHECK-NEXT: [[SUB26:%.*]] = sub <1 x i128> [[TMP52]], [[TMP53]]787// CHECK-NEXT: store volatile <1 x i128> [[SUB26]], ptr @slll, align 8788// CHECK-NEXT: [[TMP54:%.*]] = load volatile <1 x i128>, ptr @ulll, align 8789// CHECK-NEXT: [[TMP55:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 8790// CHECK-NEXT: [[SUB27:%.*]] = sub <1 x i128> [[TMP54]], [[TMP55]]791// CHECK-NEXT: store volatile <1 x i128> [[SUB27]], ptr @ulll, align 8792// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @ulll, align 8793// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @blll2, align 8794// CHECK-NEXT: [[SUB28:%.*]] = sub <1 x i128> [[TMP56]], [[TMP57]]795// CHECK-NEXT: store volatile <1 x i128> [[SUB28]], ptr @ulll, align 8796// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @blll, align 8797// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 8798// CHECK-NEXT: [[SUB29:%.*]] = sub <1 x i128> [[TMP58]], [[TMP59]]799// CHECK-NEXT: store volatile <1 x i128> [[SUB29]], ptr @ulll, align 8800// CHECK-NEXT: [[TMP60:%.*]] = load volatile <2 x double>, ptr @fd, align 8801// CHECK-NEXT: [[TMP61:%.*]] = load volatile <2 x double>, ptr @fd2, align 8802// CHECK-NEXT: [[SUB30:%.*]] = fsub <2 x double> [[TMP60]], [[TMP61]]803// CHECK-NEXT: store volatile <2 x double> [[SUB30]], ptr @fd, align 8804// CHECK-NEXT: ret void805//806void test_sub(void) {807 808 sc = sc - sc2;809 sc = sc - bc2;810 sc = bc - sc2;811 uc = uc - uc2;812 uc = uc - bc2;813 uc = bc - uc2;814 815 ss = ss - ss2;816 ss = ss - bs2;817 ss = bs - ss2;818 us = us - us2;819 us = us - bs2;820 us = bs - us2;821 822 si = si - si2;823 si = si - bi2;824 si = bi - si2;825 ui = ui - ui2;826 ui = ui - bi2;827 ui = bi - ui2;828 829 sl = sl - sl2;830 sl = sl - bl2;831 sl = bl - sl2;832 ul = ul - ul2;833 ul = ul - bl2;834 ul = bl - ul2;835 836 slll = slll - slll2;837 slll = slll - blll2;838 slll = blll - slll2;839 ulll = ulll - ulll2;840 ulll = ulll - blll2;841 ulll = blll - ulll2;842 843 fd = fd - fd2;844}845 846// CHECK-LABEL: define dso_local void @test_sub_assign(847// CHECK-SAME: ) #[[ATTR0]] {848// CHECK-NEXT: [[ENTRY:.*:]]849// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8850// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8851// CHECK-NEXT: [[SUB:%.*]] = sub <16 x i8> [[TMP1]], [[TMP0]]852// CHECK-NEXT: store volatile <16 x i8> [[SUB]], ptr @sc, align 8853// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8854// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 8855// CHECK-NEXT: [[SUB1:%.*]] = sub <16 x i8> [[TMP3]], [[TMP2]]856// CHECK-NEXT: store volatile <16 x i8> [[SUB1]], ptr @sc, align 8857// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8858// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @uc, align 8859// CHECK-NEXT: [[SUB2:%.*]] = sub <16 x i8> [[TMP5]], [[TMP4]]860// CHECK-NEXT: store volatile <16 x i8> [[SUB2]], ptr @uc, align 8861// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8862// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 8863// CHECK-NEXT: [[SUB3:%.*]] = sub <16 x i8> [[TMP7]], [[TMP6]]864// CHECK-NEXT: store volatile <16 x i8> [[SUB3]], ptr @uc, align 8865// CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8866// CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @ss, align 8867// CHECK-NEXT: [[SUB4:%.*]] = sub <8 x i16> [[TMP9]], [[TMP8]]868// CHECK-NEXT: store volatile <8 x i16> [[SUB4]], ptr @ss, align 8869// CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8870// CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @ss, align 8871// CHECK-NEXT: [[SUB5:%.*]] = sub <8 x i16> [[TMP11]], [[TMP10]]872// CHECK-NEXT: store volatile <8 x i16> [[SUB5]], ptr @ss, align 8873// CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @us2, align 8874// CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @us, align 8875// CHECK-NEXT: [[SUB6:%.*]] = sub <8 x i16> [[TMP13]], [[TMP12]]876// CHECK-NEXT: store volatile <8 x i16> [[SUB6]], ptr @us, align 8877// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8878// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @us, align 8879// CHECK-NEXT: [[SUB7:%.*]] = sub <8 x i16> [[TMP15]], [[TMP14]]880// CHECK-NEXT: store volatile <8 x i16> [[SUB7]], ptr @us, align 8881// CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @si2, align 8882// CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @si, align 8883// CHECK-NEXT: [[SUB8:%.*]] = sub <4 x i32> [[TMP17]], [[TMP16]]884// CHECK-NEXT: store volatile <4 x i32> [[SUB8]], ptr @si, align 8885// CHECK-NEXT: [[TMP18:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8886// CHECK-NEXT: [[TMP19:%.*]] = load volatile <4 x i32>, ptr @si, align 8887// CHECK-NEXT: [[SUB9:%.*]] = sub <4 x i32> [[TMP19]], [[TMP18]]888// CHECK-NEXT: store volatile <4 x i32> [[SUB9]], ptr @si, align 8889// CHECK-NEXT: [[TMP20:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8890// CHECK-NEXT: [[TMP21:%.*]] = load volatile <4 x i32>, ptr @ui, align 8891// CHECK-NEXT: [[SUB10:%.*]] = sub <4 x i32> [[TMP21]], [[TMP20]]892// CHECK-NEXT: store volatile <4 x i32> [[SUB10]], ptr @ui, align 8893// CHECK-NEXT: [[TMP22:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8894// CHECK-NEXT: [[TMP23:%.*]] = load volatile <4 x i32>, ptr @ui, align 8895// CHECK-NEXT: [[SUB11:%.*]] = sub <4 x i32> [[TMP23]], [[TMP22]]896// CHECK-NEXT: store volatile <4 x i32> [[SUB11]], ptr @ui, align 8897// CHECK-NEXT: [[TMP24:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8898// CHECK-NEXT: [[TMP25:%.*]] = load volatile <2 x i64>, ptr @sl, align 8899// CHECK-NEXT: [[SUB12:%.*]] = sub <2 x i64> [[TMP25]], [[TMP24]]900// CHECK-NEXT: store volatile <2 x i64> [[SUB12]], ptr @sl, align 8901// CHECK-NEXT: [[TMP26:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8902// CHECK-NEXT: [[TMP27:%.*]] = load volatile <2 x i64>, ptr @sl, align 8903// CHECK-NEXT: [[SUB13:%.*]] = sub <2 x i64> [[TMP27]], [[TMP26]]904// CHECK-NEXT: store volatile <2 x i64> [[SUB13]], ptr @sl, align 8905// CHECK-NEXT: [[TMP28:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8906// CHECK-NEXT: [[TMP29:%.*]] = load volatile <2 x i64>, ptr @ul, align 8907// CHECK-NEXT: [[SUB14:%.*]] = sub <2 x i64> [[TMP29]], [[TMP28]]908// CHECK-NEXT: store volatile <2 x i64> [[SUB14]], ptr @ul, align 8909// CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8910// CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @ul, align 8911// CHECK-NEXT: [[SUB15:%.*]] = sub <2 x i64> [[TMP31]], [[TMP30]]912// CHECK-NEXT: store volatile <2 x i64> [[SUB15]], ptr @ul, align 8913// CHECK-NEXT: [[TMP32:%.*]] = load volatile <1 x i128>, ptr @slll2, align 8914// CHECK-NEXT: [[TMP33:%.*]] = load volatile <1 x i128>, ptr @slll, align 8915// CHECK-NEXT: [[SUB16:%.*]] = sub <1 x i128> [[TMP33]], [[TMP32]]916// CHECK-NEXT: store volatile <1 x i128> [[SUB16]], ptr @slll, align 8917// CHECK-NEXT: [[TMP34:%.*]] = load volatile <1 x i128>, ptr @blll2, align 8918// CHECK-NEXT: [[TMP35:%.*]] = load volatile <1 x i128>, ptr @slll, align 8919// CHECK-NEXT: [[SUB17:%.*]] = sub <1 x i128> [[TMP35]], [[TMP34]]920// CHECK-NEXT: store volatile <1 x i128> [[SUB17]], ptr @slll, align 8921// CHECK-NEXT: [[TMP36:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 8922// CHECK-NEXT: [[TMP37:%.*]] = load volatile <1 x i128>, ptr @ulll, align 8923// CHECK-NEXT: [[SUB18:%.*]] = sub <1 x i128> [[TMP37]], [[TMP36]]924// CHECK-NEXT: store volatile <1 x i128> [[SUB18]], ptr @ulll, align 8925// CHECK-NEXT: [[TMP38:%.*]] = load volatile <1 x i128>, ptr @blll2, align 8926// CHECK-NEXT: [[TMP39:%.*]] = load volatile <1 x i128>, ptr @ulll, align 8927// CHECK-NEXT: [[SUB19:%.*]] = sub <1 x i128> [[TMP39]], [[TMP38]]928// CHECK-NEXT: store volatile <1 x i128> [[SUB19]], ptr @ulll, align 8929// CHECK-NEXT: [[TMP40:%.*]] = load volatile <2 x double>, ptr @fd2, align 8930// CHECK-NEXT: [[TMP41:%.*]] = load volatile <2 x double>, ptr @fd, align 8931// CHECK-NEXT: [[SUB20:%.*]] = fsub <2 x double> [[TMP41]], [[TMP40]]932// CHECK-NEXT: store volatile <2 x double> [[SUB20]], ptr @fd, align 8933// CHECK-NEXT: ret void934//935void test_sub_assign(void) {936 937 sc -= sc2;938 sc -= bc2;939 uc -= uc2;940 uc -= bc2;941 942 ss -= ss2;943 ss -= bs2;944 us -= us2;945 us -= bs2;946 947 si -= si2;948 si -= bi2;949 ui -= ui2;950 ui -= bi2;951 952 sl -= sl2;953 sl -= bl2;954 ul -= ul2;955 ul -= bl2;956 957 slll -= slll2;958 slll -= blll2;959 ulll -= ulll2;960 ulll -= blll2;961 962 fd -= fd2;963}964 965// CHECK-LABEL: define dso_local void @test_mul(966// CHECK-SAME: ) #[[ATTR0]] {967// CHECK-NEXT: [[ENTRY:.*:]]968// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8969// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8970// CHECK-NEXT: [[MUL:%.*]] = mul <16 x i8> [[TMP0]], [[TMP1]]971// CHECK-NEXT: store volatile <16 x i8> [[MUL]], ptr @sc, align 8972// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 8973// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8974// CHECK-NEXT: [[MUL1:%.*]] = mul <16 x i8> [[TMP2]], [[TMP3]]975// CHECK-NEXT: store volatile <16 x i8> [[MUL1]], ptr @uc, align 8976// CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss, align 8977// CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8978// CHECK-NEXT: [[MUL2:%.*]] = mul <8 x i16> [[TMP4]], [[TMP5]]979// CHECK-NEXT: store volatile <8 x i16> [[MUL2]], ptr @ss, align 8980// CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us, align 8981// CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us2, align 8982// CHECK-NEXT: [[MUL3:%.*]] = mul <8 x i16> [[TMP6]], [[TMP7]]983// CHECK-NEXT: store volatile <8 x i16> [[MUL3]], ptr @us, align 8984// CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si, align 8985// CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si2, align 8986// CHECK-NEXT: [[MUL4:%.*]] = mul <4 x i32> [[TMP8]], [[TMP9]]987// CHECK-NEXT: store volatile <4 x i32> [[MUL4]], ptr @si, align 8988// CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui, align 8989// CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8990// CHECK-NEXT: [[MUL5:%.*]] = mul <4 x i32> [[TMP10]], [[TMP11]]991// CHECK-NEXT: store volatile <4 x i32> [[MUL5]], ptr @ui, align 8992// CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl, align 8993// CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8994// CHECK-NEXT: [[MUL6:%.*]] = mul <2 x i64> [[TMP12]], [[TMP13]]995// CHECK-NEXT: store volatile <2 x i64> [[MUL6]], ptr @sl, align 8996// CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul, align 8997// CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8998// CHECK-NEXT: [[MUL7:%.*]] = mul <2 x i64> [[TMP14]], [[TMP15]]999// CHECK-NEXT: store volatile <2 x i64> [[MUL7]], ptr @ul, align 81000// CHECK-NEXT: [[TMP16:%.*]] = load volatile <1 x i128>, ptr @slll, align 81001// CHECK-NEXT: [[TMP17:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81002// CHECK-NEXT: [[MUL8:%.*]] = mul <1 x i128> [[TMP16]], [[TMP17]]1003// CHECK-NEXT: store volatile <1 x i128> [[MUL8]], ptr @slll, align 81004// CHECK-NEXT: [[TMP18:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81005// CHECK-NEXT: [[TMP19:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81006// CHECK-NEXT: [[MUL9:%.*]] = mul <1 x i128> [[TMP18]], [[TMP19]]1007// CHECK-NEXT: store volatile <1 x i128> [[MUL9]], ptr @ulll, align 81008// CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x double>, ptr @fd, align 81009// CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x double>, ptr @fd2, align 81010// CHECK-NEXT: [[MUL10:%.*]] = fmul <2 x double> [[TMP20]], [[TMP21]]1011// CHECK-NEXT: store volatile <2 x double> [[MUL10]], ptr @fd, align 81012// CHECK-NEXT: ret void1013//1014void test_mul(void) {1015 1016 sc = sc * sc2;1017 uc = uc * uc2;1018 1019 ss = ss * ss2;1020 us = us * us2;1021 1022 si = si * si2;1023 ui = ui * ui2;1024 1025 sl = sl * sl2;1026 ul = ul * ul2;1027 1028 slll = slll * slll2;1029 ulll = ulll * ulll2;1030 1031 fd = fd * fd2;1032}1033 1034// CHECK-LABEL: define dso_local void @test_mul_assign(1035// CHECK-SAME: ) #[[ATTR0]] {1036// CHECK-NEXT: [[ENTRY:.*:]]1037// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81038// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 81039// CHECK-NEXT: [[MUL:%.*]] = mul <16 x i8> [[TMP1]], [[TMP0]]1040// CHECK-NEXT: store volatile <16 x i8> [[MUL]], ptr @sc, align 81041// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81042// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc, align 81043// CHECK-NEXT: [[MUL1:%.*]] = mul <16 x i8> [[TMP3]], [[TMP2]]1044// CHECK-NEXT: store volatile <16 x i8> [[MUL1]], ptr @uc, align 81045// CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81046// CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss, align 81047// CHECK-NEXT: [[MUL2:%.*]] = mul <8 x i16> [[TMP5]], [[TMP4]]1048// CHECK-NEXT: store volatile <8 x i16> [[MUL2]], ptr @ss, align 81049// CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us2, align 81050// CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us, align 81051// CHECK-NEXT: [[MUL3:%.*]] = mul <8 x i16> [[TMP7]], [[TMP6]]1052// CHECK-NEXT: store volatile <8 x i16> [[MUL3]], ptr @us, align 81053// CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si2, align 81054// CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si, align 81055// CHECK-NEXT: [[MUL4:%.*]] = mul <4 x i32> [[TMP9]], [[TMP8]]1056// CHECK-NEXT: store volatile <4 x i32> [[MUL4]], ptr @si, align 81057// CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81058// CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui, align 81059// CHECK-NEXT: [[MUL5:%.*]] = mul <4 x i32> [[TMP11]], [[TMP10]]1060// CHECK-NEXT: store volatile <4 x i32> [[MUL5]], ptr @ui, align 81061// CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81062// CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl, align 81063// CHECK-NEXT: [[MUL6:%.*]] = mul <2 x i64> [[TMP13]], [[TMP12]]1064// CHECK-NEXT: store volatile <2 x i64> [[MUL6]], ptr @sl, align 81065// CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81066// CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul, align 81067// CHECK-NEXT: [[MUL7:%.*]] = mul <2 x i64> [[TMP15]], [[TMP14]]1068// CHECK-NEXT: store volatile <2 x i64> [[MUL7]], ptr @ul, align 81069// CHECK-NEXT: [[TMP16:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81070// CHECK-NEXT: [[TMP17:%.*]] = load volatile <1 x i128>, ptr @slll, align 81071// CHECK-NEXT: [[MUL8:%.*]] = mul <1 x i128> [[TMP17]], [[TMP16]]1072// CHECK-NEXT: store volatile <1 x i128> [[MUL8]], ptr @slll, align 81073// CHECK-NEXT: [[TMP18:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81074// CHECK-NEXT: [[TMP19:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81075// CHECK-NEXT: [[MUL9:%.*]] = mul <1 x i128> [[TMP19]], [[TMP18]]1076// CHECK-NEXT: store volatile <1 x i128> [[MUL9]], ptr @ulll, align 81077// CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x double>, ptr @fd2, align 81078// CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x double>, ptr @fd, align 81079// CHECK-NEXT: [[MUL10:%.*]] = fmul <2 x double> [[TMP21]], [[TMP20]]1080// CHECK-NEXT: store volatile <2 x double> [[MUL10]], ptr @fd, align 81081// CHECK-NEXT: ret void1082//1083void test_mul_assign(void) {1084 1085 sc *= sc2;1086 uc *= uc2;1087 1088 ss *= ss2;1089 us *= us2;1090 1091 si *= si2;1092 ui *= ui2;1093 1094 sl *= sl2;1095 ul *= ul2;1096 1097 slll *= slll2;1098 ulll *= ulll2;1099 1100 fd *= fd2;1101}1102 1103// CHECK-LABEL: define dso_local void @test_div(1104// CHECK-SAME: ) #[[ATTR0]] {1105// CHECK-NEXT: [[ENTRY:.*:]]1106// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 81107// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81108// CHECK-NEXT: [[DIV:%.*]] = sdiv <16 x i8> [[TMP0]], [[TMP1]]1109// CHECK-NEXT: store volatile <16 x i8> [[DIV]], ptr @sc, align 81110// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 81111// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81112// CHECK-NEXT: [[DIV1:%.*]] = udiv <16 x i8> [[TMP2]], [[TMP3]]1113// CHECK-NEXT: store volatile <16 x i8> [[DIV1]], ptr @uc, align 81114// CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss, align 81115// CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81116// CHECK-NEXT: [[DIV2:%.*]] = sdiv <8 x i16> [[TMP4]], [[TMP5]]1117// CHECK-NEXT: store volatile <8 x i16> [[DIV2]], ptr @ss, align 81118// CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us, align 81119// CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us2, align 81120// CHECK-NEXT: [[DIV3:%.*]] = udiv <8 x i16> [[TMP6]], [[TMP7]]1121// CHECK-NEXT: store volatile <8 x i16> [[DIV3]], ptr @us, align 81122// CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si, align 81123// CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si2, align 81124// CHECK-NEXT: [[DIV4:%.*]] = sdiv <4 x i32> [[TMP8]], [[TMP9]]1125// CHECK-NEXT: store volatile <4 x i32> [[DIV4]], ptr @si, align 81126// CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui, align 81127// CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81128// CHECK-NEXT: [[DIV5:%.*]] = udiv <4 x i32> [[TMP10]], [[TMP11]]1129// CHECK-NEXT: store volatile <4 x i32> [[DIV5]], ptr @ui, align 81130// CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl, align 81131// CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81132// CHECK-NEXT: [[DIV6:%.*]] = sdiv <2 x i64> [[TMP12]], [[TMP13]]1133// CHECK-NEXT: store volatile <2 x i64> [[DIV6]], ptr @sl, align 81134// CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul, align 81135// CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81136// CHECK-NEXT: [[DIV7:%.*]] = udiv <2 x i64> [[TMP14]], [[TMP15]]1137// CHECK-NEXT: store volatile <2 x i64> [[DIV7]], ptr @ul, align 81138// CHECK-NEXT: [[TMP16:%.*]] = load volatile <1 x i128>, ptr @slll, align 81139// CHECK-NEXT: [[TMP17:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81140// CHECK-NEXT: [[DIV8:%.*]] = sdiv <1 x i128> [[TMP16]], [[TMP17]]1141// CHECK-NEXT: store volatile <1 x i128> [[DIV8]], ptr @slll, align 81142// CHECK-NEXT: [[TMP18:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81143// CHECK-NEXT: [[TMP19:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81144// CHECK-NEXT: [[DIV9:%.*]] = udiv <1 x i128> [[TMP18]], [[TMP19]]1145// CHECK-NEXT: store volatile <1 x i128> [[DIV9]], ptr @ulll, align 81146// CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x double>, ptr @fd, align 81147// CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x double>, ptr @fd2, align 81148// CHECK-NEXT: [[DIV10:%.*]] = fdiv <2 x double> [[TMP20]], [[TMP21]]1149// CHECK-NEXT: store volatile <2 x double> [[DIV10]], ptr @fd, align 81150// CHECK-NEXT: ret void1151//1152void test_div(void) {1153 1154 sc = sc / sc2;1155 uc = uc / uc2;1156 1157 ss = ss / ss2;1158 us = us / us2;1159 1160 si = si / si2;1161 ui = ui / ui2;1162 1163 sl = sl / sl2;1164 ul = ul / ul2;1165 1166 slll = slll / slll2;1167 ulll = ulll / ulll2;1168 1169 fd = fd / fd2;1170}1171 1172// CHECK-LABEL: define dso_local void @test_div_assign(1173// CHECK-SAME: ) #[[ATTR0]] {1174// CHECK-NEXT: [[ENTRY:.*:]]1175// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81176// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 81177// CHECK-NEXT: [[DIV:%.*]] = sdiv <16 x i8> [[TMP1]], [[TMP0]]1178// CHECK-NEXT: store volatile <16 x i8> [[DIV]], ptr @sc, align 81179// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81180// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc, align 81181// CHECK-NEXT: [[DIV1:%.*]] = udiv <16 x i8> [[TMP3]], [[TMP2]]1182// CHECK-NEXT: store volatile <16 x i8> [[DIV1]], ptr @uc, align 81183// CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81184// CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss, align 81185// CHECK-NEXT: [[DIV2:%.*]] = sdiv <8 x i16> [[TMP5]], [[TMP4]]1186// CHECK-NEXT: store volatile <8 x i16> [[DIV2]], ptr @ss, align 81187// CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us2, align 81188// CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us, align 81189// CHECK-NEXT: [[DIV3:%.*]] = udiv <8 x i16> [[TMP7]], [[TMP6]]1190// CHECK-NEXT: store volatile <8 x i16> [[DIV3]], ptr @us, align 81191// CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si2, align 81192// CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si, align 81193// CHECK-NEXT: [[DIV4:%.*]] = sdiv <4 x i32> [[TMP9]], [[TMP8]]1194// CHECK-NEXT: store volatile <4 x i32> [[DIV4]], ptr @si, align 81195// CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81196// CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui, align 81197// CHECK-NEXT: [[DIV5:%.*]] = udiv <4 x i32> [[TMP11]], [[TMP10]]1198// CHECK-NEXT: store volatile <4 x i32> [[DIV5]], ptr @ui, align 81199// CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81200// CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl, align 81201// CHECK-NEXT: [[DIV6:%.*]] = sdiv <2 x i64> [[TMP13]], [[TMP12]]1202// CHECK-NEXT: store volatile <2 x i64> [[DIV6]], ptr @sl, align 81203// CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81204// CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul, align 81205// CHECK-NEXT: [[DIV7:%.*]] = udiv <2 x i64> [[TMP15]], [[TMP14]]1206// CHECK-NEXT: store volatile <2 x i64> [[DIV7]], ptr @ul, align 81207// CHECK-NEXT: [[TMP16:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81208// CHECK-NEXT: [[TMP17:%.*]] = load volatile <1 x i128>, ptr @slll, align 81209// CHECK-NEXT: [[DIV8:%.*]] = sdiv <1 x i128> [[TMP17]], [[TMP16]]1210// CHECK-NEXT: store volatile <1 x i128> [[DIV8]], ptr @slll, align 81211// CHECK-NEXT: [[TMP18:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81212// CHECK-NEXT: [[TMP19:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81213// CHECK-NEXT: [[DIV9:%.*]] = udiv <1 x i128> [[TMP19]], [[TMP18]]1214// CHECK-NEXT: store volatile <1 x i128> [[DIV9]], ptr @ulll, align 81215// CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x double>, ptr @fd2, align 81216// CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x double>, ptr @fd, align 81217// CHECK-NEXT: [[DIV10:%.*]] = fdiv <2 x double> [[TMP21]], [[TMP20]]1218// CHECK-NEXT: store volatile <2 x double> [[DIV10]], ptr @fd, align 81219// CHECK-NEXT: ret void1220//1221void test_div_assign(void) {1222 1223 sc /= sc2;1224 uc /= uc2;1225 1226 ss /= ss2;1227 us /= us2;1228 1229 si /= si2;1230 ui /= ui2;1231 1232 sl /= sl2;1233 ul /= ul2;1234 1235 slll /= slll2;1236 ulll /= ulll2;1237 1238 fd /= fd2;1239}1240 1241// CHECK-LABEL: define dso_local void @test_rem(1242// CHECK-SAME: ) #[[ATTR0]] {1243// CHECK-NEXT: [[ENTRY:.*:]]1244// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 81245// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81246// CHECK-NEXT: [[REM:%.*]] = srem <16 x i8> [[TMP0]], [[TMP1]]1247// CHECK-NEXT: store volatile <16 x i8> [[REM]], ptr @sc, align 81248// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 81249// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81250// CHECK-NEXT: [[REM1:%.*]] = urem <16 x i8> [[TMP2]], [[TMP3]]1251// CHECK-NEXT: store volatile <16 x i8> [[REM1]], ptr @uc, align 81252// CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss, align 81253// CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81254// CHECK-NEXT: [[REM2:%.*]] = srem <8 x i16> [[TMP4]], [[TMP5]]1255// CHECK-NEXT: store volatile <8 x i16> [[REM2]], ptr @ss, align 81256// CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us, align 81257// CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us2, align 81258// CHECK-NEXT: [[REM3:%.*]] = urem <8 x i16> [[TMP6]], [[TMP7]]1259// CHECK-NEXT: store volatile <8 x i16> [[REM3]], ptr @us, align 81260// CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si, align 81261// CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si2, align 81262// CHECK-NEXT: [[REM4:%.*]] = srem <4 x i32> [[TMP8]], [[TMP9]]1263// CHECK-NEXT: store volatile <4 x i32> [[REM4]], ptr @si, align 81264// CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui, align 81265// CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81266// CHECK-NEXT: [[REM5:%.*]] = urem <4 x i32> [[TMP10]], [[TMP11]]1267// CHECK-NEXT: store volatile <4 x i32> [[REM5]], ptr @ui, align 81268// CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl, align 81269// CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81270// CHECK-NEXT: [[REM6:%.*]] = srem <2 x i64> [[TMP12]], [[TMP13]]1271// CHECK-NEXT: store volatile <2 x i64> [[REM6]], ptr @sl, align 81272// CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul, align 81273// CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81274// CHECK-NEXT: [[REM7:%.*]] = urem <2 x i64> [[TMP14]], [[TMP15]]1275// CHECK-NEXT: store volatile <2 x i64> [[REM7]], ptr @ul, align 81276// CHECK-NEXT: [[TMP16:%.*]] = load volatile <1 x i128>, ptr @slll, align 81277// CHECK-NEXT: [[TMP17:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81278// CHECK-NEXT: [[REM8:%.*]] = srem <1 x i128> [[TMP16]], [[TMP17]]1279// CHECK-NEXT: store volatile <1 x i128> [[REM8]], ptr @slll, align 81280// CHECK-NEXT: [[TMP18:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81281// CHECK-NEXT: [[TMP19:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81282// CHECK-NEXT: [[REM9:%.*]] = urem <1 x i128> [[TMP18]], [[TMP19]]1283// CHECK-NEXT: store volatile <1 x i128> [[REM9]], ptr @ulll, align 81284// CHECK-NEXT: ret void1285//1286void test_rem(void) {1287 1288 sc = sc % sc2;1289 uc = uc % uc2;1290 1291 ss = ss % ss2;1292 us = us % us2;1293 1294 si = si % si2;1295 ui = ui % ui2;1296 1297 sl = sl % sl2;1298 ul = ul % ul2;1299 1300 slll = slll % slll2;1301 ulll = ulll % ulll2;1302}1303 1304// CHECK-LABEL: define dso_local void @test_rem_assign(1305// CHECK-SAME: ) #[[ATTR0]] {1306// CHECK-NEXT: [[ENTRY:.*:]]1307// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81308// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 81309// CHECK-NEXT: [[REM:%.*]] = srem <16 x i8> [[TMP1]], [[TMP0]]1310// CHECK-NEXT: store volatile <16 x i8> [[REM]], ptr @sc, align 81311// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81312// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc, align 81313// CHECK-NEXT: [[REM1:%.*]] = urem <16 x i8> [[TMP3]], [[TMP2]]1314// CHECK-NEXT: store volatile <16 x i8> [[REM1]], ptr @uc, align 81315// CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81316// CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss, align 81317// CHECK-NEXT: [[REM2:%.*]] = srem <8 x i16> [[TMP5]], [[TMP4]]1318// CHECK-NEXT: store volatile <8 x i16> [[REM2]], ptr @ss, align 81319// CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us2, align 81320// CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us, align 81321// CHECK-NEXT: [[REM3:%.*]] = urem <8 x i16> [[TMP7]], [[TMP6]]1322// CHECK-NEXT: store volatile <8 x i16> [[REM3]], ptr @us, align 81323// CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si2, align 81324// CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si, align 81325// CHECK-NEXT: [[REM4:%.*]] = srem <4 x i32> [[TMP9]], [[TMP8]]1326// CHECK-NEXT: store volatile <4 x i32> [[REM4]], ptr @si, align 81327// CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81328// CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui, align 81329// CHECK-NEXT: [[REM5:%.*]] = urem <4 x i32> [[TMP11]], [[TMP10]]1330// CHECK-NEXT: store volatile <4 x i32> [[REM5]], ptr @ui, align 81331// CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81332// CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl, align 81333// CHECK-NEXT: [[REM6:%.*]] = srem <2 x i64> [[TMP13]], [[TMP12]]1334// CHECK-NEXT: store volatile <2 x i64> [[REM6]], ptr @sl, align 81335// CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81336// CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul, align 81337// CHECK-NEXT: [[REM7:%.*]] = urem <2 x i64> [[TMP15]], [[TMP14]]1338// CHECK-NEXT: store volatile <2 x i64> [[REM7]], ptr @ul, align 81339// CHECK-NEXT: [[TMP16:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81340// CHECK-NEXT: [[TMP17:%.*]] = load volatile <1 x i128>, ptr @slll, align 81341// CHECK-NEXT: [[REM8:%.*]] = srem <1 x i128> [[TMP17]], [[TMP16]]1342// CHECK-NEXT: store volatile <1 x i128> [[REM8]], ptr @slll, align 81343// CHECK-NEXT: [[TMP18:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81344// CHECK-NEXT: [[TMP19:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81345// CHECK-NEXT: [[REM9:%.*]] = urem <1 x i128> [[TMP19]], [[TMP18]]1346// CHECK-NEXT: store volatile <1 x i128> [[REM9]], ptr @ulll, align 81347// CHECK-NEXT: ret void1348//1349void test_rem_assign(void) {1350 1351 sc %= sc2;1352 uc %= uc2;1353 1354 ss %= ss2;1355 us %= us2;1356 1357 si %= si2;1358 ui %= ui2;1359 1360 sl %= sl2;1361 ul %= ul2;1362 1363 slll %= slll2;1364 ulll %= ulll2;1365}1366 1367// CHECK-LABEL: define dso_local void @test_not(1368// CHECK-SAME: ) #[[ATTR0]] {1369// CHECK-NEXT: [[ENTRY:.*:]]1370// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81371// CHECK-NEXT: [[NOT:%.*]] = xor <16 x i8> [[TMP0]], splat (i8 -1)1372// CHECK-NEXT: store volatile <16 x i8> [[NOT]], ptr @sc, align 81373// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81374// CHECK-NEXT: [[NOT1:%.*]] = xor <16 x i8> [[TMP1]], splat (i8 -1)1375// CHECK-NEXT: store volatile <16 x i8> [[NOT1]], ptr @uc, align 81376// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81377// CHECK-NEXT: [[NOT2:%.*]] = xor <16 x i8> [[TMP2]], splat (i8 -1)1378// CHECK-NEXT: store volatile <16 x i8> [[NOT2]], ptr @bc, align 81379// CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81380// CHECK-NEXT: [[NOT3:%.*]] = xor <8 x i16> [[TMP3]], splat (i16 -1)1381// CHECK-NEXT: store volatile <8 x i16> [[NOT3]], ptr @ss, align 81382// CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @us2, align 81383// CHECK-NEXT: [[NOT4:%.*]] = xor <8 x i16> [[TMP4]], splat (i16 -1)1384// CHECK-NEXT: store volatile <8 x i16> [[NOT4]], ptr @us, align 81385// CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81386// CHECK-NEXT: [[NOT5:%.*]] = xor <8 x i16> [[TMP5]], splat (i16 -1)1387// CHECK-NEXT: store volatile <8 x i16> [[NOT5]], ptr @bs, align 81388// CHECK-NEXT: [[TMP6:%.*]] = load volatile <4 x i32>, ptr @si2, align 81389// CHECK-NEXT: [[NOT6:%.*]] = xor <4 x i32> [[TMP6]], splat (i32 -1)1390// CHECK-NEXT: store volatile <4 x i32> [[NOT6]], ptr @si, align 81391// CHECK-NEXT: [[TMP7:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81392// CHECK-NEXT: [[NOT7:%.*]] = xor <4 x i32> [[TMP7]], splat (i32 -1)1393// CHECK-NEXT: store volatile <4 x i32> [[NOT7]], ptr @ui, align 81394// CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @bi2, align 81395// CHECK-NEXT: [[NOT8:%.*]] = xor <4 x i32> [[TMP8]], splat (i32 -1)1396// CHECK-NEXT: store volatile <4 x i32> [[NOT8]], ptr @bi, align 81397// CHECK-NEXT: [[TMP9:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81398// CHECK-NEXT: [[NOT9:%.*]] = xor <2 x i64> [[TMP9]], splat (i64 -1)1399// CHECK-NEXT: store volatile <2 x i64> [[NOT9]], ptr @sl, align 81400// CHECK-NEXT: [[TMP10:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81401// CHECK-NEXT: [[NOT10:%.*]] = xor <2 x i64> [[TMP10]], splat (i64 -1)1402// CHECK-NEXT: store volatile <2 x i64> [[NOT10]], ptr @ul, align 81403// CHECK-NEXT: [[TMP11:%.*]] = load volatile <2 x i64>, ptr @bl2, align 81404// CHECK-NEXT: [[NOT11:%.*]] = xor <2 x i64> [[TMP11]], splat (i64 -1)1405// CHECK-NEXT: store volatile <2 x i64> [[NOT11]], ptr @bl, align 81406// CHECK-NEXT: [[TMP12:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81407// CHECK-NEXT: [[NOT12:%.*]] = xor <1 x i128> [[TMP12]], splat (i128 -1)1408// CHECK-NEXT: store volatile <1 x i128> [[NOT12]], ptr @slll, align 81409// CHECK-NEXT: [[TMP13:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81410// CHECK-NEXT: [[NOT13:%.*]] = xor <1 x i128> [[TMP13]], splat (i128 -1)1411// CHECK-NEXT: store volatile <1 x i128> [[NOT13]], ptr @ulll, align 81412// CHECK-NEXT: [[TMP14:%.*]] = load volatile <1 x i128>, ptr @blll2, align 81413// CHECK-NEXT: [[NOT14:%.*]] = xor <1 x i128> [[TMP14]], splat (i128 -1)1414// CHECK-NEXT: store volatile <1 x i128> [[NOT14]], ptr @blll, align 81415// CHECK-NEXT: ret void1416//1417void test_not(void) {1418 1419 sc = ~sc2;1420 uc = ~uc2;1421 bc = ~bc2;1422 1423 ss = ~ss2;1424 us = ~us2;1425 bs = ~bs2;1426 1427 si = ~si2;1428 ui = ~ui2;1429 bi = ~bi2;1430 1431 sl = ~sl2;1432 ul = ~ul2;1433 bl = ~bl2;1434 1435 slll = ~slll2;1436 ulll = ~ulll2;1437 blll = ~blll2;1438}1439 1440// CHECK-LABEL: define dso_local void @test_and(1441// CHECK-SAME: ) #[[ATTR0]] {1442// CHECK-NEXT: [[ENTRY:.*:]]1443// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 81444// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81445// CHECK-NEXT: [[AND:%.*]] = and <16 x i8> [[TMP0]], [[TMP1]]1446// CHECK-NEXT: store volatile <16 x i8> [[AND]], ptr @sc, align 81447// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 81448// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81449// CHECK-NEXT: [[AND1:%.*]] = and <16 x i8> [[TMP2]], [[TMP3]]1450// CHECK-NEXT: store volatile <16 x i8> [[AND1]], ptr @sc, align 81451// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 81452// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81453// CHECK-NEXT: [[AND2:%.*]] = and <16 x i8> [[TMP4]], [[TMP5]]1454// CHECK-NEXT: store volatile <16 x i8> [[AND2]], ptr @sc, align 81455// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 81456// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81457// CHECK-NEXT: [[AND3:%.*]] = and <16 x i8> [[TMP6]], [[TMP7]]1458// CHECK-NEXT: store volatile <16 x i8> [[AND3]], ptr @uc, align 81459// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 81460// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81461// CHECK-NEXT: [[AND4:%.*]] = and <16 x i8> [[TMP8]], [[TMP9]]1462// CHECK-NEXT: store volatile <16 x i8> [[AND4]], ptr @uc, align 81463// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 81464// CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81465// CHECK-NEXT: [[AND5:%.*]] = and <16 x i8> [[TMP10]], [[TMP11]]1466// CHECK-NEXT: store volatile <16 x i8> [[AND5]], ptr @uc, align 81467// CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @bc, align 81468// CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81469// CHECK-NEXT: [[AND6:%.*]] = and <16 x i8> [[TMP12]], [[TMP13]]1470// CHECK-NEXT: store volatile <16 x i8> [[AND6]], ptr @bc, align 81471// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 81472// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81473// CHECK-NEXT: [[AND7:%.*]] = and <8 x i16> [[TMP14]], [[TMP15]]1474// CHECK-NEXT: store volatile <8 x i16> [[AND7]], ptr @ss, align 81475// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 81476// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81477// CHECK-NEXT: [[AND8:%.*]] = and <8 x i16> [[TMP16]], [[TMP17]]1478// CHECK-NEXT: store volatile <8 x i16> [[AND8]], ptr @ss, align 81479// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs, align 81480// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81481// CHECK-NEXT: [[AND9:%.*]] = and <8 x i16> [[TMP18]], [[TMP19]]1482// CHECK-NEXT: store volatile <8 x i16> [[AND9]], ptr @ss, align 81483// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 81484// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us2, align 81485// CHECK-NEXT: [[AND10:%.*]] = and <8 x i16> [[TMP20]], [[TMP21]]1486// CHECK-NEXT: store volatile <8 x i16> [[AND10]], ptr @us, align 81487// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 81488// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81489// CHECK-NEXT: [[AND11:%.*]] = and <8 x i16> [[TMP22]], [[TMP23]]1490// CHECK-NEXT: store volatile <8 x i16> [[AND11]], ptr @us, align 81491// CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @bs, align 81492// CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us2, align 81493// CHECK-NEXT: [[AND12:%.*]] = and <8 x i16> [[TMP24]], [[TMP25]]1494// CHECK-NEXT: store volatile <8 x i16> [[AND12]], ptr @us, align 81495// CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @bs, align 81496// CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81497// CHECK-NEXT: [[AND13:%.*]] = and <8 x i16> [[TMP26]], [[TMP27]]1498// CHECK-NEXT: store volatile <8 x i16> [[AND13]], ptr @bs, align 81499// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 81500// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 81501// CHECK-NEXT: [[AND14:%.*]] = and <4 x i32> [[TMP28]], [[TMP29]]1502// CHECK-NEXT: store volatile <4 x i32> [[AND14]], ptr @si, align 81503// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 81504// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @bi2, align 81505// CHECK-NEXT: [[AND15:%.*]] = and <4 x i32> [[TMP30]], [[TMP31]]1506// CHECK-NEXT: store volatile <4 x i32> [[AND15]], ptr @si, align 81507// CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @bi, align 81508// CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si2, align 81509// CHECK-NEXT: [[AND16:%.*]] = and <4 x i32> [[TMP32]], [[TMP33]]1510// CHECK-NEXT: store volatile <4 x i32> [[AND16]], ptr @si, align 81511// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @ui, align 81512// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81513// CHECK-NEXT: [[AND17:%.*]] = and <4 x i32> [[TMP34]], [[TMP35]]1514// CHECK-NEXT: store volatile <4 x i32> [[AND17]], ptr @ui, align 81515// CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 81516// CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @bi2, align 81517// CHECK-NEXT: [[AND18:%.*]] = and <4 x i32> [[TMP36]], [[TMP37]]1518// CHECK-NEXT: store volatile <4 x i32> [[AND18]], ptr @ui, align 81519// CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @bi, align 81520// CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81521// CHECK-NEXT: [[AND19:%.*]] = and <4 x i32> [[TMP38]], [[TMP39]]1522// CHECK-NEXT: store volatile <4 x i32> [[AND19]], ptr @ui, align 81523// CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @bi, align 81524// CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @bi2, align 81525// CHECK-NEXT: [[AND20:%.*]] = and <4 x i32> [[TMP40]], [[TMP41]]1526// CHECK-NEXT: store volatile <4 x i32> [[AND20]], ptr @bi, align 81527// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 81528// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81529// CHECK-NEXT: [[AND21:%.*]] = and <2 x i64> [[TMP42]], [[TMP43]]1530// CHECK-NEXT: store volatile <2 x i64> [[AND21]], ptr @sl, align 81531// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 81532// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 81533// CHECK-NEXT: [[AND22:%.*]] = and <2 x i64> [[TMP44]], [[TMP45]]1534// CHECK-NEXT: store volatile <2 x i64> [[AND22]], ptr @sl, align 81535// CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 81536// CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81537// CHECK-NEXT: [[AND23:%.*]] = and <2 x i64> [[TMP46]], [[TMP47]]1538// CHECK-NEXT: store volatile <2 x i64> [[AND23]], ptr @sl, align 81539// CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @ul, align 81540// CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81541// CHECK-NEXT: [[AND24:%.*]] = and <2 x i64> [[TMP48]], [[TMP49]]1542// CHECK-NEXT: store volatile <2 x i64> [[AND24]], ptr @ul, align 81543// CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 81544// CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @bl2, align 81545// CHECK-NEXT: [[AND25:%.*]] = and <2 x i64> [[TMP50]], [[TMP51]]1546// CHECK-NEXT: store volatile <2 x i64> [[AND25]], ptr @ul, align 81547// CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @bl, align 81548// CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81549// CHECK-NEXT: [[AND26:%.*]] = and <2 x i64> [[TMP52]], [[TMP53]]1550// CHECK-NEXT: store volatile <2 x i64> [[AND26]], ptr @ul, align 81551// CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @bl, align 81552// CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @bl2, align 81553// CHECK-NEXT: [[AND27:%.*]] = and <2 x i64> [[TMP54]], [[TMP55]]1554// CHECK-NEXT: store volatile <2 x i64> [[AND27]], ptr @bl, align 81555// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @slll, align 81556// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81557// CHECK-NEXT: [[AND28:%.*]] = and <1 x i128> [[TMP56]], [[TMP57]]1558// CHECK-NEXT: store volatile <1 x i128> [[AND28]], ptr @slll, align 81559// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @slll, align 81560// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @blll2, align 81561// CHECK-NEXT: [[AND29:%.*]] = and <1 x i128> [[TMP58]], [[TMP59]]1562// CHECK-NEXT: store volatile <1 x i128> [[AND29]], ptr @slll, align 81563// CHECK-NEXT: [[TMP60:%.*]] = load volatile <1 x i128>, ptr @blll, align 81564// CHECK-NEXT: [[TMP61:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81565// CHECK-NEXT: [[AND30:%.*]] = and <1 x i128> [[TMP60]], [[TMP61]]1566// CHECK-NEXT: store volatile <1 x i128> [[AND30]], ptr @slll, align 81567// CHECK-NEXT: [[TMP62:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81568// CHECK-NEXT: [[TMP63:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81569// CHECK-NEXT: [[AND31:%.*]] = and <1 x i128> [[TMP62]], [[TMP63]]1570// CHECK-NEXT: store volatile <1 x i128> [[AND31]], ptr @ulll, align 81571// CHECK-NEXT: [[TMP64:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81572// CHECK-NEXT: [[TMP65:%.*]] = load volatile <1 x i128>, ptr @blll2, align 81573// CHECK-NEXT: [[AND32:%.*]] = and <1 x i128> [[TMP64]], [[TMP65]]1574// CHECK-NEXT: store volatile <1 x i128> [[AND32]], ptr @ulll, align 81575// CHECK-NEXT: [[TMP66:%.*]] = load volatile <1 x i128>, ptr @blll, align 81576// CHECK-NEXT: [[TMP67:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81577// CHECK-NEXT: [[AND33:%.*]] = and <1 x i128> [[TMP66]], [[TMP67]]1578// CHECK-NEXT: store volatile <1 x i128> [[AND33]], ptr @ulll, align 81579// CHECK-NEXT: [[TMP68:%.*]] = load volatile <1 x i128>, ptr @blll, align 81580// CHECK-NEXT: [[TMP69:%.*]] = load volatile <1 x i128>, ptr @blll2, align 81581// CHECK-NEXT: [[AND34:%.*]] = and <1 x i128> [[TMP68]], [[TMP69]]1582// CHECK-NEXT: store volatile <1 x i128> [[AND34]], ptr @blll, align 81583// CHECK-NEXT: ret void1584//1585void test_and(void) {1586 1587 sc = sc & sc2;1588 sc = sc & bc2;1589 sc = bc & sc2;1590 uc = uc & uc2;1591 uc = uc & bc2;1592 uc = bc & uc2;1593 bc = bc & bc2;1594 1595 ss = ss & ss2;1596 ss = ss & bs2;1597 ss = bs & ss2;1598 us = us & us2;1599 us = us & bs2;1600 us = bs & us2;1601 bs = bs & bs2;1602 1603 si = si & si2;1604 si = si & bi2;1605 si = bi & si2;1606 ui = ui & ui2;1607 ui = ui & bi2;1608 ui = bi & ui2;1609 bi = bi & bi2;1610 1611 sl = sl & sl2;1612 sl = sl & bl2;1613 sl = bl & sl2;1614 ul = ul & ul2;1615 ul = ul & bl2;1616 ul = bl & ul2;1617 bl = bl & bl2;1618 1619 slll = slll & slll2;1620 slll = slll & blll2;1621 slll = blll & slll2;1622 ulll = ulll & ulll2;1623 ulll = ulll & blll2;1624 ulll = blll & ulll2;1625 blll = blll & blll2;1626}1627 1628// CHECK-LABEL: define dso_local void @test_and_assign(1629// CHECK-SAME: ) #[[ATTR0]] {1630// CHECK-NEXT: [[ENTRY:.*:]]1631// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81632// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 81633// CHECK-NEXT: [[AND:%.*]] = and <16 x i8> [[TMP1]], [[TMP0]]1634// CHECK-NEXT: store volatile <16 x i8> [[AND]], ptr @sc, align 81635// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81636// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 81637// CHECK-NEXT: [[AND1:%.*]] = and <16 x i8> [[TMP3]], [[TMP2]]1638// CHECK-NEXT: store volatile <16 x i8> [[AND1]], ptr @sc, align 81639// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81640// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @uc, align 81641// CHECK-NEXT: [[AND2:%.*]] = and <16 x i8> [[TMP5]], [[TMP4]]1642// CHECK-NEXT: store volatile <16 x i8> [[AND2]], ptr @uc, align 81643// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81644// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 81645// CHECK-NEXT: [[AND3:%.*]] = and <16 x i8> [[TMP7]], [[TMP6]]1646// CHECK-NEXT: store volatile <16 x i8> [[AND3]], ptr @uc, align 81647// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81648// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc, align 81649// CHECK-NEXT: [[AND4:%.*]] = and <16 x i8> [[TMP9]], [[TMP8]]1650// CHECK-NEXT: store volatile <16 x i8> [[AND4]], ptr @bc, align 81651// CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81652// CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @ss, align 81653// CHECK-NEXT: [[AND5:%.*]] = and <8 x i16> [[TMP11]], [[TMP10]]1654// CHECK-NEXT: store volatile <8 x i16> [[AND5]], ptr @ss, align 81655// CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81656// CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @ss, align 81657// CHECK-NEXT: [[AND6:%.*]] = and <8 x i16> [[TMP13]], [[TMP12]]1658// CHECK-NEXT: store volatile <8 x i16> [[AND6]], ptr @ss, align 81659// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @us2, align 81660// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @us, align 81661// CHECK-NEXT: [[AND7:%.*]] = and <8 x i16> [[TMP15]], [[TMP14]]1662// CHECK-NEXT: store volatile <8 x i16> [[AND7]], ptr @us, align 81663// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81664// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @us, align 81665// CHECK-NEXT: [[AND8:%.*]] = and <8 x i16> [[TMP17]], [[TMP16]]1666// CHECK-NEXT: store volatile <8 x i16> [[AND8]], ptr @us, align 81667// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81668// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @bs, align 81669// CHECK-NEXT: [[AND9:%.*]] = and <8 x i16> [[TMP19]], [[TMP18]]1670// CHECK-NEXT: store volatile <8 x i16> [[AND9]], ptr @bs, align 81671// CHECK-NEXT: [[TMP20:%.*]] = load volatile <4 x i32>, ptr @si2, align 81672// CHECK-NEXT: [[TMP21:%.*]] = load volatile <4 x i32>, ptr @si, align 81673// CHECK-NEXT: [[AND10:%.*]] = and <4 x i32> [[TMP21]], [[TMP20]]1674// CHECK-NEXT: store volatile <4 x i32> [[AND10]], ptr @si, align 81675// CHECK-NEXT: [[TMP22:%.*]] = load volatile <4 x i32>, ptr @bi2, align 81676// CHECK-NEXT: [[TMP23:%.*]] = load volatile <4 x i32>, ptr @si, align 81677// CHECK-NEXT: [[AND11:%.*]] = and <4 x i32> [[TMP23]], [[TMP22]]1678// CHECK-NEXT: store volatile <4 x i32> [[AND11]], ptr @si, align 81679// CHECK-NEXT: [[TMP24:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81680// CHECK-NEXT: [[TMP25:%.*]] = load volatile <4 x i32>, ptr @ui, align 81681// CHECK-NEXT: [[AND12:%.*]] = and <4 x i32> [[TMP25]], [[TMP24]]1682// CHECK-NEXT: store volatile <4 x i32> [[AND12]], ptr @ui, align 81683// CHECK-NEXT: [[TMP26:%.*]] = load volatile <4 x i32>, ptr @bi2, align 81684// CHECK-NEXT: [[TMP27:%.*]] = load volatile <4 x i32>, ptr @ui, align 81685// CHECK-NEXT: [[AND13:%.*]] = and <4 x i32> [[TMP27]], [[TMP26]]1686// CHECK-NEXT: store volatile <4 x i32> [[AND13]], ptr @ui, align 81687// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @bi2, align 81688// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @bi, align 81689// CHECK-NEXT: [[AND14:%.*]] = and <4 x i32> [[TMP29]], [[TMP28]]1690// CHECK-NEXT: store volatile <4 x i32> [[AND14]], ptr @bi, align 81691// CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81692// CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @sl, align 81693// CHECK-NEXT: [[AND15:%.*]] = and <2 x i64> [[TMP31]], [[TMP30]]1694// CHECK-NEXT: store volatile <2 x i64> [[AND15]], ptr @sl, align 81695// CHECK-NEXT: [[TMP32:%.*]] = load volatile <2 x i64>, ptr @bl2, align 81696// CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x i64>, ptr @sl, align 81697// CHECK-NEXT: [[AND16:%.*]] = and <2 x i64> [[TMP33]], [[TMP32]]1698// CHECK-NEXT: store volatile <2 x i64> [[AND16]], ptr @sl, align 81699// CHECK-NEXT: [[TMP34:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81700// CHECK-NEXT: [[TMP35:%.*]] = load volatile <2 x i64>, ptr @ul, align 81701// CHECK-NEXT: [[AND17:%.*]] = and <2 x i64> [[TMP35]], [[TMP34]]1702// CHECK-NEXT: store volatile <2 x i64> [[AND17]], ptr @ul, align 81703// CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @bl2, align 81704// CHECK-NEXT: [[TMP37:%.*]] = load volatile <2 x i64>, ptr @ul, align 81705// CHECK-NEXT: [[AND18:%.*]] = and <2 x i64> [[TMP37]], [[TMP36]]1706// CHECK-NEXT: store volatile <2 x i64> [[AND18]], ptr @ul, align 81707// CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @bl2, align 81708// CHECK-NEXT: [[TMP39:%.*]] = load volatile <2 x i64>, ptr @bl, align 81709// CHECK-NEXT: [[AND19:%.*]] = and <2 x i64> [[TMP39]], [[TMP38]]1710// CHECK-NEXT: store volatile <2 x i64> [[AND19]], ptr @bl, align 81711// CHECK-NEXT: [[TMP40:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81712// CHECK-NEXT: [[TMP41:%.*]] = load volatile <1 x i128>, ptr @slll, align 81713// CHECK-NEXT: [[AND20:%.*]] = and <1 x i128> [[TMP41]], [[TMP40]]1714// CHECK-NEXT: store volatile <1 x i128> [[AND20]], ptr @slll, align 81715// CHECK-NEXT: [[TMP42:%.*]] = load volatile <1 x i128>, ptr @blll2, align 81716// CHECK-NEXT: [[TMP43:%.*]] = load volatile <1 x i128>, ptr @slll, align 81717// CHECK-NEXT: [[AND21:%.*]] = and <1 x i128> [[TMP43]], [[TMP42]]1718// CHECK-NEXT: store volatile <1 x i128> [[AND21]], ptr @slll, align 81719// CHECK-NEXT: [[TMP44:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81720// CHECK-NEXT: [[TMP45:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81721// CHECK-NEXT: [[AND22:%.*]] = and <1 x i128> [[TMP45]], [[TMP44]]1722// CHECK-NEXT: store volatile <1 x i128> [[AND22]], ptr @ulll, align 81723// CHECK-NEXT: [[TMP46:%.*]] = load volatile <1 x i128>, ptr @blll2, align 81724// CHECK-NEXT: [[TMP47:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81725// CHECK-NEXT: [[AND23:%.*]] = and <1 x i128> [[TMP47]], [[TMP46]]1726// CHECK-NEXT: store volatile <1 x i128> [[AND23]], ptr @ulll, align 81727// CHECK-NEXT: [[TMP48:%.*]] = load volatile <1 x i128>, ptr @blll2, align 81728// CHECK-NEXT: [[TMP49:%.*]] = load volatile <1 x i128>, ptr @blll, align 81729// CHECK-NEXT: [[AND24:%.*]] = and <1 x i128> [[TMP49]], [[TMP48]]1730// CHECK-NEXT: store volatile <1 x i128> [[AND24]], ptr @blll, align 81731// CHECK-NEXT: ret void1732//1733void test_and_assign(void) {1734 1735 sc &= sc2;1736 sc &= bc2;1737 uc &= uc2;1738 uc &= bc2;1739 bc &= bc2;1740 1741 ss &= ss2;1742 ss &= bs2;1743 us &= us2;1744 us &= bs2;1745 bs &= bs2;1746 1747 si &= si2;1748 si &= bi2;1749 ui &= ui2;1750 ui &= bi2;1751 bi &= bi2;1752 1753 sl &= sl2;1754 sl &= bl2;1755 ul &= ul2;1756 ul &= bl2;1757 bl &= bl2;1758 1759 slll &= slll2;1760 slll &= blll2;1761 ulll &= ulll2;1762 ulll &= blll2;1763 blll &= blll2;1764}1765 1766// CHECK-LABEL: define dso_local void @test_or(1767// CHECK-SAME: ) #[[ATTR0]] {1768// CHECK-NEXT: [[ENTRY:.*:]]1769// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 81770// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81771// CHECK-NEXT: [[OR:%.*]] = or <16 x i8> [[TMP0]], [[TMP1]]1772// CHECK-NEXT: store volatile <16 x i8> [[OR]], ptr @sc, align 81773// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 81774// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81775// CHECK-NEXT: [[OR1:%.*]] = or <16 x i8> [[TMP2]], [[TMP3]]1776// CHECK-NEXT: store volatile <16 x i8> [[OR1]], ptr @sc, align 81777// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 81778// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81779// CHECK-NEXT: [[OR2:%.*]] = or <16 x i8> [[TMP4]], [[TMP5]]1780// CHECK-NEXT: store volatile <16 x i8> [[OR2]], ptr @sc, align 81781// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 81782// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81783// CHECK-NEXT: [[OR3:%.*]] = or <16 x i8> [[TMP6]], [[TMP7]]1784// CHECK-NEXT: store volatile <16 x i8> [[OR3]], ptr @uc, align 81785// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 81786// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81787// CHECK-NEXT: [[OR4:%.*]] = or <16 x i8> [[TMP8]], [[TMP9]]1788// CHECK-NEXT: store volatile <16 x i8> [[OR4]], ptr @uc, align 81789// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 81790// CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81791// CHECK-NEXT: [[OR5:%.*]] = or <16 x i8> [[TMP10]], [[TMP11]]1792// CHECK-NEXT: store volatile <16 x i8> [[OR5]], ptr @uc, align 81793// CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @bc, align 81794// CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81795// CHECK-NEXT: [[OR6:%.*]] = or <16 x i8> [[TMP12]], [[TMP13]]1796// CHECK-NEXT: store volatile <16 x i8> [[OR6]], ptr @bc, align 81797// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 81798// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81799// CHECK-NEXT: [[OR7:%.*]] = or <8 x i16> [[TMP14]], [[TMP15]]1800// CHECK-NEXT: store volatile <8 x i16> [[OR7]], ptr @ss, align 81801// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 81802// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81803// CHECK-NEXT: [[OR8:%.*]] = or <8 x i16> [[TMP16]], [[TMP17]]1804// CHECK-NEXT: store volatile <8 x i16> [[OR8]], ptr @ss, align 81805// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs, align 81806// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81807// CHECK-NEXT: [[OR9:%.*]] = or <8 x i16> [[TMP18]], [[TMP19]]1808// CHECK-NEXT: store volatile <8 x i16> [[OR9]], ptr @ss, align 81809// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 81810// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us2, align 81811// CHECK-NEXT: [[OR10:%.*]] = or <8 x i16> [[TMP20]], [[TMP21]]1812// CHECK-NEXT: store volatile <8 x i16> [[OR10]], ptr @us, align 81813// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 81814// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81815// CHECK-NEXT: [[OR11:%.*]] = or <8 x i16> [[TMP22]], [[TMP23]]1816// CHECK-NEXT: store volatile <8 x i16> [[OR11]], ptr @us, align 81817// CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @bs, align 81818// CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us2, align 81819// CHECK-NEXT: [[OR12:%.*]] = or <8 x i16> [[TMP24]], [[TMP25]]1820// CHECK-NEXT: store volatile <8 x i16> [[OR12]], ptr @us, align 81821// CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @bs, align 81822// CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81823// CHECK-NEXT: [[OR13:%.*]] = or <8 x i16> [[TMP26]], [[TMP27]]1824// CHECK-NEXT: store volatile <8 x i16> [[OR13]], ptr @bs, align 81825// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 81826// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 81827// CHECK-NEXT: [[OR14:%.*]] = or <4 x i32> [[TMP28]], [[TMP29]]1828// CHECK-NEXT: store volatile <4 x i32> [[OR14]], ptr @si, align 81829// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 81830// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @bi2, align 81831// CHECK-NEXT: [[OR15:%.*]] = or <4 x i32> [[TMP30]], [[TMP31]]1832// CHECK-NEXT: store volatile <4 x i32> [[OR15]], ptr @si, align 81833// CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @bi, align 81834// CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si2, align 81835// CHECK-NEXT: [[OR16:%.*]] = or <4 x i32> [[TMP32]], [[TMP33]]1836// CHECK-NEXT: store volatile <4 x i32> [[OR16]], ptr @si, align 81837// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @ui, align 81838// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81839// CHECK-NEXT: [[OR17:%.*]] = or <4 x i32> [[TMP34]], [[TMP35]]1840// CHECK-NEXT: store volatile <4 x i32> [[OR17]], ptr @ui, align 81841// CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 81842// CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @bi2, align 81843// CHECK-NEXT: [[OR18:%.*]] = or <4 x i32> [[TMP36]], [[TMP37]]1844// CHECK-NEXT: store volatile <4 x i32> [[OR18]], ptr @ui, align 81845// CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @bi, align 81846// CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui2, align 81847// CHECK-NEXT: [[OR19:%.*]] = or <4 x i32> [[TMP38]], [[TMP39]]1848// CHECK-NEXT: store volatile <4 x i32> [[OR19]], ptr @ui, align 81849// CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @bi, align 81850// CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @bi2, align 81851// CHECK-NEXT: [[OR20:%.*]] = or <4 x i32> [[TMP40]], [[TMP41]]1852// CHECK-NEXT: store volatile <4 x i32> [[OR20]], ptr @bi, align 81853// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 81854// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81855// CHECK-NEXT: [[OR21:%.*]] = or <2 x i64> [[TMP42]], [[TMP43]]1856// CHECK-NEXT: store volatile <2 x i64> [[OR21]], ptr @sl, align 81857// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 81858// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 81859// CHECK-NEXT: [[OR22:%.*]] = or <2 x i64> [[TMP44]], [[TMP45]]1860// CHECK-NEXT: store volatile <2 x i64> [[OR22]], ptr @sl, align 81861// CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 81862// CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl2, align 81863// CHECK-NEXT: [[OR23:%.*]] = or <2 x i64> [[TMP46]], [[TMP47]]1864// CHECK-NEXT: store volatile <2 x i64> [[OR23]], ptr @sl, align 81865// CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @ul, align 81866// CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81867// CHECK-NEXT: [[OR24:%.*]] = or <2 x i64> [[TMP48]], [[TMP49]]1868// CHECK-NEXT: store volatile <2 x i64> [[OR24]], ptr @ul, align 81869// CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 81870// CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @bl2, align 81871// CHECK-NEXT: [[OR25:%.*]] = or <2 x i64> [[TMP50]], [[TMP51]]1872// CHECK-NEXT: store volatile <2 x i64> [[OR25]], ptr @ul, align 81873// CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @bl, align 81874// CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul2, align 81875// CHECK-NEXT: [[OR26:%.*]] = or <2 x i64> [[TMP52]], [[TMP53]]1876// CHECK-NEXT: store volatile <2 x i64> [[OR26]], ptr @ul, align 81877// CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @bl, align 81878// CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @bl2, align 81879// CHECK-NEXT: [[OR27:%.*]] = or <2 x i64> [[TMP54]], [[TMP55]]1880// CHECK-NEXT: store volatile <2 x i64> [[OR27]], ptr @bl, align 81881// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @slll, align 81882// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81883// CHECK-NEXT: [[OR28:%.*]] = or <1 x i128> [[TMP56]], [[TMP57]]1884// CHECK-NEXT: store volatile <1 x i128> [[OR28]], ptr @slll, align 81885// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @slll, align 81886// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @blll2, align 81887// CHECK-NEXT: [[OR29:%.*]] = or <1 x i128> [[TMP58]], [[TMP59]]1888// CHECK-NEXT: store volatile <1 x i128> [[OR29]], ptr @slll, align 81889// CHECK-NEXT: [[TMP60:%.*]] = load volatile <1 x i128>, ptr @blll, align 81890// CHECK-NEXT: [[TMP61:%.*]] = load volatile <1 x i128>, ptr @slll2, align 81891// CHECK-NEXT: [[OR30:%.*]] = or <1 x i128> [[TMP60]], [[TMP61]]1892// CHECK-NEXT: store volatile <1 x i128> [[OR30]], ptr @slll, align 81893// CHECK-NEXT: [[TMP62:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81894// CHECK-NEXT: [[TMP63:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81895// CHECK-NEXT: [[OR31:%.*]] = or <1 x i128> [[TMP62]], [[TMP63]]1896// CHECK-NEXT: store volatile <1 x i128> [[OR31]], ptr @ulll, align 81897// CHECK-NEXT: [[TMP64:%.*]] = load volatile <1 x i128>, ptr @ulll, align 81898// CHECK-NEXT: [[TMP65:%.*]] = load volatile <1 x i128>, ptr @blll2, align 81899// CHECK-NEXT: [[OR32:%.*]] = or <1 x i128> [[TMP64]], [[TMP65]]1900// CHECK-NEXT: store volatile <1 x i128> [[OR32]], ptr @ulll, align 81901// CHECK-NEXT: [[TMP66:%.*]] = load volatile <1 x i128>, ptr @blll, align 81902// CHECK-NEXT: [[TMP67:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 81903// CHECK-NEXT: [[OR33:%.*]] = or <1 x i128> [[TMP66]], [[TMP67]]1904// CHECK-NEXT: store volatile <1 x i128> [[OR33]], ptr @ulll, align 81905// CHECK-NEXT: [[TMP68:%.*]] = load volatile <1 x i128>, ptr @blll, align 81906// CHECK-NEXT: [[TMP69:%.*]] = load volatile <1 x i128>, ptr @blll2, align 81907// CHECK-NEXT: [[OR34:%.*]] = or <1 x i128> [[TMP68]], [[TMP69]]1908// CHECK-NEXT: store volatile <1 x i128> [[OR34]], ptr @blll, align 81909// CHECK-NEXT: ret void1910//1911void test_or(void) {1912 1913 sc = sc | sc2;1914 sc = sc | bc2;1915 sc = bc | sc2;1916 uc = uc | uc2;1917 uc = uc | bc2;1918 uc = bc | uc2;1919 bc = bc | bc2;1920 1921 ss = ss | ss2;1922 ss = ss | bs2;1923 ss = bs | ss2;1924 us = us | us2;1925 us = us | bs2;1926 us = bs | us2;1927 bs = bs | bs2;1928 1929 si = si | si2;1930 si = si | bi2;1931 si = bi | si2;1932 ui = ui | ui2;1933 ui = ui | bi2;1934 ui = bi | ui2;1935 bi = bi | bi2;1936 1937 sl = sl | sl2;1938 sl = sl | bl2;1939 sl = bl | sl2;1940 ul = ul | ul2;1941 ul = ul | bl2;1942 ul = bl | ul2;1943 bl = bl | bl2;1944 1945 slll = slll | slll2;1946 slll = slll | blll2;1947 slll = blll | slll2;1948 ulll = ulll | ulll2;1949 ulll = ulll | blll2;1950 ulll = blll | ulll2;1951 blll = blll | blll2;1952}1953 1954// CHECK-LABEL: define dso_local void @test_or_assign(1955// CHECK-SAME: ) #[[ATTR0]] {1956// CHECK-NEXT: [[ENTRY:.*:]]1957// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 81958// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 81959// CHECK-NEXT: [[OR:%.*]] = or <16 x i8> [[TMP1]], [[TMP0]]1960// CHECK-NEXT: store volatile <16 x i8> [[OR]], ptr @sc, align 81961// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81962// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 81963// CHECK-NEXT: [[OR1:%.*]] = or <16 x i8> [[TMP3]], [[TMP2]]1964// CHECK-NEXT: store volatile <16 x i8> [[OR1]], ptr @sc, align 81965// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @uc2, align 81966// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @uc, align 81967// CHECK-NEXT: [[OR2:%.*]] = or <16 x i8> [[TMP5]], [[TMP4]]1968// CHECK-NEXT: store volatile <16 x i8> [[OR2]], ptr @uc, align 81969// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81970// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 81971// CHECK-NEXT: [[OR3:%.*]] = or <16 x i8> [[TMP7]], [[TMP6]]1972// CHECK-NEXT: store volatile <16 x i8> [[OR3]], ptr @uc, align 81973// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @bc2, align 81974// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc, align 81975// CHECK-NEXT: [[OR4:%.*]] = or <16 x i8> [[TMP9]], [[TMP8]]1976// CHECK-NEXT: store volatile <16 x i8> [[OR4]], ptr @bc, align 81977// CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @ss2, align 81978// CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @ss, align 81979// CHECK-NEXT: [[OR5:%.*]] = or <8 x i16> [[TMP11]], [[TMP10]]1980// CHECK-NEXT: store volatile <8 x i16> [[OR5]], ptr @ss, align 81981// CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81982// CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @ss, align 81983// CHECK-NEXT: [[OR6:%.*]] = or <8 x i16> [[TMP13]], [[TMP12]]1984// CHECK-NEXT: store volatile <8 x i16> [[OR6]], ptr @ss, align 81985// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @us2, align 81986// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @us, align 81987// CHECK-NEXT: [[OR7:%.*]] = or <8 x i16> [[TMP15]], [[TMP14]]1988// CHECK-NEXT: store volatile <8 x i16> [[OR7]], ptr @us, align 81989// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81990// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @us, align 81991// CHECK-NEXT: [[OR8:%.*]] = or <8 x i16> [[TMP17]], [[TMP16]]1992// CHECK-NEXT: store volatile <8 x i16> [[OR8]], ptr @us, align 81993// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs2, align 81994// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @bs, align 81995// CHECK-NEXT: [[OR9:%.*]] = or <8 x i16> [[TMP19]], [[TMP18]]1996// CHECK-NEXT: store volatile <8 x i16> [[OR9]], ptr @bs, align 81997// CHECK-NEXT: [[TMP20:%.*]] = load volatile <4 x i32>, ptr @si2, align 81998// CHECK-NEXT: [[TMP21:%.*]] = load volatile <4 x i32>, ptr @si, align 81999// CHECK-NEXT: [[OR10:%.*]] = or <4 x i32> [[TMP21]], [[TMP20]]2000// CHECK-NEXT: store volatile <4 x i32> [[OR10]], ptr @si, align 82001// CHECK-NEXT: [[TMP22:%.*]] = load volatile <4 x i32>, ptr @bi2, align 82002// CHECK-NEXT: [[TMP23:%.*]] = load volatile <4 x i32>, ptr @si, align 82003// CHECK-NEXT: [[OR11:%.*]] = or <4 x i32> [[TMP23]], [[TMP22]]2004// CHECK-NEXT: store volatile <4 x i32> [[OR11]], ptr @si, align 82005// CHECK-NEXT: [[TMP24:%.*]] = load volatile <4 x i32>, ptr @ui2, align 82006// CHECK-NEXT: [[TMP25:%.*]] = load volatile <4 x i32>, ptr @ui, align 82007// CHECK-NEXT: [[OR12:%.*]] = or <4 x i32> [[TMP25]], [[TMP24]]2008// CHECK-NEXT: store volatile <4 x i32> [[OR12]], ptr @ui, align 82009// CHECK-NEXT: [[TMP26:%.*]] = load volatile <4 x i32>, ptr @bi2, align 82010// CHECK-NEXT: [[TMP27:%.*]] = load volatile <4 x i32>, ptr @ui, align 82011// CHECK-NEXT: [[OR13:%.*]] = or <4 x i32> [[TMP27]], [[TMP26]]2012// CHECK-NEXT: store volatile <4 x i32> [[OR13]], ptr @ui, align 82013// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @bi2, align 82014// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @bi, align 82015// CHECK-NEXT: [[OR14:%.*]] = or <4 x i32> [[TMP29]], [[TMP28]]2016// CHECK-NEXT: store volatile <4 x i32> [[OR14]], ptr @bi, align 82017// CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x i64>, ptr @sl2, align 82018// CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @sl, align 82019// CHECK-NEXT: [[OR15:%.*]] = or <2 x i64> [[TMP31]], [[TMP30]]2020// CHECK-NEXT: store volatile <2 x i64> [[OR15]], ptr @sl, align 82021// CHECK-NEXT: [[TMP32:%.*]] = load volatile <2 x i64>, ptr @bl2, align 82022// CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x i64>, ptr @sl, align 82023// CHECK-NEXT: [[OR16:%.*]] = or <2 x i64> [[TMP33]], [[TMP32]]2024// CHECK-NEXT: store volatile <2 x i64> [[OR16]], ptr @sl, align 82025// CHECK-NEXT: [[TMP34:%.*]] = load volatile <2 x i64>, ptr @ul2, align 82026// CHECK-NEXT: [[TMP35:%.*]] = load volatile <2 x i64>, ptr @ul, align 82027// CHECK-NEXT: [[OR17:%.*]] = or <2 x i64> [[TMP35]], [[TMP34]]2028// CHECK-NEXT: store volatile <2 x i64> [[OR17]], ptr @ul, align 82029// CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @bl2, align 82030// CHECK-NEXT: [[TMP37:%.*]] = load volatile <2 x i64>, ptr @ul, align 82031// CHECK-NEXT: [[OR18:%.*]] = or <2 x i64> [[TMP37]], [[TMP36]]2032// CHECK-NEXT: store volatile <2 x i64> [[OR18]], ptr @ul, align 82033// CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @bl2, align 82034// CHECK-NEXT: [[TMP39:%.*]] = load volatile <2 x i64>, ptr @bl, align 82035// CHECK-NEXT: [[OR19:%.*]] = or <2 x i64> [[TMP39]], [[TMP38]]2036// CHECK-NEXT: store volatile <2 x i64> [[OR19]], ptr @bl, align 82037// CHECK-NEXT: [[TMP40:%.*]] = load volatile <1 x i128>, ptr @slll2, align 82038// CHECK-NEXT: [[TMP41:%.*]] = load volatile <1 x i128>, ptr @slll, align 82039// CHECK-NEXT: [[OR20:%.*]] = or <1 x i128> [[TMP41]], [[TMP40]]2040// CHECK-NEXT: store volatile <1 x i128> [[OR20]], ptr @slll, align 82041// CHECK-NEXT: [[TMP42:%.*]] = load volatile <1 x i128>, ptr @blll2, align 82042// CHECK-NEXT: [[TMP43:%.*]] = load volatile <1 x i128>, ptr @slll, align 82043// CHECK-NEXT: [[OR21:%.*]] = or <1 x i128> [[TMP43]], [[TMP42]]2044// CHECK-NEXT: store volatile <1 x i128> [[OR21]], ptr @slll, align 82045// CHECK-NEXT: [[TMP44:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 82046// CHECK-NEXT: [[TMP45:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82047// CHECK-NEXT: [[OR22:%.*]] = or <1 x i128> [[TMP45]], [[TMP44]]2048// CHECK-NEXT: store volatile <1 x i128> [[OR22]], ptr @ulll, align 82049// CHECK-NEXT: [[TMP46:%.*]] = load volatile <1 x i128>, ptr @blll2, align 82050// CHECK-NEXT: [[TMP47:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82051// CHECK-NEXT: [[OR23:%.*]] = or <1 x i128> [[TMP47]], [[TMP46]]2052// CHECK-NEXT: store volatile <1 x i128> [[OR23]], ptr @ulll, align 82053// CHECK-NEXT: [[TMP48:%.*]] = load volatile <1 x i128>, ptr @blll2, align 82054// CHECK-NEXT: [[TMP49:%.*]] = load volatile <1 x i128>, ptr @blll, align 82055// CHECK-NEXT: [[OR24:%.*]] = or <1 x i128> [[TMP49]], [[TMP48]]2056// CHECK-NEXT: store volatile <1 x i128> [[OR24]], ptr @blll, align 82057// CHECK-NEXT: ret void2058//2059void test_or_assign(void) {2060 2061 sc |= sc2;2062 sc |= bc2;2063 uc |= uc2;2064 uc |= bc2;2065 bc |= bc2;2066 2067 ss |= ss2;2068 ss |= bs2;2069 us |= us2;2070 us |= bs2;2071 bs |= bs2;2072 2073 si |= si2;2074 si |= bi2;2075 ui |= ui2;2076 ui |= bi2;2077 bi |= bi2;2078 2079 sl |= sl2;2080 sl |= bl2;2081 ul |= ul2;2082 ul |= bl2;2083 bl |= bl2;2084 2085 slll |= slll2;2086 slll |= blll2;2087 ulll |= ulll2;2088 ulll |= blll2;2089 blll |= blll2;2090}2091 2092// CHECK-LABEL: define dso_local void @test_xor(2093// CHECK-SAME: ) #[[ATTR0]] {2094// CHECK-NEXT: [[ENTRY:.*:]]2095// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 82096// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 82097// CHECK-NEXT: [[XOR:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]]2098// CHECK-NEXT: store volatile <16 x i8> [[XOR]], ptr @sc, align 82099// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 82100// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 82101// CHECK-NEXT: [[XOR1:%.*]] = xor <16 x i8> [[TMP2]], [[TMP3]]2102// CHECK-NEXT: store volatile <16 x i8> [[XOR1]], ptr @sc, align 82103// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 82104// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 82105// CHECK-NEXT: [[XOR2:%.*]] = xor <16 x i8> [[TMP4]], [[TMP5]]2106// CHECK-NEXT: store volatile <16 x i8> [[XOR2]], ptr @sc, align 82107// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 82108// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 82109// CHECK-NEXT: [[XOR3:%.*]] = xor <16 x i8> [[TMP6]], [[TMP7]]2110// CHECK-NEXT: store volatile <16 x i8> [[XOR3]], ptr @uc, align 82111// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 82112// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 82113// CHECK-NEXT: [[XOR4:%.*]] = xor <16 x i8> [[TMP8]], [[TMP9]]2114// CHECK-NEXT: store volatile <16 x i8> [[XOR4]], ptr @uc, align 82115// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 82116// CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 82117// CHECK-NEXT: [[XOR5:%.*]] = xor <16 x i8> [[TMP10]], [[TMP11]]2118// CHECK-NEXT: store volatile <16 x i8> [[XOR5]], ptr @uc, align 82119// CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @bc, align 82120// CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @bc2, align 82121// CHECK-NEXT: [[XOR6:%.*]] = xor <16 x i8> [[TMP12]], [[TMP13]]2122// CHECK-NEXT: store volatile <16 x i8> [[XOR6]], ptr @bc, align 82123// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 82124// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 82125// CHECK-NEXT: [[XOR7:%.*]] = xor <8 x i16> [[TMP14]], [[TMP15]]2126// CHECK-NEXT: store volatile <8 x i16> [[XOR7]], ptr @ss, align 82127// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 82128// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @bs2, align 82129// CHECK-NEXT: [[XOR8:%.*]] = xor <8 x i16> [[TMP16]], [[TMP17]]2130// CHECK-NEXT: store volatile <8 x i16> [[XOR8]], ptr @ss, align 82131// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs, align 82132// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss2, align 82133// CHECK-NEXT: [[XOR9:%.*]] = xor <8 x i16> [[TMP18]], [[TMP19]]2134// CHECK-NEXT: store volatile <8 x i16> [[XOR9]], ptr @ss, align 82135// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 82136// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us2, align 82137// CHECK-NEXT: [[XOR10:%.*]] = xor <8 x i16> [[TMP20]], [[TMP21]]2138// CHECK-NEXT: store volatile <8 x i16> [[XOR10]], ptr @us, align 82139// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 82140// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @bs2, align 82141// CHECK-NEXT: [[XOR11:%.*]] = xor <8 x i16> [[TMP22]], [[TMP23]]2142// CHECK-NEXT: store volatile <8 x i16> [[XOR11]], ptr @us, align 82143// CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @bs, align 82144// CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us2, align 82145// CHECK-NEXT: [[XOR12:%.*]] = xor <8 x i16> [[TMP24]], [[TMP25]]2146// CHECK-NEXT: store volatile <8 x i16> [[XOR12]], ptr @us, align 82147// CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @bs, align 82148// CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @bs2, align 82149// CHECK-NEXT: [[XOR13:%.*]] = xor <8 x i16> [[TMP26]], [[TMP27]]2150// CHECK-NEXT: store volatile <8 x i16> [[XOR13]], ptr @bs, align 82151// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 82152// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 82153// CHECK-NEXT: [[XOR14:%.*]] = xor <4 x i32> [[TMP28]], [[TMP29]]2154// CHECK-NEXT: store volatile <4 x i32> [[XOR14]], ptr @si, align 82155// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 82156// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @bi2, align 82157// CHECK-NEXT: [[XOR15:%.*]] = xor <4 x i32> [[TMP30]], [[TMP31]]2158// CHECK-NEXT: store volatile <4 x i32> [[XOR15]], ptr @si, align 82159// CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @bi, align 82160// CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si2, align 82161// CHECK-NEXT: [[XOR16:%.*]] = xor <4 x i32> [[TMP32]], [[TMP33]]2162// CHECK-NEXT: store volatile <4 x i32> [[XOR16]], ptr @si, align 82163// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @ui, align 82164// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 82165// CHECK-NEXT: [[XOR17:%.*]] = xor <4 x i32> [[TMP34]], [[TMP35]]2166// CHECK-NEXT: store volatile <4 x i32> [[XOR17]], ptr @ui, align 82167// CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 82168// CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @bi2, align 82169// CHECK-NEXT: [[XOR18:%.*]] = xor <4 x i32> [[TMP36]], [[TMP37]]2170// CHECK-NEXT: store volatile <4 x i32> [[XOR18]], ptr @ui, align 82171// CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @bi, align 82172// CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui2, align 82173// CHECK-NEXT: [[XOR19:%.*]] = xor <4 x i32> [[TMP38]], [[TMP39]]2174// CHECK-NEXT: store volatile <4 x i32> [[XOR19]], ptr @ui, align 82175// CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @bi, align 82176// CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @bi2, align 82177// CHECK-NEXT: [[XOR20:%.*]] = xor <4 x i32> [[TMP40]], [[TMP41]]2178// CHECK-NEXT: store volatile <4 x i32> [[XOR20]], ptr @bi, align 82179// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 82180// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 82181// CHECK-NEXT: [[XOR21:%.*]] = xor <2 x i64> [[TMP42]], [[TMP43]]2182// CHECK-NEXT: store volatile <2 x i64> [[XOR21]], ptr @sl, align 82183// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 82184// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 82185// CHECK-NEXT: [[XOR22:%.*]] = xor <2 x i64> [[TMP44]], [[TMP45]]2186// CHECK-NEXT: store volatile <2 x i64> [[XOR22]], ptr @sl, align 82187// CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 82188// CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl2, align 82189// CHECK-NEXT: [[XOR23:%.*]] = xor <2 x i64> [[TMP46]], [[TMP47]]2190// CHECK-NEXT: store volatile <2 x i64> [[XOR23]], ptr @sl, align 82191// CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @ul, align 82192// CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul2, align 82193// CHECK-NEXT: [[XOR24:%.*]] = xor <2 x i64> [[TMP48]], [[TMP49]]2194// CHECK-NEXT: store volatile <2 x i64> [[XOR24]], ptr @ul, align 82195// CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 82196// CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @bl2, align 82197// CHECK-NEXT: [[XOR25:%.*]] = xor <2 x i64> [[TMP50]], [[TMP51]]2198// CHECK-NEXT: store volatile <2 x i64> [[XOR25]], ptr @ul, align 82199// CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @bl, align 82200// CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul2, align 82201// CHECK-NEXT: [[XOR26:%.*]] = xor <2 x i64> [[TMP52]], [[TMP53]]2202// CHECK-NEXT: store volatile <2 x i64> [[XOR26]], ptr @ul, align 82203// CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @bl, align 82204// CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @bl2, align 82205// CHECK-NEXT: [[XOR27:%.*]] = xor <2 x i64> [[TMP54]], [[TMP55]]2206// CHECK-NEXT: store volatile <2 x i64> [[XOR27]], ptr @bl, align 82207// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @slll, align 82208// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @slll2, align 82209// CHECK-NEXT: [[XOR28:%.*]] = xor <1 x i128> [[TMP56]], [[TMP57]]2210// CHECK-NEXT: store volatile <1 x i128> [[XOR28]], ptr @slll, align 82211// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @slll, align 82212// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @blll2, align 82213// CHECK-NEXT: [[XOR29:%.*]] = xor <1 x i128> [[TMP58]], [[TMP59]]2214// CHECK-NEXT: store volatile <1 x i128> [[XOR29]], ptr @slll, align 82215// CHECK-NEXT: [[TMP60:%.*]] = load volatile <1 x i128>, ptr @blll, align 82216// CHECK-NEXT: [[TMP61:%.*]] = load volatile <1 x i128>, ptr @slll2, align 82217// CHECK-NEXT: [[XOR30:%.*]] = xor <1 x i128> [[TMP60]], [[TMP61]]2218// CHECK-NEXT: store volatile <1 x i128> [[XOR30]], ptr @slll, align 82219// CHECK-NEXT: [[TMP62:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82220// CHECK-NEXT: [[TMP63:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 82221// CHECK-NEXT: [[XOR31:%.*]] = xor <1 x i128> [[TMP62]], [[TMP63]]2222// CHECK-NEXT: store volatile <1 x i128> [[XOR31]], ptr @ulll, align 82223// CHECK-NEXT: [[TMP64:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82224// CHECK-NEXT: [[TMP65:%.*]] = load volatile <1 x i128>, ptr @blll2, align 82225// CHECK-NEXT: [[XOR32:%.*]] = xor <1 x i128> [[TMP64]], [[TMP65]]2226// CHECK-NEXT: store volatile <1 x i128> [[XOR32]], ptr @ulll, align 82227// CHECK-NEXT: [[TMP66:%.*]] = load volatile <1 x i128>, ptr @blll, align 82228// CHECK-NEXT: [[TMP67:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 82229// CHECK-NEXT: [[XOR33:%.*]] = xor <1 x i128> [[TMP66]], [[TMP67]]2230// CHECK-NEXT: store volatile <1 x i128> [[XOR33]], ptr @ulll, align 82231// CHECK-NEXT: [[TMP68:%.*]] = load volatile <1 x i128>, ptr @blll, align 82232// CHECK-NEXT: [[TMP69:%.*]] = load volatile <1 x i128>, ptr @blll2, align 82233// CHECK-NEXT: [[XOR34:%.*]] = xor <1 x i128> [[TMP68]], [[TMP69]]2234// CHECK-NEXT: store volatile <1 x i128> [[XOR34]], ptr @blll, align 82235// CHECK-NEXT: ret void2236//2237void test_xor(void) {2238 2239 sc = sc ^ sc2;2240 sc = sc ^ bc2;2241 sc = bc ^ sc2;2242 uc = uc ^ uc2;2243 uc = uc ^ bc2;2244 uc = bc ^ uc2;2245 bc = bc ^ bc2;2246 2247 ss = ss ^ ss2;2248 ss = ss ^ bs2;2249 ss = bs ^ ss2;2250 us = us ^ us2;2251 us = us ^ bs2;2252 us = bs ^ us2;2253 bs = bs ^ bs2;2254 2255 si = si ^ si2;2256 si = si ^ bi2;2257 si = bi ^ si2;2258 ui = ui ^ ui2;2259 ui = ui ^ bi2;2260 ui = bi ^ ui2;2261 bi = bi ^ bi2;2262 2263 sl = sl ^ sl2;2264 sl = sl ^ bl2;2265 sl = bl ^ sl2;2266 ul = ul ^ ul2;2267 ul = ul ^ bl2;2268 ul = bl ^ ul2;2269 bl = bl ^ bl2;2270 2271 slll = slll ^ slll2;2272 slll = slll ^ blll2;2273 slll = blll ^ slll2;2274 ulll = ulll ^ ulll2;2275 ulll = ulll ^ blll2;2276 ulll = blll ^ ulll2;2277 blll = blll ^ blll2;2278}2279 2280// CHECK-LABEL: define dso_local void @test_xor_assign(2281// CHECK-SAME: ) #[[ATTR0]] {2282// CHECK-NEXT: [[ENTRY:.*:]]2283// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 82284// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 82285// CHECK-NEXT: [[XOR:%.*]] = xor <16 x i8> [[TMP1]], [[TMP0]]2286// CHECK-NEXT: store volatile <16 x i8> [[XOR]], ptr @sc, align 82287// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 82288// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 82289// CHECK-NEXT: [[XOR1:%.*]] = xor <16 x i8> [[TMP3]], [[TMP2]]2290// CHECK-NEXT: store volatile <16 x i8> [[XOR1]], ptr @sc, align 82291// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @uc2, align 82292// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @uc, align 82293// CHECK-NEXT: [[XOR2:%.*]] = xor <16 x i8> [[TMP5]], [[TMP4]]2294// CHECK-NEXT: store volatile <16 x i8> [[XOR2]], ptr @uc, align 82295// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @bc2, align 82296// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 82297// CHECK-NEXT: [[XOR3:%.*]] = xor <16 x i8> [[TMP7]], [[TMP6]]2298// CHECK-NEXT: store volatile <16 x i8> [[XOR3]], ptr @uc, align 82299// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @bc2, align 82300// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc, align 82301// CHECK-NEXT: [[XOR4:%.*]] = xor <16 x i8> [[TMP9]], [[TMP8]]2302// CHECK-NEXT: store volatile <16 x i8> [[XOR4]], ptr @bc, align 82303// CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @ss2, align 82304// CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @ss, align 82305// CHECK-NEXT: [[XOR5:%.*]] = xor <8 x i16> [[TMP11]], [[TMP10]]2306// CHECK-NEXT: store volatile <8 x i16> [[XOR5]], ptr @ss, align 82307// CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @bs2, align 82308// CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @ss, align 82309// CHECK-NEXT: [[XOR6:%.*]] = xor <8 x i16> [[TMP13]], [[TMP12]]2310// CHECK-NEXT: store volatile <8 x i16> [[XOR6]], ptr @ss, align 82311// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @us2, align 82312// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @us, align 82313// CHECK-NEXT: [[XOR7:%.*]] = xor <8 x i16> [[TMP15]], [[TMP14]]2314// CHECK-NEXT: store volatile <8 x i16> [[XOR7]], ptr @us, align 82315// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @bs2, align 82316// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @us, align 82317// CHECK-NEXT: [[XOR8:%.*]] = xor <8 x i16> [[TMP17]], [[TMP16]]2318// CHECK-NEXT: store volatile <8 x i16> [[XOR8]], ptr @us, align 82319// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs2, align 82320// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @bs, align 82321// CHECK-NEXT: [[XOR9:%.*]] = xor <8 x i16> [[TMP19]], [[TMP18]]2322// CHECK-NEXT: store volatile <8 x i16> [[XOR9]], ptr @bs, align 82323// CHECK-NEXT: [[TMP20:%.*]] = load volatile <4 x i32>, ptr @si2, align 82324// CHECK-NEXT: [[TMP21:%.*]] = load volatile <4 x i32>, ptr @si, align 82325// CHECK-NEXT: [[XOR10:%.*]] = xor <4 x i32> [[TMP21]], [[TMP20]]2326// CHECK-NEXT: store volatile <4 x i32> [[XOR10]], ptr @si, align 82327// CHECK-NEXT: [[TMP22:%.*]] = load volatile <4 x i32>, ptr @bi2, align 82328// CHECK-NEXT: [[TMP23:%.*]] = load volatile <4 x i32>, ptr @si, align 82329// CHECK-NEXT: [[XOR11:%.*]] = xor <4 x i32> [[TMP23]], [[TMP22]]2330// CHECK-NEXT: store volatile <4 x i32> [[XOR11]], ptr @si, align 82331// CHECK-NEXT: [[TMP24:%.*]] = load volatile <4 x i32>, ptr @ui2, align 82332// CHECK-NEXT: [[TMP25:%.*]] = load volatile <4 x i32>, ptr @ui, align 82333// CHECK-NEXT: [[XOR12:%.*]] = xor <4 x i32> [[TMP25]], [[TMP24]]2334// CHECK-NEXT: store volatile <4 x i32> [[XOR12]], ptr @ui, align 82335// CHECK-NEXT: [[TMP26:%.*]] = load volatile <4 x i32>, ptr @bi2, align 82336// CHECK-NEXT: [[TMP27:%.*]] = load volatile <4 x i32>, ptr @ui, align 82337// CHECK-NEXT: [[XOR13:%.*]] = xor <4 x i32> [[TMP27]], [[TMP26]]2338// CHECK-NEXT: store volatile <4 x i32> [[XOR13]], ptr @ui, align 82339// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @bi2, align 82340// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @bi, align 82341// CHECK-NEXT: [[XOR14:%.*]] = xor <4 x i32> [[TMP29]], [[TMP28]]2342// CHECK-NEXT: store volatile <4 x i32> [[XOR14]], ptr @bi, align 82343// CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x i64>, ptr @sl2, align 82344// CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @sl, align 82345// CHECK-NEXT: [[XOR15:%.*]] = xor <2 x i64> [[TMP31]], [[TMP30]]2346// CHECK-NEXT: store volatile <2 x i64> [[XOR15]], ptr @sl, align 82347// CHECK-NEXT: [[TMP32:%.*]] = load volatile <2 x i64>, ptr @bl2, align 82348// CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x i64>, ptr @sl, align 82349// CHECK-NEXT: [[XOR16:%.*]] = xor <2 x i64> [[TMP33]], [[TMP32]]2350// CHECK-NEXT: store volatile <2 x i64> [[XOR16]], ptr @sl, align 82351// CHECK-NEXT: [[TMP34:%.*]] = load volatile <2 x i64>, ptr @ul2, align 82352// CHECK-NEXT: [[TMP35:%.*]] = load volatile <2 x i64>, ptr @ul, align 82353// CHECK-NEXT: [[XOR17:%.*]] = xor <2 x i64> [[TMP35]], [[TMP34]]2354// CHECK-NEXT: store volatile <2 x i64> [[XOR17]], ptr @ul, align 82355// CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @bl2, align 82356// CHECK-NEXT: [[TMP37:%.*]] = load volatile <2 x i64>, ptr @ul, align 82357// CHECK-NEXT: [[XOR18:%.*]] = xor <2 x i64> [[TMP37]], [[TMP36]]2358// CHECK-NEXT: store volatile <2 x i64> [[XOR18]], ptr @ul, align 82359// CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @bl2, align 82360// CHECK-NEXT: [[TMP39:%.*]] = load volatile <2 x i64>, ptr @bl, align 82361// CHECK-NEXT: [[XOR19:%.*]] = xor <2 x i64> [[TMP39]], [[TMP38]]2362// CHECK-NEXT: store volatile <2 x i64> [[XOR19]], ptr @bl, align 82363// CHECK-NEXT: [[TMP40:%.*]] = load volatile <1 x i128>, ptr @slll2, align 82364// CHECK-NEXT: [[TMP41:%.*]] = load volatile <1 x i128>, ptr @slll, align 82365// CHECK-NEXT: [[XOR20:%.*]] = xor <1 x i128> [[TMP41]], [[TMP40]]2366// CHECK-NEXT: store volatile <1 x i128> [[XOR20]], ptr @slll, align 82367// CHECK-NEXT: [[TMP42:%.*]] = load volatile <1 x i128>, ptr @blll2, align 82368// CHECK-NEXT: [[TMP43:%.*]] = load volatile <1 x i128>, ptr @slll, align 82369// CHECK-NEXT: [[XOR21:%.*]] = xor <1 x i128> [[TMP43]], [[TMP42]]2370// CHECK-NEXT: store volatile <1 x i128> [[XOR21]], ptr @slll, align 82371// CHECK-NEXT: [[TMP44:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 82372// CHECK-NEXT: [[TMP45:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82373// CHECK-NEXT: [[XOR22:%.*]] = xor <1 x i128> [[TMP45]], [[TMP44]]2374// CHECK-NEXT: store volatile <1 x i128> [[XOR22]], ptr @ulll, align 82375// CHECK-NEXT: [[TMP46:%.*]] = load volatile <1 x i128>, ptr @blll2, align 82376// CHECK-NEXT: [[TMP47:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82377// CHECK-NEXT: [[XOR23:%.*]] = xor <1 x i128> [[TMP47]], [[TMP46]]2378// CHECK-NEXT: store volatile <1 x i128> [[XOR23]], ptr @ulll, align 82379// CHECK-NEXT: [[TMP48:%.*]] = load volatile <1 x i128>, ptr @blll2, align 82380// CHECK-NEXT: [[TMP49:%.*]] = load volatile <1 x i128>, ptr @blll, align 82381// CHECK-NEXT: [[XOR24:%.*]] = xor <1 x i128> [[TMP49]], [[TMP48]]2382// CHECK-NEXT: store volatile <1 x i128> [[XOR24]], ptr @blll, align 82383// CHECK-NEXT: ret void2384//2385void test_xor_assign(void) {2386 2387 sc ^= sc2;2388 sc ^= bc2;2389 uc ^= uc2;2390 uc ^= bc2;2391 bc ^= bc2;2392 2393 ss ^= ss2;2394 ss ^= bs2;2395 us ^= us2;2396 us ^= bs2;2397 bs ^= bs2;2398 2399 si ^= si2;2400 si ^= bi2;2401 ui ^= ui2;2402 ui ^= bi2;2403 bi ^= bi2;2404 2405 sl ^= sl2;2406 sl ^= bl2;2407 ul ^= ul2;2408 ul ^= bl2;2409 bl ^= bl2;2410 2411 slll ^= slll2;2412 slll ^= blll2;2413 ulll ^= ulll2;2414 ulll ^= blll2;2415 blll ^= blll2;2416}2417 2418// CHECK-LABEL: define dso_local void @test_sl(2419// CHECK-SAME: ) #[[ATTR0]] {2420// CHECK-NEXT: [[ENTRY:.*:]]2421// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 82422// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 82423// CHECK-NEXT: [[SHL:%.*]] = shl <16 x i8> [[TMP0]], [[TMP1]]2424// CHECK-NEXT: store volatile <16 x i8> [[SHL]], ptr @sc, align 82425// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 82426// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 82427// CHECK-NEXT: [[SHL1:%.*]] = shl <16 x i8> [[TMP2]], [[TMP3]]2428// CHECK-NEXT: store volatile <16 x i8> [[SHL1]], ptr @sc, align 82429// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @sc, align 82430// CHECK-NEXT: [[TMP5:%.*]] = load volatile i32, ptr @cnt, align 42431// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[TMP5]], i64 02432// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer2433// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT]] to <16 x i8>2434// CHECK-NEXT: [[SHL2:%.*]] = shl <16 x i8> [[TMP4]], [[SH_PROM]]2435// CHECK-NEXT: store volatile <16 x i8> [[SHL2]], ptr @sc, align 82436// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @sc, align 82437// CHECK-NEXT: [[SHL3:%.*]] = shl <16 x i8> [[TMP6]], splat (i8 5)2438// CHECK-NEXT: store volatile <16 x i8> [[SHL3]], ptr @sc, align 82439// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 82440// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @sc2, align 82441// CHECK-NEXT: [[SHL4:%.*]] = shl <16 x i8> [[TMP7]], [[TMP8]]2442// CHECK-NEXT: store volatile <16 x i8> [[SHL4]], ptr @uc, align 82443// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @uc, align 82444// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @uc2, align 82445// CHECK-NEXT: [[SHL5:%.*]] = shl <16 x i8> [[TMP9]], [[TMP10]]2446// CHECK-NEXT: store volatile <16 x i8> [[SHL5]], ptr @uc, align 82447// CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc, align 82448// CHECK-NEXT: [[TMP12:%.*]] = load volatile i32, ptr @cnt, align 42449// CHECK-NEXT: [[SPLAT_SPLATINSERT6:%.*]] = insertelement <16 x i32> poison, i32 [[TMP12]], i64 02450// CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT6]], <16 x i32> poison, <16 x i32> zeroinitializer2451// CHECK-NEXT: [[SH_PROM8:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT7]] to <16 x i8>2452// CHECK-NEXT: [[SHL9:%.*]] = shl <16 x i8> [[TMP11]], [[SH_PROM8]]2453// CHECK-NEXT: store volatile <16 x i8> [[SHL9]], ptr @uc, align 82454// CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @uc, align 82455// CHECK-NEXT: [[SHL10:%.*]] = shl <16 x i8> [[TMP13]], splat (i8 5)2456// CHECK-NEXT: store volatile <16 x i8> [[SHL10]], ptr @uc, align 82457// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 82458// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 82459// CHECK-NEXT: [[SHL11:%.*]] = shl <8 x i16> [[TMP14]], [[TMP15]]2460// CHECK-NEXT: store volatile <8 x i16> [[SHL11]], ptr @ss, align 82461// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 82462// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @us2, align 82463// CHECK-NEXT: [[SHL12:%.*]] = shl <8 x i16> [[TMP16]], [[TMP17]]2464// CHECK-NEXT: store volatile <8 x i16> [[SHL12]], ptr @ss, align 82465// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @ss, align 82466// CHECK-NEXT: [[TMP19:%.*]] = load volatile i32, ptr @cnt, align 42467// CHECK-NEXT: [[SPLAT_SPLATINSERT13:%.*]] = insertelement <8 x i32> poison, i32 [[TMP19]], i64 02468// CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT13]], <8 x i32> poison, <8 x i32> zeroinitializer2469// CHECK-NEXT: [[SH_PROM15:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT14]] to <8 x i16>2470// CHECK-NEXT: [[SHL16:%.*]] = shl <8 x i16> [[TMP18]], [[SH_PROM15]]2471// CHECK-NEXT: store volatile <8 x i16> [[SHL16]], ptr @ss, align 82472// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @ss, align 82473// CHECK-NEXT: [[SHL17:%.*]] = shl <8 x i16> [[TMP20]], splat (i16 5)2474// CHECK-NEXT: store volatile <8 x i16> [[SHL17]], ptr @ss, align 82475// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us, align 82476// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @ss2, align 82477// CHECK-NEXT: [[SHL18:%.*]] = shl <8 x i16> [[TMP21]], [[TMP22]]2478// CHECK-NEXT: store volatile <8 x i16> [[SHL18]], ptr @us, align 82479// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us, align 82480// CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @us2, align 82481// CHECK-NEXT: [[SHL19:%.*]] = shl <8 x i16> [[TMP23]], [[TMP24]]2482// CHECK-NEXT: store volatile <8 x i16> [[SHL19]], ptr @us, align 82483// CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us, align 82484// CHECK-NEXT: [[TMP26:%.*]] = load volatile i32, ptr @cnt, align 42485// CHECK-NEXT: [[SPLAT_SPLATINSERT20:%.*]] = insertelement <8 x i32> poison, i32 [[TMP26]], i64 02486// CHECK-NEXT: [[SPLAT_SPLAT21:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT20]], <8 x i32> poison, <8 x i32> zeroinitializer2487// CHECK-NEXT: [[SH_PROM22:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT21]] to <8 x i16>2488// CHECK-NEXT: [[SHL23:%.*]] = shl <8 x i16> [[TMP25]], [[SH_PROM22]]2489// CHECK-NEXT: store volatile <8 x i16> [[SHL23]], ptr @us, align 82490// CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @us, align 82491// CHECK-NEXT: [[SHL24:%.*]] = shl <8 x i16> [[TMP27]], splat (i16 5)2492// CHECK-NEXT: store volatile <8 x i16> [[SHL24]], ptr @us, align 82493// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 82494// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 82495// CHECK-NEXT: [[SHL25:%.*]] = shl <4 x i32> [[TMP28]], [[TMP29]]2496// CHECK-NEXT: store volatile <4 x i32> [[SHL25]], ptr @si, align 82497// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 82498// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @ui2, align 82499// CHECK-NEXT: [[SHL26:%.*]] = shl <4 x i32> [[TMP30]], [[TMP31]]2500// CHECK-NEXT: store volatile <4 x i32> [[SHL26]], ptr @si, align 82501// CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @si, align 82502// CHECK-NEXT: [[TMP33:%.*]] = load volatile i32, ptr @cnt, align 42503// CHECK-NEXT: [[SPLAT_SPLATINSERT27:%.*]] = insertelement <4 x i32> poison, i32 [[TMP33]], i64 02504// CHECK-NEXT: [[SPLAT_SPLAT28:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT27]], <4 x i32> poison, <4 x i32> zeroinitializer2505// CHECK-NEXT: [[SHL29:%.*]] = shl <4 x i32> [[TMP32]], [[SPLAT_SPLAT28]]2506// CHECK-NEXT: store volatile <4 x i32> [[SHL29]], ptr @si, align 82507// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @si, align 82508// CHECK-NEXT: [[SHL30:%.*]] = shl <4 x i32> [[TMP34]], splat (i32 5)2509// CHECK-NEXT: store volatile <4 x i32> [[SHL30]], ptr @si, align 82510// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui, align 82511// CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @si2, align 82512// CHECK-NEXT: [[SHL31:%.*]] = shl <4 x i32> [[TMP35]], [[TMP36]]2513// CHECK-NEXT: store volatile <4 x i32> [[SHL31]], ptr @ui, align 82514// CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @ui, align 82515// CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @ui2, align 82516// CHECK-NEXT: [[SHL32:%.*]] = shl <4 x i32> [[TMP37]], [[TMP38]]2517// CHECK-NEXT: store volatile <4 x i32> [[SHL32]], ptr @ui, align 82518// CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui, align 82519// CHECK-NEXT: [[TMP40:%.*]] = load volatile i32, ptr @cnt, align 42520// CHECK-NEXT: [[SPLAT_SPLATINSERT33:%.*]] = insertelement <4 x i32> poison, i32 [[TMP40]], i64 02521// CHECK-NEXT: [[SPLAT_SPLAT34:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT33]], <4 x i32> poison, <4 x i32> zeroinitializer2522// CHECK-NEXT: [[SHL35:%.*]] = shl <4 x i32> [[TMP39]], [[SPLAT_SPLAT34]]2523// CHECK-NEXT: store volatile <4 x i32> [[SHL35]], ptr @ui, align 82524// CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @ui, align 82525// CHECK-NEXT: [[SHL36:%.*]] = shl <4 x i32> [[TMP41]], splat (i32 5)2526// CHECK-NEXT: store volatile <4 x i32> [[SHL36]], ptr @ui, align 82527// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 82528// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 82529// CHECK-NEXT: [[SHL37:%.*]] = shl <2 x i64> [[TMP42]], [[TMP43]]2530// CHECK-NEXT: store volatile <2 x i64> [[SHL37]], ptr @sl, align 82531// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 82532// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @ul2, align 82533// CHECK-NEXT: [[SHL38:%.*]] = shl <2 x i64> [[TMP44]], [[TMP45]]2534// CHECK-NEXT: store volatile <2 x i64> [[SHL38]], ptr @sl, align 82535// CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @sl, align 82536// CHECK-NEXT: [[TMP47:%.*]] = load volatile i32, ptr @cnt, align 42537// CHECK-NEXT: [[SPLAT_SPLATINSERT39:%.*]] = insertelement <2 x i32> poison, i32 [[TMP47]], i64 02538// CHECK-NEXT: [[SPLAT_SPLAT40:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT39]], <2 x i32> poison, <2 x i32> zeroinitializer2539// CHECK-NEXT: [[SH_PROM41:%.*]] = zext <2 x i32> [[SPLAT_SPLAT40]] to <2 x i64>2540// CHECK-NEXT: [[SHL42:%.*]] = shl <2 x i64> [[TMP46]], [[SH_PROM41]]2541// CHECK-NEXT: store volatile <2 x i64> [[SHL42]], ptr @sl, align 82542// CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 82543// CHECK-NEXT: [[SHL43:%.*]] = shl <2 x i64> [[TMP48]], splat (i64 5)2544// CHECK-NEXT: store volatile <2 x i64> [[SHL43]], ptr @sl, align 82545// CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul, align 82546// CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @sl2, align 82547// CHECK-NEXT: [[SHL44:%.*]] = shl <2 x i64> [[TMP49]], [[TMP50]]2548// CHECK-NEXT: store volatile <2 x i64> [[SHL44]], ptr @ul, align 82549// CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @ul, align 82550// CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @ul2, align 82551// CHECK-NEXT: [[SHL45:%.*]] = shl <2 x i64> [[TMP51]], [[TMP52]]2552// CHECK-NEXT: store volatile <2 x i64> [[SHL45]], ptr @ul, align 82553// CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul, align 82554// CHECK-NEXT: [[TMP54:%.*]] = load volatile i32, ptr @cnt, align 42555// CHECK-NEXT: [[SPLAT_SPLATINSERT46:%.*]] = insertelement <2 x i32> poison, i32 [[TMP54]], i64 02556// CHECK-NEXT: [[SPLAT_SPLAT47:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT46]], <2 x i32> poison, <2 x i32> zeroinitializer2557// CHECK-NEXT: [[SH_PROM48:%.*]] = zext <2 x i32> [[SPLAT_SPLAT47]] to <2 x i64>2558// CHECK-NEXT: [[SHL49:%.*]] = shl <2 x i64> [[TMP53]], [[SH_PROM48]]2559// CHECK-NEXT: store volatile <2 x i64> [[SHL49]], ptr @ul, align 82560// CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @ul, align 82561// CHECK-NEXT: [[SHL50:%.*]] = shl <2 x i64> [[TMP55]], splat (i64 5)2562// CHECK-NEXT: store volatile <2 x i64> [[SHL50]], ptr @ul, align 82563// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @slll, align 82564// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @slll2, align 82565// CHECK-NEXT: [[SHL51:%.*]] = shl <1 x i128> [[TMP56]], [[TMP57]]2566// CHECK-NEXT: store volatile <1 x i128> [[SHL51]], ptr @slll, align 82567// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @slll, align 82568// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 82569// CHECK-NEXT: [[SHL52:%.*]] = shl <1 x i128> [[TMP58]], [[TMP59]]2570// CHECK-NEXT: store volatile <1 x i128> [[SHL52]], ptr @slll, align 82571// CHECK-NEXT: [[TMP60:%.*]] = load volatile <1 x i128>, ptr @slll, align 82572// CHECK-NEXT: [[TMP61:%.*]] = load volatile i32, ptr @cnt, align 42573// CHECK-NEXT: [[SPLAT_SPLATINSERT53:%.*]] = insertelement <1 x i32> poison, i32 [[TMP61]], i64 02574// CHECK-NEXT: [[SPLAT_SPLAT54:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT53]], <1 x i32> poison, <1 x i32> zeroinitializer2575// CHECK-NEXT: [[SH_PROM55:%.*]] = zext <1 x i32> [[SPLAT_SPLAT54]] to <1 x i128>2576// CHECK-NEXT: [[SHL56:%.*]] = shl <1 x i128> [[TMP60]], [[SH_PROM55]]2577// CHECK-NEXT: store volatile <1 x i128> [[SHL56]], ptr @slll, align 82578// CHECK-NEXT: [[TMP62:%.*]] = load volatile <1 x i128>, ptr @slll, align 82579// CHECK-NEXT: [[SHL57:%.*]] = shl <1 x i128> [[TMP62]], splat (i128 5)2580// CHECK-NEXT: store volatile <1 x i128> [[SHL57]], ptr @slll, align 82581// CHECK-NEXT: [[TMP63:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82582// CHECK-NEXT: [[TMP64:%.*]] = load volatile <1 x i128>, ptr @slll2, align 82583// CHECK-NEXT: [[SHL58:%.*]] = shl <1 x i128> [[TMP63]], [[TMP64]]2584// CHECK-NEXT: store volatile <1 x i128> [[SHL58]], ptr @ulll, align 82585// CHECK-NEXT: [[TMP65:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82586// CHECK-NEXT: [[TMP66:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 82587// CHECK-NEXT: [[SHL59:%.*]] = shl <1 x i128> [[TMP65]], [[TMP66]]2588// CHECK-NEXT: store volatile <1 x i128> [[SHL59]], ptr @ulll, align 82589// CHECK-NEXT: [[TMP67:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82590// CHECK-NEXT: [[TMP68:%.*]] = load volatile i32, ptr @cnt, align 42591// CHECK-NEXT: [[SPLAT_SPLATINSERT60:%.*]] = insertelement <1 x i32> poison, i32 [[TMP68]], i64 02592// CHECK-NEXT: [[SPLAT_SPLAT61:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT60]], <1 x i32> poison, <1 x i32> zeroinitializer2593// CHECK-NEXT: [[SH_PROM62:%.*]] = zext <1 x i32> [[SPLAT_SPLAT61]] to <1 x i128>2594// CHECK-NEXT: [[SHL63:%.*]] = shl <1 x i128> [[TMP67]], [[SH_PROM62]]2595// CHECK-NEXT: store volatile <1 x i128> [[SHL63]], ptr @ulll, align 82596// CHECK-NEXT: [[TMP69:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82597// CHECK-NEXT: [[SHL64:%.*]] = shl <1 x i128> [[TMP69]], splat (i128 5)2598// CHECK-NEXT: store volatile <1 x i128> [[SHL64]], ptr @ulll, align 82599// CHECK-NEXT: ret void2600//2601void test_sl(void) {2602 2603 sc = sc << sc2;2604 sc = sc << uc2;2605 sc = sc << cnt;2606 sc = sc << 5;2607 uc = uc << sc2;2608 uc = uc << uc2;2609 uc = uc << cnt;2610 uc = uc << 5;2611 2612 ss = ss << ss2;2613 ss = ss << us2;2614 ss = ss << cnt;2615 ss = ss << 5;2616 us = us << ss2;2617 us = us << us2;2618 us = us << cnt;2619 us = us << 5;2620 2621 si = si << si2;2622 si = si << ui2;2623 si = si << cnt;2624 si = si << 5;2625 ui = ui << si2;2626 ui = ui << ui2;2627 ui = ui << cnt;2628 ui = ui << 5;2629 2630 sl = sl << sl2;2631 sl = sl << ul2;2632 sl = sl << cnt;2633 sl = sl << 5;2634 ul = ul << sl2;2635 ul = ul << ul2;2636 ul = ul << cnt;2637 ul = ul << 5;2638 2639 slll = slll << slll2;2640 slll = slll << ulll2;2641 slll = slll << cnt;2642 slll = slll << 5;2643 ulll = ulll << slll2;2644 ulll = ulll << ulll2;2645 ulll = ulll << cnt;2646 ulll = ulll << 5;2647}2648 2649// CHECK-LABEL: define dso_local void @test_sl_assign(2650// CHECK-SAME: ) #[[ATTR0]] {2651// CHECK-NEXT: [[ENTRY:.*:]]2652// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 82653// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 82654// CHECK-NEXT: [[SHL:%.*]] = shl <16 x i8> [[TMP1]], [[TMP0]]2655// CHECK-NEXT: store volatile <16 x i8> [[SHL]], ptr @sc, align 82656// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc2, align 82657// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 82658// CHECK-NEXT: [[SHL1:%.*]] = shl <16 x i8> [[TMP3]], [[TMP2]]2659// CHECK-NEXT: store volatile <16 x i8> [[SHL1]], ptr @sc, align 82660// CHECK-NEXT: [[TMP4:%.*]] = load volatile i32, ptr @cnt, align 42661// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[TMP4]], i64 02662// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer2663// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc, align 82664// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT]] to <16 x i8>2665// CHECK-NEXT: [[SHL2:%.*]] = shl <16 x i8> [[TMP5]], [[SH_PROM]]2666// CHECK-NEXT: store volatile <16 x i8> [[SHL2]], ptr @sc, align 82667// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @sc, align 82668// CHECK-NEXT: [[SHL3:%.*]] = shl <16 x i8> [[TMP6]], splat (i8 5)2669// CHECK-NEXT: store volatile <16 x i8> [[SHL3]], ptr @sc, align 82670// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @sc2, align 82671// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 82672// CHECK-NEXT: [[SHL4:%.*]] = shl <16 x i8> [[TMP8]], [[TMP7]]2673// CHECK-NEXT: store volatile <16 x i8> [[SHL4]], ptr @uc, align 82674// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @uc2, align 82675// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @uc, align 82676// CHECK-NEXT: [[SHL5:%.*]] = shl <16 x i8> [[TMP10]], [[TMP9]]2677// CHECK-NEXT: store volatile <16 x i8> [[SHL5]], ptr @uc, align 82678// CHECK-NEXT: [[TMP11:%.*]] = load volatile i32, ptr @cnt, align 42679// CHECK-NEXT: [[SPLAT_SPLATINSERT6:%.*]] = insertelement <16 x i32> poison, i32 [[TMP11]], i64 02680// CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT6]], <16 x i32> poison, <16 x i32> zeroinitializer2681// CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @uc, align 82682// CHECK-NEXT: [[SH_PROM8:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT7]] to <16 x i8>2683// CHECK-NEXT: [[SHL9:%.*]] = shl <16 x i8> [[TMP12]], [[SH_PROM8]]2684// CHECK-NEXT: store volatile <16 x i8> [[SHL9]], ptr @uc, align 82685// CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @uc, align 82686// CHECK-NEXT: [[SHL10:%.*]] = shl <16 x i8> [[TMP13]], splat (i8 5)2687// CHECK-NEXT: store volatile <16 x i8> [[SHL10]], ptr @uc, align 82688// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss2, align 82689// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss, align 82690// CHECK-NEXT: [[SHL11:%.*]] = shl <8 x i16> [[TMP15]], [[TMP14]]2691// CHECK-NEXT: store volatile <8 x i16> [[SHL11]], ptr @ss, align 82692// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @us2, align 82693// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @ss, align 82694// CHECK-NEXT: [[SHL12:%.*]] = shl <8 x i16> [[TMP17]], [[TMP16]]2695// CHECK-NEXT: store volatile <8 x i16> [[SHL12]], ptr @ss, align 82696// CHECK-NEXT: [[TMP18:%.*]] = load volatile i32, ptr @cnt, align 42697// CHECK-NEXT: [[SPLAT_SPLATINSERT13:%.*]] = insertelement <8 x i32> poison, i32 [[TMP18]], i64 02698// CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT13]], <8 x i32> poison, <8 x i32> zeroinitializer2699// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss, align 82700// CHECK-NEXT: [[SH_PROM15:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT14]] to <8 x i16>2701// CHECK-NEXT: [[SHL16:%.*]] = shl <8 x i16> [[TMP19]], [[SH_PROM15]]2702// CHECK-NEXT: store volatile <8 x i16> [[SHL16]], ptr @ss, align 82703// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @ss, align 82704// CHECK-NEXT: [[SHL17:%.*]] = shl <8 x i16> [[TMP20]], splat (i16 5)2705// CHECK-NEXT: store volatile <8 x i16> [[SHL17]], ptr @ss, align 82706// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @ss2, align 82707// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 82708// CHECK-NEXT: [[SHL18:%.*]] = shl <8 x i16> [[TMP22]], [[TMP21]]2709// CHECK-NEXT: store volatile <8 x i16> [[SHL18]], ptr @us, align 82710// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us2, align 82711// CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @us, align 82712// CHECK-NEXT: [[SHL19:%.*]] = shl <8 x i16> [[TMP24]], [[TMP23]]2713// CHECK-NEXT: store volatile <8 x i16> [[SHL19]], ptr @us, align 82714// CHECK-NEXT: [[TMP25:%.*]] = load volatile i32, ptr @cnt, align 42715// CHECK-NEXT: [[SPLAT_SPLATINSERT20:%.*]] = insertelement <8 x i32> poison, i32 [[TMP25]], i64 02716// CHECK-NEXT: [[SPLAT_SPLAT21:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT20]], <8 x i32> poison, <8 x i32> zeroinitializer2717// CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @us, align 82718// CHECK-NEXT: [[SH_PROM22:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT21]] to <8 x i16>2719// CHECK-NEXT: [[SHL23:%.*]] = shl <8 x i16> [[TMP26]], [[SH_PROM22]]2720// CHECK-NEXT: store volatile <8 x i16> [[SHL23]], ptr @us, align 82721// CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @us, align 82722// CHECK-NEXT: [[SHL24:%.*]] = shl <8 x i16> [[TMP27]], splat (i16 5)2723// CHECK-NEXT: store volatile <8 x i16> [[SHL24]], ptr @us, align 82724// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si2, align 82725// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si, align 82726// CHECK-NEXT: [[SHL25:%.*]] = shl <4 x i32> [[TMP29]], [[TMP28]]2727// CHECK-NEXT: store volatile <4 x i32> [[SHL25]], ptr @si, align 82728// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @ui2, align 82729// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @si, align 82730// CHECK-NEXT: [[SHL26:%.*]] = shl <4 x i32> [[TMP31]], [[TMP30]]2731// CHECK-NEXT: store volatile <4 x i32> [[SHL26]], ptr @si, align 82732// CHECK-NEXT: [[TMP32:%.*]] = load volatile i32, ptr @cnt, align 42733// CHECK-NEXT: [[SPLAT_SPLATINSERT27:%.*]] = insertelement <4 x i32> poison, i32 [[TMP32]], i64 02734// CHECK-NEXT: [[SPLAT_SPLAT28:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT27]], <4 x i32> poison, <4 x i32> zeroinitializer2735// CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si, align 82736// CHECK-NEXT: [[SHL29:%.*]] = shl <4 x i32> [[TMP33]], [[SPLAT_SPLAT28]]2737// CHECK-NEXT: store volatile <4 x i32> [[SHL29]], ptr @si, align 82738// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @si, align 82739// CHECK-NEXT: [[SHL30:%.*]] = shl <4 x i32> [[TMP34]], splat (i32 5)2740// CHECK-NEXT: store volatile <4 x i32> [[SHL30]], ptr @si, align 82741// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @si2, align 82742// CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 82743// CHECK-NEXT: [[SHL31:%.*]] = shl <4 x i32> [[TMP36]], [[TMP35]]2744// CHECK-NEXT: store volatile <4 x i32> [[SHL31]], ptr @ui, align 82745// CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @ui2, align 82746// CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @ui, align 82747// CHECK-NEXT: [[SHL32:%.*]] = shl <4 x i32> [[TMP38]], [[TMP37]]2748// CHECK-NEXT: store volatile <4 x i32> [[SHL32]], ptr @ui, align 82749// CHECK-NEXT: [[TMP39:%.*]] = load volatile i32, ptr @cnt, align 42750// CHECK-NEXT: [[SPLAT_SPLATINSERT33:%.*]] = insertelement <4 x i32> poison, i32 [[TMP39]], i64 02751// CHECK-NEXT: [[SPLAT_SPLAT34:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT33]], <4 x i32> poison, <4 x i32> zeroinitializer2752// CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @ui, align 82753// CHECK-NEXT: [[SHL35:%.*]] = shl <4 x i32> [[TMP40]], [[SPLAT_SPLAT34]]2754// CHECK-NEXT: store volatile <4 x i32> [[SHL35]], ptr @ui, align 82755// CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @ui, align 82756// CHECK-NEXT: [[SHL36:%.*]] = shl <4 x i32> [[TMP41]], splat (i32 5)2757// CHECK-NEXT: store volatile <4 x i32> [[SHL36]], ptr @ui, align 82758// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl2, align 82759// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl, align 82760// CHECK-NEXT: [[SHL37:%.*]] = shl <2 x i64> [[TMP43]], [[TMP42]]2761// CHECK-NEXT: store volatile <2 x i64> [[SHL37]], ptr @sl, align 82762// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @ul2, align 82763// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @sl, align 82764// CHECK-NEXT: [[SHL38:%.*]] = shl <2 x i64> [[TMP45]], [[TMP44]]2765// CHECK-NEXT: store volatile <2 x i64> [[SHL38]], ptr @sl, align 82766// CHECK-NEXT: [[TMP46:%.*]] = load volatile i32, ptr @cnt, align 42767// CHECK-NEXT: [[SPLAT_SPLATINSERT39:%.*]] = insertelement <2 x i32> poison, i32 [[TMP46]], i64 02768// CHECK-NEXT: [[SPLAT_SPLAT40:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT39]], <2 x i32> poison, <2 x i32> zeroinitializer2769// CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl, align 82770// CHECK-NEXT: [[SH_PROM41:%.*]] = zext <2 x i32> [[SPLAT_SPLAT40]] to <2 x i64>2771// CHECK-NEXT: [[SHL42:%.*]] = shl <2 x i64> [[TMP47]], [[SH_PROM41]]2772// CHECK-NEXT: store volatile <2 x i64> [[SHL42]], ptr @sl, align 82773// CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 82774// CHECK-NEXT: [[SHL43:%.*]] = shl <2 x i64> [[TMP48]], splat (i64 5)2775// CHECK-NEXT: store volatile <2 x i64> [[SHL43]], ptr @sl, align 82776// CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @sl2, align 82777// CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 82778// CHECK-NEXT: [[SHL44:%.*]] = shl <2 x i64> [[TMP50]], [[TMP49]]2779// CHECK-NEXT: store volatile <2 x i64> [[SHL44]], ptr @ul, align 82780// CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @ul2, align 82781// CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @ul, align 82782// CHECK-NEXT: [[SHL45:%.*]] = shl <2 x i64> [[TMP52]], [[TMP51]]2783// CHECK-NEXT: store volatile <2 x i64> [[SHL45]], ptr @ul, align 82784// CHECK-NEXT: [[TMP53:%.*]] = load volatile i32, ptr @cnt, align 42785// CHECK-NEXT: [[SPLAT_SPLATINSERT46:%.*]] = insertelement <2 x i32> poison, i32 [[TMP53]], i64 02786// CHECK-NEXT: [[SPLAT_SPLAT47:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT46]], <2 x i32> poison, <2 x i32> zeroinitializer2787// CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @ul, align 82788// CHECK-NEXT: [[SH_PROM48:%.*]] = zext <2 x i32> [[SPLAT_SPLAT47]] to <2 x i64>2789// CHECK-NEXT: [[SHL49:%.*]] = shl <2 x i64> [[TMP54]], [[SH_PROM48]]2790// CHECK-NEXT: store volatile <2 x i64> [[SHL49]], ptr @ul, align 82791// CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @ul, align 82792// CHECK-NEXT: [[SHL50:%.*]] = shl <2 x i64> [[TMP55]], splat (i64 5)2793// CHECK-NEXT: store volatile <2 x i64> [[SHL50]], ptr @ul, align 82794// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @slll2, align 82795// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @slll, align 82796// CHECK-NEXT: [[SHL51:%.*]] = shl <1 x i128> [[TMP57]], [[TMP56]]2797// CHECK-NEXT: store volatile <1 x i128> [[SHL51]], ptr @slll, align 82798// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 82799// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @slll, align 82800// CHECK-NEXT: [[SHL52:%.*]] = shl <1 x i128> [[TMP59]], [[TMP58]]2801// CHECK-NEXT: store volatile <1 x i128> [[SHL52]], ptr @slll, align 82802// CHECK-NEXT: [[TMP60:%.*]] = load volatile i32, ptr @cnt, align 42803// CHECK-NEXT: [[SPLAT_SPLATINSERT53:%.*]] = insertelement <1 x i32> poison, i32 [[TMP60]], i64 02804// CHECK-NEXT: [[SPLAT_SPLAT54:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT53]], <1 x i32> poison, <1 x i32> zeroinitializer2805// CHECK-NEXT: [[TMP61:%.*]] = load volatile <1 x i128>, ptr @slll, align 82806// CHECK-NEXT: [[SH_PROM55:%.*]] = zext <1 x i32> [[SPLAT_SPLAT54]] to <1 x i128>2807// CHECK-NEXT: [[SHL56:%.*]] = shl <1 x i128> [[TMP61]], [[SH_PROM55]]2808// CHECK-NEXT: store volatile <1 x i128> [[SHL56]], ptr @slll, align 82809// CHECK-NEXT: [[TMP62:%.*]] = load volatile <1 x i128>, ptr @slll, align 82810// CHECK-NEXT: [[SHL57:%.*]] = shl <1 x i128> [[TMP62]], splat (i128 5)2811// CHECK-NEXT: store volatile <1 x i128> [[SHL57]], ptr @slll, align 82812// CHECK-NEXT: [[TMP63:%.*]] = load volatile <1 x i128>, ptr @slll2, align 82813// CHECK-NEXT: [[TMP64:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82814// CHECK-NEXT: [[SHL58:%.*]] = shl <1 x i128> [[TMP64]], [[TMP63]]2815// CHECK-NEXT: store volatile <1 x i128> [[SHL58]], ptr @ulll, align 82816// CHECK-NEXT: [[TMP65:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 82817// CHECK-NEXT: [[TMP66:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82818// CHECK-NEXT: [[SHL59:%.*]] = shl <1 x i128> [[TMP66]], [[TMP65]]2819// CHECK-NEXT: store volatile <1 x i128> [[SHL59]], ptr @ulll, align 82820// CHECK-NEXT: [[TMP67:%.*]] = load volatile i32, ptr @cnt, align 42821// CHECK-NEXT: [[SPLAT_SPLATINSERT60:%.*]] = insertelement <1 x i32> poison, i32 [[TMP67]], i64 02822// CHECK-NEXT: [[SPLAT_SPLAT61:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT60]], <1 x i32> poison, <1 x i32> zeroinitializer2823// CHECK-NEXT: [[TMP68:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82824// CHECK-NEXT: [[SH_PROM62:%.*]] = zext <1 x i32> [[SPLAT_SPLAT61]] to <1 x i128>2825// CHECK-NEXT: [[SHL63:%.*]] = shl <1 x i128> [[TMP68]], [[SH_PROM62]]2826// CHECK-NEXT: store volatile <1 x i128> [[SHL63]], ptr @ulll, align 82827// CHECK-NEXT: [[TMP69:%.*]] = load volatile <1 x i128>, ptr @ulll, align 82828// CHECK-NEXT: [[SHL64:%.*]] = shl <1 x i128> [[TMP69]], splat (i128 5)2829// CHECK-NEXT: store volatile <1 x i128> [[SHL64]], ptr @ulll, align 82830// CHECK-NEXT: ret void2831//2832void test_sl_assign(void) {2833 2834 sc <<= sc2;2835 sc <<= uc2;2836 sc <<= cnt;2837 sc <<= 5;2838 uc <<= sc2;2839 uc <<= uc2;2840 uc <<= cnt;2841 uc <<= 5;2842 2843 ss <<= ss2;2844 ss <<= us2;2845 ss <<= cnt;2846 ss <<= 5;2847 us <<= ss2;2848 us <<= us2;2849 us <<= cnt;2850 us <<= 5;2851 2852 si <<= si2;2853 si <<= ui2;2854 si <<= cnt;2855 si <<= 5;2856 ui <<= si2;2857 ui <<= ui2;2858 ui <<= cnt;2859 ui <<= 5;2860 2861 sl <<= sl2;2862 sl <<= ul2;2863 sl <<= cnt;2864 sl <<= 5;2865 ul <<= sl2;2866 ul <<= ul2;2867 ul <<= cnt;2868 ul <<= 5;2869 2870 slll <<= slll2;2871 slll <<= ulll2;2872 slll <<= cnt;2873 slll <<= 5;2874 ulll <<= slll2;2875 ulll <<= ulll2;2876 ulll <<= cnt;2877 ulll <<= 5;2878}2879 2880// CHECK-LABEL: define dso_local void @test_sr(2881// CHECK-SAME: ) #[[ATTR0]] {2882// CHECK-NEXT: [[ENTRY:.*:]]2883// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 82884// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 82885// CHECK-NEXT: [[SHR:%.*]] = ashr <16 x i8> [[TMP0]], [[TMP1]]2886// CHECK-NEXT: store volatile <16 x i8> [[SHR]], ptr @sc, align 82887// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 82888// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 82889// CHECK-NEXT: [[SHR1:%.*]] = ashr <16 x i8> [[TMP2]], [[TMP3]]2890// CHECK-NEXT: store volatile <16 x i8> [[SHR1]], ptr @sc, align 82891// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @sc, align 82892// CHECK-NEXT: [[TMP5:%.*]] = load volatile i32, ptr @cnt, align 42893// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[TMP5]], i64 02894// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer2895// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT]] to <16 x i8>2896// CHECK-NEXT: [[SHR2:%.*]] = ashr <16 x i8> [[TMP4]], [[SH_PROM]]2897// CHECK-NEXT: store volatile <16 x i8> [[SHR2]], ptr @sc, align 82898// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @sc, align 82899// CHECK-NEXT: [[SHR3:%.*]] = ashr <16 x i8> [[TMP6]], splat (i8 5)2900// CHECK-NEXT: store volatile <16 x i8> [[SHR3]], ptr @sc, align 82901// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 82902// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @sc2, align 82903// CHECK-NEXT: [[SHR4:%.*]] = lshr <16 x i8> [[TMP7]], [[TMP8]]2904// CHECK-NEXT: store volatile <16 x i8> [[SHR4]], ptr @uc, align 82905// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @uc, align 82906// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @uc2, align 82907// CHECK-NEXT: [[SHR5:%.*]] = lshr <16 x i8> [[TMP9]], [[TMP10]]2908// CHECK-NEXT: store volatile <16 x i8> [[SHR5]], ptr @uc, align 82909// CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc, align 82910// CHECK-NEXT: [[TMP12:%.*]] = load volatile i32, ptr @cnt, align 42911// CHECK-NEXT: [[SPLAT_SPLATINSERT6:%.*]] = insertelement <16 x i32> poison, i32 [[TMP12]], i64 02912// CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT6]], <16 x i32> poison, <16 x i32> zeroinitializer2913// CHECK-NEXT: [[SH_PROM8:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT7]] to <16 x i8>2914// CHECK-NEXT: [[SHR9:%.*]] = lshr <16 x i8> [[TMP11]], [[SH_PROM8]]2915// CHECK-NEXT: store volatile <16 x i8> [[SHR9]], ptr @uc, align 82916// CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @uc, align 82917// CHECK-NEXT: [[SHR10:%.*]] = lshr <16 x i8> [[TMP13]], splat (i8 5)2918// CHECK-NEXT: store volatile <16 x i8> [[SHR10]], ptr @uc, align 82919// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 82920// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 82921// CHECK-NEXT: [[SHR11:%.*]] = ashr <8 x i16> [[TMP14]], [[TMP15]]2922// CHECK-NEXT: store volatile <8 x i16> [[SHR11]], ptr @ss, align 82923// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 82924// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @us2, align 82925// CHECK-NEXT: [[SHR12:%.*]] = ashr <8 x i16> [[TMP16]], [[TMP17]]2926// CHECK-NEXT: store volatile <8 x i16> [[SHR12]], ptr @ss, align 82927// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @ss, align 82928// CHECK-NEXT: [[TMP19:%.*]] = load volatile i32, ptr @cnt, align 42929// CHECK-NEXT: [[SPLAT_SPLATINSERT13:%.*]] = insertelement <8 x i32> poison, i32 [[TMP19]], i64 02930// CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT13]], <8 x i32> poison, <8 x i32> zeroinitializer2931// CHECK-NEXT: [[SH_PROM15:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT14]] to <8 x i16>2932// CHECK-NEXT: [[SHR16:%.*]] = ashr <8 x i16> [[TMP18]], [[SH_PROM15]]2933// CHECK-NEXT: store volatile <8 x i16> [[SHR16]], ptr @ss, align 82934// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @ss, align 82935// CHECK-NEXT: [[SHR17:%.*]] = ashr <8 x i16> [[TMP20]], splat (i16 5)2936// CHECK-NEXT: store volatile <8 x i16> [[SHR17]], ptr @ss, align 82937// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us, align 82938// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @ss2, align 82939// CHECK-NEXT: [[SHR18:%.*]] = lshr <8 x i16> [[TMP21]], [[TMP22]]2940// CHECK-NEXT: store volatile <8 x i16> [[SHR18]], ptr @us, align 82941// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us, align 82942// CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @us2, align 82943// CHECK-NEXT: [[SHR19:%.*]] = lshr <8 x i16> [[TMP23]], [[TMP24]]2944// CHECK-NEXT: store volatile <8 x i16> [[SHR19]], ptr @us, align 82945// CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us, align 82946// CHECK-NEXT: [[TMP26:%.*]] = load volatile i32, ptr @cnt, align 42947// CHECK-NEXT: [[SPLAT_SPLATINSERT20:%.*]] = insertelement <8 x i32> poison, i32 [[TMP26]], i64 02948// CHECK-NEXT: [[SPLAT_SPLAT21:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT20]], <8 x i32> poison, <8 x i32> zeroinitializer2949// CHECK-NEXT: [[SH_PROM22:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT21]] to <8 x i16>2950// CHECK-NEXT: [[SHR23:%.*]] = lshr <8 x i16> [[TMP25]], [[SH_PROM22]]2951// CHECK-NEXT: store volatile <8 x i16> [[SHR23]], ptr @us, align 82952// CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @us, align 82953// CHECK-NEXT: [[SHR24:%.*]] = lshr <8 x i16> [[TMP27]], splat (i16 5)2954// CHECK-NEXT: store volatile <8 x i16> [[SHR24]], ptr @us, align 82955// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 82956// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 82957// CHECK-NEXT: [[SHR25:%.*]] = ashr <4 x i32> [[TMP28]], [[TMP29]]2958// CHECK-NEXT: store volatile <4 x i32> [[SHR25]], ptr @si, align 82959// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 82960// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @ui2, align 82961// CHECK-NEXT: [[SHR26:%.*]] = ashr <4 x i32> [[TMP30]], [[TMP31]]2962// CHECK-NEXT: store volatile <4 x i32> [[SHR26]], ptr @si, align 82963// CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @si, align 82964// CHECK-NEXT: [[TMP33:%.*]] = load volatile i32, ptr @cnt, align 42965// CHECK-NEXT: [[SPLAT_SPLATINSERT27:%.*]] = insertelement <4 x i32> poison, i32 [[TMP33]], i64 02966// CHECK-NEXT: [[SPLAT_SPLAT28:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT27]], <4 x i32> poison, <4 x i32> zeroinitializer2967// CHECK-NEXT: [[SHR29:%.*]] = ashr <4 x i32> [[TMP32]], [[SPLAT_SPLAT28]]2968// CHECK-NEXT: store volatile <4 x i32> [[SHR29]], ptr @si, align 82969// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @si, align 82970// CHECK-NEXT: [[SHR30:%.*]] = ashr <4 x i32> [[TMP34]], splat (i32 5)2971// CHECK-NEXT: store volatile <4 x i32> [[SHR30]], ptr @si, align 82972// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui, align 82973// CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @si2, align 82974// CHECK-NEXT: [[SHR31:%.*]] = lshr <4 x i32> [[TMP35]], [[TMP36]]2975// CHECK-NEXT: store volatile <4 x i32> [[SHR31]], ptr @ui, align 82976// CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @ui, align 82977// CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @ui2, align 82978// CHECK-NEXT: [[SHR32:%.*]] = lshr <4 x i32> [[TMP37]], [[TMP38]]2979// CHECK-NEXT: store volatile <4 x i32> [[SHR32]], ptr @ui, align 82980// CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui, align 82981// CHECK-NEXT: [[TMP40:%.*]] = load volatile i32, ptr @cnt, align 42982// CHECK-NEXT: [[SPLAT_SPLATINSERT33:%.*]] = insertelement <4 x i32> poison, i32 [[TMP40]], i64 02983// CHECK-NEXT: [[SPLAT_SPLAT34:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT33]], <4 x i32> poison, <4 x i32> zeroinitializer2984// CHECK-NEXT: [[SHR35:%.*]] = lshr <4 x i32> [[TMP39]], [[SPLAT_SPLAT34]]2985// CHECK-NEXT: store volatile <4 x i32> [[SHR35]], ptr @ui, align 82986// CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @ui, align 82987// CHECK-NEXT: [[SHR36:%.*]] = lshr <4 x i32> [[TMP41]], splat (i32 5)2988// CHECK-NEXT: store volatile <4 x i32> [[SHR36]], ptr @ui, align 82989// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 82990// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 82991// CHECK-NEXT: [[SHR37:%.*]] = ashr <2 x i64> [[TMP42]], [[TMP43]]2992// CHECK-NEXT: store volatile <2 x i64> [[SHR37]], ptr @sl, align 82993// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 82994// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @ul2, align 82995// CHECK-NEXT: [[SHR38:%.*]] = ashr <2 x i64> [[TMP44]], [[TMP45]]2996// CHECK-NEXT: store volatile <2 x i64> [[SHR38]], ptr @sl, align 82997// CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @sl, align 82998// CHECK-NEXT: [[TMP47:%.*]] = load volatile i32, ptr @cnt, align 42999// CHECK-NEXT: [[SPLAT_SPLATINSERT39:%.*]] = insertelement <2 x i32> poison, i32 [[TMP47]], i64 03000// CHECK-NEXT: [[SPLAT_SPLAT40:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT39]], <2 x i32> poison, <2 x i32> zeroinitializer3001// CHECK-NEXT: [[SH_PROM41:%.*]] = zext <2 x i32> [[SPLAT_SPLAT40]] to <2 x i64>3002// CHECK-NEXT: [[SHR42:%.*]] = ashr <2 x i64> [[TMP46]], [[SH_PROM41]]3003// CHECK-NEXT: store volatile <2 x i64> [[SHR42]], ptr @sl, align 83004// CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 83005// CHECK-NEXT: [[SHR43:%.*]] = ashr <2 x i64> [[TMP48]], splat (i64 5)3006// CHECK-NEXT: store volatile <2 x i64> [[SHR43]], ptr @sl, align 83007// CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul, align 83008// CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @sl2, align 83009// CHECK-NEXT: [[SHR44:%.*]] = lshr <2 x i64> [[TMP49]], [[TMP50]]3010// CHECK-NEXT: store volatile <2 x i64> [[SHR44]], ptr @ul, align 83011// CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @ul, align 83012// CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @ul2, align 83013// CHECK-NEXT: [[SHR45:%.*]] = lshr <2 x i64> [[TMP51]], [[TMP52]]3014// CHECK-NEXT: store volatile <2 x i64> [[SHR45]], ptr @ul, align 83015// CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul, align 83016// CHECK-NEXT: [[TMP54:%.*]] = load volatile i32, ptr @cnt, align 43017// CHECK-NEXT: [[SPLAT_SPLATINSERT46:%.*]] = insertelement <2 x i32> poison, i32 [[TMP54]], i64 03018// CHECK-NEXT: [[SPLAT_SPLAT47:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT46]], <2 x i32> poison, <2 x i32> zeroinitializer3019// CHECK-NEXT: [[SH_PROM48:%.*]] = zext <2 x i32> [[SPLAT_SPLAT47]] to <2 x i64>3020// CHECK-NEXT: [[SHR49:%.*]] = lshr <2 x i64> [[TMP53]], [[SH_PROM48]]3021// CHECK-NEXT: store volatile <2 x i64> [[SHR49]], ptr @ul, align 83022// CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @ul, align 83023// CHECK-NEXT: [[SHR50:%.*]] = lshr <2 x i64> [[TMP55]], splat (i64 5)3024// CHECK-NEXT: store volatile <2 x i64> [[SHR50]], ptr @ul, align 83025// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @slll, align 83026// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @slll2, align 83027// CHECK-NEXT: [[SHR51:%.*]] = ashr <1 x i128> [[TMP56]], [[TMP57]]3028// CHECK-NEXT: store volatile <1 x i128> [[SHR51]], ptr @slll, align 83029// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @slll, align 83030// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 83031// CHECK-NEXT: [[SHR52:%.*]] = ashr <1 x i128> [[TMP58]], [[TMP59]]3032// CHECK-NEXT: store volatile <1 x i128> [[SHR52]], ptr @slll, align 83033// CHECK-NEXT: [[TMP60:%.*]] = load volatile <1 x i128>, ptr @slll, align 83034// CHECK-NEXT: [[TMP61:%.*]] = load volatile i32, ptr @cnt, align 43035// CHECK-NEXT: [[SPLAT_SPLATINSERT53:%.*]] = insertelement <1 x i32> poison, i32 [[TMP61]], i64 03036// CHECK-NEXT: [[SPLAT_SPLAT54:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT53]], <1 x i32> poison, <1 x i32> zeroinitializer3037// CHECK-NEXT: [[SH_PROM55:%.*]] = zext <1 x i32> [[SPLAT_SPLAT54]] to <1 x i128>3038// CHECK-NEXT: [[SHR56:%.*]] = ashr <1 x i128> [[TMP60]], [[SH_PROM55]]3039// CHECK-NEXT: store volatile <1 x i128> [[SHR56]], ptr @slll, align 83040// CHECK-NEXT: [[TMP62:%.*]] = load volatile <1 x i128>, ptr @slll, align 83041// CHECK-NEXT: [[SHR57:%.*]] = ashr <1 x i128> [[TMP62]], splat (i128 5)3042// CHECK-NEXT: store volatile <1 x i128> [[SHR57]], ptr @slll, align 83043// CHECK-NEXT: [[TMP63:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83044// CHECK-NEXT: [[TMP64:%.*]] = load volatile <1 x i128>, ptr @slll2, align 83045// CHECK-NEXT: [[SHR58:%.*]] = lshr <1 x i128> [[TMP63]], [[TMP64]]3046// CHECK-NEXT: store volatile <1 x i128> [[SHR58]], ptr @ulll, align 83047// CHECK-NEXT: [[TMP65:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83048// CHECK-NEXT: [[TMP66:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 83049// CHECK-NEXT: [[SHR59:%.*]] = lshr <1 x i128> [[TMP65]], [[TMP66]]3050// CHECK-NEXT: store volatile <1 x i128> [[SHR59]], ptr @ulll, align 83051// CHECK-NEXT: [[TMP67:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83052// CHECK-NEXT: [[TMP68:%.*]] = load volatile i32, ptr @cnt, align 43053// CHECK-NEXT: [[SPLAT_SPLATINSERT60:%.*]] = insertelement <1 x i32> poison, i32 [[TMP68]], i64 03054// CHECK-NEXT: [[SPLAT_SPLAT61:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT60]], <1 x i32> poison, <1 x i32> zeroinitializer3055// CHECK-NEXT: [[SH_PROM62:%.*]] = zext <1 x i32> [[SPLAT_SPLAT61]] to <1 x i128>3056// CHECK-NEXT: [[SHR63:%.*]] = lshr <1 x i128> [[TMP67]], [[SH_PROM62]]3057// CHECK-NEXT: store volatile <1 x i128> [[SHR63]], ptr @ulll, align 83058// CHECK-NEXT: [[TMP69:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83059// CHECK-NEXT: [[SHR64:%.*]] = lshr <1 x i128> [[TMP69]], splat (i128 5)3060// CHECK-NEXT: store volatile <1 x i128> [[SHR64]], ptr @ulll, align 83061// CHECK-NEXT: ret void3062//3063void test_sr(void) {3064 3065 sc = sc >> sc2;3066 sc = sc >> uc2;3067 sc = sc >> cnt;3068 sc = sc >> 5;3069 uc = uc >> sc2;3070 uc = uc >> uc2;3071 uc = uc >> cnt;3072 uc = uc >> 5;3073 3074 ss = ss >> ss2;3075 ss = ss >> us2;3076 ss = ss >> cnt;3077 ss = ss >> 5;3078 us = us >> ss2;3079 us = us >> us2;3080 us = us >> cnt;3081 us = us >> 5;3082 3083 si = si >> si2;3084 si = si >> ui2;3085 si = si >> cnt;3086 si = si >> 5;3087 ui = ui >> si2;3088 ui = ui >> ui2;3089 ui = ui >> cnt;3090 ui = ui >> 5;3091 3092 sl = sl >> sl2;3093 sl = sl >> ul2;3094 sl = sl >> cnt;3095 sl = sl >> 5;3096 ul = ul >> sl2;3097 ul = ul >> ul2;3098 ul = ul >> cnt;3099 ul = ul >> 5;3100 3101 slll = slll >> slll2;3102 slll = slll >> ulll2;3103 slll = slll >> cnt;3104 slll = slll >> 5;3105 ulll = ulll >> slll2;3106 ulll = ulll >> ulll2;3107 ulll = ulll >> cnt;3108 ulll = ulll >> 5;3109}3110 3111// CHECK-LABEL: define dso_local void @test_sr_assign(3112// CHECK-SAME: ) #[[ATTR0]] {3113// CHECK-NEXT: [[ENTRY:.*:]]3114// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 83115// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 83116// CHECK-NEXT: [[SHR:%.*]] = ashr <16 x i8> [[TMP1]], [[TMP0]]3117// CHECK-NEXT: store volatile <16 x i8> [[SHR]], ptr @sc, align 83118// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc2, align 83119// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 83120// CHECK-NEXT: [[SHR1:%.*]] = ashr <16 x i8> [[TMP3]], [[TMP2]]3121// CHECK-NEXT: store volatile <16 x i8> [[SHR1]], ptr @sc, align 83122// CHECK-NEXT: [[TMP4:%.*]] = load volatile i32, ptr @cnt, align 43123// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[TMP4]], i64 03124// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer3125// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc, align 83126// CHECK-NEXT: [[SH_PROM:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT]] to <16 x i8>3127// CHECK-NEXT: [[SHR2:%.*]] = ashr <16 x i8> [[TMP5]], [[SH_PROM]]3128// CHECK-NEXT: store volatile <16 x i8> [[SHR2]], ptr @sc, align 83129// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @sc, align 83130// CHECK-NEXT: [[SHR3:%.*]] = ashr <16 x i8> [[TMP6]], splat (i8 5)3131// CHECK-NEXT: store volatile <16 x i8> [[SHR3]], ptr @sc, align 83132// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @sc2, align 83133// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 83134// CHECK-NEXT: [[SHR4:%.*]] = lshr <16 x i8> [[TMP8]], [[TMP7]]3135// CHECK-NEXT: store volatile <16 x i8> [[SHR4]], ptr @uc, align 83136// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @uc2, align 83137// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @uc, align 83138// CHECK-NEXT: [[SHR5:%.*]] = lshr <16 x i8> [[TMP10]], [[TMP9]]3139// CHECK-NEXT: store volatile <16 x i8> [[SHR5]], ptr @uc, align 83140// CHECK-NEXT: [[TMP11:%.*]] = load volatile i32, ptr @cnt, align 43141// CHECK-NEXT: [[SPLAT_SPLATINSERT6:%.*]] = insertelement <16 x i32> poison, i32 [[TMP11]], i64 03142// CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT6]], <16 x i32> poison, <16 x i32> zeroinitializer3143// CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @uc, align 83144// CHECK-NEXT: [[SH_PROM8:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT7]] to <16 x i8>3145// CHECK-NEXT: [[SHR9:%.*]] = lshr <16 x i8> [[TMP12]], [[SH_PROM8]]3146// CHECK-NEXT: store volatile <16 x i8> [[SHR9]], ptr @uc, align 83147// CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @uc, align 83148// CHECK-NEXT: [[SHR10:%.*]] = lshr <16 x i8> [[TMP13]], splat (i8 5)3149// CHECK-NEXT: store volatile <16 x i8> [[SHR10]], ptr @uc, align 83150// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss2, align 83151// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss, align 83152// CHECK-NEXT: [[SHR11:%.*]] = ashr <8 x i16> [[TMP15]], [[TMP14]]3153// CHECK-NEXT: store volatile <8 x i16> [[SHR11]], ptr @ss, align 83154// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @us2, align 83155// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @ss, align 83156// CHECK-NEXT: [[SHR12:%.*]] = ashr <8 x i16> [[TMP17]], [[TMP16]]3157// CHECK-NEXT: store volatile <8 x i16> [[SHR12]], ptr @ss, align 83158// CHECK-NEXT: [[TMP18:%.*]] = load volatile i32, ptr @cnt, align 43159// CHECK-NEXT: [[SPLAT_SPLATINSERT13:%.*]] = insertelement <8 x i32> poison, i32 [[TMP18]], i64 03160// CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT13]], <8 x i32> poison, <8 x i32> zeroinitializer3161// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss, align 83162// CHECK-NEXT: [[SH_PROM15:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT14]] to <8 x i16>3163// CHECK-NEXT: [[SHR16:%.*]] = ashr <8 x i16> [[TMP19]], [[SH_PROM15]]3164// CHECK-NEXT: store volatile <8 x i16> [[SHR16]], ptr @ss, align 83165// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @ss, align 83166// CHECK-NEXT: [[SHR17:%.*]] = ashr <8 x i16> [[TMP20]], splat (i16 5)3167// CHECK-NEXT: store volatile <8 x i16> [[SHR17]], ptr @ss, align 83168// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @ss2, align 83169// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 83170// CHECK-NEXT: [[SHR18:%.*]] = lshr <8 x i16> [[TMP22]], [[TMP21]]3171// CHECK-NEXT: store volatile <8 x i16> [[SHR18]], ptr @us, align 83172// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us2, align 83173// CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @us, align 83174// CHECK-NEXT: [[SHR19:%.*]] = lshr <8 x i16> [[TMP24]], [[TMP23]]3175// CHECK-NEXT: store volatile <8 x i16> [[SHR19]], ptr @us, align 83176// CHECK-NEXT: [[TMP25:%.*]] = load volatile i32, ptr @cnt, align 43177// CHECK-NEXT: [[SPLAT_SPLATINSERT20:%.*]] = insertelement <8 x i32> poison, i32 [[TMP25]], i64 03178// CHECK-NEXT: [[SPLAT_SPLAT21:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT20]], <8 x i32> poison, <8 x i32> zeroinitializer3179// CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @us, align 83180// CHECK-NEXT: [[SH_PROM22:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT21]] to <8 x i16>3181// CHECK-NEXT: [[SHR23:%.*]] = lshr <8 x i16> [[TMP26]], [[SH_PROM22]]3182// CHECK-NEXT: store volatile <8 x i16> [[SHR23]], ptr @us, align 83183// CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @us, align 83184// CHECK-NEXT: [[SHR24:%.*]] = lshr <8 x i16> [[TMP27]], splat (i16 5)3185// CHECK-NEXT: store volatile <8 x i16> [[SHR24]], ptr @us, align 83186// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si2, align 83187// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si, align 83188// CHECK-NEXT: [[SHR25:%.*]] = ashr <4 x i32> [[TMP29]], [[TMP28]]3189// CHECK-NEXT: store volatile <4 x i32> [[SHR25]], ptr @si, align 83190// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @ui2, align 83191// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @si, align 83192// CHECK-NEXT: [[SHR26:%.*]] = ashr <4 x i32> [[TMP31]], [[TMP30]]3193// CHECK-NEXT: store volatile <4 x i32> [[SHR26]], ptr @si, align 83194// CHECK-NEXT: [[TMP32:%.*]] = load volatile i32, ptr @cnt, align 43195// CHECK-NEXT: [[SPLAT_SPLATINSERT27:%.*]] = insertelement <4 x i32> poison, i32 [[TMP32]], i64 03196// CHECK-NEXT: [[SPLAT_SPLAT28:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT27]], <4 x i32> poison, <4 x i32> zeroinitializer3197// CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si, align 83198// CHECK-NEXT: [[SHR29:%.*]] = ashr <4 x i32> [[TMP33]], [[SPLAT_SPLAT28]]3199// CHECK-NEXT: store volatile <4 x i32> [[SHR29]], ptr @si, align 83200// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @si, align 83201// CHECK-NEXT: [[SHR30:%.*]] = ashr <4 x i32> [[TMP34]], splat (i32 5)3202// CHECK-NEXT: store volatile <4 x i32> [[SHR30]], ptr @si, align 83203// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @si2, align 83204// CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 83205// CHECK-NEXT: [[SHR31:%.*]] = lshr <4 x i32> [[TMP36]], [[TMP35]]3206// CHECK-NEXT: store volatile <4 x i32> [[SHR31]], ptr @ui, align 83207// CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @ui2, align 83208// CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @ui, align 83209// CHECK-NEXT: [[SHR32:%.*]] = lshr <4 x i32> [[TMP38]], [[TMP37]]3210// CHECK-NEXT: store volatile <4 x i32> [[SHR32]], ptr @ui, align 83211// CHECK-NEXT: [[TMP39:%.*]] = load volatile i32, ptr @cnt, align 43212// CHECK-NEXT: [[SPLAT_SPLATINSERT33:%.*]] = insertelement <4 x i32> poison, i32 [[TMP39]], i64 03213// CHECK-NEXT: [[SPLAT_SPLAT34:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT33]], <4 x i32> poison, <4 x i32> zeroinitializer3214// CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @ui, align 83215// CHECK-NEXT: [[SHR35:%.*]] = lshr <4 x i32> [[TMP40]], [[SPLAT_SPLAT34]]3216// CHECK-NEXT: store volatile <4 x i32> [[SHR35]], ptr @ui, align 83217// CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @ui, align 83218// CHECK-NEXT: [[SHR36:%.*]] = lshr <4 x i32> [[TMP41]], splat (i32 5)3219// CHECK-NEXT: store volatile <4 x i32> [[SHR36]], ptr @ui, align 83220// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl2, align 83221// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl, align 83222// CHECK-NEXT: [[SHR37:%.*]] = ashr <2 x i64> [[TMP43]], [[TMP42]]3223// CHECK-NEXT: store volatile <2 x i64> [[SHR37]], ptr @sl, align 83224// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @ul2, align 83225// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @sl, align 83226// CHECK-NEXT: [[SHR38:%.*]] = ashr <2 x i64> [[TMP45]], [[TMP44]]3227// CHECK-NEXT: store volatile <2 x i64> [[SHR38]], ptr @sl, align 83228// CHECK-NEXT: [[TMP46:%.*]] = load volatile i32, ptr @cnt, align 43229// CHECK-NEXT: [[SPLAT_SPLATINSERT39:%.*]] = insertelement <2 x i32> poison, i32 [[TMP46]], i64 03230// CHECK-NEXT: [[SPLAT_SPLAT40:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT39]], <2 x i32> poison, <2 x i32> zeroinitializer3231// CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl, align 83232// CHECK-NEXT: [[SH_PROM41:%.*]] = zext <2 x i32> [[SPLAT_SPLAT40]] to <2 x i64>3233// CHECK-NEXT: [[SHR42:%.*]] = ashr <2 x i64> [[TMP47]], [[SH_PROM41]]3234// CHECK-NEXT: store volatile <2 x i64> [[SHR42]], ptr @sl, align 83235// CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 83236// CHECK-NEXT: [[SHR43:%.*]] = ashr <2 x i64> [[TMP48]], splat (i64 5)3237// CHECK-NEXT: store volatile <2 x i64> [[SHR43]], ptr @sl, align 83238// CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @sl2, align 83239// CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 83240// CHECK-NEXT: [[SHR44:%.*]] = lshr <2 x i64> [[TMP50]], [[TMP49]]3241// CHECK-NEXT: store volatile <2 x i64> [[SHR44]], ptr @ul, align 83242// CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @ul2, align 83243// CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @ul, align 83244// CHECK-NEXT: [[SHR45:%.*]] = lshr <2 x i64> [[TMP52]], [[TMP51]]3245// CHECK-NEXT: store volatile <2 x i64> [[SHR45]], ptr @ul, align 83246// CHECK-NEXT: [[TMP53:%.*]] = load volatile i32, ptr @cnt, align 43247// CHECK-NEXT: [[SPLAT_SPLATINSERT46:%.*]] = insertelement <2 x i32> poison, i32 [[TMP53]], i64 03248// CHECK-NEXT: [[SPLAT_SPLAT47:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT46]], <2 x i32> poison, <2 x i32> zeroinitializer3249// CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @ul, align 83250// CHECK-NEXT: [[SH_PROM48:%.*]] = zext <2 x i32> [[SPLAT_SPLAT47]] to <2 x i64>3251// CHECK-NEXT: [[SHR49:%.*]] = lshr <2 x i64> [[TMP54]], [[SH_PROM48]]3252// CHECK-NEXT: store volatile <2 x i64> [[SHR49]], ptr @ul, align 83253// CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @ul, align 83254// CHECK-NEXT: [[SHR50:%.*]] = lshr <2 x i64> [[TMP55]], splat (i64 5)3255// CHECK-NEXT: store volatile <2 x i64> [[SHR50]], ptr @ul, align 83256// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @slll2, align 83257// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @slll, align 83258// CHECK-NEXT: [[SHR51:%.*]] = ashr <1 x i128> [[TMP57]], [[TMP56]]3259// CHECK-NEXT: store volatile <1 x i128> [[SHR51]], ptr @slll, align 83260// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 83261// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @slll, align 83262// CHECK-NEXT: [[SHR52:%.*]] = ashr <1 x i128> [[TMP59]], [[TMP58]]3263// CHECK-NEXT: store volatile <1 x i128> [[SHR52]], ptr @slll, align 83264// CHECK-NEXT: [[TMP60:%.*]] = load volatile i32, ptr @cnt, align 43265// CHECK-NEXT: [[SPLAT_SPLATINSERT53:%.*]] = insertelement <1 x i32> poison, i32 [[TMP60]], i64 03266// CHECK-NEXT: [[SPLAT_SPLAT54:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT53]], <1 x i32> poison, <1 x i32> zeroinitializer3267// CHECK-NEXT: [[TMP61:%.*]] = load volatile <1 x i128>, ptr @slll, align 83268// CHECK-NEXT: [[SH_PROM55:%.*]] = zext <1 x i32> [[SPLAT_SPLAT54]] to <1 x i128>3269// CHECK-NEXT: [[SHR56:%.*]] = ashr <1 x i128> [[TMP61]], [[SH_PROM55]]3270// CHECK-NEXT: store volatile <1 x i128> [[SHR56]], ptr @slll, align 83271// CHECK-NEXT: [[TMP62:%.*]] = load volatile <1 x i128>, ptr @slll, align 83272// CHECK-NEXT: [[SHR57:%.*]] = ashr <1 x i128> [[TMP62]], splat (i128 5)3273// CHECK-NEXT: store volatile <1 x i128> [[SHR57]], ptr @slll, align 83274// CHECK-NEXT: [[TMP63:%.*]] = load volatile <1 x i128>, ptr @slll2, align 83275// CHECK-NEXT: [[TMP64:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83276// CHECK-NEXT: [[SHR58:%.*]] = lshr <1 x i128> [[TMP64]], [[TMP63]]3277// CHECK-NEXT: store volatile <1 x i128> [[SHR58]], ptr @ulll, align 83278// CHECK-NEXT: [[TMP65:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 83279// CHECK-NEXT: [[TMP66:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83280// CHECK-NEXT: [[SHR59:%.*]] = lshr <1 x i128> [[TMP66]], [[TMP65]]3281// CHECK-NEXT: store volatile <1 x i128> [[SHR59]], ptr @ulll, align 83282// CHECK-NEXT: [[TMP67:%.*]] = load volatile i32, ptr @cnt, align 43283// CHECK-NEXT: [[SPLAT_SPLATINSERT60:%.*]] = insertelement <1 x i32> poison, i32 [[TMP67]], i64 03284// CHECK-NEXT: [[SPLAT_SPLAT61:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT60]], <1 x i32> poison, <1 x i32> zeroinitializer3285// CHECK-NEXT: [[TMP68:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83286// CHECK-NEXT: [[SH_PROM62:%.*]] = zext <1 x i32> [[SPLAT_SPLAT61]] to <1 x i128>3287// CHECK-NEXT: [[SHR63:%.*]] = lshr <1 x i128> [[TMP68]], [[SH_PROM62]]3288// CHECK-NEXT: store volatile <1 x i128> [[SHR63]], ptr @ulll, align 83289// CHECK-NEXT: [[TMP69:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83290// CHECK-NEXT: [[SHR64:%.*]] = lshr <1 x i128> [[TMP69]], splat (i128 5)3291// CHECK-NEXT: store volatile <1 x i128> [[SHR64]], ptr @ulll, align 83292// CHECK-NEXT: ret void3293//3294void test_sr_assign(void) {3295 3296 sc >>= sc2;3297 sc >>= uc2;3298 sc >>= cnt;3299 sc >>= 5;3300 uc >>= sc2;3301 uc >>= uc2;3302 uc >>= cnt;3303 uc >>= 5;3304 3305 ss >>= ss2;3306 ss >>= us2;3307 ss >>= cnt;3308 ss >>= 5;3309 us >>= ss2;3310 us >>= us2;3311 us >>= cnt;3312 us >>= 5;3313 3314 si >>= si2;3315 si >>= ui2;3316 si >>= cnt;3317 si >>= 5;3318 ui >>= si2;3319 ui >>= ui2;3320 ui >>= cnt;3321 ui >>= 5;3322 3323 sl >>= sl2;3324 sl >>= ul2;3325 sl >>= cnt;3326 sl >>= 5;3327 ul >>= sl2;3328 ul >>= ul2;3329 ul >>= cnt;3330 ul >>= 5;3331 3332 slll >>= slll2;3333 slll >>= ulll2;3334 slll >>= cnt;3335 slll >>= 5;3336 ulll >>= slll2;3337 ulll >>= ulll2;3338 ulll >>= cnt;3339 ulll >>= 5;3340}3341 3342 3343// CHECK-LABEL: define dso_local void @test_cmpeq(3344// CHECK-SAME: ) #[[ATTR0]] {3345// CHECK-NEXT: [[ENTRY:.*:]]3346// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 83347// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 83348// CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]3349// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>3350// CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 83351// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 83352// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 83353// CHECK-NEXT: [[CMP1:%.*]] = icmp eq <16 x i8> [[TMP2]], [[TMP3]]3354// CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>3355// CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 83356// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 83357// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 83358// CHECK-NEXT: [[CMP3:%.*]] = icmp eq <16 x i8> [[TMP4]], [[TMP5]]3359// CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>3360// CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 83361// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 83362// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 83363// CHECK-NEXT: [[CMP5:%.*]] = icmp eq <16 x i8> [[TMP6]], [[TMP7]]3364// CHECK-NEXT: [[SEXT6:%.*]] = sext <16 x i1> [[CMP5]] to <16 x i8>3365// CHECK-NEXT: store volatile <16 x i8> [[SEXT6]], ptr @bc, align 83366// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 83367// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 83368// CHECK-NEXT: [[CMP7:%.*]] = icmp eq <16 x i8> [[TMP8]], [[TMP9]]3369// CHECK-NEXT: [[SEXT8:%.*]] = sext <16 x i1> [[CMP7]] to <16 x i8>3370// CHECK-NEXT: store volatile <16 x i8> [[SEXT8]], ptr @bc, align 83371// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 83372// CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 83373// CHECK-NEXT: [[CMP9:%.*]] = icmp eq <16 x i8> [[TMP10]], [[TMP11]]3374// CHECK-NEXT: [[SEXT10:%.*]] = sext <16 x i1> [[CMP9]] to <16 x i8>3375// CHECK-NEXT: store volatile <16 x i8> [[SEXT10]], ptr @bc, align 83376// CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @bc, align 83377// CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @bc2, align 83378// CHECK-NEXT: [[CMP11:%.*]] = icmp eq <16 x i8> [[TMP12]], [[TMP13]]3379// CHECK-NEXT: [[SEXT12:%.*]] = sext <16 x i1> [[CMP11]] to <16 x i8>3380// CHECK-NEXT: store volatile <16 x i8> [[SEXT12]], ptr @bc, align 83381// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 83382// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 83383// CHECK-NEXT: [[CMP13:%.*]] = icmp eq <8 x i16> [[TMP14]], [[TMP15]]3384// CHECK-NEXT: [[SEXT14:%.*]] = sext <8 x i1> [[CMP13]] to <8 x i16>3385// CHECK-NEXT: store volatile <8 x i16> [[SEXT14]], ptr @bs, align 83386// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 83387// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @bs2, align 83388// CHECK-NEXT: [[CMP15:%.*]] = icmp eq <8 x i16> [[TMP16]], [[TMP17]]3389// CHECK-NEXT: [[SEXT16:%.*]] = sext <8 x i1> [[CMP15]] to <8 x i16>3390// CHECK-NEXT: store volatile <8 x i16> [[SEXT16]], ptr @bs, align 83391// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs, align 83392// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss2, align 83393// CHECK-NEXT: [[CMP17:%.*]] = icmp eq <8 x i16> [[TMP18]], [[TMP19]]3394// CHECK-NEXT: [[SEXT18:%.*]] = sext <8 x i1> [[CMP17]] to <8 x i16>3395// CHECK-NEXT: store volatile <8 x i16> [[SEXT18]], ptr @bs, align 83396// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 83397// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us2, align 83398// CHECK-NEXT: [[CMP19:%.*]] = icmp eq <8 x i16> [[TMP20]], [[TMP21]]3399// CHECK-NEXT: [[SEXT20:%.*]] = sext <8 x i1> [[CMP19]] to <8 x i16>3400// CHECK-NEXT: store volatile <8 x i16> [[SEXT20]], ptr @bs, align 83401// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 83402// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @bs2, align 83403// CHECK-NEXT: [[CMP21:%.*]] = icmp eq <8 x i16> [[TMP22]], [[TMP23]]3404// CHECK-NEXT: [[SEXT22:%.*]] = sext <8 x i1> [[CMP21]] to <8 x i16>3405// CHECK-NEXT: store volatile <8 x i16> [[SEXT22]], ptr @bs, align 83406// CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @bs, align 83407// CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us2, align 83408// CHECK-NEXT: [[CMP23:%.*]] = icmp eq <8 x i16> [[TMP24]], [[TMP25]]3409// CHECK-NEXT: [[SEXT24:%.*]] = sext <8 x i1> [[CMP23]] to <8 x i16>3410// CHECK-NEXT: store volatile <8 x i16> [[SEXT24]], ptr @bs, align 83411// CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @bs, align 83412// CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @bs2, align 83413// CHECK-NEXT: [[CMP25:%.*]] = icmp eq <8 x i16> [[TMP26]], [[TMP27]]3414// CHECK-NEXT: [[SEXT26:%.*]] = sext <8 x i1> [[CMP25]] to <8 x i16>3415// CHECK-NEXT: store volatile <8 x i16> [[SEXT26]], ptr @bs, align 83416// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 83417// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 83418// CHECK-NEXT: [[CMP27:%.*]] = icmp eq <4 x i32> [[TMP28]], [[TMP29]]3419// CHECK-NEXT: [[SEXT28:%.*]] = sext <4 x i1> [[CMP27]] to <4 x i32>3420// CHECK-NEXT: store volatile <4 x i32> [[SEXT28]], ptr @bi, align 83421// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 83422// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @bi2, align 83423// CHECK-NEXT: [[CMP29:%.*]] = icmp eq <4 x i32> [[TMP30]], [[TMP31]]3424// CHECK-NEXT: [[SEXT30:%.*]] = sext <4 x i1> [[CMP29]] to <4 x i32>3425// CHECK-NEXT: store volatile <4 x i32> [[SEXT30]], ptr @bi, align 83426// CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @bi, align 83427// CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si2, align 83428// CHECK-NEXT: [[CMP31:%.*]] = icmp eq <4 x i32> [[TMP32]], [[TMP33]]3429// CHECK-NEXT: [[SEXT32:%.*]] = sext <4 x i1> [[CMP31]] to <4 x i32>3430// CHECK-NEXT: store volatile <4 x i32> [[SEXT32]], ptr @bi, align 83431// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @ui, align 83432// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 83433// CHECK-NEXT: [[CMP33:%.*]] = icmp eq <4 x i32> [[TMP34]], [[TMP35]]3434// CHECK-NEXT: [[SEXT34:%.*]] = sext <4 x i1> [[CMP33]] to <4 x i32>3435// CHECK-NEXT: store volatile <4 x i32> [[SEXT34]], ptr @bi, align 83436// CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 83437// CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @bi2, align 83438// CHECK-NEXT: [[CMP35:%.*]] = icmp eq <4 x i32> [[TMP36]], [[TMP37]]3439// CHECK-NEXT: [[SEXT36:%.*]] = sext <4 x i1> [[CMP35]] to <4 x i32>3440// CHECK-NEXT: store volatile <4 x i32> [[SEXT36]], ptr @bi, align 83441// CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @bi, align 83442// CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui2, align 83443// CHECK-NEXT: [[CMP37:%.*]] = icmp eq <4 x i32> [[TMP38]], [[TMP39]]3444// CHECK-NEXT: [[SEXT38:%.*]] = sext <4 x i1> [[CMP37]] to <4 x i32>3445// CHECK-NEXT: store volatile <4 x i32> [[SEXT38]], ptr @bi, align 83446// CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @bi, align 83447// CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @bi2, align 83448// CHECK-NEXT: [[CMP39:%.*]] = icmp eq <4 x i32> [[TMP40]], [[TMP41]]3449// CHECK-NEXT: [[SEXT40:%.*]] = sext <4 x i1> [[CMP39]] to <4 x i32>3450// CHECK-NEXT: store volatile <4 x i32> [[SEXT40]], ptr @bi, align 83451// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 83452// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 83453// CHECK-NEXT: [[CMP41:%.*]] = icmp eq <2 x i64> [[TMP42]], [[TMP43]]3454// CHECK-NEXT: [[SEXT42:%.*]] = sext <2 x i1> [[CMP41]] to <2 x i64>3455// CHECK-NEXT: store volatile <2 x i64> [[SEXT42]], ptr @bl, align 83456// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 83457// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 83458// CHECK-NEXT: [[CMP43:%.*]] = icmp eq <2 x i64> [[TMP44]], [[TMP45]]3459// CHECK-NEXT: [[SEXT44:%.*]] = sext <2 x i1> [[CMP43]] to <2 x i64>3460// CHECK-NEXT: store volatile <2 x i64> [[SEXT44]], ptr @bl, align 83461// CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 83462// CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl2, align 83463// CHECK-NEXT: [[CMP45:%.*]] = icmp eq <2 x i64> [[TMP46]], [[TMP47]]3464// CHECK-NEXT: [[SEXT46:%.*]] = sext <2 x i1> [[CMP45]] to <2 x i64>3465// CHECK-NEXT: store volatile <2 x i64> [[SEXT46]], ptr @bl, align 83466// CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @ul, align 83467// CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul2, align 83468// CHECK-NEXT: [[CMP47:%.*]] = icmp eq <2 x i64> [[TMP48]], [[TMP49]]3469// CHECK-NEXT: [[SEXT48:%.*]] = sext <2 x i1> [[CMP47]] to <2 x i64>3470// CHECK-NEXT: store volatile <2 x i64> [[SEXT48]], ptr @bl, align 83471// CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 83472// CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @bl2, align 83473// CHECK-NEXT: [[CMP49:%.*]] = icmp eq <2 x i64> [[TMP50]], [[TMP51]]3474// CHECK-NEXT: [[SEXT50:%.*]] = sext <2 x i1> [[CMP49]] to <2 x i64>3475// CHECK-NEXT: store volatile <2 x i64> [[SEXT50]], ptr @bl, align 83476// CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @bl, align 83477// CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul2, align 83478// CHECK-NEXT: [[CMP51:%.*]] = icmp eq <2 x i64> [[TMP52]], [[TMP53]]3479// CHECK-NEXT: [[SEXT52:%.*]] = sext <2 x i1> [[CMP51]] to <2 x i64>3480// CHECK-NEXT: store volatile <2 x i64> [[SEXT52]], ptr @bl, align 83481// CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @bl, align 83482// CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @bl2, align 83483// CHECK-NEXT: [[CMP53:%.*]] = icmp eq <2 x i64> [[TMP54]], [[TMP55]]3484// CHECK-NEXT: [[SEXT54:%.*]] = sext <2 x i1> [[CMP53]] to <2 x i64>3485// CHECK-NEXT: store volatile <2 x i64> [[SEXT54]], ptr @bl, align 83486// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @slll, align 83487// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @slll2, align 83488// CHECK-NEXT: [[CMP55:%.*]] = icmp eq <1 x i128> [[TMP56]], [[TMP57]]3489// CHECK-NEXT: [[SEXT56:%.*]] = sext <1 x i1> [[CMP55]] to <1 x i128>3490// CHECK-NEXT: store volatile <1 x i128> [[SEXT56]], ptr @blll, align 83491// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @slll, align 83492// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @blll2, align 83493// CHECK-NEXT: [[CMP57:%.*]] = icmp eq <1 x i128> [[TMP58]], [[TMP59]]3494// CHECK-NEXT: [[SEXT58:%.*]] = sext <1 x i1> [[CMP57]] to <1 x i128>3495// CHECK-NEXT: store volatile <1 x i128> [[SEXT58]], ptr @blll, align 83496// CHECK-NEXT: [[TMP60:%.*]] = load volatile <1 x i128>, ptr @blll, align 83497// CHECK-NEXT: [[TMP61:%.*]] = load volatile <1 x i128>, ptr @slll2, align 83498// CHECK-NEXT: [[CMP59:%.*]] = icmp eq <1 x i128> [[TMP60]], [[TMP61]]3499// CHECK-NEXT: [[SEXT60:%.*]] = sext <1 x i1> [[CMP59]] to <1 x i128>3500// CHECK-NEXT: store volatile <1 x i128> [[SEXT60]], ptr @blll, align 83501// CHECK-NEXT: [[TMP62:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83502// CHECK-NEXT: [[TMP63:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 83503// CHECK-NEXT: [[CMP61:%.*]] = icmp eq <1 x i128> [[TMP62]], [[TMP63]]3504// CHECK-NEXT: [[SEXT62:%.*]] = sext <1 x i1> [[CMP61]] to <1 x i128>3505// CHECK-NEXT: store volatile <1 x i128> [[SEXT62]], ptr @blll, align 83506// CHECK-NEXT: [[TMP64:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83507// CHECK-NEXT: [[TMP65:%.*]] = load volatile <1 x i128>, ptr @blll2, align 83508// CHECK-NEXT: [[CMP63:%.*]] = icmp eq <1 x i128> [[TMP64]], [[TMP65]]3509// CHECK-NEXT: [[SEXT64:%.*]] = sext <1 x i1> [[CMP63]] to <1 x i128>3510// CHECK-NEXT: store volatile <1 x i128> [[SEXT64]], ptr @blll, align 83511// CHECK-NEXT: [[TMP66:%.*]] = load volatile <1 x i128>, ptr @blll, align 83512// CHECK-NEXT: [[TMP67:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 83513// CHECK-NEXT: [[CMP65:%.*]] = icmp eq <1 x i128> [[TMP66]], [[TMP67]]3514// CHECK-NEXT: [[SEXT66:%.*]] = sext <1 x i1> [[CMP65]] to <1 x i128>3515// CHECK-NEXT: store volatile <1 x i128> [[SEXT66]], ptr @blll, align 83516// CHECK-NEXT: [[TMP68:%.*]] = load volatile <1 x i128>, ptr @blll, align 83517// CHECK-NEXT: [[TMP69:%.*]] = load volatile <1 x i128>, ptr @blll2, align 83518// CHECK-NEXT: [[CMP67:%.*]] = icmp eq <1 x i128> [[TMP68]], [[TMP69]]3519// CHECK-NEXT: [[SEXT68:%.*]] = sext <1 x i1> [[CMP67]] to <1 x i128>3520// CHECK-NEXT: store volatile <1 x i128> [[SEXT68]], ptr @blll, align 83521// CHECK-NEXT: [[TMP70:%.*]] = load volatile <2 x double>, ptr @fd, align 83522// CHECK-NEXT: [[TMP71:%.*]] = load volatile <2 x double>, ptr @fd2, align 83523// CHECK-NEXT: [[CMP69:%.*]] = fcmp oeq <2 x double> [[TMP70]], [[TMP71]]3524// CHECK-NEXT: [[SEXT70:%.*]] = sext <2 x i1> [[CMP69]] to <2 x i64>3525// CHECK-NEXT: store volatile <2 x i64> [[SEXT70]], ptr @bl, align 83526// CHECK-NEXT: ret void3527//3528void test_cmpeq(void) {3529 3530 bc = sc == sc2;3531 bc = sc == bc2;3532 bc = bc == sc2;3533 bc = uc == uc2;3534 bc = uc == bc2;3535 bc = bc == uc2;3536 bc = bc == bc2;3537 3538 bs = ss == ss2;3539 bs = ss == bs2;3540 bs = bs == ss2;3541 bs = us == us2;3542 bs = us == bs2;3543 bs = bs == us2;3544 bs = bs == bs2;3545 3546 bi = si == si2;3547 bi = si == bi2;3548 bi = bi == si2;3549 bi = ui == ui2;3550 bi = ui == bi2;3551 bi = bi == ui2;3552 bi = bi == bi2;3553 3554 bl = sl == sl2;3555 bl = sl == bl2;3556 bl = bl == sl2;3557 bl = ul == ul2;3558 bl = ul == bl2;3559 bl = bl == ul2;3560 bl = bl == bl2;3561 3562 blll = slll == slll2;3563 blll = slll == blll2;3564 blll = blll == slll2;3565 blll = ulll == ulll2;3566 blll = ulll == blll2;3567 blll = blll == ulll2;3568 blll = blll == blll2;3569 3570 bl = fd == fd2;3571}3572 3573// CHECK-LABEL: define dso_local void @test_cmpne(3574// CHECK-SAME: ) #[[ATTR0]] {3575// CHECK-NEXT: [[ENTRY:.*:]]3576// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 83577// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 83578// CHECK-NEXT: [[CMP:%.*]] = icmp ne <16 x i8> [[TMP0]], [[TMP1]]3579// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>3580// CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 83581// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 83582// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 83583// CHECK-NEXT: [[CMP1:%.*]] = icmp ne <16 x i8> [[TMP2]], [[TMP3]]3584// CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>3585// CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 83586// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 83587// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 83588// CHECK-NEXT: [[CMP3:%.*]] = icmp ne <16 x i8> [[TMP4]], [[TMP5]]3589// CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>3590// CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 83591// CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 83592// CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 83593// CHECK-NEXT: [[CMP5:%.*]] = icmp ne <16 x i8> [[TMP6]], [[TMP7]]3594// CHECK-NEXT: [[SEXT6:%.*]] = sext <16 x i1> [[CMP5]] to <16 x i8>3595// CHECK-NEXT: store volatile <16 x i8> [[SEXT6]], ptr @bc, align 83596// CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 83597// CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 83598// CHECK-NEXT: [[CMP7:%.*]] = icmp ne <16 x i8> [[TMP8]], [[TMP9]]3599// CHECK-NEXT: [[SEXT8:%.*]] = sext <16 x i1> [[CMP7]] to <16 x i8>3600// CHECK-NEXT: store volatile <16 x i8> [[SEXT8]], ptr @bc, align 83601// CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 83602// CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 83603// CHECK-NEXT: [[CMP9:%.*]] = icmp ne <16 x i8> [[TMP10]], [[TMP11]]3604// CHECK-NEXT: [[SEXT10:%.*]] = sext <16 x i1> [[CMP9]] to <16 x i8>3605// CHECK-NEXT: store volatile <16 x i8> [[SEXT10]], ptr @bc, align 83606// CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @bc, align 83607// CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @bc2, align 83608// CHECK-NEXT: [[CMP11:%.*]] = icmp ne <16 x i8> [[TMP12]], [[TMP13]]3609// CHECK-NEXT: [[SEXT12:%.*]] = sext <16 x i1> [[CMP11]] to <16 x i8>3610// CHECK-NEXT: store volatile <16 x i8> [[SEXT12]], ptr @bc, align 83611// CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 83612// CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 83613// CHECK-NEXT: [[CMP13:%.*]] = icmp ne <8 x i16> [[TMP14]], [[TMP15]]3614// CHECK-NEXT: [[SEXT14:%.*]] = sext <8 x i1> [[CMP13]] to <8 x i16>3615// CHECK-NEXT: store volatile <8 x i16> [[SEXT14]], ptr @bs, align 83616// CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 83617// CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @bs2, align 83618// CHECK-NEXT: [[CMP15:%.*]] = icmp ne <8 x i16> [[TMP16]], [[TMP17]]3619// CHECK-NEXT: [[SEXT16:%.*]] = sext <8 x i1> [[CMP15]] to <8 x i16>3620// CHECK-NEXT: store volatile <8 x i16> [[SEXT16]], ptr @bs, align 83621// CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs, align 83622// CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss2, align 83623// CHECK-NEXT: [[CMP17:%.*]] = icmp ne <8 x i16> [[TMP18]], [[TMP19]]3624// CHECK-NEXT: [[SEXT18:%.*]] = sext <8 x i1> [[CMP17]] to <8 x i16>3625// CHECK-NEXT: store volatile <8 x i16> [[SEXT18]], ptr @bs, align 83626// CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 83627// CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us2, align 83628// CHECK-NEXT: [[CMP19:%.*]] = icmp ne <8 x i16> [[TMP20]], [[TMP21]]3629// CHECK-NEXT: [[SEXT20:%.*]] = sext <8 x i1> [[CMP19]] to <8 x i16>3630// CHECK-NEXT: store volatile <8 x i16> [[SEXT20]], ptr @bs, align 83631// CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 83632// CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @bs2, align 83633// CHECK-NEXT: [[CMP21:%.*]] = icmp ne <8 x i16> [[TMP22]], [[TMP23]]3634// CHECK-NEXT: [[SEXT22:%.*]] = sext <8 x i1> [[CMP21]] to <8 x i16>3635// CHECK-NEXT: store volatile <8 x i16> [[SEXT22]], ptr @bs, align 83636// CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @bs, align 83637// CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us2, align 83638// CHECK-NEXT: [[CMP23:%.*]] = icmp ne <8 x i16> [[TMP24]], [[TMP25]]3639// CHECK-NEXT: [[SEXT24:%.*]] = sext <8 x i1> [[CMP23]] to <8 x i16>3640// CHECK-NEXT: store volatile <8 x i16> [[SEXT24]], ptr @bs, align 83641// CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @bs, align 83642// CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @bs2, align 83643// CHECK-NEXT: [[CMP25:%.*]] = icmp ne <8 x i16> [[TMP26]], [[TMP27]]3644// CHECK-NEXT: [[SEXT26:%.*]] = sext <8 x i1> [[CMP25]] to <8 x i16>3645// CHECK-NEXT: store volatile <8 x i16> [[SEXT26]], ptr @bs, align 83646// CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 83647// CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 83648// CHECK-NEXT: [[CMP27:%.*]] = icmp ne <4 x i32> [[TMP28]], [[TMP29]]3649// CHECK-NEXT: [[SEXT28:%.*]] = sext <4 x i1> [[CMP27]] to <4 x i32>3650// CHECK-NEXT: store volatile <4 x i32> [[SEXT28]], ptr @bi, align 83651// CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 83652// CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @bi2, align 83653// CHECK-NEXT: [[CMP29:%.*]] = icmp ne <4 x i32> [[TMP30]], [[TMP31]]3654// CHECK-NEXT: [[SEXT30:%.*]] = sext <4 x i1> [[CMP29]] to <4 x i32>3655// CHECK-NEXT: store volatile <4 x i32> [[SEXT30]], ptr @bi, align 83656// CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @bi, align 83657// CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si2, align 83658// CHECK-NEXT: [[CMP31:%.*]] = icmp ne <4 x i32> [[TMP32]], [[TMP33]]3659// CHECK-NEXT: [[SEXT32:%.*]] = sext <4 x i1> [[CMP31]] to <4 x i32>3660// CHECK-NEXT: store volatile <4 x i32> [[SEXT32]], ptr @bi, align 83661// CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @ui, align 83662// CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 83663// CHECK-NEXT: [[CMP33:%.*]] = icmp ne <4 x i32> [[TMP34]], [[TMP35]]3664// CHECK-NEXT: [[SEXT34:%.*]] = sext <4 x i1> [[CMP33]] to <4 x i32>3665// CHECK-NEXT: store volatile <4 x i32> [[SEXT34]], ptr @bi, align 83666// CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 83667// CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @bi2, align 83668// CHECK-NEXT: [[CMP35:%.*]] = icmp ne <4 x i32> [[TMP36]], [[TMP37]]3669// CHECK-NEXT: [[SEXT36:%.*]] = sext <4 x i1> [[CMP35]] to <4 x i32>3670// CHECK-NEXT: store volatile <4 x i32> [[SEXT36]], ptr @bi, align 83671// CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @bi, align 83672// CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui2, align 83673// CHECK-NEXT: [[CMP37:%.*]] = icmp ne <4 x i32> [[TMP38]], [[TMP39]]3674// CHECK-NEXT: [[SEXT38:%.*]] = sext <4 x i1> [[CMP37]] to <4 x i32>3675// CHECK-NEXT: store volatile <4 x i32> [[SEXT38]], ptr @bi, align 83676// CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @bi, align 83677// CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @bi2, align 83678// CHECK-NEXT: [[CMP39:%.*]] = icmp ne <4 x i32> [[TMP40]], [[TMP41]]3679// CHECK-NEXT: [[SEXT40:%.*]] = sext <4 x i1> [[CMP39]] to <4 x i32>3680// CHECK-NEXT: store volatile <4 x i32> [[SEXT40]], ptr @bi, align 83681// CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 83682// CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 83683// CHECK-NEXT: [[CMP41:%.*]] = icmp ne <2 x i64> [[TMP42]], [[TMP43]]3684// CHECK-NEXT: [[SEXT42:%.*]] = sext <2 x i1> [[CMP41]] to <2 x i64>3685// CHECK-NEXT: store volatile <2 x i64> [[SEXT42]], ptr @bl, align 83686// CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 83687// CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 83688// CHECK-NEXT: [[CMP43:%.*]] = icmp ne <2 x i64> [[TMP44]], [[TMP45]]3689// CHECK-NEXT: [[SEXT44:%.*]] = sext <2 x i1> [[CMP43]] to <2 x i64>3690// CHECK-NEXT: store volatile <2 x i64> [[SEXT44]], ptr @bl, align 83691// CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 83692// CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl2, align 83693// CHECK-NEXT: [[CMP45:%.*]] = icmp ne <2 x i64> [[TMP46]], [[TMP47]]3694// CHECK-NEXT: [[SEXT46:%.*]] = sext <2 x i1> [[CMP45]] to <2 x i64>3695// CHECK-NEXT: store volatile <2 x i64> [[SEXT46]], ptr @bl, align 83696// CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @ul, align 83697// CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul2, align 83698// CHECK-NEXT: [[CMP47:%.*]] = icmp ne <2 x i64> [[TMP48]], [[TMP49]]3699// CHECK-NEXT: [[SEXT48:%.*]] = sext <2 x i1> [[CMP47]] to <2 x i64>3700// CHECK-NEXT: store volatile <2 x i64> [[SEXT48]], ptr @bl, align 83701// CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 83702// CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @bl2, align 83703// CHECK-NEXT: [[CMP49:%.*]] = icmp ne <2 x i64> [[TMP50]], [[TMP51]]3704// CHECK-NEXT: [[SEXT50:%.*]] = sext <2 x i1> [[CMP49]] to <2 x i64>3705// CHECK-NEXT: store volatile <2 x i64> [[SEXT50]], ptr @bl, align 83706// CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @bl, align 83707// CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul2, align 83708// CHECK-NEXT: [[CMP51:%.*]] = icmp ne <2 x i64> [[TMP52]], [[TMP53]]3709// CHECK-NEXT: [[SEXT52:%.*]] = sext <2 x i1> [[CMP51]] to <2 x i64>3710// CHECK-NEXT: store volatile <2 x i64> [[SEXT52]], ptr @bl, align 83711// CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @bl, align 83712// CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @bl2, align 83713// CHECK-NEXT: [[CMP53:%.*]] = icmp ne <2 x i64> [[TMP54]], [[TMP55]]3714// CHECK-NEXT: [[SEXT54:%.*]] = sext <2 x i1> [[CMP53]] to <2 x i64>3715// CHECK-NEXT: store volatile <2 x i64> [[SEXT54]], ptr @bl, align 83716// CHECK-NEXT: [[TMP56:%.*]] = load volatile <1 x i128>, ptr @slll, align 83717// CHECK-NEXT: [[TMP57:%.*]] = load volatile <1 x i128>, ptr @slll2, align 83718// CHECK-NEXT: [[CMP55:%.*]] = icmp ne <1 x i128> [[TMP56]], [[TMP57]]3719// CHECK-NEXT: [[SEXT56:%.*]] = sext <1 x i1> [[CMP55]] to <1 x i128>3720// CHECK-NEXT: store volatile <1 x i128> [[SEXT56]], ptr @blll, align 83721// CHECK-NEXT: [[TMP58:%.*]] = load volatile <1 x i128>, ptr @slll, align 83722// CHECK-NEXT: [[TMP59:%.*]] = load volatile <1 x i128>, ptr @blll2, align 83723// CHECK-NEXT: [[CMP57:%.*]] = icmp ne <1 x i128> [[TMP58]], [[TMP59]]3724// CHECK-NEXT: [[SEXT58:%.*]] = sext <1 x i1> [[CMP57]] to <1 x i128>3725// CHECK-NEXT: store volatile <1 x i128> [[SEXT58]], ptr @blll, align 83726// CHECK-NEXT: [[TMP60:%.*]] = load volatile <1 x i128>, ptr @blll, align 83727// CHECK-NEXT: [[TMP61:%.*]] = load volatile <1 x i128>, ptr @slll2, align 83728// CHECK-NEXT: [[CMP59:%.*]] = icmp ne <1 x i128> [[TMP60]], [[TMP61]]3729// CHECK-NEXT: [[SEXT60:%.*]] = sext <1 x i1> [[CMP59]] to <1 x i128>3730// CHECK-NEXT: store volatile <1 x i128> [[SEXT60]], ptr @blll, align 83731// CHECK-NEXT: [[TMP62:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83732// CHECK-NEXT: [[TMP63:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 83733// CHECK-NEXT: [[CMP61:%.*]] = icmp ne <1 x i128> [[TMP62]], [[TMP63]]3734// CHECK-NEXT: [[SEXT62:%.*]] = sext <1 x i1> [[CMP61]] to <1 x i128>3735// CHECK-NEXT: store volatile <1 x i128> [[SEXT62]], ptr @blll, align 83736// CHECK-NEXT: [[TMP64:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83737// CHECK-NEXT: [[TMP65:%.*]] = load volatile <1 x i128>, ptr @blll2, align 83738// CHECK-NEXT: [[CMP63:%.*]] = icmp ne <1 x i128> [[TMP64]], [[TMP65]]3739// CHECK-NEXT: [[SEXT64:%.*]] = sext <1 x i1> [[CMP63]] to <1 x i128>3740// CHECK-NEXT: store volatile <1 x i128> [[SEXT64]], ptr @blll, align 83741// CHECK-NEXT: [[TMP66:%.*]] = load volatile <1 x i128>, ptr @blll, align 83742// CHECK-NEXT: [[TMP67:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 83743// CHECK-NEXT: [[CMP65:%.*]] = icmp ne <1 x i128> [[TMP66]], [[TMP67]]3744// CHECK-NEXT: [[SEXT66:%.*]] = sext <1 x i1> [[CMP65]] to <1 x i128>3745// CHECK-NEXT: store volatile <1 x i128> [[SEXT66]], ptr @blll, align 83746// CHECK-NEXT: [[TMP68:%.*]] = load volatile <1 x i128>, ptr @blll, align 83747// CHECK-NEXT: [[TMP69:%.*]] = load volatile <1 x i128>, ptr @blll2, align 83748// CHECK-NEXT: [[CMP67:%.*]] = icmp ne <1 x i128> [[TMP68]], [[TMP69]]3749// CHECK-NEXT: [[SEXT68:%.*]] = sext <1 x i1> [[CMP67]] to <1 x i128>3750// CHECK-NEXT: store volatile <1 x i128> [[SEXT68]], ptr @blll, align 83751// CHECK-NEXT: [[TMP70:%.*]] = load volatile <2 x double>, ptr @fd, align 83752// CHECK-NEXT: [[TMP71:%.*]] = load volatile <2 x double>, ptr @fd2, align 83753// CHECK-NEXT: [[CMP69:%.*]] = fcmp une <2 x double> [[TMP70]], [[TMP71]]3754// CHECK-NEXT: [[SEXT70:%.*]] = sext <2 x i1> [[CMP69]] to <2 x i64>3755// CHECK-NEXT: store volatile <2 x i64> [[SEXT70]], ptr @bl, align 83756// CHECK-NEXT: ret void3757//3758void test_cmpne(void) {3759 3760 bc = sc != sc2;3761 bc = sc != bc2;3762 bc = bc != sc2;3763 bc = uc != uc2;3764 bc = uc != bc2;3765 bc = bc != uc2;3766 bc = bc != bc2;3767 3768 bs = ss != ss2;3769 bs = ss != bs2;3770 bs = bs != ss2;3771 bs = us != us2;3772 bs = us != bs2;3773 bs = bs != us2;3774 bs = bs != bs2;3775 3776 bi = si != si2;3777 bi = si != bi2;3778 bi = bi != si2;3779 bi = ui != ui2;3780 bi = ui != bi2;3781 bi = bi != ui2;3782 bi = bi != bi2;3783 3784 bl = sl != sl2;3785 bl = sl != bl2;3786 bl = bl != sl2;3787 bl = ul != ul2;3788 bl = ul != bl2;3789 bl = bl != ul2;3790 bl = bl != bl2;3791 3792 blll = slll != slll2;3793 blll = slll != blll2;3794 blll = blll != slll2;3795 blll = ulll != ulll2;3796 blll = ulll != blll2;3797 blll = blll != ulll2;3798 blll = blll != blll2;3799 3800 bl = fd != fd2;3801}3802 3803// CHECK-LABEL: define dso_local void @test_cmpge(3804// CHECK-SAME: ) #[[ATTR0]] {3805// CHECK-NEXT: [[ENTRY:.*:]]3806// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 83807// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 83808// CHECK-NEXT: [[CMP:%.*]] = icmp sge <16 x i8> [[TMP0]], [[TMP1]]3809// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>3810// CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 83811// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 83812// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 83813// CHECK-NEXT: [[CMP1:%.*]] = icmp uge <16 x i8> [[TMP2]], [[TMP3]]3814// CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>3815// CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 83816// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 83817// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @bc2, align 83818// CHECK-NEXT: [[CMP3:%.*]] = icmp uge <16 x i8> [[TMP4]], [[TMP5]]3819// CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>3820// CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 83821// CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @ss, align 83822// CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @ss2, align 83823// CHECK-NEXT: [[CMP5:%.*]] = icmp sge <8 x i16> [[TMP6]], [[TMP7]]3824// CHECK-NEXT: [[SEXT6:%.*]] = sext <8 x i1> [[CMP5]] to <8 x i16>3825// CHECK-NEXT: store volatile <8 x i16> [[SEXT6]], ptr @bs, align 83826// CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @us, align 83827// CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @us2, align 83828// CHECK-NEXT: [[CMP7:%.*]] = icmp uge <8 x i16> [[TMP8]], [[TMP9]]3829// CHECK-NEXT: [[SEXT8:%.*]] = sext <8 x i1> [[CMP7]] to <8 x i16>3830// CHECK-NEXT: store volatile <8 x i16> [[SEXT8]], ptr @bs, align 83831// CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs, align 83832// CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @bs2, align 83833// CHECK-NEXT: [[CMP9:%.*]] = icmp uge <8 x i16> [[TMP10]], [[TMP11]]3834// CHECK-NEXT: [[SEXT10:%.*]] = sext <8 x i1> [[CMP9]] to <8 x i16>3835// CHECK-NEXT: store volatile <8 x i16> [[SEXT10]], ptr @bs, align 83836// CHECK-NEXT: [[TMP12:%.*]] = load volatile <4 x i32>, ptr @si, align 83837// CHECK-NEXT: [[TMP13:%.*]] = load volatile <4 x i32>, ptr @si2, align 83838// CHECK-NEXT: [[CMP11:%.*]] = icmp sge <4 x i32> [[TMP12]], [[TMP13]]3839// CHECK-NEXT: [[SEXT12:%.*]] = sext <4 x i1> [[CMP11]] to <4 x i32>3840// CHECK-NEXT: store volatile <4 x i32> [[SEXT12]], ptr @bi, align 83841// CHECK-NEXT: [[TMP14:%.*]] = load volatile <4 x i32>, ptr @ui, align 83842// CHECK-NEXT: [[TMP15:%.*]] = load volatile <4 x i32>, ptr @ui2, align 83843// CHECK-NEXT: [[CMP13:%.*]] = icmp uge <4 x i32> [[TMP14]], [[TMP15]]3844// CHECK-NEXT: [[SEXT14:%.*]] = sext <4 x i1> [[CMP13]] to <4 x i32>3845// CHECK-NEXT: store volatile <4 x i32> [[SEXT14]], ptr @bi, align 83846// CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @bi, align 83847// CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @bi2, align 83848// CHECK-NEXT: [[CMP15:%.*]] = icmp uge <4 x i32> [[TMP16]], [[TMP17]]3849// CHECK-NEXT: [[SEXT16:%.*]] = sext <4 x i1> [[CMP15]] to <4 x i32>3850// CHECK-NEXT: store volatile <4 x i32> [[SEXT16]], ptr @bi, align 83851// CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 83852// CHECK-NEXT: [[TMP19:%.*]] = load volatile <2 x i64>, ptr @sl2, align 83853// CHECK-NEXT: [[CMP17:%.*]] = icmp sge <2 x i64> [[TMP18]], [[TMP19]]3854// CHECK-NEXT: [[SEXT18:%.*]] = sext <2 x i1> [[CMP17]] to <2 x i64>3855// CHECK-NEXT: store volatile <2 x i64> [[SEXT18]], ptr @bl, align 83856// CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x i64>, ptr @ul, align 83857// CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x i64>, ptr @ul2, align 83858// CHECK-NEXT: [[CMP19:%.*]] = icmp uge <2 x i64> [[TMP20]], [[TMP21]]3859// CHECK-NEXT: [[SEXT20:%.*]] = sext <2 x i1> [[CMP19]] to <2 x i64>3860// CHECK-NEXT: store volatile <2 x i64> [[SEXT20]], ptr @bl, align 83861// CHECK-NEXT: [[TMP22:%.*]] = load volatile <2 x i64>, ptr @bl, align 83862// CHECK-NEXT: [[TMP23:%.*]] = load volatile <2 x i64>, ptr @bl2, align 83863// CHECK-NEXT: [[CMP21:%.*]] = icmp uge <2 x i64> [[TMP22]], [[TMP23]]3864// CHECK-NEXT: [[SEXT22:%.*]] = sext <2 x i1> [[CMP21]] to <2 x i64>3865// CHECK-NEXT: store volatile <2 x i64> [[SEXT22]], ptr @bl, align 83866// CHECK-NEXT: [[TMP24:%.*]] = load volatile <1 x i128>, ptr @slll, align 83867// CHECK-NEXT: [[TMP25:%.*]] = load volatile <1 x i128>, ptr @slll2, align 83868// CHECK-NEXT: [[CMP23:%.*]] = icmp sge <1 x i128> [[TMP24]], [[TMP25]]3869// CHECK-NEXT: [[SEXT24:%.*]] = sext <1 x i1> [[CMP23]] to <1 x i128>3870// CHECK-NEXT: store volatile <1 x i128> [[SEXT24]], ptr @blll, align 83871// CHECK-NEXT: [[TMP26:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83872// CHECK-NEXT: [[TMP27:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 83873// CHECK-NEXT: [[CMP25:%.*]] = icmp uge <1 x i128> [[TMP26]], [[TMP27]]3874// CHECK-NEXT: [[SEXT26:%.*]] = sext <1 x i1> [[CMP25]] to <1 x i128>3875// CHECK-NEXT: store volatile <1 x i128> [[SEXT26]], ptr @blll, align 83876// CHECK-NEXT: [[TMP28:%.*]] = load volatile <1 x i128>, ptr @blll, align 83877// CHECK-NEXT: [[TMP29:%.*]] = load volatile <1 x i128>, ptr @blll2, align 83878// CHECK-NEXT: [[CMP27:%.*]] = icmp uge <1 x i128> [[TMP28]], [[TMP29]]3879// CHECK-NEXT: [[SEXT28:%.*]] = sext <1 x i1> [[CMP27]] to <1 x i128>3880// CHECK-NEXT: store volatile <1 x i128> [[SEXT28]], ptr @blll, align 83881// CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x double>, ptr @fd, align 83882// CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x double>, ptr @fd2, align 83883// CHECK-NEXT: [[CMP29:%.*]] = fcmp oge <2 x double> [[TMP30]], [[TMP31]]3884// CHECK-NEXT: [[SEXT30:%.*]] = sext <2 x i1> [[CMP29]] to <2 x i64>3885// CHECK-NEXT: store volatile <2 x i64> [[SEXT30]], ptr @bl, align 83886// CHECK-NEXT: ret void3887//3888void test_cmpge(void) {3889 3890 bc = sc >= sc2;3891 bc = uc >= uc2;3892 bc = bc >= bc2;3893 3894 bs = ss >= ss2;3895 bs = us >= us2;3896 bs = bs >= bs2;3897 3898 bi = si >= si2;3899 bi = ui >= ui2;3900 bi = bi >= bi2;3901 3902 bl = sl >= sl2;3903 bl = ul >= ul2;3904 bl = bl >= bl2;3905 3906 blll = slll >= slll2;3907 blll = ulll >= ulll2;3908 blll = blll >= blll2;3909 3910 bl = fd >= fd2;3911}3912 3913// CHECK-LABEL: define dso_local void @test_cmpgt(3914// CHECK-SAME: ) #[[ATTR0]] {3915// CHECK-NEXT: [[ENTRY:.*:]]3916// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 83917// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 83918// CHECK-NEXT: [[CMP:%.*]] = icmp sgt <16 x i8> [[TMP0]], [[TMP1]]3919// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>3920// CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 83921// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 83922// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 83923// CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <16 x i8> [[TMP2]], [[TMP3]]3924// CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>3925// CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 83926// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 83927// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @bc2, align 83928// CHECK-NEXT: [[CMP3:%.*]] = icmp ugt <16 x i8> [[TMP4]], [[TMP5]]3929// CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>3930// CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 83931// CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @ss, align 83932// CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @ss2, align 83933// CHECK-NEXT: [[CMP5:%.*]] = icmp sgt <8 x i16> [[TMP6]], [[TMP7]]3934// CHECK-NEXT: [[SEXT6:%.*]] = sext <8 x i1> [[CMP5]] to <8 x i16>3935// CHECK-NEXT: store volatile <8 x i16> [[SEXT6]], ptr @bs, align 83936// CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @us, align 83937// CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @us2, align 83938// CHECK-NEXT: [[CMP7:%.*]] = icmp ugt <8 x i16> [[TMP8]], [[TMP9]]3939// CHECK-NEXT: [[SEXT8:%.*]] = sext <8 x i1> [[CMP7]] to <8 x i16>3940// CHECK-NEXT: store volatile <8 x i16> [[SEXT8]], ptr @bs, align 83941// CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs, align 83942// CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @bs2, align 83943// CHECK-NEXT: [[CMP9:%.*]] = icmp ugt <8 x i16> [[TMP10]], [[TMP11]]3944// CHECK-NEXT: [[SEXT10:%.*]] = sext <8 x i1> [[CMP9]] to <8 x i16>3945// CHECK-NEXT: store volatile <8 x i16> [[SEXT10]], ptr @bs, align 83946// CHECK-NEXT: [[TMP12:%.*]] = load volatile <4 x i32>, ptr @si, align 83947// CHECK-NEXT: [[TMP13:%.*]] = load volatile <4 x i32>, ptr @si2, align 83948// CHECK-NEXT: [[CMP11:%.*]] = icmp sgt <4 x i32> [[TMP12]], [[TMP13]]3949// CHECK-NEXT: [[SEXT12:%.*]] = sext <4 x i1> [[CMP11]] to <4 x i32>3950// CHECK-NEXT: store volatile <4 x i32> [[SEXT12]], ptr @bi, align 83951// CHECK-NEXT: [[TMP14:%.*]] = load volatile <4 x i32>, ptr @ui, align 83952// CHECK-NEXT: [[TMP15:%.*]] = load volatile <4 x i32>, ptr @ui2, align 83953// CHECK-NEXT: [[CMP13:%.*]] = icmp ugt <4 x i32> [[TMP14]], [[TMP15]]3954// CHECK-NEXT: [[SEXT14:%.*]] = sext <4 x i1> [[CMP13]] to <4 x i32>3955// CHECK-NEXT: store volatile <4 x i32> [[SEXT14]], ptr @bi, align 83956// CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @bi, align 83957// CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @bi2, align 83958// CHECK-NEXT: [[CMP15:%.*]] = icmp ugt <4 x i32> [[TMP16]], [[TMP17]]3959// CHECK-NEXT: [[SEXT16:%.*]] = sext <4 x i1> [[CMP15]] to <4 x i32>3960// CHECK-NEXT: store volatile <4 x i32> [[SEXT16]], ptr @bi, align 83961// CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 83962// CHECK-NEXT: [[TMP19:%.*]] = load volatile <2 x i64>, ptr @sl2, align 83963// CHECK-NEXT: [[CMP17:%.*]] = icmp sgt <2 x i64> [[TMP18]], [[TMP19]]3964// CHECK-NEXT: [[SEXT18:%.*]] = sext <2 x i1> [[CMP17]] to <2 x i64>3965// CHECK-NEXT: store volatile <2 x i64> [[SEXT18]], ptr @bl, align 83966// CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x i64>, ptr @ul, align 83967// CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x i64>, ptr @ul2, align 83968// CHECK-NEXT: [[CMP19:%.*]] = icmp ugt <2 x i64> [[TMP20]], [[TMP21]]3969// CHECK-NEXT: [[SEXT20:%.*]] = sext <2 x i1> [[CMP19]] to <2 x i64>3970// CHECK-NEXT: store volatile <2 x i64> [[SEXT20]], ptr @bl, align 83971// CHECK-NEXT: [[TMP22:%.*]] = load volatile <2 x i64>, ptr @bl, align 83972// CHECK-NEXT: [[TMP23:%.*]] = load volatile <2 x i64>, ptr @bl2, align 83973// CHECK-NEXT: [[CMP21:%.*]] = icmp ugt <2 x i64> [[TMP22]], [[TMP23]]3974// CHECK-NEXT: [[SEXT22:%.*]] = sext <2 x i1> [[CMP21]] to <2 x i64>3975// CHECK-NEXT: store volatile <2 x i64> [[SEXT22]], ptr @bl, align 83976// CHECK-NEXT: [[TMP24:%.*]] = load volatile <1 x i128>, ptr @slll, align 83977// CHECK-NEXT: [[TMP25:%.*]] = load volatile <1 x i128>, ptr @slll2, align 83978// CHECK-NEXT: [[CMP23:%.*]] = icmp sgt <1 x i128> [[TMP24]], [[TMP25]]3979// CHECK-NEXT: [[SEXT24:%.*]] = sext <1 x i1> [[CMP23]] to <1 x i128>3980// CHECK-NEXT: store volatile <1 x i128> [[SEXT24]], ptr @blll, align 83981// CHECK-NEXT: [[TMP26:%.*]] = load volatile <1 x i128>, ptr @ulll, align 83982// CHECK-NEXT: [[TMP27:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 83983// CHECK-NEXT: [[CMP25:%.*]] = icmp ugt <1 x i128> [[TMP26]], [[TMP27]]3984// CHECK-NEXT: [[SEXT26:%.*]] = sext <1 x i1> [[CMP25]] to <1 x i128>3985// CHECK-NEXT: store volatile <1 x i128> [[SEXT26]], ptr @blll, align 83986// CHECK-NEXT: [[TMP28:%.*]] = load volatile <1 x i128>, ptr @blll, align 83987// CHECK-NEXT: [[TMP29:%.*]] = load volatile <1 x i128>, ptr @blll2, align 83988// CHECK-NEXT: [[CMP27:%.*]] = icmp ugt <1 x i128> [[TMP28]], [[TMP29]]3989// CHECK-NEXT: [[SEXT28:%.*]] = sext <1 x i1> [[CMP27]] to <1 x i128>3990// CHECK-NEXT: store volatile <1 x i128> [[SEXT28]], ptr @blll, align 83991// CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x double>, ptr @fd, align 83992// CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x double>, ptr @fd2, align 83993// CHECK-NEXT: [[CMP29:%.*]] = fcmp ogt <2 x double> [[TMP30]], [[TMP31]]3994// CHECK-NEXT: [[SEXT30:%.*]] = sext <2 x i1> [[CMP29]] to <2 x i64>3995// CHECK-NEXT: store volatile <2 x i64> [[SEXT30]], ptr @bl, align 83996// CHECK-NEXT: ret void3997//3998void test_cmpgt(void) {3999 4000 bc = sc > sc2;4001 bc = uc > uc2;4002 bc = bc > bc2;4003 4004 bs = ss > ss2;4005 bs = us > us2;4006 bs = bs > bs2;4007 4008 bi = si > si2;4009 bi = ui > ui2;4010 bi = bi > bi2;4011 4012 bl = sl > sl2;4013 bl = ul > ul2;4014 bl = bl > bl2;4015 4016 blll = slll > slll2;4017 blll = ulll > ulll2;4018 blll = blll > blll2;4019 4020 bl = fd > fd2;4021}4022 4023// CHECK-LABEL: define dso_local void @test_cmple(4024// CHECK-SAME: ) #[[ATTR0]] {4025// CHECK-NEXT: [[ENTRY:.*:]]4026// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 84027// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 84028// CHECK-NEXT: [[CMP:%.*]] = icmp sle <16 x i8> [[TMP0]], [[TMP1]]4029// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>4030// CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 84031// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 84032// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 84033// CHECK-NEXT: [[CMP1:%.*]] = icmp ule <16 x i8> [[TMP2]], [[TMP3]]4034// CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>4035// CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 84036// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 84037// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @bc2, align 84038// CHECK-NEXT: [[CMP3:%.*]] = icmp ule <16 x i8> [[TMP4]], [[TMP5]]4039// CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>4040// CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 84041// CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @ss, align 84042// CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @ss2, align 84043// CHECK-NEXT: [[CMP5:%.*]] = icmp sle <8 x i16> [[TMP6]], [[TMP7]]4044// CHECK-NEXT: [[SEXT6:%.*]] = sext <8 x i1> [[CMP5]] to <8 x i16>4045// CHECK-NEXT: store volatile <8 x i16> [[SEXT6]], ptr @bs, align 84046// CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @us, align 84047// CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @us2, align 84048// CHECK-NEXT: [[CMP7:%.*]] = icmp ule <8 x i16> [[TMP8]], [[TMP9]]4049// CHECK-NEXT: [[SEXT8:%.*]] = sext <8 x i1> [[CMP7]] to <8 x i16>4050// CHECK-NEXT: store volatile <8 x i16> [[SEXT8]], ptr @bs, align 84051// CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs, align 84052// CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @bs2, align 84053// CHECK-NEXT: [[CMP9:%.*]] = icmp ule <8 x i16> [[TMP10]], [[TMP11]]4054// CHECK-NEXT: [[SEXT10:%.*]] = sext <8 x i1> [[CMP9]] to <8 x i16>4055// CHECK-NEXT: store volatile <8 x i16> [[SEXT10]], ptr @bs, align 84056// CHECK-NEXT: [[TMP12:%.*]] = load volatile <4 x i32>, ptr @si, align 84057// CHECK-NEXT: [[TMP13:%.*]] = load volatile <4 x i32>, ptr @si2, align 84058// CHECK-NEXT: [[CMP11:%.*]] = icmp sle <4 x i32> [[TMP12]], [[TMP13]]4059// CHECK-NEXT: [[SEXT12:%.*]] = sext <4 x i1> [[CMP11]] to <4 x i32>4060// CHECK-NEXT: store volatile <4 x i32> [[SEXT12]], ptr @bi, align 84061// CHECK-NEXT: [[TMP14:%.*]] = load volatile <4 x i32>, ptr @ui, align 84062// CHECK-NEXT: [[TMP15:%.*]] = load volatile <4 x i32>, ptr @ui2, align 84063// CHECK-NEXT: [[CMP13:%.*]] = icmp ule <4 x i32> [[TMP14]], [[TMP15]]4064// CHECK-NEXT: [[SEXT14:%.*]] = sext <4 x i1> [[CMP13]] to <4 x i32>4065// CHECK-NEXT: store volatile <4 x i32> [[SEXT14]], ptr @bi, align 84066// CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @bi, align 84067// CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @bi2, align 84068// CHECK-NEXT: [[CMP15:%.*]] = icmp ule <4 x i32> [[TMP16]], [[TMP17]]4069// CHECK-NEXT: [[SEXT16:%.*]] = sext <4 x i1> [[CMP15]] to <4 x i32>4070// CHECK-NEXT: store volatile <4 x i32> [[SEXT16]], ptr @bi, align 84071// CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 84072// CHECK-NEXT: [[TMP19:%.*]] = load volatile <2 x i64>, ptr @sl2, align 84073// CHECK-NEXT: [[CMP17:%.*]] = icmp sle <2 x i64> [[TMP18]], [[TMP19]]4074// CHECK-NEXT: [[SEXT18:%.*]] = sext <2 x i1> [[CMP17]] to <2 x i64>4075// CHECK-NEXT: store volatile <2 x i64> [[SEXT18]], ptr @bl, align 84076// CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x i64>, ptr @ul, align 84077// CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x i64>, ptr @ul2, align 84078// CHECK-NEXT: [[CMP19:%.*]] = icmp ule <2 x i64> [[TMP20]], [[TMP21]]4079// CHECK-NEXT: [[SEXT20:%.*]] = sext <2 x i1> [[CMP19]] to <2 x i64>4080// CHECK-NEXT: store volatile <2 x i64> [[SEXT20]], ptr @bl, align 84081// CHECK-NEXT: [[TMP22:%.*]] = load volatile <2 x i64>, ptr @bl, align 84082// CHECK-NEXT: [[TMP23:%.*]] = load volatile <2 x i64>, ptr @bl2, align 84083// CHECK-NEXT: [[CMP21:%.*]] = icmp ule <2 x i64> [[TMP22]], [[TMP23]]4084// CHECK-NEXT: [[SEXT22:%.*]] = sext <2 x i1> [[CMP21]] to <2 x i64>4085// CHECK-NEXT: store volatile <2 x i64> [[SEXT22]], ptr @bl, align 84086// CHECK-NEXT: [[TMP24:%.*]] = load volatile <1 x i128>, ptr @slll, align 84087// CHECK-NEXT: [[TMP25:%.*]] = load volatile <1 x i128>, ptr @slll2, align 84088// CHECK-NEXT: [[CMP23:%.*]] = icmp sle <1 x i128> [[TMP24]], [[TMP25]]4089// CHECK-NEXT: [[SEXT24:%.*]] = sext <1 x i1> [[CMP23]] to <1 x i128>4090// CHECK-NEXT: store volatile <1 x i128> [[SEXT24]], ptr @blll, align 84091// CHECK-NEXT: [[TMP26:%.*]] = load volatile <1 x i128>, ptr @ulll, align 84092// CHECK-NEXT: [[TMP27:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 84093// CHECK-NEXT: [[CMP25:%.*]] = icmp ule <1 x i128> [[TMP26]], [[TMP27]]4094// CHECK-NEXT: [[SEXT26:%.*]] = sext <1 x i1> [[CMP25]] to <1 x i128>4095// CHECK-NEXT: store volatile <1 x i128> [[SEXT26]], ptr @blll, align 84096// CHECK-NEXT: [[TMP28:%.*]] = load volatile <1 x i128>, ptr @blll, align 84097// CHECK-NEXT: [[TMP29:%.*]] = load volatile <1 x i128>, ptr @blll2, align 84098// CHECK-NEXT: [[CMP27:%.*]] = icmp ule <1 x i128> [[TMP28]], [[TMP29]]4099// CHECK-NEXT: [[SEXT28:%.*]] = sext <1 x i1> [[CMP27]] to <1 x i128>4100// CHECK-NEXT: store volatile <1 x i128> [[SEXT28]], ptr @blll, align 84101// CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x double>, ptr @fd, align 84102// CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x double>, ptr @fd2, align 84103// CHECK-NEXT: [[CMP29:%.*]] = fcmp ole <2 x double> [[TMP30]], [[TMP31]]4104// CHECK-NEXT: [[SEXT30:%.*]] = sext <2 x i1> [[CMP29]] to <2 x i64>4105// CHECK-NEXT: store volatile <2 x i64> [[SEXT30]], ptr @bl, align 84106// CHECK-NEXT: ret void4107//4108void test_cmple(void) {4109 4110 bc = sc <= sc2;4111 bc = uc <= uc2;4112 bc = bc <= bc2;4113 4114 bs = ss <= ss2;4115 bs = us <= us2;4116 bs = bs <= bs2;4117 4118 bi = si <= si2;4119 bi = ui <= ui2;4120 bi = bi <= bi2;4121 4122 bl = sl <= sl2;4123 bl = ul <= ul2;4124 bl = bl <= bl2;4125 4126 blll = slll <= slll2;4127 blll = ulll <= ulll2;4128 blll = blll <= blll2;4129 4130 bl = fd <= fd2;4131}4132 4133// CHECK-LABEL: define dso_local void @test_cmplt(4134// CHECK-SAME: ) #[[ATTR0]] {4135// CHECK-NEXT: [[ENTRY:.*:]]4136// CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 84137// CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 84138// CHECK-NEXT: [[CMP:%.*]] = icmp slt <16 x i8> [[TMP0]], [[TMP1]]4139// CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>4140// CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 84141// CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 84142// CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 84143// CHECK-NEXT: [[CMP1:%.*]] = icmp ult <16 x i8> [[TMP2]], [[TMP3]]4144// CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>4145// CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 84146// CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 84147// CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @bc2, align 84148// CHECK-NEXT: [[CMP3:%.*]] = icmp ult <16 x i8> [[TMP4]], [[TMP5]]4149// CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>4150// CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 84151// CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @ss, align 84152// CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @ss2, align 84153// CHECK-NEXT: [[CMP5:%.*]] = icmp slt <8 x i16> [[TMP6]], [[TMP7]]4154// CHECK-NEXT: [[SEXT6:%.*]] = sext <8 x i1> [[CMP5]] to <8 x i16>4155// CHECK-NEXT: store volatile <8 x i16> [[SEXT6]], ptr @bs, align 84156// CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @us, align 84157// CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @us2, align 84158// CHECK-NEXT: [[CMP7:%.*]] = icmp ult <8 x i16> [[TMP8]], [[TMP9]]4159// CHECK-NEXT: [[SEXT8:%.*]] = sext <8 x i1> [[CMP7]] to <8 x i16>4160// CHECK-NEXT: store volatile <8 x i16> [[SEXT8]], ptr @bs, align 84161// CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs, align 84162// CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @bs2, align 84163// CHECK-NEXT: [[CMP9:%.*]] = icmp ult <8 x i16> [[TMP10]], [[TMP11]]4164// CHECK-NEXT: [[SEXT10:%.*]] = sext <8 x i1> [[CMP9]] to <8 x i16>4165// CHECK-NEXT: store volatile <8 x i16> [[SEXT10]], ptr @bs, align 84166// CHECK-NEXT: [[TMP12:%.*]] = load volatile <4 x i32>, ptr @si, align 84167// CHECK-NEXT: [[TMP13:%.*]] = load volatile <4 x i32>, ptr @si2, align 84168// CHECK-NEXT: [[CMP11:%.*]] = icmp slt <4 x i32> [[TMP12]], [[TMP13]]4169// CHECK-NEXT: [[SEXT12:%.*]] = sext <4 x i1> [[CMP11]] to <4 x i32>4170// CHECK-NEXT: store volatile <4 x i32> [[SEXT12]], ptr @bi, align 84171// CHECK-NEXT: [[TMP14:%.*]] = load volatile <4 x i32>, ptr @ui, align 84172// CHECK-NEXT: [[TMP15:%.*]] = load volatile <4 x i32>, ptr @ui2, align 84173// CHECK-NEXT: [[CMP13:%.*]] = icmp ult <4 x i32> [[TMP14]], [[TMP15]]4174// CHECK-NEXT: [[SEXT14:%.*]] = sext <4 x i1> [[CMP13]] to <4 x i32>4175// CHECK-NEXT: store volatile <4 x i32> [[SEXT14]], ptr @bi, align 84176// CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @bi, align 84177// CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @bi2, align 84178// CHECK-NEXT: [[CMP15:%.*]] = icmp ult <4 x i32> [[TMP16]], [[TMP17]]4179// CHECK-NEXT: [[SEXT16:%.*]] = sext <4 x i1> [[CMP15]] to <4 x i32>4180// CHECK-NEXT: store volatile <4 x i32> [[SEXT16]], ptr @bi, align 84181// CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 84182// CHECK-NEXT: [[TMP19:%.*]] = load volatile <2 x i64>, ptr @sl2, align 84183// CHECK-NEXT: [[CMP17:%.*]] = icmp slt <2 x i64> [[TMP18]], [[TMP19]]4184// CHECK-NEXT: [[SEXT18:%.*]] = sext <2 x i1> [[CMP17]] to <2 x i64>4185// CHECK-NEXT: store volatile <2 x i64> [[SEXT18]], ptr @bl, align 84186// CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x i64>, ptr @ul, align 84187// CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x i64>, ptr @ul2, align 84188// CHECK-NEXT: [[CMP19:%.*]] = icmp ult <2 x i64> [[TMP20]], [[TMP21]]4189// CHECK-NEXT: [[SEXT20:%.*]] = sext <2 x i1> [[CMP19]] to <2 x i64>4190// CHECK-NEXT: store volatile <2 x i64> [[SEXT20]], ptr @bl, align 84191// CHECK-NEXT: [[TMP22:%.*]] = load volatile <2 x i64>, ptr @bl, align 84192// CHECK-NEXT: [[TMP23:%.*]] = load volatile <2 x i64>, ptr @bl2, align 84193// CHECK-NEXT: [[CMP21:%.*]] = icmp ult <2 x i64> [[TMP22]], [[TMP23]]4194// CHECK-NEXT: [[SEXT22:%.*]] = sext <2 x i1> [[CMP21]] to <2 x i64>4195// CHECK-NEXT: store volatile <2 x i64> [[SEXT22]], ptr @bl, align 84196// CHECK-NEXT: [[TMP24:%.*]] = load volatile <1 x i128>, ptr @slll, align 84197// CHECK-NEXT: [[TMP25:%.*]] = load volatile <1 x i128>, ptr @slll2, align 84198// CHECK-NEXT: [[CMP23:%.*]] = icmp slt <1 x i128> [[TMP24]], [[TMP25]]4199// CHECK-NEXT: [[SEXT24:%.*]] = sext <1 x i1> [[CMP23]] to <1 x i128>4200// CHECK-NEXT: store volatile <1 x i128> [[SEXT24]], ptr @blll, align 84201// CHECK-NEXT: [[TMP26:%.*]] = load volatile <1 x i128>, ptr @ulll, align 84202// CHECK-NEXT: [[TMP27:%.*]] = load volatile <1 x i128>, ptr @ulll2, align 84203// CHECK-NEXT: [[CMP25:%.*]] = icmp ult <1 x i128> [[TMP26]], [[TMP27]]4204// CHECK-NEXT: [[SEXT26:%.*]] = sext <1 x i1> [[CMP25]] to <1 x i128>4205// CHECK-NEXT: store volatile <1 x i128> [[SEXT26]], ptr @blll, align 84206// CHECK-NEXT: [[TMP28:%.*]] = load volatile <1 x i128>, ptr @blll, align 84207// CHECK-NEXT: [[TMP29:%.*]] = load volatile <1 x i128>, ptr @blll2, align 84208// CHECK-NEXT: [[CMP27:%.*]] = icmp ult <1 x i128> [[TMP28]], [[TMP29]]4209// CHECK-NEXT: [[SEXT28:%.*]] = sext <1 x i1> [[CMP27]] to <1 x i128>4210// CHECK-NEXT: store volatile <1 x i128> [[SEXT28]], ptr @blll, align 84211// CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x double>, ptr @fd, align 84212// CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x double>, ptr @fd2, align 84213// CHECK-NEXT: [[CMP29:%.*]] = fcmp olt <2 x double> [[TMP30]], [[TMP31]]4214// CHECK-NEXT: [[SEXT30:%.*]] = sext <2 x i1> [[CMP29]] to <2 x i64>4215// CHECK-NEXT: store volatile <2 x i64> [[SEXT30]], ptr @bl, align 84216// CHECK-NEXT: ret void4217//4218void test_cmplt(void) {4219 4220 bc = sc < sc2;4221 bc = uc < uc2;4222 bc = bc < bc2;4223 4224 bs = ss < ss2;4225 bs = us < us2;4226 bs = bs < bs2;4227 4228 bi = si < si2;4229 bi = ui < ui2;4230 bi = bi < bi2;4231 4232 bl = sl < sl2;4233 bl = ul < ul2;4234 bl = bl < bl2;4235 4236 blll = slll < slll2;4237 blll = ulll < ulll2;4238 blll = blll < blll2;4239 4240 bl = fd < fd2;4241}4242 4243