533 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -triple x86_64-linux-gnu -target-cpu core2 %s -emit-llvm -o - | FileCheck --check-prefixes=X64 %s3// RUN: %clang_cc1 -triple i686-linux-gnu -target-cpu core2 %s -emit-llvm -o - | FileCheck --check-prefixes=X86 %s4 5// X64-LABEL: define dso_local x86_fp80 @testinc(6// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0:[0-9]+]] {7// X64-NEXT: [[ENTRY:.*]]:8// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 89// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 1610// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 1611// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 1612// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 1613// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 814// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 815// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i128, ptr [[TMP0]] seq_cst, align 1616// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 1617// X64-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 1618// X64-NEXT: br label %[[ATOMIC_OP:.*]]19// X64: [[ATOMIC_OP]]:20// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]21// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF800000000000000022// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)23// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 1624// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 1625// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)26// X64-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 1627// X64-NEXT: [[TMP4:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 1628// X64-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[TMP0]], i128 [[TMP3]], i128 [[TMP4]] seq_cst seq_cst, align 1629// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP5]], 030// X64-NEXT: [[TMP7:%.*]] = extractvalue { i128, i1 } [[TMP5]], 131// X64-NEXT: store i128 [[TMP6]], ptr [[ATOMIC_TEMP3]], align 1632// X64-NEXT: [[TMP8]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 1633// X64-NEXT: br i1 [[TMP7]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]34// X64: [[ATOMIC_CONT]]:35// X64-NEXT: ret x86_fp80 [[INC]]36//37// X86-LABEL: define dso_local x86_fp80 @testinc(38// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0:[0-9]+]] {39// X86-NEXT: [[ENTRY:.*]]:40// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 441// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 442// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 443// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 444// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 445// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 446// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)47// X86-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 448// X86-NEXT: br label %[[ATOMIC_OP:.*]]49// X86: [[ATOMIC_OP]]:50// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]51// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF800000000000000052// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)53// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 454// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)55// X86-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 456// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)57// X86-NEXT: [[TMP3]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 458// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]59// X86: [[ATOMIC_CONT]]:60// X86-NEXT: ret x86_fp80 [[INC]]61//62long double testinc(_Atomic long double *addr) {63 64 return ++*addr;65}66 67// X64-LABEL: define dso_local x86_fp80 @testdec(68// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {69// X64-NEXT: [[ENTRY:.*]]:70// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 871// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 1672// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 1673// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 1674// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 1675// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 876// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 877// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i128, ptr [[TMP0]] seq_cst, align 1678// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 1679// X64-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 1680// X64-NEXT: br label %[[ATOMIC_OP:.*]]81// X64: [[ATOMIC_OP]]:82// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]83// X64-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF800000000000000084// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)85// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 1686// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 1687// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)88// X64-NEXT: store x86_fp80 [[DEC]], ptr [[ATOMIC_TEMP2]], align 1689// X64-NEXT: [[TMP4:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 1690// X64-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[TMP0]], i128 [[TMP3]], i128 [[TMP4]] seq_cst seq_cst, align 1691// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP5]], 092// X64-NEXT: [[TMP7:%.*]] = extractvalue { i128, i1 } [[TMP5]], 193// X64-NEXT: store i128 [[TMP6]], ptr [[ATOMIC_TEMP3]], align 1694// X64-NEXT: [[TMP8]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 1695// X64-NEXT: br i1 [[TMP7]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]96// X64: [[ATOMIC_CONT]]:97// X64-NEXT: ret x86_fp80 [[TMP1]]98//99// X86-LABEL: define dso_local x86_fp80 @testdec(100// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {101// X86-NEXT: [[ENTRY:.*]]:102// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4103// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4104// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4105// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4106// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4107// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4108// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)109// X86-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4110// X86-NEXT: br label %[[ATOMIC_OP:.*]]111// X86: [[ATOMIC_OP]]:112// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]113// X86-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000114// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)115// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4116// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)117// X86-NEXT: store x86_fp80 [[DEC]], ptr [[ATOMIC_TEMP2]], align 4118// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)119// X86-NEXT: [[TMP3]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4120// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]121// X86: [[ATOMIC_CONT]]:122// X86-NEXT: ret x86_fp80 [[TMP1]]123//124long double testdec(_Atomic long double *addr) {125 126 return (*addr)--;127}128 129// X64-LABEL: define dso_local x86_fp80 @testcompassign(130// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {131// X64-NEXT: [[ENTRY:.*]]:132// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8133// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16134// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16135// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 16136// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 16137// X64-NEXT: [[ATOMIC_TEMP5:%.*]] = alloca x86_fp80, align 16138// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8139// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8140// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i128, ptr [[TMP0]] seq_cst, align 16141// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 16142// X64-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 16143// X64-NEXT: br label %[[ATOMIC_OP:.*]]144// X64: [[ATOMIC_OP]]:145// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]146// X64-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 0xK4003C800000000000000147// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)148// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16149// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16150// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)151// X64-NEXT: store x86_fp80 [[SUB]], ptr [[ATOMIC_TEMP2]], align 16152// X64-NEXT: [[TMP4:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 16153// X64-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[TMP0]], i128 [[TMP3]], i128 [[TMP4]] seq_cst seq_cst, align 16154// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP5]], 0155// X64-NEXT: [[TMP7:%.*]] = extractvalue { i128, i1 } [[TMP5]], 1156// X64-NEXT: store i128 [[TMP6]], ptr [[ATOMIC_TEMP3]], align 16157// X64-NEXT: [[TMP8]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16158// X64-NEXT: br i1 [[TMP7]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]159// X64: [[ATOMIC_CONT]]:160// X64-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8161// X64-NEXT: [[ATOMIC_LOAD4:%.*]] = load atomic i128, ptr [[TMP9]] seq_cst, align 16162// X64-NEXT: store i128 [[ATOMIC_LOAD4]], ptr [[ATOMIC_TEMP5]], align 16163// X64-NEXT: [[TMP10:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP5]], align 16164// X64-NEXT: ret x86_fp80 [[TMP10]]165//166// X86-LABEL: define dso_local x86_fp80 @testcompassign(167// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {168// X86-NEXT: [[ENTRY:.*]]:169// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4170// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4171// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4172// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4173// X86-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 4174// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4175// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4176// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)177// X86-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4178// X86-NEXT: br label %[[ATOMIC_OP:.*]]179// X86: [[ATOMIC_OP]]:180// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]181// X86-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 0xK4003C800000000000000182// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)183// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4184// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)185// X86-NEXT: store x86_fp80 [[SUB]], ptr [[ATOMIC_TEMP2]], align 4186// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)187// X86-NEXT: [[TMP3]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4188// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]189// X86: [[ATOMIC_CONT]]:190// X86-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4191// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP4]], ptr noundef [[ATOMIC_TEMP3]], i32 noundef 5)192// X86-NEXT: [[TMP5:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 4193// X86-NEXT: ret x86_fp80 [[TMP5]]194//195long double testcompassign(_Atomic long double *addr) {196 *addr -= 25;197 return *addr;198}199 200// X64-LABEL: define dso_local x86_fp80 @testassign(201// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {202// X64-NEXT: [[ENTRY:.*:]]203// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8204// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16205// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16206// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8207// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8208// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP]], i8 0, i64 16, i1 false)209// X64-NEXT: store x86_fp80 0xK4005E600000000000000, ptr [[ATOMIC_TEMP]], align 16210// X64-NEXT: [[TMP1:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 16211// X64-NEXT: store atomic i128 [[TMP1]], ptr [[TMP0]] seq_cst, align 16212// X64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8213// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i128, ptr [[TMP2]] seq_cst, align 16214// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP1]], align 16215// X64-NEXT: [[TMP3:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 16216// X64-NEXT: ret x86_fp80 [[TMP3]]217//218// X86-LABEL: define dso_local x86_fp80 @testassign(219// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {220// X86-NEXT: [[ENTRY:.*:]]221// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4222// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4223// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4224// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4225// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4226// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP]], i8 0, i64 12, i1 false)227// X86-NEXT: store x86_fp80 0xK4005E600000000000000, ptr [[ATOMIC_TEMP]], align 4228// X86-NEXT: call void @__atomic_store(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)229// X86-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4230// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP1]], i32 noundef 5)231// X86-NEXT: [[TMP2:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4232// X86-NEXT: ret x86_fp80 [[TMP2]]233//234long double testassign(_Atomic long double *addr) {235 *addr = 115;236 237 return *addr;238}239 240// X64-LABEL: define dso_local x86_fp80 @test_volatile_inc(241// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {242// X64-NEXT: [[ENTRY:.*]]:243// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8244// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16245// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16246// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 16247// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 16248// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8249// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8250// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic volatile i128, ptr [[TMP0]] seq_cst, align 16251// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 16252// X64-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 16253// X64-NEXT: br label %[[ATOMIC_OP:.*]]254// X64: [[ATOMIC_OP]]:255// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]256// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF8000000000000000257// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)258// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16259// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16260// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)261// X64-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 16262// X64-NEXT: [[TMP4:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 16263// X64-NEXT: [[TMP5:%.*]] = cmpxchg volatile ptr [[TMP0]], i128 [[TMP3]], i128 [[TMP4]] seq_cst seq_cst, align 16264// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP5]], 0265// X64-NEXT: [[TMP7:%.*]] = extractvalue { i128, i1 } [[TMP5]], 1266// X64-NEXT: store i128 [[TMP6]], ptr [[ATOMIC_TEMP3]], align 16267// X64-NEXT: [[TMP8]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16268// X64-NEXT: br i1 [[TMP7]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]269// X64: [[ATOMIC_CONT]]:270// X64-NEXT: ret x86_fp80 [[INC]]271//272// X86-LABEL: define dso_local x86_fp80 @test_volatile_inc(273// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {274// X86-NEXT: [[ENTRY:.*]]:275// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4276// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4277// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4278// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4279// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4280// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4281// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)282// X86-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4283// X86-NEXT: br label %[[ATOMIC_OP:.*]]284// X86: [[ATOMIC_OP]]:285// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]286// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF8000000000000000287// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)288// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4289// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)290// X86-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 4291// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)292// X86-NEXT: [[TMP3]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4293// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]294// X86: [[ATOMIC_CONT]]:295// X86-NEXT: ret x86_fp80 [[INC]]296//297long double test_volatile_inc(volatile _Atomic long double *addr) {298 return ++*addr;299}300 301// X64-LABEL: define dso_local x86_fp80 @test_volatile_dec(302// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {303// X64-NEXT: [[ENTRY:.*]]:304// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8305// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16306// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16307// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 16308// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 16309// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8310// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8311// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic volatile i128, ptr [[TMP0]] seq_cst, align 16312// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 16313// X64-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 16314// X64-NEXT: br label %[[ATOMIC_OP:.*]]315// X64: [[ATOMIC_OP]]:316// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]317// X64-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000318// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)319// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16320// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16321// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)322// X64-NEXT: store x86_fp80 [[DEC]], ptr [[ATOMIC_TEMP2]], align 16323// X64-NEXT: [[TMP4:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 16324// X64-NEXT: [[TMP5:%.*]] = cmpxchg volatile ptr [[TMP0]], i128 [[TMP3]], i128 [[TMP4]] seq_cst seq_cst, align 16325// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP5]], 0326// X64-NEXT: [[TMP7:%.*]] = extractvalue { i128, i1 } [[TMP5]], 1327// X64-NEXT: store i128 [[TMP6]], ptr [[ATOMIC_TEMP3]], align 16328// X64-NEXT: [[TMP8]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16329// X64-NEXT: br i1 [[TMP7]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]330// X64: [[ATOMIC_CONT]]:331// X64-NEXT: ret x86_fp80 [[TMP1]]332//333// X86-LABEL: define dso_local x86_fp80 @test_volatile_dec(334// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {335// X86-NEXT: [[ENTRY:.*]]:336// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4337// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4338// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4339// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4340// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4341// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4342// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)343// X86-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4344// X86-NEXT: br label %[[ATOMIC_OP:.*]]345// X86: [[ATOMIC_OP]]:346// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]347// X86-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000348// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)349// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4350// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)351// X86-NEXT: store x86_fp80 [[DEC]], ptr [[ATOMIC_TEMP2]], align 4352// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)353// X86-NEXT: [[TMP3]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4354// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]355// X86: [[ATOMIC_CONT]]:356// X86-NEXT: ret x86_fp80 [[TMP1]]357//358long double test_volatile_dec(volatile _Atomic long double *addr) {359 return (*addr)--;360}361 362// X64-LABEL: define dso_local x86_fp80 @test_volatile_compassign(363// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {364// X64-NEXT: [[ENTRY:.*]]:365// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8366// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16367// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16368// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 16369// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 16370// X64-NEXT: [[ATOMIC_TEMP5:%.*]] = alloca x86_fp80, align 16371// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8372// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8373// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic volatile i128, ptr [[TMP0]] seq_cst, align 16374// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 16375// X64-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 16376// X64-NEXT: br label %[[ATOMIC_OP:.*]]377// X64: [[ATOMIC_OP]]:378// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]379// X64-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 0xK4003C800000000000000380// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)381// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16382// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16383// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)384// X64-NEXT: store x86_fp80 [[SUB]], ptr [[ATOMIC_TEMP2]], align 16385// X64-NEXT: [[TMP4:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 16386// X64-NEXT: [[TMP5:%.*]] = cmpxchg volatile ptr [[TMP0]], i128 [[TMP3]], i128 [[TMP4]] seq_cst seq_cst, align 16387// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP5]], 0388// X64-NEXT: [[TMP7:%.*]] = extractvalue { i128, i1 } [[TMP5]], 1389// X64-NEXT: store i128 [[TMP6]], ptr [[ATOMIC_TEMP3]], align 16390// X64-NEXT: [[TMP8]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16391// X64-NEXT: br i1 [[TMP7]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]392// X64: [[ATOMIC_CONT]]:393// X64-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8394// X64-NEXT: [[ATOMIC_LOAD4:%.*]] = load atomic volatile i128, ptr [[TMP9]] seq_cst, align 16395// X64-NEXT: store i128 [[ATOMIC_LOAD4]], ptr [[ATOMIC_TEMP5]], align 16396// X64-NEXT: [[TMP10:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP5]], align 16397// X64-NEXT: ret x86_fp80 [[TMP10]]398//399// X86-LABEL: define dso_local x86_fp80 @test_volatile_compassign(400// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {401// X86-NEXT: [[ENTRY:.*]]:402// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4403// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4404// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4405// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4406// X86-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 4407// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4408// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4409// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)410// X86-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4411// X86-NEXT: br label %[[ATOMIC_OP:.*]]412// X86: [[ATOMIC_OP]]:413// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]414// X86-NEXT: [[SUB:%.*]] = fsub x86_fp80 [[TMP2]], 0xK4003C800000000000000415// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)416// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4417// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)418// X86-NEXT: store x86_fp80 [[SUB]], ptr [[ATOMIC_TEMP2]], align 4419// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)420// X86-NEXT: [[TMP3]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4421// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]422// X86: [[ATOMIC_CONT]]:423// X86-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4424// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP4]], ptr noundef [[ATOMIC_TEMP3]], i32 noundef 5)425// X86-NEXT: [[TMP5:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 4426// X86-NEXT: ret x86_fp80 [[TMP5]]427//428long double test_volatile_compassign(volatile _Atomic long double *addr) {429 *addr -= 25;430 return *addr;431}432 433// X64-LABEL: define dso_local x86_fp80 @test_volatile_assign(434// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {435// X64-NEXT: [[ENTRY:.*:]]436// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8437// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16438// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16439// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8440// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8441// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP]], i8 0, i64 16, i1 false)442// X64-NEXT: store x86_fp80 0xK4005E600000000000000, ptr [[ATOMIC_TEMP]], align 16443// X64-NEXT: [[TMP1:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 16444// X64-NEXT: store atomic volatile i128 [[TMP1]], ptr [[TMP0]] seq_cst, align 16445// X64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8446// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic volatile i128, ptr [[TMP2]] seq_cst, align 16447// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP1]], align 16448// X64-NEXT: [[TMP3:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 16449// X64-NEXT: ret x86_fp80 [[TMP3]]450//451// X86-LABEL: define dso_local x86_fp80 @test_volatile_assign(452// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {453// X86-NEXT: [[ENTRY:.*:]]454// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4455// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4456// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4457// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4458// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4459// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP]], i8 0, i64 12, i1 false)460// X86-NEXT: store x86_fp80 0xK4005E600000000000000, ptr [[ATOMIC_TEMP]], align 4461// X86-NEXT: call void @__atomic_store(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)462// X86-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4463// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP1]], ptr noundef [[ATOMIC_TEMP1]], i32 noundef 5)464// X86-NEXT: [[TMP2:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4465// X86-NEXT: ret x86_fp80 [[TMP2]]466//467long double test_volatile_assign(volatile _Atomic long double *addr) {468 *addr = 115;469 470 return *addr;471}472 473// X64-LABEL: define dso_local i32 @pr107054(474// X64-SAME: ) #[[ATTR0]] {475// X64-NEXT: [[ENTRY:.*]]:476// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16477// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16478// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 16479// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 16480// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i128, ptr @pr107054.n seq_cst, align 16481// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 16482// X64-NEXT: [[TMP0:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 16483// X64-NEXT: br label %[[ATOMIC_OP:.*]]484// X64: [[ATOMIC_OP]]:485// X64-NEXT: [[TMP1:%.*]] = phi x86_fp80 [ [[TMP0]], %[[ENTRY]] ], [ [[TMP7:%.*]], %[[ATOMIC_OP]] ]486// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP1]], 0xK3FFF8000000000000000487// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)488// X64-NEXT: store x86_fp80 [[TMP1]], ptr [[ATOMIC_TEMP1]], align 16489// X64-NEXT: [[TMP2:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16490// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)491// X64-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 16492// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 16493// X64-NEXT: [[TMP4:%.*]] = cmpxchg ptr @pr107054.n, i128 [[TMP2]], i128 [[TMP3]] seq_cst seq_cst, align 16494// X64-NEXT: [[TMP5:%.*]] = extractvalue { i128, i1 } [[TMP4]], 0495// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP4]], 1496// X64-NEXT: store i128 [[TMP5]], ptr [[ATOMIC_TEMP3]], align 16497// X64-NEXT: [[TMP7]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16498// X64-NEXT: br i1 [[TMP6]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]499// X64: [[ATOMIC_CONT]]:500// X64-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[INC]], 0xK3FFF8000000000000000501// X64-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32502// X64-NEXT: ret i32 [[CONV]]503//504// X86-LABEL: define dso_local i32 @pr107054(505// X86-SAME: ) #[[ATTR0]] {506// X86-NEXT: [[ENTRY:.*]]:507// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4508// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4509// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4510// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef @pr107054.n, ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)511// X86-NEXT: [[TMP0:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4512// X86-NEXT: br label %[[ATOMIC_OP:.*]]513// X86: [[ATOMIC_OP]]:514// X86-NEXT: [[TMP1:%.*]] = phi x86_fp80 [ [[TMP0]], %[[ENTRY]] ], [ [[TMP2:%.*]], %[[ATOMIC_OP]] ]515// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP1]], 0xK3FFF8000000000000000516// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)517// X86-NEXT: store x86_fp80 [[TMP1]], ptr [[ATOMIC_TEMP1]], align 4518// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)519// X86-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 4520// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef @pr107054.n, ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)521// X86-NEXT: [[TMP2]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4522// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]523// X86: [[ATOMIC_CONT]]:524// X86-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[INC]], 0xK3FFF8000000000000000525// X86-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32526// X86-NEXT: ret i32 [[CONV]]527//528int pr107054()529{530 static _Atomic long double n;531 return (++n) == 1;532}533