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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple x86_64-pc-linux -emit-llvm -o - %s | FileCheck %s3 4__INT32_TYPE__*m1(__INT32_TYPE__ i) __attribute__((alloc_align(1)));5 6// Condition where parameter to m1 is not size_t.7// CHECK-LABEL: @test1(8// CHECK-NEXT: entry:9// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 410// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 411// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 412// CHECK-NEXT: [[CALL:%.*]] = call ptr @m1(i32 noundef [[TMP0]])13// CHECK-NEXT: [[CASTED_ALIGN:%.*]] = zext i32 [[TMP0]] to i6414// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[CALL]], i64 [[CASTED_ALIGN]]) ]15// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[CALL]], align 416// CHECK-NEXT: ret i32 [[TMP1]]17//18__INT32_TYPE__ test1(__INT32_TYPE__ a) {19 return *m1(a);20}21// Condition where test2 param needs casting.22// CHECK-LABEL: @test2(23// CHECK-NEXT: entry:24// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 825// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 826// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 827// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i3228// CHECK-NEXT: [[CALL:%.*]] = call ptr @m1(i32 noundef [[CONV]])29// CHECK-NEXT: [[CASTED_ALIGN:%.*]] = zext i32 [[CONV]] to i6430// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[CALL]], i64 [[CASTED_ALIGN]]) ]31// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[CALL]], align 432// CHECK-NEXT: ret i32 [[TMP1]]33//34__INT32_TYPE__ test2(__SIZE_TYPE__ a) {35 return *m1(a);36}37__INT32_TYPE__ *m2(__SIZE_TYPE__ i) __attribute__((alloc_align(1)));38 39// test3 param needs casting, but 'm2' is correct.40// CHECK-LABEL: @test3(41// CHECK-NEXT: entry:42// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 443// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 444// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 445// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i6446// CHECK-NEXT: [[CALL:%.*]] = call ptr @m2(i64 noundef [[CONV]])47// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[CALL]], i64 [[CONV]]) ]48// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[CALL]], align 449// CHECK-NEXT: ret i32 [[TMP1]]50//51__INT32_TYPE__ test3(__INT32_TYPE__ a) {52 return *m2(a);53}54 55// Every type matches, canonical example.56// CHECK-LABEL: @test4(57// CHECK-NEXT: entry:58// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 859// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 860// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 861// CHECK-NEXT: [[CALL:%.*]] = call ptr @m2(i64 noundef [[TMP0]])62// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[CALL]], i64 [[TMP0]]) ]63// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[CALL]], align 464// CHECK-NEXT: ret i32 [[TMP1]]65//66__INT32_TYPE__ test4(__SIZE_TYPE__ a) {67 return *m2(a);68}69 70 71struct Empty {};72struct MultiArgs { __INT64_TYPE__ a, b;};73// Struct parameter doesn't take up an IR parameter, 'i' takes up 1.74// Truncation to i64 is permissible, since alignments of greater than 2^64 are insane.75__INT32_TYPE__ *m3(struct Empty s, __int128_t i) __attribute__((alloc_align(2)));76// CHECK-LABEL: @test5(77// CHECK-NEXT: entry:78// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i128, align 1679// CHECK-NEXT: [[E:%.*]] = alloca [[STRUCT_EMPTY:%.*]], align 180// CHECK-NEXT: store i128 [[A:%.*]], ptr [[A_ADDR]], align 1681// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A_ADDR]], align 1682// CHECK-NEXT: [[CALL:%.*]] = call ptr @m3(i128 noundef [[TMP0]])83// CHECK-NEXT: [[CASTED_ALIGN:%.*]] = trunc i128 [[TMP0]] to i6484// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[CALL]], i64 [[CASTED_ALIGN]]) ]85// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[CALL]], align 486// CHECK-NEXT: ret i32 [[TMP1]]87//88__INT32_TYPE__ test5(__int128_t a) {89 struct Empty e;90 return *m3(e, a);91}92// Struct parameter takes up 2 parameters, 'i' takes up 1.93__INT32_TYPE__ *m4(struct MultiArgs s, __int128_t i) __attribute__((alloc_align(2)));94// CHECK-LABEL: @test6(95// CHECK-NEXT: entry:96// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i128, align 1697// CHECK-NEXT: [[E:%.*]] = alloca [[STRUCT_MULTIARGS:%.*]], align 898// CHECK-NEXT: store i128 [[A:%.*]], ptr [[A_ADDR]], align 1699// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A_ADDR]], align 16100// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw { i64, i64 }, ptr [[E]], i32 0, i32 0101// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8102// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw { i64, i64 }, ptr [[E]], i32 0, i32 1103// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[TMP3]], align 8104// CHECK-NEXT: [[CALL:%.*]] = call ptr @m4(i64 [[TMP2]], i64 [[TMP4]], i128 noundef [[TMP0]])105// CHECK-NEXT: [[CASTED_ALIGN:%.*]] = trunc i128 [[TMP0]] to i64106// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[CALL]], i64 [[CASTED_ALIGN]]) ]107// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[CALL]], align 4108// CHECK-NEXT: ret i32 [[TMP5]]109//110__INT32_TYPE__ test6(__int128_t a) {111 struct MultiArgs e;112 return *m4(e, a);113}114 115