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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \3// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg,sroa | FileCheck %s4// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft \5// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg,sroa | FileCheck %s6 7// REQUIRES: aarch64-registered-target || arm-registered-target8 9#include <arm_neon.h>10 11// CHECK-LABEL: @test_vcreate_bf16(12// CHECK-NEXT: entry:13// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A:%.*]] to <4 x bfloat>14// CHECK-NEXT: ret <4 x bfloat> [[TMP0]]15//16bfloat16x4_t test_vcreate_bf16(uint64_t a) {17 return vcreate_bf16(a);18}19 20// CHECK-LABEL: @test_vdup_n_bf16(21// CHECK-NEXT: entry:22// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x bfloat> poison, bfloat [[V:%.*]], i32 023// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x bfloat> [[VECINIT_I]], bfloat [[V]], i32 124// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x bfloat> [[VECINIT1_I]], bfloat [[V]], i32 225// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x bfloat> [[VECINIT2_I]], bfloat [[V]], i32 326// CHECK-NEXT: ret <4 x bfloat> [[VECINIT3_I]]27//28bfloat16x4_t test_vdup_n_bf16(bfloat16_t v) {29 return vdup_n_bf16(v);30}31 32// CHECK-LABEL: @test_vdupq_n_bf16(33// CHECK-NEXT: entry:34// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x bfloat> poison, bfloat [[V:%.*]], i32 035// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x bfloat> [[VECINIT_I]], bfloat [[V]], i32 136// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x bfloat> [[VECINIT1_I]], bfloat [[V]], i32 237// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x bfloat> [[VECINIT2_I]], bfloat [[V]], i32 338// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x bfloat> [[VECINIT3_I]], bfloat [[V]], i32 439// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x bfloat> [[VECINIT4_I]], bfloat [[V]], i32 540// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x bfloat> [[VECINIT5_I]], bfloat [[V]], i32 641// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x bfloat> [[VECINIT6_I]], bfloat [[V]], i32 742// CHECK-NEXT: ret <8 x bfloat> [[VECINIT7_I]]43//44bfloat16x8_t test_vdupq_n_bf16(bfloat16_t v) {45 return vdupq_n_bf16(v);46}47 48// CHECK-LABEL: @test_vdup_lane_bf16(49// CHECK-NEXT: entry:50// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x bfloat> [[V:%.*]] to <4 x i16>51// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>52// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x bfloat>53// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x bfloat> [[TMP2]], <4 x bfloat> [[TMP2]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>54// CHECK-NEXT: ret <4 x bfloat> [[LANE]]55//56bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) {57 return vdup_lane_bf16(v, 1);58}59 60// CHECK-LABEL: @test_vdupq_lane_bf16(61// CHECK-NEXT: entry:62// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x bfloat> [[V:%.*]] to <4 x i16>63// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>64// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x bfloat>65// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x bfloat> [[TMP2]], <4 x bfloat> [[TMP2]], <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>66// CHECK-NEXT: ret <8 x bfloat> [[LANE]]67//68bfloat16x8_t test_vdupq_lane_bf16(bfloat16x4_t v) {69 return vdupq_lane_bf16(v, 1);70}71 72// CHECK-LABEL: @test_vdup_laneq_bf16(73// CHECK-NEXT: entry:74// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x bfloat> [[V:%.*]] to <8 x i16>75// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>76// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x bfloat>77// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x bfloat> [[TMP2]], <8 x bfloat> [[TMP2]], <4 x i32> <i32 7, i32 7, i32 7, i32 7>78// CHECK-NEXT: ret <4 x bfloat> [[LANE]]79//80bfloat16x4_t test_vdup_laneq_bf16(bfloat16x8_t v) {81 return vdup_laneq_bf16(v, 7);82}83 84// CHECK-LABEL: @test_vdupq_laneq_bf16(85// CHECK-NEXT: entry:86// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x bfloat> [[V:%.*]] to <8 x i16>87// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>88// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x bfloat>89// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x bfloat> [[TMP2]], <8 x bfloat> [[TMP2]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>90// CHECK-NEXT: ret <8 x bfloat> [[LANE]]91//92bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) {93 return vdupq_laneq_bf16(v, 7);94}95 96// CHECK-LABEL: @test_vcombine_bf16(97// CHECK-NEXT: entry:98// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x bfloat> [[LOW:%.*]], <4 x bfloat> [[HIGH:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>99// CHECK-NEXT: ret <8 x bfloat> [[SHUFFLE_I]]100//101bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) {102 return vcombine_bf16(low, high);103}104 105// CHECK-LABEL: @test_vget_high_bf16(106// CHECK-NEXT: entry:107// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>108// CHECK-NEXT: ret <4 x bfloat> [[SHUFFLE_I]]109//110bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) {111 return vget_high_bf16(a);112}113 114// CHECK-LABEL: @test_vget_low_bf16(115// CHECK-NEXT: entry:116// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> [[A]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>117// CHECK-NEXT: ret <4 x bfloat> [[SHUFFLE_I]]118//119bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) {120 return vget_low_bf16(a);121}122 123// CHECK-LABEL: @test_vget_lane_bf16(124// CHECK-NEXT: entry:125// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1126// CHECK-NEXT: ret bfloat [[VGET_LANE]]127//128bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {129 return vget_lane_bf16(v, 1);130}131 132// CHECK-LABEL: @test_vgetq_lane_bf16(133// CHECK-NEXT: entry:134// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7135// CHECK-NEXT: ret bfloat [[VGET_LANE]]136//137bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {138 return vgetq_lane_bf16(v, 7);139}140 141// CHECK-LABEL: @test_vset_lane_bf16(142// CHECK-NEXT: entry:143// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <4 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 1144// CHECK-NEXT: ret <4 x bfloat> [[VSET_LANE]]145//146bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) {147 return vset_lane_bf16(a, v, 1);148}149 150// CHECK-LABEL: @test_vsetq_lane_bf16(151// CHECK-NEXT: entry:152// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <8 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 7153// CHECK-NEXT: ret <8 x bfloat> [[VSET_LANE]]154//155bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) {156 return vsetq_lane_bf16(a, v, 7);157}158 159// CHECK-LABEL: @test_vduph_lane_bf16(160// CHECK-NEXT: entry:161// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1162// CHECK-NEXT: ret bfloat [[VGET_LANE]]163//164bfloat16_t test_vduph_lane_bf16(bfloat16x4_t v) {165 return vduph_lane_bf16(v, 1);166}167 168// CHECK-LABEL: @test_vduph_laneq_bf16(169// CHECK-NEXT: entry:170// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7171// CHECK-NEXT: ret bfloat [[VGET_LANE]]172//173bfloat16_t test_vduph_laneq_bf16(bfloat16x8_t v) {174 return vduph_laneq_bf16(v, 7);175}176