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1// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi \2// RUN: -target-feature +cdecp0 -target-feature +mve.fp \3// RUN: -mfloat-abi hard -O0 -disable-O0-optnone \4// RUN: -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s --check-prefixes=CHECK,CHECK-LE5// RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi \6// RUN: -target-feature +cdecp0 -target-feature +mve.fp \7// RUN: -mfloat-abi hard -O0 -disable-O0-optnone \8// RUN: -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s --check-prefixes=CHECK,CHECK-BE9 10// REQUIRES: aarch64-registered-target || arm-registered-target11 12#include <arm_cde.h>13 14// CHECK-LABEL: @test_s8(15// CHECK-NEXT: entry:16// CHECK-NEXT: ret <16 x i8> [[X:%.*]]17//18int8x16_t test_s8(uint8x16_t x) {19 return __arm_vreinterpretq_s8_u8(x);20}21 22// CHECK-LABEL: @test_u16(23// CHECK-NEXT: entry:24// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x i16>25// CHECK-BE-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> [[X:%.*]])26// CHECK-NEXT: ret <8 x i16> [[TMP0]]27//28uint16x8_t test_u16(uint8x16_t x) {29 return __arm_vreinterpretq_u16_u8(x);30}31 32// CHECK-LABEL: @test_s32(33// CHECK-NEXT: entry:34// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32>35// CHECK-BE-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v16i8(<16 x i8> [[X:%.*]])36// CHECK-NEXT: ret <4 x i32> [[TMP0]]37//38int32x4_t test_s32(uint8x16_t x) {39 return __arm_vreinterpretq_s32_u8(x);40}41 42// CHECK-LABEL: @test_u32(43// CHECK-NEXT: entry:44// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32>45// CHECK-BE-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v16i8(<16 x i8> [[X:%.*]])46// CHECK-NEXT: ret <4 x i32> [[TMP0]]47//48uint32x4_t test_u32(uint8x16_t x) {49 return __arm_vreinterpretq_u32_u8(x);50}51 52// CHECK-LABEL: @test_s64(53// CHECK-NEXT: entry:54// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64>55// CHECK-BE-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.arm.mve.vreinterpretq.v2i64.v16i8(<16 x i8> [[X:%.*]])56// CHECK-NEXT: ret <2 x i64> [[TMP0]]57//58int64x2_t test_s64(uint8x16_t x) {59 return __arm_vreinterpretq_s64_u8(x);60}61 62// CHECK-LABEL: @test_u64(63// CHECK-NEXT: entry:64// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64>65// CHECK-BE-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.arm.mve.vreinterpretq.v2i64.v16i8(<16 x i8> [[X:%.*]])66// CHECK-NEXT: ret <2 x i64> [[TMP0]]67//68uint64x2_t test_u64(uint8x16_t x) {69 return __arm_vreinterpretq_u64_u8(x);70}71 72// CHECK-LABEL: @test_f16(73// CHECK-NEXT: entry:74// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x half>75// CHECK-BE-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v16i8(<16 x i8> [[X:%.*]])76// CHECK-NEXT: ret <8 x half> [[TMP0]]77//78float16x8_t test_f16(uint8x16_t x) {79 return __arm_vreinterpretq_f16_u8(x);80}81 82// CHECK-LABEL: @test_f32(83// CHECK-NEXT: entry:84// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x float>85// CHECK-BE-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vreinterpretq.v4f32.v16i8(<16 x i8> [[X:%.*]])86// CHECK-NEXT: ret <4 x float> [[TMP0]]87//88float32x4_t test_f32(uint8x16_t x) {89 return __arm_vreinterpretq_f32_u8(x);90}91