252 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s3// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s4 5// REQUIRES: aarch64-registered-target || arm-registered-target6 7#include <arm_mve.h>8 9// CHECK-LABEL: @test_vadciq_s32(10// CHECK-NEXT: entry:11// CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0)12// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 113// CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2914// CHECK-NEXT: [[TMP3:%.*]] = and i32 1, [[TMP2]]15// CHECK-NEXT: store i32 [[TMP3]], ptr [[CARRY_OUT:%.*]], align 416// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 017// CHECK-NEXT: ret <4 x i32> [[TMP4]]18//19int32x4_t test_vadciq_s32(int32x4_t a, int32x4_t b, unsigned *carry_out)20{21#ifdef POLYMORPHIC22 return vadciq(a, b, carry_out);23#else /* POLYMORPHIC */24 return vadciq_s32(a, b, carry_out);25#endif /* POLYMORPHIC */26}27 28// CHECK-LABEL: @test_vadcq_u32(29// CHECK-NEXT: entry:30// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[CARRY:%.*]], align 431// CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 2932// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]])33// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 134// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 2935// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]36// CHECK-NEXT: store i32 [[TMP5]], ptr [[CARRY]], align 437// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 038// CHECK-NEXT: ret <4 x i32> [[TMP6]]39//40uint32x4_t test_vadcq_u32(uint32x4_t a, uint32x4_t b, unsigned *carry)41{42#ifdef POLYMORPHIC43 return vadcq(a, b, carry);44#else /* POLYMORPHIC */45 return vadcq_u32(a, b, carry);46#endif /* POLYMORPHIC */47}48 49// CHECK-LABEL: @test_vadciq_m_u32(50// CHECK-NEXT: entry:51// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i3252// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])53// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]])54// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 155// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 2956// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]57// CHECK-NEXT: store i32 [[TMP5]], ptr [[CARRY_OUT:%.*]], align 458// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 059// CHECK-NEXT: ret <4 x i32> [[TMP6]]60//61uint32x4_t test_vadciq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)62{63#ifdef POLYMORPHIC64 return vadciq_m(inactive, a, b, carry_out, p);65#else /* POLYMORPHIC */66 return vadciq_m_u32(inactive, a, b, carry_out, p);67#endif /* POLYMORPHIC */68}69 70// CHECK-LABEL: @test_vadcq_m_s32(71// CHECK-NEXT: entry:72// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[CARRY:%.*]], align 473// CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 2974// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i3275// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])76// CHECK-NEXT: [[TMP4:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]], <4 x i1> [[TMP3]])77// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 178// CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], 2979// CHECK-NEXT: [[TMP7:%.*]] = and i32 1, [[TMP6]]80// CHECK-NEXT: store i32 [[TMP7]], ptr [[CARRY]], align 481// CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 082// CHECK-NEXT: ret <4 x i32> [[TMP8]]83//84int32x4_t test_vadcq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)85{86#ifdef POLYMORPHIC87 return vadcq_m(inactive, a, b, carry, p);88#else /* POLYMORPHIC */89 return vadcq_m_s32(inactive, a, b, carry, p);90#endif /* POLYMORPHIC */91}92 93// CHECK-LABEL: @test_vsbciq_s32(94// CHECK-NEXT: entry:95// CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 536870912)96// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 197// CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2998// CHECK-NEXT: [[TMP3:%.*]] = and i32 1, [[TMP2]]99// CHECK-NEXT: store i32 [[TMP3]], ptr [[CARRY_OUT:%.*]], align 4100// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 0101// CHECK-NEXT: ret <4 x i32> [[TMP4]]102//103int32x4_t test_vsbciq_s32(int32x4_t a, int32x4_t b, unsigned *carry_out) {104#ifdef POLYMORPHIC105 return vsbciq(a, b, carry_out);106#else /* POLYMORPHIC */107 return vsbciq_s32(a, b, carry_out);108#endif /* POLYMORPHIC */109}110 111// CHECK-LABEL: @test_vsbciq_u32(112// CHECK-NEXT: entry:113// CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 536870912)114// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 1115// CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 29116// CHECK-NEXT: [[TMP3:%.*]] = and i32 1, [[TMP2]]117// CHECK-NEXT: store i32 [[TMP3]], ptr [[CARRY_OUT:%.*]], align 4118// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 0119// CHECK-NEXT: ret <4 x i32> [[TMP4]]120//121uint32x4_t test_vsbciq_u32(uint32x4_t a, uint32x4_t b, unsigned *carry_out) {122#ifdef POLYMORPHIC123 return vsbciq(a, b, carry_out);124#else /* POLYMORPHIC */125 return vsbciq_u32(a, b, carry_out);126#endif /* POLYMORPHIC */127}128 129// CHECK-LABEL: @test_vsbcq_s32(130// CHECK-NEXT: entry:131// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[CARRY:%.*]], align 4132// CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 29133// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]])134// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1135// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29136// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]137// CHECK-NEXT: store i32 [[TMP5]], ptr [[CARRY]], align 4138// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0139// CHECK-NEXT: ret <4 x i32> [[TMP6]]140//141int32x4_t test_vsbcq_s32(int32x4_t a, int32x4_t b, unsigned *carry) {142#ifdef POLYMORPHIC143 return vsbcq(a, b, carry);144#else /* POLYMORPHIC */145 return vsbcq_s32(a, b, carry);146#endif /* POLYMORPHIC */147}148 149// CHECK-LABEL: @test_vsbcq_u32(150// CHECK-NEXT: entry:151// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[CARRY:%.*]], align 4152// CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 29153// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]])154// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1155// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29156// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]157// CHECK-NEXT: store i32 [[TMP5]], ptr [[CARRY]], align 4158// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0159// CHECK-NEXT: ret <4 x i32> [[TMP6]]160//161uint32x4_t test_vsbcq_u32(uint32x4_t a, uint32x4_t b, unsigned *carry) {162#ifdef POLYMORPHIC163 return vsbcq(a, b, carry);164#else /* POLYMORPHIC */165 return vsbcq_u32(a, b, carry);166#endif /* POLYMORPHIC */167}168 169// CHECK-LABEL: @test_vsbciq_m_s32(170// CHECK-NEXT: entry:171// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32172// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])173// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 536870912, <4 x i1> [[TMP1]])174// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1175// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29176// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]177// CHECK-NEXT: store i32 [[TMP5]], ptr [[CARRY_OUT:%.*]], align 4178// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0179// CHECK-NEXT: ret <4 x i32> [[TMP6]]180//181int32x4_t test_vsbciq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p) {182#ifdef POLYMORPHIC183 return vsbciq_m(inactive, a, b, carry_out, p);184#else /* POLYMORPHIC */185 return vsbciq_m_s32(inactive, a, b, carry_out, p);186#endif /* POLYMORPHIC */187}188 189// CHECK-LABEL: @test_vsbciq_m_u32(190// CHECK-NEXT: entry:191// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32192// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])193// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 536870912, <4 x i1> [[TMP1]])194// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1195// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29196// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]197// CHECK-NEXT: store i32 [[TMP5]], ptr [[CARRY_OUT:%.*]], align 4198// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0199// CHECK-NEXT: ret <4 x i32> [[TMP6]]200//201uint32x4_t test_vsbciq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p) {202#ifdef POLYMORPHIC203 return vsbciq_m(inactive, a, b, carry_out, p);204#else /* POLYMORPHIC */205 return vsbciq_m_u32(inactive, a, b, carry_out, p);206#endif /* POLYMORPHIC */207}208 209// CHECK-LABEL: @test_vsbcq_m_s32(210// CHECK-NEXT: entry:211// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[CARRY:%.*]], align 4212// CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 29213// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32214// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])215// CHECK-NEXT: [[TMP4:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]], <4 x i1> [[TMP3]])216// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 1217// CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], 29218// CHECK-NEXT: [[TMP7:%.*]] = and i32 1, [[TMP6]]219// CHECK-NEXT: store i32 [[TMP7]], ptr [[CARRY]], align 4220// CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 0221// CHECK-NEXT: ret <4 x i32> [[TMP8]]222//223int32x4_t test_vsbcq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p) {224#ifdef POLYMORPHIC225 return vsbcq_m(inactive, a, b, carry, p);226#else /* POLYMORPHIC */227 return vsbcq_m_s32(inactive, a, b, carry, p);228#endif /* POLYMORPHIC */229}230 231// CHECK-LABEL: @test_vsbcq_m_u32(232// CHECK-NEXT: entry:233// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[CARRY:%.*]], align 4234// CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 29235// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32236// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])237// CHECK-NEXT: [[TMP4:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]], <4 x i1> [[TMP3]])238// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 1239// CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], 29240// CHECK-NEXT: [[TMP7:%.*]] = and i32 1, [[TMP6]]241// CHECK-NEXT: store i32 [[TMP7]], ptr [[CARRY]], align 4242// CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 0243// CHECK-NEXT: ret <4 x i32> [[TMP8]]244//245uint32x4_t test_vsbcq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p) {246#ifdef POLYMORPHIC247 return vsbcq_m(inactive, a, b, carry, p);248#else /* POLYMORPHIC */249 return vsbcq_m_u32(inactive, a, b, carry, p);250#endif /* POLYMORPHIC */251}252