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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s3// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s4 5// REQUIRES: aarch64-registered-target || arm-registered-target6 7#include <arm_mve.h>8 9// CHECK-LABEL: @test_vcaddq_rot90_u8(10// CHECK-NEXT: entry:11// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])12// CHECK-NEXT: ret <16 x i8> [[TMP0]]13//14uint8x16_t test_vcaddq_rot90_u8(uint8x16_t a, uint8x16_t b)15{16#ifdef POLYMORPHIC17 return vcaddq_rot90(a, b);18#else19 return vcaddq_rot90_u8(a, b);20#endif21}22 23// CHECK-LABEL: @test_vcaddq_rot90_u16(24// CHECK-NEXT: entry:25// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])26// CHECK-NEXT: ret <8 x i16> [[TMP0]]27//28uint16x8_t test_vcaddq_rot90_u16(uint16x8_t a, uint16x8_t b)29{30#ifdef POLYMORPHIC31 return vcaddq_rot90(a, b);32#else33 return vcaddq_rot90_u16(a, b);34#endif35}36 37// CHECK-LABEL: @test_vcaddq_rot90_u32(38// CHECK-NEXT: entry:39// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])40// CHECK-NEXT: ret <4 x i32> [[TMP0]]41//42uint32x4_t test_vcaddq_rot90_u32(uint32x4_t a, uint32x4_t b)43{44#ifdef POLYMORPHIC45 return vcaddq_rot90(a, b);46#else47 return vcaddq_rot90_u32(a, b);48#endif49}50 51// CHECK-LABEL: @test_vcaddq_rot90_s8(52// CHECK-NEXT: entry:53// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])54// CHECK-NEXT: ret <16 x i8> [[TMP0]]55//56int8x16_t test_vcaddq_rot90_s8(int8x16_t a, int8x16_t b)57{58#ifdef POLYMORPHIC59 return vcaddq_rot90(a, b);60#else61 return vcaddq_rot90_s8(a, b);62#endif63}64 65// CHECK-LABEL: @test_vcaddq_rot90_s16(66// CHECK-NEXT: entry:67// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])68// CHECK-NEXT: ret <8 x i16> [[TMP0]]69//70int16x8_t test_vcaddq_rot90_s16(int16x8_t a, int16x8_t b)71{72#ifdef POLYMORPHIC73 return vcaddq_rot90(a, b);74#else75 return vcaddq_rot90_s16(a, b);76#endif77}78 79// CHECK-LABEL: @test_vcaddq_rot90_s32(80// CHECK-NEXT: entry:81// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])82// CHECK-NEXT: ret <4 x i32> [[TMP0]]83//84int32x4_t test_vcaddq_rot90_s32(int32x4_t a, int32x4_t b)85{86#ifdef POLYMORPHIC87 return vcaddq_rot90(a, b);88#else89 return vcaddq_rot90_s32(a, b);90#endif91}92 93// CHECK-LABEL: @test_vcaddq_rot90_f16(94// CHECK-NEXT: entry:95// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])96// CHECK-NEXT: ret <8 x half> [[TMP0]]97//98float16x8_t test_vcaddq_rot90_f16(float16x8_t a, float16x8_t b)99{100#ifdef POLYMORPHIC101 return vcaddq_rot90(a, b);102#else103 return vcaddq_rot90_f16(a, b);104#endif105}106 107// CHECK-LABEL: @test_vcaddq_rot90_f32(108// CHECK-NEXT: entry:109// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])110// CHECK-NEXT: ret <4 x float> [[TMP0]]111//112float32x4_t test_vcaddq_rot90_f32(float32x4_t a, float32x4_t b)113{114#ifdef POLYMORPHIC115 return vcaddq_rot90(a, b);116#else117 return vcaddq_rot90_f32(a, b);118#endif119}120 121// CHECK-LABEL: @test_vcaddq_rot270_u8(122// CHECK-NEXT: entry:123// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])124// CHECK-NEXT: ret <16 x i8> [[TMP0]]125//126uint8x16_t test_vcaddq_rot270_u8(uint8x16_t a, uint8x16_t b)127{128#ifdef POLYMORPHIC129 return vcaddq_rot270(a, b);130#else131 return vcaddq_rot270_u8(a, b);132#endif133}134 135// CHECK-LABEL: @test_vcaddq_rot270_u16(136// CHECK-NEXT: entry:137// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])138// CHECK-NEXT: ret <8 x i16> [[TMP0]]139//140uint16x8_t test_vcaddq_rot270_u16(uint16x8_t a, uint16x8_t b)141{142#ifdef POLYMORPHIC143 return vcaddq_rot270(a, b);144#else145 return vcaddq_rot270_u16(a, b);146#endif147}148 149// CHECK-LABEL: @test_vcaddq_rot270_u32(150// CHECK-NEXT: entry:151// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])152// CHECK-NEXT: ret <4 x i32> [[TMP0]]153//154uint32x4_t test_vcaddq_rot270_u32(uint32x4_t a, uint32x4_t b)155{156#ifdef POLYMORPHIC157 return vcaddq_rot270(a, b);158#else159 return vcaddq_rot270_u32(a, b);160#endif161}162 163// CHECK-LABEL: @test_vcaddq_rot270_s8(164// CHECK-NEXT: entry:165// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])166// CHECK-NEXT: ret <16 x i8> [[TMP0]]167//168int8x16_t test_vcaddq_rot270_s8(int8x16_t a, int8x16_t b)169{170#ifdef POLYMORPHIC171 return vcaddq_rot270(a, b);172#else173 return vcaddq_rot270_s8(a, b);174#endif175}176 177// CHECK-LABEL: @test_vcaddq_rot270_s16(178// CHECK-NEXT: entry:179// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])180// CHECK-NEXT: ret <8 x i16> [[TMP0]]181//182int16x8_t test_vcaddq_rot270_s16(int16x8_t a, int16x8_t b)183{184#ifdef POLYMORPHIC185 return vcaddq_rot270(a, b);186#else187 return vcaddq_rot270_s16(a, b);188#endif189}190 191// CHECK-LABEL: @test_vcaddq_rot270_s32(192// CHECK-NEXT: entry:193// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])194// CHECK-NEXT: ret <4 x i32> [[TMP0]]195//196int32x4_t test_vcaddq_rot270_s32(int32x4_t a, int32x4_t b)197{198#ifdef POLYMORPHIC199 return vcaddq_rot270(a, b);200#else201 return vcaddq_rot270_s32(a, b);202#endif203}204 205// CHECK-LABEL: @test_vcaddq_rot270_f16(206// CHECK-NEXT: entry:207// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])208// CHECK-NEXT: ret <8 x half> [[TMP0]]209//210float16x8_t test_vcaddq_rot270_f16(float16x8_t a, float16x8_t b)211{212#ifdef POLYMORPHIC213 return vcaddq_rot270(a, b);214#else215 return vcaddq_rot270_f16(a, b);216#endif217}218 219// CHECK-LABEL: @test_vcaddq_rot270_f32(220// CHECK-NEXT: entry:221// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])222// CHECK-NEXT: ret <4 x float> [[TMP0]]223//224float32x4_t test_vcaddq_rot270_f32(float32x4_t a, float32x4_t b)225{226#ifdef POLYMORPHIC227 return vcaddq_rot270(a, b);228#else229 return vcaddq_rot270_f32(a, b);230#endif231}232 233 234// CHECK-LABEL: @test_vcaddq_rot90_m_u8(235// CHECK-NEXT: entry:236// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32237// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])238// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])239// CHECK-NEXT: ret <16 x i8> [[TMP2]]240//241uint8x16_t test_vcaddq_rot90_m_u8(uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)242{243#ifdef POLYMORPHIC244 return vcaddq_rot90_m(inactive, a, b, p);245#else246 return vcaddq_rot90_m_u8(inactive, a, b, p);247#endif248}249 250// CHECK-LABEL: @test_vcaddq_rot90_m_u16(251// CHECK-NEXT: entry:252// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32253// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])254// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])255// CHECK-NEXT: ret <8 x i16> [[TMP2]]256//257uint16x8_t test_vcaddq_rot90_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)258{259#ifdef POLYMORPHIC260 return vcaddq_rot90_m(inactive, a, b, p);261#else262 return vcaddq_rot90_m_u16(inactive, a, b, p);263#endif264}265 266// CHECK-LABEL: @test_vcaddq_rot90_m_u32(267// CHECK-NEXT: entry:268// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32269// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])270// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])271// CHECK-NEXT: ret <4 x i32> [[TMP2]]272//273uint32x4_t test_vcaddq_rot90_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)274{275#ifdef POLYMORPHIC276 return vcaddq_rot90_m(inactive, a, b, p);277#else278 return vcaddq_rot90_m_u32(inactive, a, b, p);279#endif280}281 282// CHECK-LABEL: @test_vcaddq_rot90_m_s8(283// CHECK-NEXT: entry:284// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32285// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])286// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])287// CHECK-NEXT: ret <16 x i8> [[TMP2]]288//289int8x16_t test_vcaddq_rot90_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)290{291#ifdef POLYMORPHIC292 return vcaddq_rot90_m(inactive, a, b, p);293#else294 return vcaddq_rot90_m_s8(inactive, a, b, p);295#endif296}297 298// CHECK-LABEL: @test_vcaddq_rot90_m_s16(299// CHECK-NEXT: entry:300// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32301// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])302// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])303// CHECK-NEXT: ret <8 x i16> [[TMP2]]304//305int16x8_t test_vcaddq_rot90_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)306{307#ifdef POLYMORPHIC308 return vcaddq_rot90_m(inactive, a, b, p);309#else310 return vcaddq_rot90_m_s16(inactive, a, b, p);311#endif312}313 314// CHECK-LABEL: @test_vcaddq_rot90_m_s32(315// CHECK-NEXT: entry:316// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32317// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])318// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])319// CHECK-NEXT: ret <4 x i32> [[TMP2]]320//321int32x4_t test_vcaddq_rot90_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)322{323#ifdef POLYMORPHIC324 return vcaddq_rot90_m(inactive, a, b, p);325#else326 return vcaddq_rot90_m_s32(inactive, a, b, p);327#endif328}329 330// CHECK-LABEL: @test_vcaddq_rot90_m_f16(331// CHECK-NEXT: entry:332// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32333// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])334// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 0, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])335// CHECK-NEXT: ret <8 x half> [[TMP2]]336//337float16x8_t test_vcaddq_rot90_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)338{339#ifdef POLYMORPHIC340 return vcaddq_rot90_m(inactive, a, b, p);341#else342 return vcaddq_rot90_m_f16(inactive, a, b, p);343#endif344}345 346// CHECK-LABEL: @test_vcaddq_rot90_m_f32(347// CHECK-NEXT: entry:348// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32349// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])350// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 0, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])351// CHECK-NEXT: ret <4 x float> [[TMP2]]352//353float32x4_t test_vcaddq_rot90_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)354{355#ifdef POLYMORPHIC356 return vcaddq_rot90_m(inactive, a, b, p);357#else358 return vcaddq_rot90_m_f32(inactive, a, b, p);359#endif360}361 362// CHECK-LABEL: @test_vcaddq_rot270_m_u8(363// CHECK-NEXT: entry:364// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32365// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])366// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])367// CHECK-NEXT: ret <16 x i8> [[TMP2]]368//369uint8x16_t test_vcaddq_rot270_m_u8(uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)370{371#ifdef POLYMORPHIC372 return vcaddq_rot270_m(inactive, a, b, p);373#else374 return vcaddq_rot270_m_u8(inactive, a, b, p);375#endif376}377 378// CHECK-LABEL: @test_vcaddq_rot270_m_u16(379// CHECK-NEXT: entry:380// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32381// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])382// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])383// CHECK-NEXT: ret <8 x i16> [[TMP2]]384//385uint16x8_t test_vcaddq_rot270_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)386{387#ifdef POLYMORPHIC388 return vcaddq_rot270_m(inactive, a, b, p);389#else390 return vcaddq_rot270_m_u16(inactive, a, b, p);391#endif392}393 394// CHECK-LABEL: @test_vcaddq_rot270_m_u32(395// CHECK-NEXT: entry:396// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32397// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])398// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])399// CHECK-NEXT: ret <4 x i32> [[TMP2]]400//401uint32x4_t test_vcaddq_rot270_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)402{403#ifdef POLYMORPHIC404 return vcaddq_rot270_m(inactive, a, b, p);405#else406 return vcaddq_rot270_m_u32(inactive, a, b, p);407#endif408}409 410// CHECK-LABEL: @test_vcaddq_rot270_m_s8(411// CHECK-NEXT: entry:412// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32413// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])414// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])415// CHECK-NEXT: ret <16 x i8> [[TMP2]]416//417int8x16_t test_vcaddq_rot270_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)418{419#ifdef POLYMORPHIC420 return vcaddq_rot270_m(inactive, a, b, p);421#else422 return vcaddq_rot270_m_s8(inactive, a, b, p);423#endif424}425 426// CHECK-LABEL: @test_vcaddq_rot270_m_s16(427// CHECK-NEXT: entry:428// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32429// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])430// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])431// CHECK-NEXT: ret <8 x i16> [[TMP2]]432//433int16x8_t test_vcaddq_rot270_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)434{435#ifdef POLYMORPHIC436 return vcaddq_rot270_m(inactive, a, b, p);437#else438 return vcaddq_rot270_m_s16(inactive, a, b, p);439#endif440}441 442// CHECK-LABEL: @test_vcaddq_rot270_m_s32(443// CHECK-NEXT: entry:444// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32445// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])446// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])447// CHECK-NEXT: ret <4 x i32> [[TMP2]]448//449int32x4_t test_vcaddq_rot270_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)450{451#ifdef POLYMORPHIC452 return vcaddq_rot270_m(inactive, a, b, p);453#else454 return vcaddq_rot270_m_s32(inactive, a, b, p);455#endif456}457 458// CHECK-LABEL: @test_vcaddq_rot270_m_f16(459// CHECK-NEXT: entry:460// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32461// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])462// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 1, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])463// CHECK-NEXT: ret <8 x half> [[TMP2]]464//465float16x8_t test_vcaddq_rot270_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)466{467#ifdef POLYMORPHIC468 return vcaddq_rot270_m(inactive, a, b, p);469#else470 return vcaddq_rot270_m_f16(inactive, a, b, p);471#endif472}473 474// CHECK-LABEL: @test_vcaddq_rot270_m_f32(475// CHECK-NEXT: entry:476// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32477// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])478// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 1, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])479// CHECK-NEXT: ret <4 x float> [[TMP2]]480//481float32x4_t test_vcaddq_rot270_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)482{483#ifdef POLYMORPHIC484 return vcaddq_rot270_m(inactive, a, b, p);485#else486 return vcaddq_rot270_m_f32(inactive, a, b, p);487#endif488}489 490// CHECK-LABEL: @test_vcaddq_rot90_x_u8(491// CHECK-NEXT: entry:492// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32493// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])494// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])495// CHECK-NEXT: ret <16 x i8> [[TMP2]]496//497uint8x16_t test_vcaddq_rot90_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)498{499#ifdef POLYMORPHIC500 return vcaddq_rot90_x(a, b, p);501#else502 return vcaddq_rot90_x_u8(a, b, p);503#endif504}505 506// CHECK-LABEL: @test_vcaddq_rot90_x_u16(507// CHECK-NEXT: entry:508// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32509// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])510// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])511// CHECK-NEXT: ret <8 x i16> [[TMP2]]512//513uint16x8_t test_vcaddq_rot90_x_u16(uint16x8_t a, uint16x8_t b, mve_pred16_t p)514{515#ifdef POLYMORPHIC516 return vcaddq_rot90_x(a, b, p);517#else518 return vcaddq_rot90_x_u16(a, b, p);519#endif520}521 522// CHECK-LABEL: @test_vcaddq_rot90_x_u32(523// CHECK-NEXT: entry:524// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32525// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])526// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])527// CHECK-NEXT: ret <4 x i32> [[TMP2]]528//529uint32x4_t test_vcaddq_rot90_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)530{531#ifdef POLYMORPHIC532 return vcaddq_rot90_x(a, b, p);533#else534 return vcaddq_rot90_x_u32(a, b, p);535#endif536}537 538// CHECK-LABEL: @test_vcaddq_rot90_x_s8(539// CHECK-NEXT: entry:540// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32541// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])542// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])543// CHECK-NEXT: ret <16 x i8> [[TMP2]]544//545int8x16_t test_vcaddq_rot90_x_s8(int8x16_t a, int8x16_t b, mve_pred16_t p)546{547#ifdef POLYMORPHIC548 return vcaddq_rot90_x(a, b, p);549#else550 return vcaddq_rot90_x_s8(a, b, p);551#endif552}553 554// CHECK-LABEL: @test_vcaddq_rot90_x_s16(555// CHECK-NEXT: entry:556// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32557// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])558// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])559// CHECK-NEXT: ret <8 x i16> [[TMP2]]560//561int16x8_t test_vcaddq_rot90_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)562{563#ifdef POLYMORPHIC564 return vcaddq_rot90_x(a, b, p);565#else566 return vcaddq_rot90_x_s16(a, b, p);567#endif568}569 570// CHECK-LABEL: @test_vcaddq_rot90_x_s32(571// CHECK-NEXT: entry:572// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32573// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])574// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])575// CHECK-NEXT: ret <4 x i32> [[TMP2]]576//577int32x4_t test_vcaddq_rot90_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p)578{579#ifdef POLYMORPHIC580 return vcaddq_rot90_x(a, b, p);581#else582 return vcaddq_rot90_x_s32(a, b, p);583#endif584}585 586// CHECK-LABEL: @test_vcaddq_rot90_x_f16(587// CHECK-NEXT: entry:588// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32589// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])590// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 0, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])591// CHECK-NEXT: ret <8 x half> [[TMP2]]592//593float16x8_t test_vcaddq_rot90_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)594{595#ifdef POLYMORPHIC596 return vcaddq_rot90_x(a, b, p);597#else598 return vcaddq_rot90_x_f16(a, b, p);599#endif600}601 602// CHECK-LABEL: @test_vcaddq_rot90_x_f32(603// CHECK-NEXT: entry:604// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32605// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])606// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 0, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])607// CHECK-NEXT: ret <4 x float> [[TMP2]]608//609float32x4_t test_vcaddq_rot90_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)610{611#ifdef POLYMORPHIC612 return vcaddq_rot90_x(a, b, p);613#else614 return vcaddq_rot90_x_f32(a, b, p);615#endif616}617 618// CHECK-LABEL: @test_vcaddq_rot270_x_u8(619// CHECK-NEXT: entry:620// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32621// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])622// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])623// CHECK-NEXT: ret <16 x i8> [[TMP2]]624//625uint8x16_t test_vcaddq_rot270_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)626{627#ifdef POLYMORPHIC628 return vcaddq_rot270_x(a, b, p);629#else630 return vcaddq_rot270_x_u8(a, b, p);631#endif632}633 634// CHECK-LABEL: @test_vcaddq_rot270_x_u16(635// CHECK-NEXT: entry:636// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32637// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])638// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])639// CHECK-NEXT: ret <8 x i16> [[TMP2]]640//641uint16x8_t test_vcaddq_rot270_x_u16(uint16x8_t a, uint16x8_t b, mve_pred16_t p)642{643#ifdef POLYMORPHIC644 return vcaddq_rot270_x(a, b, p);645#else646 return vcaddq_rot270_x_u16(a, b, p);647#endif648}649 650// CHECK-LABEL: @test_vcaddq_rot270_x_u32(651// CHECK-NEXT: entry:652// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32653// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])654// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])655// CHECK-NEXT: ret <4 x i32> [[TMP2]]656//657uint32x4_t test_vcaddq_rot270_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)658{659#ifdef POLYMORPHIC660 return vcaddq_rot270_x(a, b, p);661#else662 return vcaddq_rot270_x_u32(a, b, p);663#endif664}665 666// CHECK-LABEL: @test_vcaddq_rot270_x_s8(667// CHECK-NEXT: entry:668// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32669// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])670// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])671// CHECK-NEXT: ret <16 x i8> [[TMP2]]672//673int8x16_t test_vcaddq_rot270_x_s8(int8x16_t a, int8x16_t b, mve_pred16_t p)674{675#ifdef POLYMORPHIC676 return vcaddq_rot270_x(a, b, p);677#else678 return vcaddq_rot270_x_s8(a, b, p);679#endif680}681 682// CHECK-LABEL: @test_vcaddq_rot270_x_s16(683// CHECK-NEXT: entry:684// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32685// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])686// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])687// CHECK-NEXT: ret <8 x i16> [[TMP2]]688//689int16x8_t test_vcaddq_rot270_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)690{691#ifdef POLYMORPHIC692 return vcaddq_rot270_x(a, b, p);693#else694 return vcaddq_rot270_x_s16(a, b, p);695#endif696}697 698// CHECK-LABEL: @test_vcaddq_rot270_x_s32(699// CHECK-NEXT: entry:700// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32701// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])702// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])703// CHECK-NEXT: ret <4 x i32> [[TMP2]]704//705int32x4_t test_vcaddq_rot270_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p)706{707#ifdef POLYMORPHIC708 return vcaddq_rot270_x(a, b, p);709#else710 return vcaddq_rot270_x_s32(a, b, p);711#endif712}713 714// CHECK-LABEL: @test_vcaddq_rot270_x_f16(715// CHECK-NEXT: entry:716// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32717// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])718// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 1, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])719// CHECK-NEXT: ret <8 x half> [[TMP2]]720//721float16x8_t test_vcaddq_rot270_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)722{723#ifdef POLYMORPHIC724 return vcaddq_rot270_x(a, b, p);725#else726 return vcaddq_rot270_x_f16(a, b, p);727#endif728}729 730// CHECK-LABEL: @test_vcaddq_rot270_x_f32(731// CHECK-NEXT: entry:732// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32733// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])734// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 1, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])735// CHECK-NEXT: ret <4 x float> [[TMP2]]736//737float32x4_t test_vcaddq_rot270_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)738{739#ifdef POLYMORPHIC740 return vcaddq_rot270_x(a, b, p);741#else742 return vcaddq_rot270_x_f32(a, b, p);743#endif744}745