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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s3// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s4 5// REQUIRES: aarch64-registered-target || arm-registered-target6 7#include <arm_mve.h>8 9// CHECK-LABEL: @test_vcmulq_f16(10// CHECK-NEXT: entry:11// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])12// CHECK-NEXT: ret <8 x half> [[TMP0]]13//14float16x8_t test_vcmulq_f16(float16x8_t a, float16x8_t b)15{16#ifdef POLYMORPHIC17 return vcmulq(a, b);18#else19 return vcmulq_f16(a, b);20#endif21}22 23// CHECK-LABEL: @test_vcmulq_f32(24// CHECK-NEXT: entry:25// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])26// CHECK-NEXT: ret <4 x float> [[TMP0]]27//28float32x4_t test_vcmulq_f32(float32x4_t a, float32x4_t b)29{30#ifdef POLYMORPHIC31 return vcmulq(a, b);32#else33 return vcmulq_f32(a, b);34#endif35}36 37// CHECK-LABEL: @test_vcmulq_rot90_f16(38// CHECK-NEXT: entry:39// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])40// CHECK-NEXT: ret <8 x half> [[TMP0]]41//42float16x8_t test_vcmulq_rot90_f16(float16x8_t a, float16x8_t b)43{44#ifdef POLYMORPHIC45 return vcmulq_rot90(a, b);46#else47 return vcmulq_rot90_f16(a, b);48#endif49}50 51// CHECK-LABEL: @test_vcmulq_rot90_f32(52// CHECK-NEXT: entry:53// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])54// CHECK-NEXT: ret <4 x float> [[TMP0]]55//56float32x4_t test_vcmulq_rot90_f32(float32x4_t a, float32x4_t b)57{58#ifdef POLYMORPHIC59 return vcmulq_rot90(a, b);60#else61 return vcmulq_rot90_f32(a, b);62#endif63}64 65// CHECK-LABEL: @test_vcmulq_rot180_f16(66// CHECK-NEXT: entry:67// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])68// CHECK-NEXT: ret <8 x half> [[TMP0]]69//70float16x8_t test_vcmulq_rot180_f16(float16x8_t a, float16x8_t b)71{72#ifdef POLYMORPHIC73 return vcmulq_rot180(a, b);74#else75 return vcmulq_rot180_f16(a, b);76#endif77}78 79// CHECK-LABEL: @test_vcmulq_rot180_f32(80// CHECK-NEXT: entry:81// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])82// CHECK-NEXT: ret <4 x float> [[TMP0]]83//84float32x4_t test_vcmulq_rot180_f32(float32x4_t a, float32x4_t b)85{86#ifdef POLYMORPHIC87 return vcmulq_rot180(a, b);88#else89 return vcmulq_rot180_f32(a, b);90#endif91}92 93// CHECK-LABEL: @test_vcmulq_rot270_f16(94// CHECK-NEXT: entry:95// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])96// CHECK-NEXT: ret <8 x half> [[TMP0]]97//98float16x8_t test_vcmulq_rot270_f16(float16x8_t a, float16x8_t b)99{100#ifdef POLYMORPHIC101 return vcmulq_rot270(a, b);102#else103 return vcmulq_rot270_f16(a, b);104#endif105}106 107// CHECK-LABEL: @test_vcmulq_rot270_f32(108// CHECK-NEXT: entry:109// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])110// CHECK-NEXT: ret <4 x float> [[TMP0]]111//112float32x4_t test_vcmulq_rot270_f32(float32x4_t a, float32x4_t b)113{114#ifdef POLYMORPHIC115 return vcmulq_rot270(a, b);116#else117 return vcmulq_rot270_f32(a, b);118#endif119}120 121// CHECK-LABEL: @test_vcmulq_m_f16(122// CHECK-NEXT: entry:123// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32124// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])125// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])126// CHECK-NEXT: ret <8 x half> [[TMP2]]127//128float16x8_t test_vcmulq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)129{130#ifdef polymorphic131 return vcmulq_m(inactive, a, b, p);132#else133 return vcmulq_m_f16(inactive, a, b, p);134#endif135}136 137// CHECK-LABEL: @test_vcmulq_m_f32(138// CHECK-NEXT: entry:139// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32140// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])141// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])142// CHECK-NEXT: ret <4 x float> [[TMP2]]143//144float32x4_t test_vcmulq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)145{146#ifdef polymorphic147 return vcmulq_m(inactive, a, b, p);148#else149 return vcmulq_m_f32(inactive, a, b, p);150#endif151}152 153// CHECK-LABEL: @test_vcmulq_rot90_m_f16(154// CHECK-NEXT: entry:155// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32156// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])157// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])158// CHECK-NEXT: ret <8 x half> [[TMP2]]159//160float16x8_t test_vcmulq_rot90_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)161{162#ifdef polymorphic163 return vcmulq_rot90_m(inactive, a, b, p);164#else165 return vcmulq_rot90_m_f16(inactive, a, b, p);166#endif167}168 169// CHECK-LABEL: @test_vcmulq_rot90_m_f32(170// CHECK-NEXT: entry:171// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32172// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])173// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])174// CHECK-NEXT: ret <4 x float> [[TMP2]]175//176float32x4_t test_vcmulq_rot90_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)177{178#ifdef polymorphic179 return vcmulq_rot90_m(inactive, a, b, p);180#else181 return vcmulq_rot90_m_f32(inactive, a, b, p);182#endif183}184 185// CHECK-LABEL: @test_vcmulq_rot180_m_f16(186// CHECK-NEXT: entry:187// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32188// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])189// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 2, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])190// CHECK-NEXT: ret <8 x half> [[TMP2]]191//192float16x8_t test_vcmulq_rot180_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)193{194#ifdef polymorphic195 return vcmulq_rot180_m(inactive, a, b, p);196#else197 return vcmulq_rot180_m_f16(inactive, a, b, p);198#endif199}200 201// CHECK-LABEL: @test_vcmulq_rot180_m_f32(202// CHECK-NEXT: entry:203// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32204// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])205// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 2, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])206// CHECK-NEXT: ret <4 x float> [[TMP2]]207//208float32x4_t test_vcmulq_rot180_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)209{210#ifdef polymorphic211 return vcmulq_rot180_m(inactive, a, b, p);212#else213 return vcmulq_rot180_m_f32(inactive, a, b, p);214#endif215}216 217// CHECK-LABEL: @test_vcmulq_rot270_m_f16(218// CHECK-NEXT: entry:219// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32220// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])221// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 3, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])222// CHECK-NEXT: ret <8 x half> [[TMP2]]223//224float16x8_t test_vcmulq_rot270_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)225{226#ifdef polymorphic227 return vcmulq_rot270_m(inactive, a, b, p);228#else229 return vcmulq_rot270_m_f16(inactive, a, b, p);230#endif231}232 233// CHECK-LABEL: @test_vcmulq_rot270_m_f32(234// CHECK-NEXT: entry:235// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32236// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])237// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 3, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])238// CHECK-NEXT: ret <4 x float> [[TMP2]]239//240float32x4_t test_vcmulq_rot270_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)241{242#ifdef polymorphic243 return vcmulq_rot270_m(inactive, a, b, p);244#else245 return vcmulq_rot270_m_f32(inactive, a, b, p);246#endif247}248 249// CHECK-LABEL: @test_vcmulq_x_f16(250// CHECK-NEXT: entry:251// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32252// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])253// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])254// CHECK-NEXT: ret <8 x half> [[TMP2]]255//256float16x8_t test_vcmulq_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)257{258#ifdef POLYMORPHIC259 return vcmulq_x(a, b, p);260#else261 return vcmulq_x_f16(a, b, p);262#endif263}264 265// CHECK-LABEL: @test_vcmulq_x_f32(266// CHECK-NEXT: entry:267// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32268// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])269// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])270// CHECK-NEXT: ret <4 x float> [[TMP2]]271//272float32x4_t test_vcmulq_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)273{274#ifdef POLYMORPHIC275 return vcmulq_x(a, b, p);276#else277 return vcmulq_x_f32(a, b, p);278#endif279}280 281// CHECK-LABEL: @test_vcmulq_rot90_x_f16(282// CHECK-NEXT: entry:283// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32284// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])285// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])286// CHECK-NEXT: ret <8 x half> [[TMP2]]287//288float16x8_t test_vcmulq_rot90_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)289{290#ifdef POLYMORPHIC291 return vcmulq_rot90_x(a, b, p);292#else293 return vcmulq_rot90_x_f16(a, b, p);294#endif295}296 297// CHECK-LABEL: @test_vcmulq_rot90_x_f32(298// CHECK-NEXT: entry:299// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32300// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])301// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])302// CHECK-NEXT: ret <4 x float> [[TMP2]]303//304float32x4_t test_vcmulq_rot90_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)305{306#ifdef POLYMORPHIC307 return vcmulq_rot90_x(a, b, p);308#else309 return vcmulq_rot90_x_f32(a, b, p);310#endif311}312 313// CHECK-LABEL: @test_vcmulq_rot180_x_f16(314// CHECK-NEXT: entry:315// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32316// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])317// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 2, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])318// CHECK-NEXT: ret <8 x half> [[TMP2]]319//320float16x8_t test_vcmulq_rot180_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)321{322#ifdef POLYMORPHIC323 return vcmulq_rot180_x(a, b, p);324#else325 return vcmulq_rot180_x_f16(a, b, p);326#endif327}328 329// CHECK-LABEL: @test_vcmulq_rot180_x_f32(330// CHECK-NEXT: entry:331// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32332// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])333// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 2, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])334// CHECK-NEXT: ret <4 x float> [[TMP2]]335//336float32x4_t test_vcmulq_rot180_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)337{338#ifdef POLYMORPHIC339 return vcmulq_rot180_x(a, b, p);340#else341 return vcmulq_rot180_x_f32(a, b, p);342#endif343}344 345// CHECK-LABEL: @test_vcmulq_rot270_x_f16(346// CHECK-NEXT: entry:347// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32348// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])349// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 3, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])350// CHECK-NEXT: ret <8 x half> [[TMP2]]351//352float16x8_t test_vcmulq_rot270_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)353{354#ifdef POLYMORPHIC355 return vcmulq_rot270_x(a, b, p);356#else357 return vcmulq_rot270_x_f16(a, b, p);358#endif359}360 361// CHECK-LABEL: @test_vcmulq_rot270_x_f32(362// CHECK-NEXT: entry:363// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32364// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])365// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 3, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])366// CHECK-NEXT: ret <4 x float> [[TMP2]]367//368float32x4_t test_vcmulq_rot270_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)369{370#ifdef POLYMORPHIC371 return vcmulq_rot270_x(a, b, p);372#else373 return vcmulq_rot270_x_f32(a, b, p);374#endif375}376