110 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s3// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -DPOLYMORPHIC -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s4 5// REQUIRES: aarch64-registered-target || arm-registered-target6 7#include <arm_mve.h>8 9// CHECK-LABEL: @test_vminaq_s8(10// CHECK-NEXT: entry:11// CHECK-NEXT: [[TMP0:%.*]] = icmp slt <16 x i8> [[B:%.*]], zeroinitializer12// CHECK-NEXT: [[TMP1:%.*]] = sub <16 x i8> zeroinitializer, [[B]]13// CHECK-NEXT: [[TMP2:%.*]] = select <16 x i1> [[TMP0]], <16 x i8> [[TMP1]], <16 x i8> [[B]]14// CHECK-NEXT: [[TMP3:%.*]] = icmp ule <16 x i8> [[A:%.*]], [[TMP2]]15// CHECK-NEXT: [[TMP4:%.*]] = select <16 x i1> [[TMP3]], <16 x i8> [[A]], <16 x i8> [[TMP2]]16// CHECK-NEXT: ret <16 x i8> [[TMP4]]17//18uint8x16_t test_vminaq_s8(uint8x16_t a, int8x16_t b)19{20#ifdef POLYMORPHIC21 return vminaq(a, b);22#else /* POLYMORPHIC */23 return vminaq_s8(a, b);24#endif /* POLYMORPHIC */25}26 27// CHECK-LABEL: @test_vminaq_s16(28// CHECK-NEXT: entry:29// CHECK-NEXT: [[TMP0:%.*]] = icmp slt <8 x i16> [[B:%.*]], zeroinitializer30// CHECK-NEXT: [[TMP1:%.*]] = sub <8 x i16> zeroinitializer, [[B]]31// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP0]], <8 x i16> [[TMP1]], <8 x i16> [[B]]32// CHECK-NEXT: [[TMP3:%.*]] = icmp ule <8 x i16> [[A:%.*]], [[TMP2]]33// CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[A]], <8 x i16> [[TMP2]]34// CHECK-NEXT: ret <8 x i16> [[TMP4]]35//36uint16x8_t test_vminaq_s16(uint16x8_t a, int16x8_t b)37{38#ifdef POLYMORPHIC39 return vminaq(a, b);40#else /* POLYMORPHIC */41 return vminaq_s16(a, b);42#endif /* POLYMORPHIC */43}44 45// CHECK-LABEL: @test_vminaq_s32(46// CHECK-NEXT: entry:47// CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer48// CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> zeroinitializer, [[B]]49// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[TMP1]], <4 x i32> [[B]]50// CHECK-NEXT: [[TMP3:%.*]] = icmp ule <4 x i32> [[A:%.*]], [[TMP2]]51// CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[A]], <4 x i32> [[TMP2]]52// CHECK-NEXT: ret <4 x i32> [[TMP4]]53//54uint32x4_t test_vminaq_s32(uint32x4_t a, int32x4_t b)55{56#ifdef POLYMORPHIC57 return vminaq(a, b);58#else /* POLYMORPHIC */59 return vminaq_s32(a, b);60#endif /* POLYMORPHIC */61}62 63// CHECK-LABEL: @test_vminaq_m_s8(64// CHECK-NEXT: entry:65// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i3266// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])67// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])68// CHECK-NEXT: ret <16 x i8> [[TMP2]]69//70uint8x16_t test_vminaq_m_s8(uint8x16_t a, int8x16_t b, mve_pred16_t p)71{72#ifdef POLYMORPHIC73 return vminaq_m(a, b, p);74#else /* POLYMORPHIC */75 return vminaq_m_s8(a, b, p);76#endif /* POLYMORPHIC */77}78 79// CHECK-LABEL: @test_vminaq_m_s16(80// CHECK-NEXT: entry:81// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i3282// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])83// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])84// CHECK-NEXT: ret <8 x i16> [[TMP2]]85//86uint16x8_t test_vminaq_m_s16(uint16x8_t a, int16x8_t b, mve_pred16_t p)87{88#ifdef POLYMORPHIC89 return vminaq_m(a, b, p);90#else /* POLYMORPHIC */91 return vminaq_m_s16(a, b, p);92#endif /* POLYMORPHIC */93}94 95// CHECK-LABEL: @test_vminaq_m_s32(96// CHECK-NEXT: entry:97// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i3298// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])99// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])100// CHECK-NEXT: ret <4 x i32> [[TMP2]]101//102uint32x4_t test_vminaq_m_s32(uint32x4_t a, int32x4_t b, mve_pred16_t p)103{104#ifdef POLYMORPHIC105 return vminaq_m(a, b, p);106#else /* POLYMORPHIC */107 return vminaq_m_s32(a, b, p);108#endif /* POLYMORPHIC */109}110