1298 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s3// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s4 5// REQUIRES: aarch64-registered-target || arm-registered-target6 7#include <arm_mve.h>8 9// CHECK-LABEL: @test_vmlaldavaq_s16(10// CHECK-NEXT: entry:11// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 3212// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i3213// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i3214// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]])15// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 116// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i6417// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 3218// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 019// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i6420// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]21// CHECK-NEXT: ret i64 [[TMP9]]22//23int64_t test_vmlaldavaq_s16(int64_t a, int16x8_t b, int16x8_t c) {24#ifdef POLYMORPHIC25 return vmlaldavaq(a, b, c);26#else27 return vmlaldavaq_s16(a, b, c);28#endif29}30 31// CHECK-LABEL: @test_vmlaldavaq_s32(32// CHECK-NEXT: entry:33// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 3234// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i3235// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i3236// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]])37// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 138// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i6439// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 3240// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 041// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i6442// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]43// CHECK-NEXT: ret i64 [[TMP9]]44//45int64_t test_vmlaldavaq_s32(int64_t a, int32x4_t b, int32x4_t c) {46#ifdef POLYMORPHIC47 return vmlaldavaq(a, b, c);48#else49 return vmlaldavaq_s32(a, b, c);50#endif51}52 53// CHECK-LABEL: @test_vmlaldavaq_u16(54// CHECK-NEXT: entry:55// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 3256// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i3257// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i3258// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]])59// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 160// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i6461// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 3262// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 063// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i6464// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]65// CHECK-NEXT: ret i64 [[TMP9]]66//67uint64_t test_vmlaldavaq_u16(uint64_t a, uint16x8_t b, uint16x8_t c) {68#ifdef POLYMORPHIC69 return vmlaldavaq(a, b, c);70#else71 return vmlaldavaq_u16(a, b, c);72#endif73}74 75// CHECK-LABEL: @test_vmlaldavaq_u32(76// CHECK-NEXT: entry:77// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 3278// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i3279// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i3280// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]])81// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 182// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i6483// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 3284// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 085// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i6486// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]87// CHECK-NEXT: ret i64 [[TMP9]]88//89uint64_t test_vmlaldavaq_u32(uint64_t a, uint32x4_t b, uint32x4_t c) {90#ifdef POLYMORPHIC91 return vmlaldavaq(a, b, c);92#else93 return vmlaldavaq_u32(a, b, c);94#endif95}96 97// CHECK-LABEL: @test_vmlaldavaxq_s16(98// CHECK-NEXT: entry:99// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32100// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32101// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32102// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 [[TMP2]], i32 [[TMP1]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]])103// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1104// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64105// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32106// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0107// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64108// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]109// CHECK-NEXT: ret i64 [[TMP9]]110//111int64_t test_vmlaldavaxq_s16(int64_t a, int16x8_t b, int16x8_t c) {112#ifdef POLYMORPHIC113 return vmlaldavaxq(a, b, c);114#else115 return vmlaldavaxq_s16(a, b, c);116#endif117}118 119// CHECK-LABEL: @test_vmlaldavaxq_s32(120// CHECK-NEXT: entry:121// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32122// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32123// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32124// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]])125// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1126// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64127// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32128// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0129// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64130// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]131// CHECK-NEXT: ret i64 [[TMP9]]132//133int64_t test_vmlaldavaxq_s32(int64_t a, int32x4_t b, int32x4_t c) {134#ifdef POLYMORPHIC135 return vmlaldavaxq(a, b, c);136#else137 return vmlaldavaxq_s32(a, b, c);138#endif139}140 141// CHECK-LABEL: @test_vmlsldavaq_s16(142// CHECK-NEXT: entry:143// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32144// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32145// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32146// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 [[TMP2]], i32 [[TMP1]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]])147// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1148// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64149// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32150// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0151// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64152// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]153// CHECK-NEXT: ret i64 [[TMP9]]154//155int64_t test_vmlsldavaq_s16(int64_t a, int16x8_t b, int16x8_t c) {156#ifdef POLYMORPHIC157 return vmlsldavaq(a, b, c);158#else159 return vmlsldavaq_s16(a, b, c);160#endif161}162 163// CHECK-LABEL: @test_vmlsldavaq_s32(164// CHECK-NEXT: entry:165// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32166// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32167// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32168// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]])169// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1170// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64171// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32172// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0173// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64174// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]175// CHECK-NEXT: ret i64 [[TMP9]]176//177int64_t test_vmlsldavaq_s32(int64_t a, int32x4_t b, int32x4_t c) {178#ifdef POLYMORPHIC179 return vmlsldavaq(a, b, c);180#else181 return vmlsldavaq_s32(a, b, c);182#endif183}184 185// CHECK-LABEL: @test_vmlsldaxvaq_s16(186// CHECK-NEXT: entry:187// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32188// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32189// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32190// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 [[TMP2]], i32 [[TMP1]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]])191// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1192// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64193// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32194// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0195// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64196// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]197// CHECK-NEXT: ret i64 [[TMP9]]198//199int64_t test_vmlsldaxvaq_s16(int64_t a, int16x8_t b, int16x8_t c) {200#ifdef POLYMORPHIC201 return vmlsldavaxq(a, b, c);202#else203 return vmlsldavaxq_s16(a, b, c);204#endif205}206 207// CHECK-LABEL: @test_vmlsldavaxq_s32(208// CHECK-NEXT: entry:209// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32210// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32211// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32212// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]])213// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1214// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64215// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32216// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0217// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64218// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]219// CHECK-NEXT: ret i64 [[TMP9]]220//221int64_t test_vmlsldavaxq_s32(int64_t a, int32x4_t b, int32x4_t c) {222#ifdef POLYMORPHIC223 return vmlsldavaxq(a, b, c);224#else225 return vmlsldavaxq_s32(a, b, c);226#endif227}228 229// CHECK-LABEL: @test_vrmlaldavhaq_s32(230// CHECK-NEXT: entry:231// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32232// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32233// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32234// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.v4i32(i32 0, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]])235// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1236// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64237// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32238// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0239// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64240// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]241// CHECK-NEXT: ret i64 [[TMP9]]242//243int64_t test_vrmlaldavhaq_s32(int64_t a, int32x4_t b, int32x4_t c) {244#ifdef POLYMORPHIC245 return vrmlaldavhaq(a, b, c);246#else247 return vrmlaldavhaq_s32(a, b, c);248#endif249}250 251// CHECK-LABEL: @test_vrmlaldavhaq_u32(252// CHECK-NEXT: entry:253// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32254// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32255// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32256// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.v4i32(i32 1, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]])257// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1258// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64259// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32260// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0261// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64262// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]263// CHECK-NEXT: ret i64 [[TMP9]]264//265uint64_t test_vrmlaldavhaq_u32(uint64_t a, uint32x4_t b, uint32x4_t c) {266#ifdef POLYMORPHIC267 return vrmlaldavhaq(a, b, c);268#else269 return vrmlaldavhaq_u32(a, b, c);270#endif271}272 273// CHECK-LABEL: @test_vrmlaldavhaxq_s32(274// CHECK-NEXT: entry:275// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32276// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32277// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32278// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.v4i32(i32 0, i32 0, i32 1, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]])279// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1280// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64281// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32282// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0283// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64284// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]285// CHECK-NEXT: ret i64 [[TMP9]]286//287int64_t test_vrmlaldavhaxq_s32(int64_t a, int32x4_t b, int32x4_t c) {288#ifdef POLYMORPHIC289 return vrmlaldavhaxq(a, b, c);290#else291 return vrmlaldavhaxq_s32(a, b, c);292#endif293}294 295// CHECK-LABEL: @test_vrmlsldavhaq_s32(296// CHECK-NEXT: entry:297// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32298// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32299// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32300// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.v4i32(i32 0, i32 1, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]])301// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1302// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64303// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32304// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0305// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64306// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]307// CHECK-NEXT: ret i64 [[TMP9]]308//309int64_t test_vrmlsldavhaq_s32(int64_t a, int32x4_t b, int32x4_t c) {310#ifdef POLYMORPHIC311 return vrmlsldavhaq(a, b, c);312#else313 return vrmlsldavhaq_s32(a, b, c);314#endif315}316 317// CHECK-LABEL: @test_vrmlsldavhaxq_s32(318// CHECK-NEXT: entry:319// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32320// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32321// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32322// CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.v4i32(i32 0, i32 1, i32 1, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]])323// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1324// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64325// CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32326// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0327// CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64328// CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]329// CHECK-NEXT: ret i64 [[TMP9]]330//331int64_t test_vrmlsldavhaxq_s32(int64_t a, int32x4_t b, int32x4_t c) {332#ifdef POLYMORPHIC333 return vrmlsldavhaxq(a, b, c);334#else335 return vrmlsldavhaxq_s32(a, b, c);336#endif337}338 339// CHECK-LABEL: @test_vmlaldavaq_p_s16(340// CHECK-NEXT: entry:341// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32342// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32343// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32344// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32345// CHECK-NEXT: [[TMP4:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP3]])346// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v8i16.v8i1(i32 0, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]], <8 x i1> [[TMP4]])347// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1348// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64349// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32350// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0351// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64352// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]353// CHECK-NEXT: ret i64 [[TMP11]]354//355int64_t test_vmlaldavaq_p_s16(int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) {356#ifdef POLYMORPHIC357 return vmlaldavaq_p(a, b, c, p);358#else359 return vmlaldavaq_p_s16(a, b, c, p);360#endif361}362 363// CHECK-LABEL: @test_vmlaldavaq_p_s32(364// CHECK-NEXT: entry:365// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32366// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32367// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32368// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32369// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP3]])370// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]], <4 x i1> [[TMP4]])371// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1372// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64373// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32374// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0375// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64376// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]377// CHECK-NEXT: ret i64 [[TMP11]]378//379int64_t test_vmlaldavaq_p_s32(int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) {380#ifdef POLYMORPHIC381 return vmlaldavaq_p(a, b, c, p);382#else383 return vmlaldavaq_p_s32(a, b, c, p);384#endif385}386 387// CHECK-LABEL: @test_vmlaldavaq_p_u16(388// CHECK-NEXT: entry:389// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32390// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32391// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32392// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32393// CHECK-NEXT: [[TMP4:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP3]])394// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v8i16.v8i1(i32 1, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]], <8 x i1> [[TMP4]])395// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1396// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64397// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32398// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0399// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64400// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]401// CHECK-NEXT: ret i64 [[TMP11]]402//403uint64_t test_vmlaldavaq_p_u16(uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) {404#ifdef POLYMORPHIC405 return vmlaldavaq_p(a, b, c, p);406#else407 return vmlaldavaq_p_u16(a, b, c, p);408#endif409}410 411// CHECK-LABEL: @test_vmlaldavaq_p_u32(412// CHECK-NEXT: entry:413// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32414// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32415// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32416// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32417// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP3]])418// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v4i32.v4i1(i32 1, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]], <4 x i1> [[TMP4]])419// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1420// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64421// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32422// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0423// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64424// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]425// CHECK-NEXT: ret i64 [[TMP11]]426//427uint64_t test_vmlaldavaq_p_u32(uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) {428#ifdef POLYMORPHIC429 return vmlaldavaq_p(a, b, c, p);430#else431 return vmlaldavaq_p_u32(a, b, c, p);432#endif433}434 435// CHECK-LABEL: @test_vmlaldavaxq_p_s16(436// CHECK-NEXT: entry:437// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32438// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32439// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32440// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32441// CHECK-NEXT: [[TMP4:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP3]])442// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v8i16.v8i1(i32 0, i32 0, i32 1, i32 [[TMP2]], i32 [[TMP1]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]], <8 x i1> [[TMP4]])443// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1444// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64445// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32446// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0447// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64448// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]449// CHECK-NEXT: ret i64 [[TMP11]]450//451int64_t test_vmlaldavaxq_p_s16(int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) {452#ifdef POLYMORPHIC453 return vmlaldavaxq_p(a, b, c, p);454#else455 return vmlaldavaxq_p_s16(a, b, c, p);456#endif457}458 459// CHECK-LABEL: @test_vmlaldavaxq_p_s32(460// CHECK-NEXT: entry:461// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32462// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32463// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32464// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32465// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP3]])466// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 1, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]], <4 x i1> [[TMP4]])467// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1468// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64469// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32470// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0471// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64472// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]473// CHECK-NEXT: ret i64 [[TMP11]]474//475int64_t test_vmlaldavaxq_p_s32(int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) {476#ifdef POLYMORPHIC477 return vmlaldavaxq_p(a, b, c, p);478#else479 return vmlaldavaxq_p_s32(a, b, c, p);480#endif481}482 483// CHECK-LABEL: @test_vmlsldavaq_p_s16(484// CHECK-NEXT: entry:485// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32486// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32487// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32488// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32489// CHECK-NEXT: [[TMP4:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP3]])490// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v8i16.v8i1(i32 0, i32 1, i32 0, i32 [[TMP2]], i32 [[TMP1]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]], <8 x i1> [[TMP4]])491// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1492// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64493// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32494// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0495// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64496// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]497// CHECK-NEXT: ret i64 [[TMP11]]498//499int64_t test_vmlsldavaq_p_s16(int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) {500#ifdef POLYMORPHIC501 return vmlsldavaq_p(a, b, c, p);502#else503 return vmlsldavaq_p_s16(a, b, c, p);504#endif505}506 507// CHECK-LABEL: @test_vmlsldavaq_p_s32(508// CHECK-NEXT: entry:509// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32510// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32511// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32512// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32513// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP3]])514// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v4i32.v4i1(i32 0, i32 1, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]], <4 x i1> [[TMP4]])515// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1516// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64517// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32518// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0519// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64520// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]521// CHECK-NEXT: ret i64 [[TMP11]]522//523int64_t test_vmlsldavaq_p_s32(int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) {524#ifdef POLYMORPHIC525 return vmlsldavaq_p(a, b, c, p);526#else527 return vmlsldavaq_p_s32(a, b, c, p);528#endif529}530 531// CHECK-LABEL: @test_vmlsldaxvaq_p_s16(532// CHECK-NEXT: entry:533// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32534// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32535// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32536// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32537// CHECK-NEXT: [[TMP4:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP3]])538// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v8i16.v8i1(i32 0, i32 1, i32 1, i32 [[TMP2]], i32 [[TMP1]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]], <8 x i1> [[TMP4]])539// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1540// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64541// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32542// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0543// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64544// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]545// CHECK-NEXT: ret i64 [[TMP11]]546//547int64_t test_vmlsldaxvaq_p_s16(int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) {548#ifdef POLYMORPHIC549 return vmlsldavaxq_p(a, b, c, p);550#else551 return vmlsldavaxq_p_s16(a, b, c, p);552#endif553}554 555// CHECK-LABEL: @test_vmlsldavaxq_p_s32(556// CHECK-NEXT: entry:557// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32558// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32559// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32560// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32561// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP3]])562// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v4i32.v4i1(i32 0, i32 1, i32 1, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]], <4 x i1> [[TMP4]])563// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1564// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64565// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32566// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0567// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64568// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]569// CHECK-NEXT: ret i64 [[TMP11]]570//571int64_t test_vmlsldavaxq_p_s32(int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) {572#ifdef POLYMORPHIC573 return vmlsldavaxq_p(a, b, c, p);574#else575 return vmlsldavaxq_p_s32(a, b, c, p);576#endif577}578 579// CHECK-LABEL: @test_vrmlaldavhaq_p_s32(580// CHECK-NEXT: entry:581// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32582// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32583// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32584// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32585// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP3]])586// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.predicated.v4i32.v4i1(i32 0, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]], <4 x i1> [[TMP4]])587// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1588// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64589// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32590// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0591// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64592// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]593// CHECK-NEXT: ret i64 [[TMP11]]594//595int64_t test_vrmlaldavhaq_p_s32(int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) {596#ifdef POLYMORPHIC597 return vrmlaldavhaq_p(a, b, c, p);598#else599 return vrmlaldavhaq_p_s32(a, b, c, p);600#endif601}602 603// CHECK-LABEL: @test_vrmlaldavhaq_p_u32(604// CHECK-NEXT: entry:605// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32606// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32607// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32608// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32609// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP3]])610// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.predicated.v4i32.v4i1(i32 1, i32 0, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]], <4 x i1> [[TMP4]])611// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1612// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64613// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32614// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0615// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64616// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]617// CHECK-NEXT: ret i64 [[TMP11]]618//619uint64_t test_vrmlaldavhaq_p_u32(uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) {620#ifdef POLYMORPHIC621 return vrmlaldavhaq_p(a, b, c, p);622#else623 return vrmlaldavhaq_p_u32(a, b, c, p);624#endif625}626 627// CHECK-LABEL: @test_vrmlaldavhaxq_p_s32(628// CHECK-NEXT: entry:629// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32630// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32631// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32632// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32633// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP3]])634// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.predicated.v4i32.v4i1(i32 0, i32 0, i32 1, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]], <4 x i1> [[TMP4]])635// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1636// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64637// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32638// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0639// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64640// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]641// CHECK-NEXT: ret i64 [[TMP11]]642//643int64_t test_vrmlaldavhaxq_p_s32(int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) {644#ifdef POLYMORPHIC645 return vrmlaldavhaxq_p(a, b, c, p);646#else647 return vrmlaldavhaxq_p_s32(a, b, c, p);648#endif649}650 651// CHECK-LABEL: @test_vrmlsldavhaq_p_s32(652// CHECK-NEXT: entry:653// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32654// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32655// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32656// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32657// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP3]])658// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.predicated.v4i32.v4i1(i32 0, i32 1, i32 0, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]], <4 x i1> [[TMP4]])659// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1660// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64661// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32662// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0663// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64664// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]665// CHECK-NEXT: ret i64 [[TMP11]]666//667int64_t test_vrmlsldavhaq_p_s32(int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) {668#ifdef POLYMORPHIC669 return vrmlsldavhaq_p(a, b, c, p);670#else671 return vrmlsldavhaq_p_s32(a, b, c, p);672#endif673}674 675// CHECK-LABEL: @test_vrmlsldavhaxq_p_s32(676// CHECK-NEXT: entry:677// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32678// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32679// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A]] to i32680// CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[P:%.*]] to i32681// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP3]])682// CHECK-NEXT: [[TMP5:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.predicated.v4i32.v4i1(i32 0, i32 1, i32 1, i32 [[TMP2]], i32 [[TMP1]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]], <4 x i1> [[TMP4]])683// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP5]], 1684// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64685// CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32686// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i32 } [[TMP5]], 0687// CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64688// CHECK-NEXT: [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]689// CHECK-NEXT: ret i64 [[TMP11]]690//691int64_t test_vrmlsldavhaxq_p_s32(int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) {692#ifdef POLYMORPHIC693 return vrmlsldavhaxq_p(a, b, c, p);694#else695 return vrmlsldavhaxq_p_s32(a, b, c, p);696#endif697}698 699// CHECK-LABEL: @test_vmlaldavq_s16(700// CHECK-NEXT: entry:701// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])702// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1703// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64704// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32705// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0706// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64707// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]708// CHECK-NEXT: ret i64 [[TMP6]]709//710int64_t test_vmlaldavq_s16(int16x8_t a, int16x8_t b) {711#ifdef POLYMORPHIC712 return vmlaldavq(a, b);713#else714 return vmlaldavq_s16(a, b);715#endif716}717 718// CHECK-LABEL: @test_vmlaldavq_s32(719// CHECK-NEXT: entry:720// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])721// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1722// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64723// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32724// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0725// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64726// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]727// CHECK-NEXT: ret i64 [[TMP6]]728//729int64_t test_vmlaldavq_s32(int32x4_t a, int32x4_t b) {730#ifdef POLYMORPHIC731 return vmlaldavq(a, b);732#else733 return vmlaldavq_s32(a, b);734#endif735}736 737// CHECK-LABEL: @test_vmlaldavq_u16(738// CHECK-NEXT: entry:739// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])740// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1741// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64742// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32743// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0744// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64745// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]746// CHECK-NEXT: ret i64 [[TMP6]]747//748uint64_t test_vmlaldavq_u16(uint16x8_t a, uint16x8_t b) {749#ifdef POLYMORPHIC750 return vmlaldavq(a, b);751#else752 return vmlaldavq_u16(a, b);753#endif754}755 756// CHECK-LABEL: @test_vmlaldavq_u32(757// CHECK-NEXT: entry:758// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])759// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1760// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64761// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32762// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0763// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64764// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]765// CHECK-NEXT: ret i64 [[TMP6]]766//767uint64_t test_vmlaldavq_u32(uint32x4_t a, uint32x4_t b) {768#ifdef POLYMORPHIC769 return vmlaldavq(a, b);770#else771 return vmlaldavq_u32(a, b);772#endif773}774 775// CHECK-LABEL: @test_vmlaldavxq_s16(776// CHECK-NEXT: entry:777// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])778// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1779// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64780// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32781// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0782// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64783// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]784// CHECK-NEXT: ret i64 [[TMP6]]785//786int64_t test_vmlaldavxq_s16(int16x8_t a, int16x8_t b) {787#ifdef POLYMORPHIC788 return vmlaldavxq(a, b);789#else790 return vmlaldavxq_s16(a, b);791#endif792}793 794// CHECK-LABEL: @test_vmlaldavxq_s32(795// CHECK-NEXT: entry:796// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])797// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1798// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64799// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32800// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0801// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64802// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]803// CHECK-NEXT: ret i64 [[TMP6]]804//805int64_t test_vmlaldavxq_s32(int32x4_t a, int32x4_t b) {806#ifdef POLYMORPHIC807 return vmlaldavxq(a, b);808#else809 return vmlaldavxq_s32(a, b);810#endif811}812 813// CHECK-LABEL: @test_vmlsldavq_s16(814// CHECK-NEXT: entry:815// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])816// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1817// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64818// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32819// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0820// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64821// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]822// CHECK-NEXT: ret i64 [[TMP6]]823//824int64_t test_vmlsldavq_s16(int16x8_t a, int16x8_t b) {825#ifdef POLYMORPHIC826 return vmlsldavq(a, b);827#else828 return vmlsldavq_s16(a, b);829#endif830}831 832// CHECK-LABEL: @test_vmlsldavq_s32(833// CHECK-NEXT: entry:834// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])835// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1836// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64837// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32838// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0839// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64840// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]841// CHECK-NEXT: ret i64 [[TMP6]]842//843int64_t test_vmlsldavq_s32(int32x4_t a, int32x4_t b) {844#ifdef POLYMORPHIC845 return vmlsldavq(a, b);846#else847 return vmlsldavq_s32(a, b);848#endif849}850 851// CHECK-LABEL: @test_vmlsldavxvq_s16(852// CHECK-NEXT: entry:853// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])854// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1855// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64856// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32857// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0858// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64859// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]860// CHECK-NEXT: ret i64 [[TMP6]]861//862int64_t test_vmlsldavxvq_s16(int16x8_t a, int16x8_t b) {863#ifdef POLYMORPHIC864 return vmlsldavxq(a, b);865#else866 return vmlsldavxq_s16(a, b);867#endif868}869 870// CHECK-LABEL: @test_vmlsldavxq_s32(871// CHECK-NEXT: entry:872// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])873// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1874// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64875// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32876// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0877// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64878// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]879// CHECK-NEXT: ret i64 [[TMP6]]880//881int64_t test_vmlsldavxq_s32(int32x4_t a, int32x4_t b) {882#ifdef POLYMORPHIC883 return vmlsldavxq(a, b);884#else885 return vmlsldavxq_s32(a, b);886#endif887}888 889// CHECK-LABEL: @test_vrmlaldavhq_s32(890// CHECK-NEXT: entry:891// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.v4i32(i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])892// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1893// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64894// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32895// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0896// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64897// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]898// CHECK-NEXT: ret i64 [[TMP6]]899//900int64_t test_vrmlaldavhq_s32(int32x4_t a, int32x4_t b) {901#ifdef POLYMORPHIC902 return vrmlaldavhq(a, b);903#else904 return vrmlaldavhq_s32(a, b);905#endif906}907 908// CHECK-LABEL: @test_vrmlaldavhq_u32(909// CHECK-NEXT: entry:910// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.v4i32(i32 1, i32 0, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])911// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1912// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64913// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32914// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0915// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64916// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]917// CHECK-NEXT: ret i64 [[TMP6]]918//919uint64_t test_vrmlaldavhq_u32(uint32x4_t a, uint32x4_t b) {920#ifdef POLYMORPHIC921 return vrmlaldavhq(a, b);922#else923 return vrmlaldavhq_u32(a, b);924#endif925}926 927// CHECK-LABEL: @test_vrmlaldavhxq_s32(928// CHECK-NEXT: entry:929// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.v4i32(i32 0, i32 0, i32 1, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])930// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1931// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64932// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32933// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0934// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64935// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]936// CHECK-NEXT: ret i64 [[TMP6]]937//938int64_t test_vrmlaldavhxq_s32(int32x4_t a, int32x4_t b) {939#ifdef POLYMORPHIC940 return vrmlaldavhxq(a, b);941#else942 return vrmlaldavhxq_s32(a, b);943#endif944}945 946// CHECK-LABEL: @test_vrmlsldavhq_s32(947// CHECK-NEXT: entry:948// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.v4i32(i32 0, i32 1, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])949// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1950// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64951// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32952// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0953// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64954// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]955// CHECK-NEXT: ret i64 [[TMP6]]956//957int64_t test_vrmlsldavhq_s32(int32x4_t a, int32x4_t b) {958#ifdef POLYMORPHIC959 return vrmlsldavhq(a, b);960#else961 return vrmlsldavhq_s32(a, b);962#endif963}964 965// CHECK-LABEL: @test_vrmlsldavhxq_s32(966// CHECK-NEXT: entry:967// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.v4i32(i32 0, i32 1, i32 1, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])968// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1969// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64970// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32971// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0972// CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64973// CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]974// CHECK-NEXT: ret i64 [[TMP6]]975//976int64_t test_vrmlsldavhxq_s32(int32x4_t a, int32x4_t b) {977#ifdef POLYMORPHIC978 return vrmlsldavhxq(a, b);979#else980 return vrmlsldavhxq_s32(a, b);981#endif982}983 984// CHECK-LABEL: @test_vmlaldavq_p_s16(985// CHECK-NEXT: entry:986// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32987// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])988// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v8i16.v8i1(i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])989// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 1990// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64991// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 32992// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 0993// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64994// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]995// CHECK-NEXT: ret i64 [[TMP8]]996//997int64_t test_vmlaldavq_p_s16(int16x8_t a, int16x8_t b, mve_pred16_t p) {998#ifdef POLYMORPHIC999 return vmlaldavq_p(a, b, p);1000#else1001 return vmlaldavq_p_s16(a, b, p);1002#endif1003}1004 1005// CHECK-LABEL: @test_vmlaldavq_p_s32(1006// CHECK-NEXT: entry:1007// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321008// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])1009// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])1010// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11011// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641012// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321013// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01014// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641015// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1016// CHECK-NEXT: ret i64 [[TMP8]]1017//1018int64_t test_vmlaldavq_p_s32(int32x4_t a, int32x4_t b, mve_pred16_t p) {1019#ifdef POLYMORPHIC1020 return vmlaldavq_p(a, b, p);1021#else1022 return vmlaldavq_p_s32(a, b, p);1023#endif1024}1025 1026// CHECK-LABEL: @test_vmlaldavq_p_u16(1027// CHECK-NEXT: entry:1028// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321029// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])1030// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v8i16.v8i1(i32 1, i32 0, i32 0, i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])1031// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11032// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641033// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321034// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01035// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641036// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1037// CHECK-NEXT: ret i64 [[TMP8]]1038//1039uint64_t test_vmlaldavq_p_u16(uint16x8_t a, uint16x8_t b, mve_pred16_t p) {1040#ifdef POLYMORPHIC1041 return vmlaldavq_p(a, b, p);1042#else1043 return vmlaldavq_p_u16(a, b, p);1044#endif1045}1046 1047// CHECK-LABEL: @test_vmlaldavq_p_u32(1048// CHECK-NEXT: entry:1049// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321050// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])1051// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v4i32.v4i1(i32 1, i32 0, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])1052// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11053// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641054// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321055// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01056// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641057// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1058// CHECK-NEXT: ret i64 [[TMP8]]1059//1060uint64_t test_vmlaldavq_p_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p) {1061#ifdef POLYMORPHIC1062 return vmlaldavq_p(a, b, p);1063#else1064 return vmlaldavq_p_u32(a, b, p);1065#endif1066}1067 1068// CHECK-LABEL: @test_vmlaldavxq_p_s16(1069// CHECK-NEXT: entry:1070// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321071// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])1072// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v8i16.v8i1(i32 0, i32 0, i32 1, i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])1073// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11074// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641075// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321076// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01077// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641078// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1079// CHECK-NEXT: ret i64 [[TMP8]]1080//1081int64_t test_vmlaldavxq_p_s16(int16x8_t a, int16x8_t b, mve_pred16_t p) {1082#ifdef POLYMORPHIC1083 return vmlaldavxq_p(a, b, p);1084#else1085 return vmlaldavxq_p_s16(a, b, p);1086#endif1087}1088 1089// CHECK-LABEL: @test_vmlaldavxq_p_s32(1090// CHECK-NEXT: entry:1091// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321092// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])1093// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 1, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])1094// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11095// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641096// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321097// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01098// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641099// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1100// CHECK-NEXT: ret i64 [[TMP8]]1101//1102int64_t test_vmlaldavxq_p_s32(int32x4_t a, int32x4_t b, mve_pred16_t p) {1103#ifdef POLYMORPHIC1104 return vmlaldavxq_p(a, b, p);1105#else1106 return vmlaldavxq_p_s32(a, b, p);1107#endif1108}1109 1110// CHECK-LABEL: @test_vmlsldavq_p_s16(1111// CHECK-NEXT: entry:1112// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321113// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])1114// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v8i16.v8i1(i32 0, i32 1, i32 0, i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])1115// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11116// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641117// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321118// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01119// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641120// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1121// CHECK-NEXT: ret i64 [[TMP8]]1122//1123int64_t test_vmlsldavq_p_s16(int16x8_t a, int16x8_t b, mve_pred16_t p) {1124#ifdef POLYMORPHIC1125 return vmlsldavq_p(a, b, p);1126#else1127 return vmlsldavq_p_s16(a, b, p);1128#endif1129}1130 1131// CHECK-LABEL: @test_vmlsldavq_p_s32(1132// CHECK-NEXT: entry:1133// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321134// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])1135// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v4i32.v4i1(i32 0, i32 1, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])1136// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11137// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641138// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321139// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01140// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641141// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1142// CHECK-NEXT: ret i64 [[TMP8]]1143//1144int64_t test_vmlsldavq_p_s32(int32x4_t a, int32x4_t b, mve_pred16_t p) {1145#ifdef POLYMORPHIC1146 return vmlsldavq_p(a, b, p);1147#else1148 return vmlsldavq_p_s32(a, b, p);1149#endif1150}1151 1152// CHECK-LABEL: @test_vmlsldaxvq_p_s16(1153// CHECK-NEXT: entry:1154// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321155// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])1156// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v8i16.v8i1(i32 0, i32 1, i32 1, i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])1157// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11158// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641159// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321160// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01161// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641162// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1163// CHECK-NEXT: ret i64 [[TMP8]]1164//1165int64_t test_vmlsldaxvq_p_s16(int16x8_t a, int16x8_t b, mve_pred16_t p) {1166#ifdef POLYMORPHIC1167 return vmlsldavxq_p(a, b, p);1168#else1169 return vmlsldavxq_p_s16(a, b, p);1170#endif1171}1172 1173// CHECK-LABEL: @test_vmlsldavxq_p_s32(1174// CHECK-NEXT: entry:1175// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321176// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])1177// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vmlldava.predicated.v4i32.v4i1(i32 0, i32 1, i32 1, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])1178// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11179// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641180// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321181// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01182// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641183// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1184// CHECK-NEXT: ret i64 [[TMP8]]1185//1186int64_t test_vmlsldavxq_p_s32(int32x4_t a, int32x4_t b, mve_pred16_t p) {1187#ifdef POLYMORPHIC1188 return vmlsldavxq_p(a, b, p);1189#else1190 return vmlsldavxq_p_s32(a, b, p);1191#endif1192}1193 1194// CHECK-LABEL: @test_vrmlaldavhq_p_s32(1195// CHECK-NEXT: entry:1196// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321197// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])1198// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.predicated.v4i32.v4i1(i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])1199// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11200// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641201// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321202// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01203// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641204// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1205// CHECK-NEXT: ret i64 [[TMP8]]1206//1207int64_t test_vrmlaldavhq_p_s32(int32x4_t a, int32x4_t b, mve_pred16_t p) {1208#ifdef POLYMORPHIC1209 return vrmlaldavhq_p(a, b, p);1210#else1211 return vrmlaldavhq_p_s32(a, b, p);1212#endif1213}1214 1215// CHECK-LABEL: @test_vrmlaldavhq_p_u32(1216// CHECK-NEXT: entry:1217// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321218// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])1219// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.predicated.v4i32.v4i1(i32 1, i32 0, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])1220// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11221// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641222// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321223// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01224// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641225// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1226// CHECK-NEXT: ret i64 [[TMP8]]1227//1228uint64_t test_vrmlaldavhq_p_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p) {1229#ifdef POLYMORPHIC1230 return vrmlaldavhq_p(a, b, p);1231#else1232 return vrmlaldavhq_p_u32(a, b, p);1233#endif1234}1235 1236// CHECK-LABEL: @test_vrmlaldavhxq_p_s32(1237// CHECK-NEXT: entry:1238// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321239// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])1240// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.predicated.v4i32.v4i1(i32 0, i32 0, i32 1, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])1241// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11242// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641243// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321244// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01245// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641246// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1247// CHECK-NEXT: ret i64 [[TMP8]]1248//1249int64_t test_vrmlaldavhxq_p_s32(int32x4_t a, int32x4_t b, mve_pred16_t p) {1250#ifdef POLYMORPHIC1251 return vrmlaldavhxq_p(a, b, p);1252#else1253 return vrmlaldavhxq_p_s32(a, b, p);1254#endif1255}1256 1257// CHECK-LABEL: @test_vrmlsldavhq_p_s32(1258// CHECK-NEXT: entry:1259// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321260// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])1261// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.predicated.v4i32.v4i1(i32 0, i32 1, i32 0, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])1262// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11263// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641264// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321265// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01266// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641267// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1268// CHECK-NEXT: ret i64 [[TMP8]]1269//1270int64_t test_vrmlsldavhq_p_s32(int32x4_t a, int32x4_t b, mve_pred16_t p) {1271#ifdef POLYMORPHIC1272 return vrmlsldavhq_p(a, b, p);1273#else1274 return vrmlsldavhq_p_s32(a, b, p);1275#endif1276}1277 1278// CHECK-LABEL: @test_vrmlsldavhxq_p_s32(1279// CHECK-NEXT: entry:1280// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i321281// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])1282// CHECK-NEXT: [[TMP2:%.*]] = call { i32, i32 } @llvm.arm.mve.vrmlldavha.predicated.v4i32.v4i1(i32 0, i32 1, i32 1, i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])1283// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP2]], 11284// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i641285// CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[TMP4]], 321286// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP2]], 01287// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i641288// CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP5]], [[TMP7]]1289// CHECK-NEXT: ret i64 [[TMP8]]1290//1291int64_t test_vrmlsldavhxq_p_s32(int32x4_t a, int32x4_t b, mve_pred16_t p) {1292#ifdef POLYMORPHIC1293 return vrmlsldavhxq_p(a, b, p);1294#else1295 return vrmlsldavhxq_p_s32(a, b, p);1296#endif1297}1298