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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s3// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s4 5// REQUIRES: aarch64-registered-target || arm-registered-target6 7#include <arm_mve.h>8 9// CHECK-LABEL: @test_vshlcq_s8(10// CHECK-NEXT: entry:11// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 412// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> [[A:%.*]], i32 [[TMP0]], i32 18)13// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <16 x i8> } [[TMP1]], 014// CHECK-NEXT: store i32 [[TMP2]], ptr [[B]], align 415// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <16 x i8> } [[TMP1]], 116// CHECK-NEXT: ret <16 x i8> [[TMP3]]17//18int8x16_t test_vshlcq_s8(int8x16_t a, uint32_t *b) {19#ifdef POLYMORPHIC20 return vshlcq(a, b, 18);21#else /* POLYMORPHIC */22 return vshlcq_s8(a, b, 18);23#endif /* POLYMORPHIC */24}25 26// CHECK-LABEL: @test_vshlcq_s16(27// CHECK-NEXT: entry:28// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 429// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> [[A:%.*]], i32 [[TMP0]], i32 16)30// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <8 x i16> } [[TMP1]], 031// CHECK-NEXT: store i32 [[TMP2]], ptr [[B]], align 432// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <8 x i16> } [[TMP1]], 133// CHECK-NEXT: ret <8 x i16> [[TMP3]]34//35int16x8_t test_vshlcq_s16(int16x8_t a, uint32_t *b) {36#ifdef POLYMORPHIC37 return vshlcq(a, b, 16);38#else /* POLYMORPHIC */39 return vshlcq_s16(a, b, 16);40#endif /* POLYMORPHIC */41}42 43// CHECK-LABEL: @test_vshlcq_s32(44// CHECK-NEXT: entry:45// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 446// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> [[A:%.*]], i32 [[TMP0]], i32 4)47// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <4 x i32> } [[TMP1]], 048// CHECK-NEXT: store i32 [[TMP2]], ptr [[B]], align 449// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <4 x i32> } [[TMP1]], 150// CHECK-NEXT: ret <4 x i32> [[TMP3]]51//52int32x4_t test_vshlcq_s32(int32x4_t a, uint32_t *b) {53#ifdef POLYMORPHIC54 return vshlcq(a, b, 4);55#else /* POLYMORPHIC */56 return vshlcq_s32(a, b, 4);57#endif /* POLYMORPHIC */58}59 60// CHECK-LABEL: @test_vshlcq_u8(61// CHECK-NEXT: entry:62// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 463// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> [[A:%.*]], i32 [[TMP0]], i32 17)64// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <16 x i8> } [[TMP1]], 065// CHECK-NEXT: store i32 [[TMP2]], ptr [[B]], align 466// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <16 x i8> } [[TMP1]], 167// CHECK-NEXT: ret <16 x i8> [[TMP3]]68//69uint8x16_t test_vshlcq_u8(uint8x16_t a, uint32_t *b) {70#ifdef POLYMORPHIC71 return vshlcq(a, b, 17);72#else /* POLYMORPHIC */73 return vshlcq_u8(a, b, 17);74#endif /* POLYMORPHIC */75}76 77// CHECK-LABEL: @test_vshlcq_u16(78// CHECK-NEXT: entry:79// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 480// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> [[A:%.*]], i32 [[TMP0]], i32 17)81// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <8 x i16> } [[TMP1]], 082// CHECK-NEXT: store i32 [[TMP2]], ptr [[B]], align 483// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <8 x i16> } [[TMP1]], 184// CHECK-NEXT: ret <8 x i16> [[TMP3]]85//86uint16x8_t test_vshlcq_u16(uint16x8_t a, uint32_t *b) {87#ifdef POLYMORPHIC88 return vshlcq(a, b, 17);89#else /* POLYMORPHIC */90 return vshlcq_u16(a, b, 17);91#endif /* POLYMORPHIC */92}93 94// CHECK-LABEL: @test_vshlcq_u32(95// CHECK-NEXT: entry:96// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 497// CHECK-NEXT: [[TMP1:%.*]] = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> [[A:%.*]], i32 [[TMP0]], i32 20)98// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, <4 x i32> } [[TMP1]], 099// CHECK-NEXT: store i32 [[TMP2]], ptr [[B]], align 4100// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, <4 x i32> } [[TMP1]], 1101// CHECK-NEXT: ret <4 x i32> [[TMP3]]102//103uint32x4_t test_vshlcq_u32(uint32x4_t a, uint32_t *b) {104#ifdef POLYMORPHIC105 return vshlcq(a, b, 20);106#else /* POLYMORPHIC */107 return vshlcq_u32(a, b, 20);108#endif /* POLYMORPHIC */109}110 111// CHECK-LABEL: @test_vshlcq_m_s8(112// CHECK-NEXT: entry:113// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 4114// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32115// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])116// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[TMP0]], i32 29, <16 x i1> [[TMP2]])117// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <16 x i8> } [[TMP3]], 0118// CHECK-NEXT: store i32 [[TMP4]], ptr [[B]], align 4119// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <16 x i8> } [[TMP3]], 1120// CHECK-NEXT: ret <16 x i8> [[TMP5]]121//122int8x16_t test_vshlcq_m_s8(int8x16_t a, uint32_t *b, mve_pred16_t p) {123#ifdef POLYMORPHIC124 return vshlcq_m(a, b, 29, p);125#else /* POLYMORPHIC */126 return vshlcq_m_s8(a, b, 29, p);127#endif /* POLYMORPHIC */128}129 130// CHECK-LABEL: @test_vshlcq_m_s16(131// CHECK-NEXT: entry:132// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 4133// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32134// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])135// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[TMP0]], i32 17, <8 x i1> [[TMP2]])136// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <8 x i16> } [[TMP3]], 0137// CHECK-NEXT: store i32 [[TMP4]], ptr [[B]], align 4138// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <8 x i16> } [[TMP3]], 1139// CHECK-NEXT: ret <8 x i16> [[TMP5]]140//141int16x8_t test_vshlcq_m_s16(int16x8_t a, uint32_t *b, mve_pred16_t p) {142#ifdef POLYMORPHIC143 return vshlcq_m(a, b, 17, p);144#else /* POLYMORPHIC */145 return vshlcq_m_s16(a, b, 17, p);146#endif /* POLYMORPHIC */147}148 149// CHECK-LABEL: @test_vshlcq_m_s32(150// CHECK-NEXT: entry:151// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 4152// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32153// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]])154// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[TMP0]], i32 9, <4 x i1> [[TMP2]])155// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <4 x i32> } [[TMP3]], 0156// CHECK-NEXT: store i32 [[TMP4]], ptr [[B]], align 4157// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <4 x i32> } [[TMP3]], 1158// CHECK-NEXT: ret <4 x i32> [[TMP5]]159//160int32x4_t test_vshlcq_m_s32(int32x4_t a, uint32_t *b, mve_pred16_t p) {161#ifdef POLYMORPHIC162 return vshlcq_m(a, b, 9, p);163#else /* POLYMORPHIC */164 return vshlcq_m_s32(a, b, 9, p);165#endif /* POLYMORPHIC */166}167 168// CHECK-LABEL: @test_vshlcq_m_u8(169// CHECK-NEXT: entry:170// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 4171// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32172// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])173// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[TMP0]], i32 21, <16 x i1> [[TMP2]])174// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <16 x i8> } [[TMP3]], 0175// CHECK-NEXT: store i32 [[TMP4]], ptr [[B]], align 4176// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <16 x i8> } [[TMP3]], 1177// CHECK-NEXT: ret <16 x i8> [[TMP5]]178//179uint8x16_t test_vshlcq_m_u8(uint8x16_t a, uint32_t *b, mve_pred16_t p) {180#ifdef POLYMORPHIC181 return vshlcq_m(a, b, 21, p);182#else /* POLYMORPHIC */183 return vshlcq_m_u8(a, b, 21, p);184#endif /* POLYMORPHIC */185}186 187// CHECK-LABEL: @test_vshlcq_m_u16(188// CHECK-NEXT: entry:189// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 4190// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32191// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])192// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[TMP0]], i32 24, <8 x i1> [[TMP2]])193// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <8 x i16> } [[TMP3]], 0194// CHECK-NEXT: store i32 [[TMP4]], ptr [[B]], align 4195// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <8 x i16> } [[TMP3]], 1196// CHECK-NEXT: ret <8 x i16> [[TMP5]]197//198uint16x8_t test_vshlcq_m_u16(uint16x8_t a, uint32_t *b, mve_pred16_t p) {199#ifdef POLYMORPHIC200 return vshlcq_m(a, b, 24, p);201#else /* POLYMORPHIC */202 return vshlcq_m_u16(a, b, 24, p);203#endif /* POLYMORPHIC */204}205 206// CHECK-LABEL: @test_vshlcq_m_u32(207// CHECK-NEXT: entry:208// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B:%.*]], align 4209// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32210// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]])211// CHECK-NEXT: [[TMP3:%.*]] = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[TMP0]], i32 26, <4 x i1> [[TMP2]])212// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, <4 x i32> } [[TMP3]], 0213// CHECK-NEXT: store i32 [[TMP4]], ptr [[B]], align 4214// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, <4 x i32> } [[TMP3]], 1215// CHECK-NEXT: ret <4 x i32> [[TMP5]]216//217uint32x4_t test_vshlcq_m_u32(uint32x4_t a, uint32_t *b, mve_pred16_t p) {218#ifdef POLYMORPHIC219 return vshlcq_m(a, b, 26, p);220#else /* POLYMORPHIC */221 return vshlcq_m_u32(a, b, 26, p);222#endif /* POLYMORPHIC */223}224