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1// REQUIRES: arm-registered-target2// RUN: %clang_cc1 -triple thumbv7-apple-darwin \3// RUN: -target-abi apcs-gnu \4// RUN: -target-cpu cortex-a8 \5// RUN: -mfloat-abi soft \6// RUN: -target-feature +soft-float-abi \7// RUN: -ffreestanding \8// RUN: -emit-llvm -w -o - %s | FileCheck %s9 10#include <arm_neon.h>11 12// Avoid using i64 types for vld1q_lane and vst1q_lane Neon intrinsics with13// <2 x i64> vectors to avoid poor code for i64 in the backend.14void t1(uint64_t *src, uint8_t *dst) {15// CHECK: @t116 uint64x2_t q = vld1q_u64(src);17// CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64.p018 vst1q_lane_u64(dst, q, 1);19// CHECK: shufflevector <2 x i64>20// CHECK: call void @llvm.arm.neon.vst1.p0.v1i6421}22 23void t2(uint64_t *src1, uint8_t *src2, uint64x2_t *dst) {24// CHECK: @t225 uint64x2_t q = vld1q_u64(src1);26// CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64.p027 q = vld1q_lane_u64(src2, q, 0);28// CHECK: shufflevector <2 x i64>29// CHECK: call <1 x i64> @llvm.arm.neon.vld1.v1i64.p030// CHECK: shufflevector <1 x i64>31 *dst = q;32// CHECK: store <2 x i64>33}34