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1// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \2// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | \3// RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s4// RUN: %clang_cc1 -triple armv8-none-linux-gnueabi -target-feature +neon \5// RUN: -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - %s | \6// RUN: opt -S -passes=mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s7 8// REQUIRES: aarch64-registered-target || arm-registered-target9 10#include <arm_neon.h>11 12// CHECK-LABEL: @test_vld1_f16_x2(13// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 814// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 [[RETVAL:%.*]],15// CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 816// CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x2.v4f16.p0|arm.neon.vld1x2.v4i16.p0}}(ptr %a)17// CHECK: store { <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]]18// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)19// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x4x2_t, ptr [[RETVAL]], align 820// CHECK-A64: ret %struct.float16x4x2_t [[TMP6]]21// CHECK-A32: ret void22float16x4x2_t test_vld1_f16_x2(float16_t const *a) {23 return vld1_f16_x2(a);24}25 26// CHECK-LABEL: @test_vld1_f16_x3(27// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x3_t, align 828// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x4x3_t) align 8 [[RETVAL:%.*]],29// CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 830// CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x3.v4f16.p0|arm.neon.vld1x3.v4i16.p0}}(ptr %a)31// CHECK: store { <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]]32// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)33// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x4x3_t, ptr [[RETVAL]], align 834// CHECK-A64: ret %struct.float16x4x3_t [[TMP6]]35// CHECK-A32: ret void36float16x4x3_t test_vld1_f16_x3(float16_t const *a) {37 return vld1_f16_x3(a);38}39 40// CHECK-LABEL: @test_vld1_f16_x4(41// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x4_t, align 842// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x4x4_t) align 8 [[RETVAL:%.*]],43// CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 844// CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x4.v4f16.p0|arm.neon.vld1x4.v4i16.p0}}(ptr %a)45// CHECK: store { <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]]46// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)47// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x4x4_t, ptr [[RETVAL]], align 848// CHECK-A64: ret %struct.float16x4x4_t [[TMP6]]49// CHECK-A32: ret void50float16x4x4_t test_vld1_f16_x4(float16_t const *a) {51 return vld1_f16_x4(a);52}53 54// CHECK-LABEL: @test_vld1_f32_x2(55// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x2_t, align 856// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x2x2_t) align 8 [[RETVAL:%.*]],57// CHECK: [[__RET:%.*]] = alloca %struct.float32x2x2_t, align 858// CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2f32.p0(ptr %a)59// CHECK: store { <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]]60// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)61// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x2x2_t, ptr [[RETVAL]], align 862// CHECK-A64: ret %struct.float32x2x2_t [[TMP6]]63// CHECK-A32: ret void64float32x2x2_t test_vld1_f32_x2(float32_t const *a) {65 return vld1_f32_x2(a);66}67 68// CHECK-LABEL: @test_vld1_f32_x3(69// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x3_t, align 870// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x2x3_t) align 8 [[RETVAL:%.*]],71// CHECK: [[__RET:%.*]] = alloca %struct.float32x2x3_t, align 872// CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2f32.p0(ptr %a)73// CHECK: store { <2 x float>, <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]]74// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)75// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x2x3_t, ptr [[RETVAL]], align 876// CHECK-A64: ret %struct.float32x2x3_t [[TMP6]]77float32x2x3_t test_vld1_f32_x3(float32_t const *a) {78 return vld1_f32_x3(a);79}80 81// CHECK-LABEL: @test_vld1_f32_x4(82// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x4_t, align 883// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x2x4_t) align 8 [[RETVAL:%.*]],84// CHECK: [[__RET:%.*]] = alloca %struct.float32x2x4_t, align 885// CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2f32.p0(ptr %a)86// CHECK: store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]]87// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)88// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x2x4_t, ptr [[RETVAL]], align 889// CHECK-A64: ret %struct.float32x2x4_t [[TMP6]]90// CHECK-A32: ret void91float32x2x4_t test_vld1_f32_x4(float32_t const *a) {92 return vld1_f32_x4(a);93}94 95// CHECK-LABEL: @test_vld1_p16_x2(96// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x2_t, align 897// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x4x2_t) align 8 [[RETVAL:%.*]],98// CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x2_t, align 899// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0(ptr %a)100// CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]]101// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)102// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x4x2_t, ptr [[RETVAL]], align 8103// CHECK-A64: ret %struct.poly16x4x2_t [[TMP6]]104// CHECK-A32: ret void105poly16x4x2_t test_vld1_p16_x2(poly16_t const *a) {106 return vld1_p16_x2(a);107}108 109// CHECK-LABEL: @test_vld1_p16_x3(110// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x3_t, align 8111// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x4x3_t) align 8 [[RETVAL:%.*]],112// CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x3_t, align 8113// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0(ptr %a)114// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]]115// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)116// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x4x3_t, ptr [[RETVAL]], align 8117// CHECK-A64: ret %struct.poly16x4x3_t [[TMP6]]118// CHECK-A32: ret void119poly16x4x3_t test_vld1_p16_x3(poly16_t const *a) {120 return vld1_p16_x3(a);121}122 123// CHECK-LABEL: @test_vld1_p16_x4(124// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x4_t, align 8125// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x4x4_t) align 8 [[RETVAL:%.*]],126// CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x4_t, align 8127// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0(ptr %a)128// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]]129// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)130// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x4x4_t, ptr [[RETVAL]], align 8131// CHECK-A64: ret %struct.poly16x4x4_t [[TMP6]]132// CHECK-A32: ret void133poly16x4x4_t test_vld1_p16_x4(poly16_t const *a) {134 return vld1_p16_x4(a);135}136 137// CHECK-LABEL: @test_vld1_p8_x2(138// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x2_t, align 8139// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x8x2_t) align 8 [[RETVAL:%.*]],140// CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x2_t, align 8141// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0(ptr %a)142// CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]]143// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)144// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x8x2_t, ptr [[RETVAL]], align 8145// CHECK-A64: ret %struct.poly8x8x2_t [[TMP4]]146// CHECK-A32: ret void147poly8x8x2_t test_vld1_p8_x2(poly8_t const *a) {148 return vld1_p8_x2(a);149}150 151// CHECK-LABEL: @test_vld1_p8_x3(152// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x3_t, align 8153// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x8x3_t) align 8 [[RETVAL:%.*]],154// CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x3_t, align 8155// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0(ptr %a)156// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]]157// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)158// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x8x3_t, ptr [[RETVAL]], align 8159// CHECK-A64: ret %struct.poly8x8x3_t [[TMP4]]160// CHECK-A32: ret void161poly8x8x3_t test_vld1_p8_x3(poly8_t const *a) {162 return vld1_p8_x3(a);163}164 165// CHECK-LABEL: @test_vld1_p8_x4(166// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x4_t, align 8167// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x8x4_t) align 8 [[RETVAL:%.*]],168// CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x4_t, align 8169// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0(ptr %a)170// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]]171// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)172// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x8x4_t, ptr [[RETVAL]], align 8173// CHECK-A64: ret %struct.poly8x8x4_t [[TMP4]]174// CHECK-A32: ret void175poly8x8x4_t test_vld1_p8_x4(poly8_t const *a) {176 return vld1_p8_x4(a);177}178 179// CHECK-LABEL: @test_vld1_s16_x2(180// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x2_t, align 8181// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x4x2_t) align 8 [[RETVAL:%.*]],182// CHECK: [[__RET:%.*]] = alloca %struct.int16x4x2_t, align 8183// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0(ptr %a)184// CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]]185// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)186// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x4x2_t, ptr [[RETVAL]], align 8187// CHECK-A64: ret %struct.int16x4x2_t [[TMP6]]188// CHECK-A32: ret void189int16x4x2_t test_vld1_s16_x2(int16_t const *a) {190 return vld1_s16_x2(a);191}192 193// CHECK-LABEL: @test_vld1_s16_x3(194// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x3_t, align 8195// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x4x3_t) align 8 [[RETVAL:%.*]],196// CHECK: [[__RET:%.*]] = alloca %struct.int16x4x3_t, align 8197// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0(ptr %a)198// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]]199// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)200// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x4x3_t, ptr [[RETVAL]], align 8201// CHECK-A64: ret %struct.int16x4x3_t [[TMP6]]202// CHECK-A32: ret void203int16x4x3_t test_vld1_s16_x3(int16_t const *a) {204 return vld1_s16_x3(a);205}206 207// CHECK-LABEL: @test_vld1_s16_x4(208// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x4_t, align 8209// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x4x4_t) align 8 [[RETVAL:%.*]],210// CHECK: [[__RET:%.*]] = alloca %struct.int16x4x4_t, align 8211// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0(ptr %a)212// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]]213// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)214// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x4x4_t, ptr [[RETVAL]], align 8215// CHECK-A64: ret %struct.int16x4x4_t [[TMP6]]216// CHECK-A32: ret void217int16x4x4_t test_vld1_s16_x4(int16_t const *a) {218 return vld1_s16_x4(a);219}220 221// CHECK-LABEL: @test_vld1_s32_x2(222// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x2_t, align 8223// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x2x2_t) align 8 [[RETVAL:%.*]],224// CHECK: [[__RET:%.*]] = alloca %struct.int32x2x2_t, align 8225// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i32.p0(ptr %a)226// CHECK: store { <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]]227// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)228// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x2x2_t, ptr [[RETVAL]], align 8229// CHECK-A64: ret %struct.int32x2x2_t [[TMP6]]230// CHECK-A32: ret void231int32x2x2_t test_vld1_s32_x2(int32_t const *a) {232 return vld1_s32_x2(a);233}234 235// CHECK-LABEL: @test_vld1_s32_x3(236// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x3_t, align 8237// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x2x3_t) align 8 [[RETVAL:%.*]],238// CHECK: [[__RET:%.*]] = alloca %struct.int32x2x3_t, align 8239// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i32.p0(ptr %a)240// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]]241// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)242// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x2x3_t, ptr [[RETVAL]], align 8243// CHECK-A64: ret %struct.int32x2x3_t [[TMP6]]244// CHECK-A32: ret void245int32x2x3_t test_vld1_s32_x3(int32_t const *a) {246 return vld1_s32_x3(a);247}248 249// CHECK-LABEL: @test_vld1_s32_x4(250// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x4_t, align 8251// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x2x4_t) align 8 [[RETVAL:%.*]],252// CHECK: [[__RET:%.*]] = alloca %struct.int32x2x4_t, align 8253// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i32.p0(ptr %a)254// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]]255// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)256// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x2x4_t, ptr [[RETVAL]], align 8257// CHECK-A64: ret %struct.int32x2x4_t [[TMP6]]258// CHECK-A32: ret void259int32x2x4_t test_vld1_s32_x4(int32_t const *a) {260 return vld1_s32_x4(a);261}262 263// CHECK-LABEL: @test_vld1_s64_x2(264// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x2_t, align 8265// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x1x2_t) align 8 [[RETVAL:%.*]],266// CHECK: [[__RET:%.*]] = alloca %struct.int64x1x2_t, align 8267// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v1i64.p0(ptr %a)268// CHECK: store { <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]]269// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)270// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x1x2_t, ptr [[RETVAL]], align 8271// CHECK-A64: ret %struct.int64x1x2_t [[TMP6]]272// CHECK-A32: ret void273int64x1x2_t test_vld1_s64_x2(int64_t const *a) {274 return vld1_s64_x2(a);275}276 277// CHECK-LABEL: @test_vld1_s64_x3(278// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x3_t, align 8279// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x1x3_t) align 8 [[RETVAL:%.*]],280// CHECK: [[__RET:%.*]] = alloca %struct.int64x1x3_t, align 8281// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v1i64.p0(ptr %a)282// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]]283// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)284// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x1x3_t, ptr [[RETVAL]], align 8285// CHECK-A64: ret %struct.int64x1x3_t [[TMP6]]286// CHECK-A32: ret void287int64x1x3_t test_vld1_s64_x3(int64_t const *a) {288 return vld1_s64_x3(a);289}290 291// CHECK-LABEL: @test_vld1_s64_x4(292// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x4_t, align 8293// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x1x4_t) align 8 [[RETVAL:%.*]],294// CHECK: [[__RET:%.*]] = alloca %struct.int64x1x4_t, align 8295// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v1i64.p0(ptr %a)296// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]]297// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)298// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x1x4_t, ptr [[RETVAL]], align 8299// CHECK-A64: ret %struct.int64x1x4_t [[TMP6]]300// CHECK-A32: ret void301int64x1x4_t test_vld1_s64_x4(int64_t const *a) {302 return vld1_s64_x4(a);303}304 305// CHECK-LABEL: @test_vld1_s8_x2(306// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x2_t, align 8307// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x8x2_t) align 8 [[RETVAL:%.*]],308// CHECK: [[__RET:%.*]] = alloca %struct.int8x8x2_t, align 8309// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0(ptr %a)310// CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]]311// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)312// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x8x2_t, ptr [[RETVAL]], align 8313// CHECK-A64: ret %struct.int8x8x2_t [[TMP4]]314// CHECK-A32: ret void315int8x8x2_t test_vld1_s8_x2(int8_t const *a) {316 return vld1_s8_x2(a);317}318 319// CHECK-LABEL: @test_vld1_s8_x3(320// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x3_t, align 8321// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x8x3_t) align 8 [[RETVAL:%.*]],322// CHECK: [[__RET:%.*]] = alloca %struct.int8x8x3_t, align 8323// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0(ptr %a)324// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]]325// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)326// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x8x3_t, ptr [[RETVAL]], align 8327// CHECK-A64: ret %struct.int8x8x3_t [[TMP4]]328// CHECK-A32: ret void329int8x8x3_t test_vld1_s8_x3(int8_t const *a) {330 return vld1_s8_x3(a);331}332 333// CHECK-LABEL: @test_vld1_s8_x4(334// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x4_t, align 8335// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x8x4_t) align 8 [[RETVAL:%.*]],336// CHECK: [[__RET:%.*]] = alloca %struct.int8x8x4_t, align 8337// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0(ptr %a)338// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]]339// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)340// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x8x4_t, ptr [[RETVAL]], align 8341// CHECK-A64: ret %struct.int8x8x4_t [[TMP4]]342// CHECK-A32: ret void343int8x8x4_t test_vld1_s8_x4(int8_t const *a) {344 return vld1_s8_x4(a);345}346 347// CHECK-LABEL: @test_vld1_u16_x2(348// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x2_t, align 8349// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x4x2_t) align 8 [[RETVAL:%.*]],350// CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x2_t, align 8351// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0(ptr %a)352// CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]]353// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)354// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x4x2_t, ptr [[RETVAL]], align 8355// CHECK-A64: ret %struct.uint16x4x2_t [[TMP6]]356// CHECK-A32: ret void357uint16x4x2_t test_vld1_u16_x2(uint16_t const *a) {358 return vld1_u16_x2(a);359}360 361// CHECK-LABEL: @test_vld1_u16_x3(362// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x3_t, align 8363// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x4x3_t) align 8 [[RETVAL:%.*]],364// CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x3_t, align 8365// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0(ptr %a)366// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]]367// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)368// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x4x3_t, ptr [[RETVAL]], align 8369// CHECK-A64: ret %struct.uint16x4x3_t [[TMP6]]370// CHECK-A32: ret void371uint16x4x3_t test_vld1_u16_x3(uint16_t const *a) {372 return vld1_u16_x3(a);373}374 375// CHECK-LABEL: @test_vld1_u16_x4(376// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x4_t, align 8377// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x4x4_t) align 8 [[RETVAL:%.*]],378// CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x4_t, align 8379// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0(ptr %a)380// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]]381// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)382// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x4x4_t, ptr [[RETVAL]], align 8383// CHECK-A64: ret %struct.uint16x4x4_t [[TMP6]]384// CHECK-A32: ret void385uint16x4x4_t test_vld1_u16_x4(uint16_t const *a) {386 return vld1_u16_x4(a);387}388 389// CHECK-LABEL: @test_vld1_u32_x2(390// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x2_t, align 8391// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x2x2_t) align 8 [[RETVAL:%.*]],392// CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x2_t, align 8393// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i32.p0(ptr %a)394// CHECK: store { <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]]395// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)396// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x2x2_t, ptr [[RETVAL]], align 8397// CHECK-A64: ret %struct.uint32x2x2_t [[TMP6]]398// CHECK-A32: ret void399uint32x2x2_t test_vld1_u32_x2(uint32_t const *a) {400 return vld1_u32_x2(a);401}402 403// CHECK-LABEL: @test_vld1_u32_x3(404// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x3_t, align 8405// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x2x3_t) align 8 [[RETVAL:%.*]],406// CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x3_t, align 8407// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i32.p0(ptr %a)408// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]]409// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)410// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x2x3_t, ptr [[RETVAL]], align 8411// CHECK-A64: ret %struct.uint32x2x3_t [[TMP6]]412// CHECK-A32: ret void413uint32x2x3_t test_vld1_u32_x3(uint32_t const *a) {414 return vld1_u32_x3(a);415}416 417// CHECK-LABEL: @test_vld1_u32_x4(418// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x4_t, align 8419// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x2x4_t) align 8 [[RETVAL:%.*]],420// CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x4_t, align 8421// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i32.p0(ptr %a)422// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]]423// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)424// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x2x4_t, ptr [[RETVAL]], align 8425// CHECK-A64: ret %struct.uint32x2x4_t [[TMP6]]426// CHECK-A32: ret void427uint32x2x4_t test_vld1_u32_x4(uint32_t const *a) {428 return vld1_u32_x4(a);429}430 431// CHECK-LABEL: @test_vld1_u64_x2(432// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x2_t, align 8433// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x1x2_t) align 8 [[RETVAL:%.*]],434// CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x2_t, align 8435// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v1i64.p0(ptr %a)436// CHECK: store { <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]]437// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)438// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x1x2_t, ptr [[RETVAL]], align 8439// CHECK-A64: ret %struct.uint64x1x2_t [[TMP6]]440// CHECK-A32: ret void441uint64x1x2_t test_vld1_u64_x2(uint64_t const *a) {442 return vld1_u64_x2(a);443}444 445// CHECK-LABEL: @test_vld1_u64_x3(446// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x3_t, align 8447// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x1x3_t) align 8 [[RETVAL:%.*]],448// CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x3_t, align 8449// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v1i64.p0(ptr %a)450// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]]451// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)452// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x1x3_t, ptr [[RETVAL]], align 8453// CHECK-A64: ret %struct.uint64x1x3_t [[TMP6]]454// CHECK-A32: ret void455uint64x1x3_t test_vld1_u64_x3(uint64_t const *a) {456 return vld1_u64_x3(a);457}458 459// CHECK-LABEL: @test_vld1_u64_x4(460// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x4_t, align 8461// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x1x4_t) align 8 [[RETVAL:%.*]],462// CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x4_t, align 8463// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v1i64.p0(ptr %a)464// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]]465// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)466// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x1x4_t, ptr [[RETVAL]], align 8467// CHECK-A64: ret %struct.uint64x1x4_t [[TMP6]]468// CHECK-A32: ret void469uint64x1x4_t test_vld1_u64_x4(uint64_t const *a) {470 return vld1_u64_x4(a);471}472 473// CHECK-LABEL: @test_vld1_u8_x2(474// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x2_t, align 8475// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x8x2_t) align 8 [[RETVAL:%.*]],476// CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x2_t, align 8477// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0(ptr %a)478// CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]]479// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)480// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x8x2_t, ptr [[RETVAL]], align 8481// CHECK-A64: ret %struct.uint8x8x2_t [[TMP4]]482// CHECK-A32: ret void483uint8x8x2_t test_vld1_u8_x2(uint8_t const *a) {484 return vld1_u8_x2(a);485}486 487// CHECK-LABEL: @test_vld1_u8_x3(488// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x3_t, align 8489// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x8x3_t) align 8 [[RETVAL:%.*]],490// CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x3_t, align 8491// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0(ptr %a)492// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]]493// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)494// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x8x3_t, ptr [[RETVAL]], align 8495// CHECK-A64: ret %struct.uint8x8x3_t [[TMP4]]496// CHECK-A32: ret void497uint8x8x3_t test_vld1_u8_x3(uint8_t const *a) {498 return vld1_u8_x3(a);499}500 501// CHECK-LABEL: @test_vld1_u8_x4(502// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x4_t, align 8503// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x8x4_t) align 8 [[RETVAL:%.*]],504// CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x4_t, align 8505// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0(ptr %a)506// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]]507// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)508// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x8x4_t, ptr [[RETVAL]], align 8509// CHECK-A64: ret %struct.uint8x8x4_t [[TMP4]]510// CHECK-A32: ret void511uint8x8x4_t test_vld1_u8_x4(uint8_t const *a) {512 return vld1_u8_x4(a);513}514 515// CHECK-LABEL: @test_vld1q_f16_x2(516// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16517// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 8 [[RETVAL:%.*]],518// CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align {{16|8}}519// CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x2.v8f16.p0|arm.neon.vld1x2.v8i16.p0}}(ptr %a)520// CHECK: store { <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]]521// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)522// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x8x2_t, ptr [[RETVAL]], align 16523// CHECK-A64: ret %struct.float16x8x2_t [[TMP6]]524// CHECK-A32: ret void525float16x8x2_t test_vld1q_f16_x2(float16_t const *a) {526 return vld1q_f16_x2(a);527}528 529// CHECK-LABEL: @test_vld1q_f16_x3(530// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x3_t, align 16531// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x8x3_t) align 8 [[RETVAL:%.*]],532// CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align {{16|8}}533// CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x3.v8f16.p0|arm.neon.vld1x3.v8i16.p0}}(ptr %a)534// CHECK: store { <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]]535// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)536// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x8x3_t, ptr [[RETVAL]], align 16537// CHECK-A64: ret %struct.float16x8x3_t [[TMP6]]538// CHECK-A32: ret void539float16x8x3_t test_vld1q_f16_x3(float16_t const *a) {540 return vld1q_f16_x3(a);541}542 543// CHECK-LABEL: @test_vld1q_f16_x4(544// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x4_t, align 16545// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x8x4_t) align 8 [[RETVAL:%.*]],546// CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align {{16|8}}547// CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x4.v8f16.p0|arm.neon.vld1x4.v8i16.p0}}(ptr %a)548// CHECK: store { <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]]549// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)550// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x8x4_t, ptr [[RETVAL]], align 16551// CHECK-A64: ret %struct.float16x8x4_t [[TMP6]]552// CHECK-A32: ret void553float16x8x4_t test_vld1q_f16_x4(float16_t const *a) {554 return vld1q_f16_x4(a);555}556 557// CHECK-LABEL: @test_vld1q_f32_x2(558// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x2_t, align 16559// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x4x2_t) align 8 [[RETVAL:%.*]],560// CHECK: [[__RET:%.*]] = alloca %struct.float32x4x2_t, align {{16|8}}561// CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4f32.p0(ptr %a)562// CHECK: store { <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]]563// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)564// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x4x2_t, ptr [[RETVAL]], align 16565// CHECK-A64: ret %struct.float32x4x2_t [[TMP6]]566// CHECK-A32: ret void567float32x4x2_t test_vld1q_f32_x2(float32_t const *a) {568 return vld1q_f32_x2(a);569}570 571// CHECK-LABEL: @test_vld1q_f32_x3(572// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x3_t, align 16573// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x4x3_t) align 8 [[RETVAL:%.*]],574// CHECK: [[__RET:%.*]] = alloca %struct.float32x4x3_t, align {{16|8}}575// CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4f32.p0(ptr %a)576// CHECK: store { <4 x float>, <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]]577// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)578// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x4x3_t, ptr [[RETVAL]], align 16579// CHECK-A64: ret %struct.float32x4x3_t [[TMP6]]580// CHECK-A32: ret void581float32x4x3_t test_vld1q_f32_x3(float32_t const *a) {582 return vld1q_f32_x3(a);583}584 585// CHECK-LABEL: @test_vld1q_f32_x4(586// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x4_t, align 16587// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x4x4_t) align 8 [[RETVAL:%.*]],588// CHECK: [[__RET:%.*]] = alloca %struct.float32x4x4_t, align {{16|8}}589// CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4f32.p0(ptr %a)590// CHECK: store { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]]591// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)592// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x4x4_t, ptr [[RETVAL]], align 16593// CHECK-A64: ret %struct.float32x4x4_t [[TMP6]]594// CHECK-A32: ret void595float32x4x4_t test_vld1q_f32_x4(float32_t const *a) {596 return vld1q_f32_x4(a);597}598 599// CHECK-LABEL: @test_vld1q_p16_x2(600// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x2_t, align 16601// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x8x2_t) align 8 [[RETVAL:%.*]],602// CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x2_t, align {{16|8}}603// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0(ptr %a)604// CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]]605// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)606// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x8x2_t, ptr [[RETVAL]], align 16607// CHECK-A64: ret %struct.poly16x8x2_t [[TMP6]]608// CHECK-A32: ret void609poly16x8x2_t test_vld1q_p16_x2(poly16_t const *a) {610 return vld1q_p16_x2(a);611}612 613// CHECK-LABEL: @test_vld1q_p16_x3(614// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x3_t, align 16615// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x8x3_t) align 8 [[RETVAL:%.*]],616// CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x3_t, align {{16|8}}617// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0(ptr %a)618// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]]619// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)620// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x8x3_t, ptr [[RETVAL]], align 16621// CHECK-A64: ret %struct.poly16x8x3_t [[TMP6]]622// CHECK-A32: ret void623poly16x8x3_t test_vld1q_p16_x3(poly16_t const *a) {624 return vld1q_p16_x3(a);625}626 627// CHECK-LABEL: @test_vld1q_p16_x4(628// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x4_t, align 16629// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x8x4_t) align 8 [[RETVAL:%.*]],630// CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x4_t, align {{16|8}}631// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0(ptr %a)632// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]]633// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)634// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x8x4_t, ptr [[RETVAL]], align 16635// CHECK-A64: ret %struct.poly16x8x4_t [[TMP6]]636// CHECK-A32: ret void637poly16x8x4_t test_vld1q_p16_x4(poly16_t const *a) {638 return vld1q_p16_x4(a);639}640 641// CHECK-LABEL: @test_vld1q_p8_x2(642// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x2_t, align 16643// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x16x2_t) align 8 [[RETVAL:%.*]],644// CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x2_t, align {{16|8}}645// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0(ptr %a)646// CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]]647// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)648// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x16x2_t, ptr [[RETVAL]], align 16649// CHECK-A64: ret %struct.poly8x16x2_t [[TMP4]]650// CHECK-A32: ret void651poly8x16x2_t test_vld1q_p8_x2(poly8_t const *a) {652 return vld1q_p8_x2(a);653}654 655// CHECK-LABEL: @test_vld1q_p8_x3(656// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x3_t, align 16657// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x16x3_t) align 8 [[RETVAL:%.*]],658// CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x3_t, align {{16|8}}659// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0(ptr %a)660// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]]661// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)662// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x16x3_t, ptr [[RETVAL]], align 16663// CHECK-A64: ret %struct.poly8x16x3_t [[TMP4]]664// CHECK-A32: ret void665poly8x16x3_t test_vld1q_p8_x3(poly8_t const *a) {666 return vld1q_p8_x3(a);667}668 669// CHECK-LABEL: @test_vld1q_p8_x4(670// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x4_t, align 16671// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x16x4_t) align 8 [[RETVAL:%.*]],672// CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x4_t, align {{16|8}}673// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0(ptr %a)674// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]]675// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)676// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x16x4_t, ptr [[RETVAL]], align 16677// CHECK-A64: ret %struct.poly8x16x4_t [[TMP4]]678// CHECK-A32: ret void679poly8x16x4_t test_vld1q_p8_x4(poly8_t const *a) {680 return vld1q_p8_x4(a);681}682 683// CHECK-LABEL: @test_vld1q_s16_x2(684// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x2_t, align 16685// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x8x2_t) align 8 [[RETVAL:%.*]],686// CHECK: [[__RET:%.*]] = alloca %struct.int16x8x2_t, align {{16|8}}687// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0(ptr %a)688// CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]]689// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)690// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x8x2_t, ptr [[RETVAL]], align 16691// CHECK-A64: ret %struct.int16x8x2_t [[TMP6]]692// CHECK-A32: ret void693int16x8x2_t test_vld1q_s16_x2(int16_t const *a) {694 return vld1q_s16_x2(a);695}696 697// CHECK-LABEL: @test_vld1q_s16_x3(698// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x3_t, align 16699// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x8x3_t) align 8 [[RETVAL:%.*]],700// CHECK: [[__RET:%.*]] = alloca %struct.int16x8x3_t, align {{16|8}}701// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0(ptr %a)702// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]]703// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)704// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x8x3_t, ptr [[RETVAL]], align 16705// CHECK-A64: ret %struct.int16x8x3_t [[TMP6]]706// CHECK-A32: ret void707int16x8x3_t test_vld1q_s16_x3(int16_t const *a) {708 return vld1q_s16_x3(a);709}710 711// CHECK-LABEL: @test_vld1q_s16_x4(712// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x4_t, align 16713// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x8x4_t) align 8 [[RETVAL:%.*]],714// CHECK: [[__RET:%.*]] = alloca %struct.int16x8x4_t, align {{16|8}}715// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0(ptr %a)716// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]]717// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)718// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x8x4_t, ptr [[RETVAL]], align 16719// CHECK-A64: ret %struct.int16x8x4_t [[TMP6]]720// CHECK-A32: ret void721int16x8x4_t test_vld1q_s16_x4(int16_t const *a) {722 return vld1q_s16_x4(a);723}724 725// CHECK-LABEL: @test_vld1q_s32_x2(726// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x2_t, align 16727// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x4x2_t) align 8 [[RETVAL:%.*]],728// CHECK: [[__RET:%.*]] = alloca %struct.int32x4x2_t, align {{16|8}}729// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i32.p0(ptr %a)730// CHECK: store { <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]]731// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)732// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x4x2_t, ptr [[RETVAL]], align 16733// CHECK-A64: ret %struct.int32x4x2_t [[TMP6]]734// CHECK-A32: ret void735int32x4x2_t test_vld1q_s32_x2(int32_t const *a) {736 return vld1q_s32_x2(a);737}738 739// CHECK-LABEL: @test_vld1q_s32_x3(740// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x3_t, align 16741// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x4x3_t) align 8 [[RETVAL:%.*]],742// CHECK: [[__RET:%.*]] = alloca %struct.int32x4x3_t, align {{16|8}}743// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i32.p0(ptr %a)744// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]]745// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)746// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x4x3_t, ptr [[RETVAL]], align 16747// CHECK-A64: ret %struct.int32x4x3_t [[TMP6]]748// CHECK-A32: ret void749int32x4x3_t test_vld1q_s32_x3(int32_t const *a) {750 return vld1q_s32_x3(a);751}752 753// CHECK-LABEL: @test_vld1q_s32_x4(754// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x4_t, align 16755// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x4x4_t) align 8 [[RETVAL:%.*]],756// CHECK: [[__RET:%.*]] = alloca %struct.int32x4x4_t, align {{16|8}}757// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i32.p0(ptr %a)758// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]]759// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)760// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x4x4_t, ptr [[RETVAL]], align 16761// CHECK-A64: ret %struct.int32x4x4_t [[TMP6]]762// CHECK-A32: ret void763int32x4x4_t test_vld1q_s32_x4(int32_t const *a) {764 return vld1q_s32_x4(a);765}766 767// CHECK-LABEL: @test_vld1q_s64_x2(768// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x2_t, align 16769// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x2x2_t) align 8 [[RETVAL:%.*]],770// CHECK: [[__RET:%.*]] = alloca %struct.int64x2x2_t, align {{16|8}}771// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i64.p0(ptr %a)772// CHECK: store { <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]]773// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)774// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x2x2_t, ptr [[RETVAL]], align 16775// CHECK-A64: ret %struct.int64x2x2_t [[TMP6]]776// CHECK-A32: ret void777int64x2x2_t test_vld1q_s64_x2(int64_t const *a) {778 return vld1q_s64_x2(a);779}780 781// CHECK-LABEL: @test_vld1q_s64_x3(782// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x3_t, align 16783// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x2x3_t) align 8 [[RETVAL:%.*]],784// CHECK: [[__RET:%.*]] = alloca %struct.int64x2x3_t, align {{16|8}}785// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i64.p0(ptr %a)786// CHECK: store { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]]787// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)788// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x2x3_t, ptr [[RETVAL]], align 16789// CHECK-A64: ret %struct.int64x2x3_t [[TMP6]]790// CHECK-A32: ret void791int64x2x3_t test_vld1q_s64_x3(int64_t const *a) {792 return vld1q_s64_x3(a);793}794 795// CHECK-LABEL: @test_vld1q_s64_x4(796// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x4_t, align 16797// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x2x4_t) align 8 [[RETVAL:%.*]],798// CHECK: [[__RET:%.*]] = alloca %struct.int64x2x4_t, align {{16|8}}799// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i64.p0(ptr %a)800// CHECK: store { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]]801// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)802// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x2x4_t, ptr [[RETVAL]], align 16803// CHECK-A64: ret %struct.int64x2x4_t [[TMP6]]804// CHECK-A32: ret void805int64x2x4_t test_vld1q_s64_x4(int64_t const *a) {806 return vld1q_s64_x4(a);807}808 809// CHECK-LABEL: @test_vld1q_s8_x2(810// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x2_t, align 16811// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x16x2_t) align 8 [[RETVAL:%.*]],812// CHECK: [[__RET:%.*]] = alloca %struct.int8x16x2_t, align {{16|8}}813// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0(ptr %a)814// CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]]815// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)816// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x16x2_t, ptr [[RETVAL]], align 16817// CHECK-A64: ret %struct.int8x16x2_t [[TMP4]]818// CHECK-A32: ret void819int8x16x2_t test_vld1q_s8_x2(int8_t const *a) {820 return vld1q_s8_x2(a);821}822 823// CHECK-LABEL: @test_vld1q_s8_x3(824// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x3_t, align 16825// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x16x3_t) align 8 [[RETVAL:%.*]],826// CHECK: [[__RET:%.*]] = alloca %struct.int8x16x3_t, align {{16|8}}827// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0(ptr %a)828// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]]829// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)830// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x16x3_t, ptr [[RETVAL]], align 16831// CHECK-A64: ret %struct.int8x16x3_t [[TMP4]]832// CHECK-A32: ret void833int8x16x3_t test_vld1q_s8_x3(int8_t const *a) {834 return vld1q_s8_x3(a);835}836 837// CHECK-LABEL: @test_vld1q_s8_x4(838// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x4_t, align 16839// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x16x4_t) align 8 [[RETVAL:%.*]],840// CHECK: [[__RET:%.*]] = alloca %struct.int8x16x4_t, align {{16|8}}841// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0(ptr %a)842// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]]843// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)844// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x16x4_t, ptr [[RETVAL]], align 16845// CHECK-A64: ret %struct.int8x16x4_t [[TMP4]]846// CHECK-A32: ret void847int8x16x4_t test_vld1q_s8_x4(int8_t const *a) {848 return vld1q_s8_x4(a);849}850 851// CHECK-LABEL: @test_vld1q_u16_x2(852// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x2_t, align 16853// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x8x2_t) align 8 [[RETVAL:%.*]],854// CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x2_t, align {{16|8}}855// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0(ptr %a)856// CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]]857// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)858// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x8x2_t, ptr [[RETVAL]], align 16859// CHECK-A64: ret %struct.uint16x8x2_t [[TMP6]]860// CHECK-A32: ret void861uint16x8x2_t test_vld1q_u16_x2(uint16_t const *a) {862 return vld1q_u16_x2(a);863}864 865// CHECK-LABEL: @test_vld1q_u16_x3(866// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x3_t, align 16867// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x8x3_t) align 8 [[RETVAL:%.*]],868// CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x3_t, align {{16|8}}869// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0(ptr %a)870// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]]871// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)872// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x8x3_t, ptr [[RETVAL]], align 16873// CHECK-A64: ret %struct.uint16x8x3_t [[TMP6]]874// CHECK-A32: ret void875uint16x8x3_t test_vld1q_u16_x3(uint16_t const *a) {876 return vld1q_u16_x3(a);877}878 879// CHECK-LABEL: @test_vld1q_u16_x4(880// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x4_t, align 16881// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x8x4_t) align 8 [[RETVAL:%.*]],882// CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x4_t, align {{16|8}}883// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0(ptr %a)884// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]]885// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)886// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x8x4_t, ptr [[RETVAL]], align 16887// CHECK-A64: ret %struct.uint16x8x4_t [[TMP6]]888// CHECK-A32: ret void889uint16x8x4_t test_vld1q_u16_x4(uint16_t const *a) {890 return vld1q_u16_x4(a);891}892 893// CHECK-LABEL: @test_vld1q_u32_x2(894// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x2_t, align 16895// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x4x2_t) align 8 [[RETVAL:%.*]],896// CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x2_t, align {{16|8}}897// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i32.p0(ptr %a)898// CHECK: store { <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]]899// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)900// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x4x2_t, ptr [[RETVAL]], align 16901// CHECK-A64: ret %struct.uint32x4x2_t [[TMP6]]902// CHECK-A32: ret void903uint32x4x2_t test_vld1q_u32_x2(uint32_t const *a) {904 return vld1q_u32_x2(a);905}906 907// CHECK-LABEL: @test_vld1q_u32_x3(908// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x3_t, align 16909// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x4x3_t) align 8 [[RETVAL:%.*]],910// CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x3_t, align {{16|8}}911// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i32.p0(ptr %a)912// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]]913// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)914// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x4x3_t, ptr [[RETVAL]], align 16915// CHECK-A64: ret %struct.uint32x4x3_t [[TMP6]]916// CHECK-A32: ret void917uint32x4x3_t test_vld1q_u32_x3(uint32_t const *a) {918 return vld1q_u32_x3(a);919}920 921// CHECK-LABEL: @test_vld1q_u32_x4(922// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x4_t, align 16923// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x4x4_t) align 8 [[RETVAL:%.*]],924// CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x4_t, align {{16|8}}925// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i32.p0(ptr %a)926// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]]927// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)928// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x4x4_t, ptr [[RETVAL]], align 16929// CHECK-A64: ret %struct.uint32x4x4_t [[TMP6]]930// CHECK-A32: ret void931uint32x4x4_t test_vld1q_u32_x4(uint32_t const *a) {932 return vld1q_u32_x4(a);933}934 935// CHECK-LABEL: @test_vld1q_u64_x2(936// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x2_t, align 16937// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x2x2_t) align 8 [[RETVAL:%.*]],938// CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x2_t, align {{16|8}}939// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i64.p0(ptr %a)940// CHECK: store { <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]]941// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)942// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x2x2_t, ptr [[RETVAL]], align 16943// CHECK-A64: ret %struct.uint64x2x2_t [[TMP6]]944// CHECK-A32: ret void945uint64x2x2_t test_vld1q_u64_x2(uint64_t const *a) {946 return vld1q_u64_x2(a);947}948 949// CHECK-LABEL: @test_vld1q_u64_x3(950// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x3_t, align 16951// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x2x3_t) align 8 [[RETVAL:%.*]],952// CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x3_t, align {{16|8}}953// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i64.p0(ptr %a)954// CHECK: store { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]]955// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)956// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x2x3_t, ptr [[RETVAL]], align 16957// CHECK-A64: ret %struct.uint64x2x3_t [[TMP6]]958// CHECK-A32: ret void959uint64x2x3_t test_vld1q_u64_x3(uint64_t const *a) {960 return vld1q_u64_x3(a);961}962 963// CHECK-LABEL: @test_vld1q_u64_x4(964// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x4_t, align 16965// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x2x4_t) align 8 [[RETVAL:%.*]],966// CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x4_t, align {{16|8}}967// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i64.p0(ptr %a)968// CHECK: store { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]]969// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)970// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x2x4_t, ptr [[RETVAL]], align 16971// CHECK-A64: ret %struct.uint64x2x4_t [[TMP6]]972// CHECK-A32: ret void973uint64x2x4_t test_vld1q_u64_x4(uint64_t const *a) {974 return vld1q_u64_x4(a);975}976 977// CHECK-LABEL: @test_vld1q_u8_x2(978// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x2_t, align 16979// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x16x2_t) align 8 [[RETVAL:%.*]],980// CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x2_t, align {{16|8}}981// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0(ptr %a)982// CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]]983// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)984// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x16x2_t, ptr [[RETVAL]], align 16985// CHECK-A64: ret %struct.uint8x16x2_t [[TMP4]]986// CHECK-A32: ret void987uint8x16x2_t test_vld1q_u8_x2(uint8_t const *a) {988 return vld1q_u8_x2(a);989}990 991// CHECK-LABEL: @test_vld1q_u8_x3(992// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x3_t, align 16993// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x16x3_t) align 8 [[RETVAL:%.*]],994// CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x3_t, align {{16|8}}995// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0(ptr %a)996// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]]997// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)998// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x16x3_t, ptr [[RETVAL]], align 16999// CHECK-A64: ret %struct.uint8x16x3_t [[TMP4]]1000// CHECK-A32: ret void1001uint8x16x3_t test_vld1q_u8_x3(uint8_t const *a) {1002 return vld1q_u8_x3(a);1003}1004 1005// CHECK-LABEL: @test_vld1q_u8_x4(1006// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x4_t, align 161007// CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x16x4_t) align 8 [[RETVAL:%.*]],1008// CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x4_t, align {{16|8}}1009// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0(ptr %a)1010// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]]1011// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1012// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x16x4_t, ptr [[RETVAL]], align 161013// CHECK-A64: ret %struct.uint8x16x4_t [[TMP4]]1014// CHECK-A32: ret void1015uint8x16x4_t test_vld1q_u8_x4(uint8_t const *a) {1016 return vld1q_u8_x4(a);1017}1018 1019// CHECK-LABEL: @test_vld2_dup_f16(1020// CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 81021// CHECK-A64: [[VLD2:%.*]] = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0(ptr %src)1022// CHECK-A32: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2dup.v4i16.p0(ptr %src, i32 2)1023// CHECK: store { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]> } [[VLD2]], ptr [[__RET]]1024// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1025// CHECK: ret void1026void test_vld2_dup_f16(float16x4x2_t *dest, const float16_t *src) {1027 *dest = vld2_dup_f16(src);1028}1029 1030// CHECK-LABEL: @test_vld2_dup_f32(1031// CHECK: [[__RET:%.*]] = alloca %struct.float32x2x2_t, align 81032// CHECK-A64: [[VLD2:%.*]] = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2r.v2f32.p0(ptr %src)1033// CHECK-A32: [[VLD2:%.*]] = call { <2 x float>, <2 x float> } @llvm.arm.neon.vld2dup.v2f32.p0(ptr %src, i32 4)1034// CHECK: store { <2 x float>, <2 x float> } [[VLD2]], ptr [[__RET]]1035// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1036// CHECK: ret void1037void test_vld2_dup_f32(float32x2x2_t *dest, const float32_t *src) {1038 *dest = vld2_dup_f32(src);1039}1040 1041// CHECK-LABEL: @test_vld2_dup_p16(1042// CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x2_t, align 81043// CHECK-A64: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0(ptr %src)1044// CHECK-A32: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2dup.v4i16.p0(ptr %src, i32 2)1045// CHECK: store { <4 x i16>, <4 x i16> } [[VLD2]], ptr [[__RET]]1046// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1047// CHECK: ret void1048void test_vld2_dup_p16(poly16x4x2_t *dest, const poly16_t *src) {1049 *dest = vld2_dup_p16(src);1050}1051 1052// CHECK-LABEL: @test_vld2_dup_p8(1053// CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x2_t, align 81054// CHECK-A64: [[VLD2:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0(ptr %src)1055// CHECK-A32: [[VLD2:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2dup.v8i8.p0(ptr %src, i32 1)1056// CHECK: store { <8 x i8>, <8 x i8> } [[VLD2]], ptr [[__RET]]1057// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1058// CHECK: ret void1059void test_vld2_dup_p8(poly8x8x2_t *dest, poly8_t *src) {1060 *dest = vld2_dup_p8(src);1061}1062 1063// CHECK-LABEL: @test_vld2_dup_s16(1064// CHECK: [[__RET:%.*]] = alloca %struct.int16x4x2_t, align 81065// CHECK-A64: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0(ptr %src)1066// CHECK-A32: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2dup.v4i16.p0(ptr %src, i32 2)1067// CHECK: store { <4 x i16>, <4 x i16> } [[VLD2]], ptr [[__RET]]1068// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1069// CHECK: ret void1070void test_vld2_dup_s16(int16x4x2_t *dest, const int16_t *src) {1071 *dest = vld2_dup_s16(src);1072}1073 1074// CHECK-LABEL: @test_vld2_dup_s32(1075// CHECK: [[__RET:%.*]] = alloca %struct.int32x2x2_t, align 81076// CHECK-A64: [[VLD2:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2r.v2i32.p0(ptr %src)1077// CHECK-A32: [[VLD2:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2dup.v2i32.p0(ptr %src, i32 4)1078// CHECK: store { <2 x i32>, <2 x i32> } [[VLD2]], ptr [[__RET]]1079// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1080// CHECK: ret void1081void test_vld2_dup_s32(int32x2x2_t *dest, const int32_t *src) {1082 *dest = vld2_dup_s32(src);1083}1084 1085// CHECK-LABEL: @test_vld2_dup_s8(1086// CHECK: [[__RET:%.*]] = alloca %struct.int8x8x2_t, align 81087// CHECK-A64: [[VLD2:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0(ptr %src)1088// CHECK-A32: [[VLD2:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2dup.v8i8.p0(ptr %src, i32 1)1089// CHECK: store { <8 x i8>, <8 x i8> } [[VLD2]], ptr [[__RET]]1090// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1091// CHECK: ret void1092void test_vld2_dup_s8(int8x8x2_t *dest, int8_t *src) {1093 *dest = vld2_dup_s8(src);1094}1095 1096// CHECK-LABEL: @test_vld2_dup_u16(1097// CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x2_t, align 81098// CHECK-A64: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0(ptr %src)1099// CHECK-A32: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2dup.v4i16.p0(ptr %src, i32 2)1100// CHECK: store { <4 x i16>, <4 x i16> } [[VLD2]], ptr [[__RET]]1101// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1102// CHECK: ret void1103void test_vld2_dup_u16(uint16x4x2_t *dest, const uint16_t *src) {1104 *dest = vld2_dup_u16(src);1105}1106 1107// CHECK-LABEL: @test_vld2_dup_u32(1108// CHECK: entry:1109// CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x2_t, align 81110// CHECK-A64: [[VLD2:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2r.v2i32.p0(ptr %src)1111// CHECK-A32: [[VLD2:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2dup.v2i32.p0(ptr %src, i32 4)1112// CHECK: store { <2 x i32>, <2 x i32> } [[VLD2]], ptr [[__RET]]1113// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1114// CHECK: ret void1115void test_vld2_dup_u32(uint32x2x2_t *dest, const uint32_t *src) {1116 *dest = vld2_dup_u32(src);1117}1118 1119// CHECK-LABEL: @test_vld2_dup_s64(1120// CHECK: [[__RET:%.*]] = alloca %struct.int64x1x2_t, align 81121// CHECK-A64: [[VLD2:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2r.v1i64.p0(ptr %src)1122// CHECK-A32: [[VLD2:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.arm.neon.vld2dup.v1i64.p0(ptr %src, i32 8)1123// CHECK: store { <1 x i64>, <1 x i64> } [[VLD2]], ptr [[__RET]]1124// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1125// CHECK: ret void1126void test_vld2_dup_s64(int64x1x2_t *dest, const int64_t *src) {1127 *dest = vld2_dup_s64(src);1128}1129 1130// CHECK-LABEL: @test_vld2_dup_u64(1131// CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x2_t, align 81132// CHECK-A64: [[VLD2:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2r.v1i64.p0(ptr %src)1133// CHECK-A32: [[VLD2:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.arm.neon.vld2dup.v1i64.p0(ptr %src, i32 8)1134// CHECK: store { <1 x i64>, <1 x i64> } [[VLD2]], ptr [[__RET]]1135// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1136// CHECK: ret void1137void test_vld2_dup_u64(uint64x1x2_t *dest, const uint64_t *src) {1138 *dest = vld2_dup_u64(src);1139}1140 1141// CHECK-LABEL: @test_vld2_dup_u8(1142// CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x2_t, align 81143// CHECK-A64: [[VLD2:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0(ptr %src)1144// CHECK-A32: [[VLD2:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2dup.v8i8.p0(ptr %src, i32 1)1145// CHECK: store { <8 x i8>, <8 x i8> } [[VLD2]], ptr [[__RET]]1146// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false)1147// CHECK: ret void1148void test_vld2_dup_u8(uint8x8x2_t *dest, const uint8_t *src) {1149 *dest = vld2_dup_u8(src);1150}1151 1152// CHECK-LABEL: @test_vld3_dup_f16(1153// CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 81154// CHECK-A64: [[VLD3:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0(ptr %src)1155// CHECK-A32: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3dup.v4i16.p0(ptr %src, i32 2)1156// CHECK: store { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD3]], ptr [[__RET]]1157// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1158// CHECK: ret void1159void test_vld3_dup_f16(float16x4x3_t *dest, float16_t *src) {1160 *dest = vld3_dup_f16(src);1161}1162 1163// CHECK-LABEL: @test_vld3_dup_f32(1164// CHECK: [[__RET:%.*]] = alloca %struct.float32x2x3_t, align 81165// CHECK-A64: [[VLD3:%.*]] = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3r.v2f32.p0(ptr %src)1166// CHECK-A32: [[VLD3:%.*]] = call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld3dup.v2f32.p0(ptr %src, i32 4)1167// CHECK: store { <2 x float>, <2 x float>, <2 x float> } [[VLD3]], ptr [[__RET]]1168// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1169// CHECK: ret void1170void test_vld3_dup_f32(float32x2x3_t *dest, const float32_t *src) {1171 *dest = vld3_dup_f32(src);1172}1173 1174// CHECK-LABEL: @test_vld3_dup_p16(1175// CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x3_t, align 81176// CHECK-A64: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0(ptr %src)1177// CHECK-A32: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3dup.v4i16.p0(ptr %src, i32 2)1178// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3]], ptr [[__RET]]1179// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1180// CHECK: ret void1181void test_vld3_dup_p16(poly16x4x3_t *dest, const poly16_t *src) {1182 *dest = vld3_dup_p16(src);1183}1184 1185// CHECK-LABEL: @test_vld3_dup_p8(1186// CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x3_t, align 81187// CHECK-A64: [[VLD3:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0(ptr %src)1188// CHECK-A32: [[VLD3:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3dup.v8i8.p0(ptr %src, i32 1)1189// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3]], ptr [[__RET]]1190// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1191// CHECK: ret void1192void test_vld3_dup_p8(poly8x8x3_t *dest, const poly8_t *src) {1193 *dest = vld3_dup_p8(src);1194}1195 1196// CHECK-LABEL: @test_vld3_dup_s16(1197// CHECK: [[__RET:%.*]] = alloca %struct.int16x4x3_t, align 81198// CHECK-A64: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0(ptr %src)1199// CHECK-A32: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3dup.v4i16.p0(ptr %src, i32 2)1200// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3]], ptr [[__RET]]1201// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1202// CHECK: ret void1203void test_vld3_dup_s16(int16x4x3_t *dest, const int16_t *src) {1204 *dest = vld3_dup_s16(src);1205}1206 1207// CHECK-LABEL: @test_vld3_dup_s32(1208// CHECK: [[__RET:%.*]] = alloca %struct.int32x2x3_t, align 81209// CHECK-A64: [[VLD3:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3r.v2i32.p0(ptr %src)1210// CHECK-A32: [[VLD3:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3dup.v2i32.p0(ptr %src, i32 4)1211// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3]], ptr [[__RET]]1212// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1213// CHECK: ret void1214void test_vld3_dup_s32(int32x2x3_t *dest, const int32_t *src) {1215 *dest = vld3_dup_s32(src);1216}1217 1218// CHECK-LABEL: @test_vld3_dup_s8(1219// CHECK: [[__RET:%.*]] = alloca %struct.int8x8x3_t, align 81220// CHECK-A64: [[VLD3:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0(ptr %src)1221// CHECK-A32: [[VLD3:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3dup.v8i8.p0(ptr %src, i32 1)1222// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3]], ptr [[__RET]]1223// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1224// CHECK: ret void1225void test_vld3_dup_s8(int8x8x3_t *dest, const int8_t *src) {1226 *dest = vld3_dup_s8(src);1227}1228 1229// CHECK-LABEL: @test_vld3_dup_u16(1230// CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x3_t, align 81231// CHECK-A64: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0(ptr %src)1232// CHECK-A32: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3dup.v4i16.p0(ptr %src, i32 2)1233// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3]], ptr [[__RET]]1234// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1235// CHECK: ret void1236void test_vld3_dup_u16(uint16x4x3_t *dest, const uint16_t *src) {1237 *dest = vld3_dup_u16(src);1238}1239 1240// CHECK-LABEL: @test_vld3_dup_u32(1241// CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x3_t, align 81242// CHECK-A64: [[VLD3:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3r.v2i32.p0(ptr %src)1243// CHECK-A32: [[VLD3:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3dup.v2i32.p0(ptr %src, i32 4)1244// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3]], ptr [[__RET]]1245// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1246// CHECK: ret void1247void test_vld3_dup_u32(uint32x2x3_t *dest, const uint32_t *src) {1248 *dest = vld3_dup_u32(src);1249}1250 1251// CHECK-LABEL: @test_vld3_dup_u8(1252// CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x3_t, align 81253// CHECK-A64: [[VLD3:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0(ptr %src)1254// CHECK-A32: [[VLD3:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3dup.v8i8.p0(ptr %src, i32 1)1255// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3]], ptr [[__RET]]1256// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1257// CHECK: ret void1258void test_vld3_dup_u8(uint8x8x3_t *dest, const uint8_t *src) {1259 *dest = vld3_dup_u8(src);1260}1261 1262// CHECK-LABEL: @test_vld3_dup_s64(1263// CHECK: [[__RET:%.*]] = alloca %struct.int64x1x3_t, align 81264// CHECK-A64: [[VLD3:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3r.v1i64.p0(ptr %src)1265// CHECK-A32: [[VLD3:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld3dup.v1i64.p0(ptr %src, i32 8)1266// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD3]], ptr [[__RET]]1267// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1268// CHECK: ret void1269void test_vld3_dup_s64(int64x1x3_t *dest, const int64_t *src) {1270 *dest = vld3_dup_s64(src);1271}1272 1273// CHECK-LABEL: @test_vld3_dup_u64(1274// CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x3_t, align 81275// CHECK-A64: [[VLD3:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3r.v1i64.p0(ptr %src)1276// CHECK-A32: [[VLD3:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld3dup.v1i64.p0(ptr %src, i32 8)1277// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD3]], ptr [[__RET]]1278// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false)1279// CHECK: ret void1280void test_vld3_dup_u64(uint64x1x3_t *dest, const uint64_t *src) {1281 *dest = vld3_dup_u64(src);1282}1283 1284// CHECK-LABEL: @test_vld4_dup_f16(1285// CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 81286// CHECK-A64: [[VLD4:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0(ptr %src)1287// CHECK-A32: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4dup.v4i16.p0(ptr %src, i32 2)1288// CHECK: store { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD4]], ptr [[__RET]]1289// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1290// CHECK: ret void1291void test_vld4_dup_f16(float16x4x4_t *dest, const float16_t *src) {1292 *dest = vld4_dup_f16(src);1293}1294 1295// CHECK-LABEL: @test_vld4_dup_f32(1296// CHECK: [[__RET:%.*]] = alloca %struct.float32x2x4_t, align 81297// CHECK-A64: [[VLD4:%.*]] = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4r.v2f32.p0(ptr %src)1298// CHECK-A32: [[VLD4:%.*]] = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld4dup.v2f32.p0(ptr %src, i32 4)1299// CHECK: store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD4]], ptr [[__RET]]1300// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1301// CHECK: ret void1302void test_vld4_dup_f32(float32x2x4_t *dest, const float32_t *src) {1303 *dest = vld4_dup_f32(src);1304}1305 1306// CHECK-LABEL: @test_vld4_dup_p16(1307// CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x4_t, align 81308// CHECK-A64: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0(ptr %src)1309// CHECK-A32: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4dup.v4i16.p0(ptr %src, i32 2)1310// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4]], ptr [[__RET]]1311// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1312// CHECK: ret void1313void test_vld4_dup_p16(poly16x4x4_t *dest, const poly16_t *src) {1314 *dest = vld4_dup_p16(src);1315}1316 1317// CHECK-LABEL: @test_vld4_dup_p8(1318// CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x4_t, align 81319// CHECK-A64: [[VLD4:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0(ptr %src)1320// CHECK-A32: [[VLD4:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4dup.v8i8.p0(ptr %src, i32 1)1321// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4]], ptr [[__RET]]1322// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1323// CHECK: ret void1324void test_vld4_dup_p8(poly8x8x4_t *dest, const poly8_t *src) {1325 *dest = vld4_dup_p8(src);1326}1327 1328// CHECK-LABEL: @test_vld4_dup_s16(1329// CHECK: [[__RET:%.*]] = alloca %struct.int16x4x4_t, align 81330// CHECK-A64: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0(ptr %src)1331// CHECK-A32: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4dup.v4i16.p0(ptr %src, i32 2)1332// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4]], ptr [[__RET]]1333// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1334// CHECK: ret void1335void test_vld4_dup_s16(int16x4x4_t *dest, const int16_t *src) {1336 *dest = vld4_dup_s16(src);1337}1338 1339// CHECK-LABEL: @test_vld4_dup_s32(1340// CHECK: [[__RET:%.*]] = alloca %struct.int32x2x4_t, align 81341// CHECK-A64: [[VLD4:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4r.v2i32.p0(ptr %src)1342// CHECK-A32: [[VLD4:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4dup.v2i32.p0(ptr %src, i32 4)1343// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4]], ptr [[__RET]]1344// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1345// CHECK: ret void1346void test_vld4_dup_s32(int32x2x4_t *dest, const int32_t *src) {1347 *dest = vld4_dup_s32(src);1348}1349 1350// CHECK-LABEL: @test_vld4_dup_s8(1351// CHECK: [[__RET:%.*]] = alloca %struct.int8x8x4_t, align 81352// CHECK-A64: [[VLD4:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0(ptr %src)1353// CHECK-A32: [[VLD4:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4dup.v8i8.p0(ptr %src, i32 1)1354// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4]], ptr [[__RET]]1355// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1356// CHECK: ret void1357void test_vld4_dup_s8(int8x8x4_t *dest, const int8_t *src) {1358 *dest = vld4_dup_s8(src);1359}1360 1361// CHECK-LABEL: @test_vld4_dup_u16(1362// CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x4_t, align 81363// CHECK-A64: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0(ptr %src)1364// CHECK-A32: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4dup.v4i16.p0(ptr %src, i32 2)1365// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4]], ptr [[__RET]]1366// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1367// CHECK: ret void1368void test_vld4_dup_u16(uint16x4x4_t *dest, const uint16_t *src) {1369 *dest = vld4_dup_u16(src);1370}1371 1372// CHECK-LABEL: @test_vld4_dup_u32(1373// CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x4_t, align 81374// CHECK-A64: [[VLD4:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4r.v2i32.p0(ptr %src)1375// CHECK-A32: [[VLD4:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4dup.v2i32.p0(ptr %src, i32 4)1376// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4]], ptr [[__RET]]1377// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1378// CHECK: ret void1379void test_vld4_dup_u32(uint32x2x4_t *dest, const uint32_t *src) {1380 *dest = vld4_dup_u32(src);1381}1382 1383// CHECK-LABEL: @test_vld4_dup_u8(1384// CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x4_t, align 81385// CHECK-A64: [[VLD4:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0(ptr %src)1386// CHECK-A32: [[VLD4:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4dup.v8i8.p0(ptr %src, i32 1)1387// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4]], ptr [[__RET]]1388// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1389// CHECK: ret void1390void test_vld4_dup_u8(uint8x8x4_t *dest, const uint8_t *src) {1391 *dest = vld4_dup_u8(src);1392}1393 1394// CHECK-LABEL: @test_vld4_dup_s64(1395// CHECK: [[__RET:%.*]] = alloca %struct.int64x1x4_t, align 81396// CHECK-A64: [[VLD4:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4r.v1i64.p0(ptr %src)1397// CHECK-A32: [[VLD4:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld4dup.v1i64.p0(ptr %src, i32 8)1398// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4]], ptr [[__RET]]1399// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1400// CHECK: ret void1401void test_vld4_dup_s64(int64x1x4_t *dest, const int64_t *src) {1402 *dest = vld4_dup_s64(src);1403}1404 1405// CHECK-LABEL: @test_vld4_dup_u64(1406// CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x4_t, align 81407// CHECK-A64: [[VLD4:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4r.v1i64.p0(ptr %src)1408// CHECK-A32: [[VLD4:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld4dup.v1i64.p0(ptr %src, i32 8)1409// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4]], ptr [[__RET]]1410// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 %dest, ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false)1411// CHECK: ret void1412void test_vld4_dup_u64(uint64x1x4_t *dest, const uint64_t *src) {1413 *dest = vld4_dup_u64(src);1414}1415 1416// CHECK-LABEL: @test_vld2q_dup_f16(1417// CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align {{16|8}}1418// CHECK-A64: [[VLD2:%.*]] = call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0(ptr %src)1419// CHECK-A32: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2dup.v8i16.p0(ptr %src, i32 2)1420// CHECK: store { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]> } [[VLD2]], ptr [[__RET]]1421// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)1422// CHECK: ret void1423void test_vld2q_dup_f16(float16x8x2_t *dest, const float16_t *src) {1424 *dest = vld2q_dup_f16(src);1425}1426 1427// CHECK-LABEL: @test_vld2q_dup_f32(1428// CHECK: [[__RET:%.*]] = alloca %struct.float32x4x2_t, align {{16|8}}1429// CHECK-A64: [[VLD2:%.*]] = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2r.v4f32.p0(ptr %src)1430// CHECK-A32: [[VLD2:%.*]] = call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2dup.v4f32.p0(ptr %src, i32 4)1431// CHECK: store { <4 x float>, <4 x float> } [[VLD2]], ptr [[__RET]]1432// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)1433// CHECK: ret void1434void test_vld2q_dup_f32(float32x4x2_t *dest, const float32_t *src) {1435 *dest = vld2q_dup_f32(src);1436}1437 1438// CHECK-LABEL: @test_vld2q_dup_p16(1439// CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x2_t, align {{16|8}}1440// CHECK-A64: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0(ptr %src)1441// CHECK-A32: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2dup.v8i16.p0(ptr %src, i32 2)1442// CHECK: store { <8 x i16>, <8 x i16> } [[VLD2]], ptr [[__RET]]1443// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)1444// CHECK: ret void1445void test_vld2q_dup_p16(poly16x8x2_t *dest, const poly16_t *src) {1446 *dest = vld2q_dup_p16(src);1447}1448 1449// CHECK-LABEL: @test_vld2q_dup_p8(1450// CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x2_t, align {{16|8}}1451// CHECK-A64: [[VLD2:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0(ptr %src)1452// CHECK-A32: [[VLD2:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2dup.v16i8.p0(ptr %src, i32 1)1453// CHECK: store { <16 x i8>, <16 x i8> } [[VLD2]], ptr [[__RET]]1454// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)1455// CHECK: ret void1456void test_vld2q_dup_p8(poly8x16x2_t *dest, const poly8_t *src) {1457 *dest = vld2q_dup_p8(src);1458}1459 1460// CHECK-LABEL: @test_vld2q_dup_s16(1461// CHECK: [[__RET:%.*]] = alloca %struct.int16x8x2_t, align {{16|8}}1462// CHECK-A64: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0(ptr %src)1463// CHECK-A32: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2dup.v8i16.p0(ptr %src, i32 2)1464// CHECK: store { <8 x i16>, <8 x i16> } [[VLD2]], ptr [[__RET]]1465// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)1466// CHECK: ret void1467void test_vld2q_dup_s16(int16x8x2_t *dest, const int16_t *src) {1468 *dest = vld2q_dup_s16(src);1469}1470 1471// CHECK-LABEL: @test_vld2q_dup_s32(1472// CHECK: [[__RET:%.*]] = alloca %struct.int32x4x2_t, align {{16|8}}1473// CHECK-A64: [[VLD2:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2r.v4i32.p0(ptr %src)1474// CHECK-A32: [[VLD2:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2dup.v4i32.p0(ptr %src, i32 4)1475// CHECK: store { <4 x i32>, <4 x i32> } [[VLD2]], ptr [[__RET]]1476// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)1477// CHECK: ret void1478void test_vld2q_dup_s32(int32x4x2_t *dest, const int32_t *src) {1479 *dest = vld2q_dup_s32(src);1480}1481 1482// CHECK-LABEL: @test_vld2q_dup_s8(1483// CHECK: [[__RET:%.*]] = alloca %struct.int8x16x2_t, align {{16|8}}1484// CHECK-A64: [[VLD2:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0(ptr %src)1485// CHECK-A32: [[VLD2:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2dup.v16i8.p0(ptr %src, i32 1)1486// CHECK: store { <16 x i8>, <16 x i8> } [[VLD2]], ptr [[__RET]]1487// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)1488// CHECK: ret void1489void test_vld2q_dup_s8(int8x16x2_t *dest, const int8_t *src) {1490 *dest = vld2q_dup_s8(src);1491}1492 1493// CHECK-LABEL: @test_vld2q_dup_u16(1494// CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x2_t, align {{16|8}}1495// CHECK-A64: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0(ptr %src)1496// CHECK-A32: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2dup.v8i16.p0(ptr %src, i32 2)1497// CHECK: store { <8 x i16>, <8 x i16> } [[VLD2]], ptr [[__RET]]1498// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)1499// CHECK: ret void1500void test_vld2q_dup_u16(uint16x8x2_t *dest, const uint16_t *src) {1501 *dest = vld2q_dup_u16(src);1502}1503 1504// CHECK-LABEL: @test_vld2q_dup_u32(1505// CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x2_t, align {{16|8}}1506// CHECK-A64: [[VLD2:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2r.v4i32.p0(ptr %src)1507// CHECK-A32: [[VLD2:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2dup.v4i32.p0(ptr %src, i32 4)1508// CHECK: store { <4 x i32>, <4 x i32> } [[VLD2]], ptr [[__RET]]1509// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)1510// CHECK: ret void1511void test_vld2q_dup_u32(uint32x4x2_t *dest, const uint32_t *src) {1512 *dest = vld2q_dup_u32(src);1513}1514 1515// CHECK-LABEL: @test_vld2q_dup_u8(1516// CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x2_t, align {{16|8}}1517// CHECK-A64: [[VLD2:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0(ptr %src)1518// CHECK-A32: [[VLD2:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2dup.v16i8.p0(ptr %src, i32 1)1519// CHECK: store { <16 x i8>, <16 x i8> } [[VLD2]], ptr [[__RET]]1520// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false)1521// CHECK: ret void1522void test_vld2q_dup_u8(uint8x16x2_t *dest, const uint8_t *src) {1523 *dest = vld2q_dup_u8(src);1524}1525 1526// CHECK-LABEL: @test_vld3q_dup_f16(1527// CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align {{16|8}}1528// CHECK-A64: [[VLD3:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0(ptr %src)1529// CHECK-A32: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3dup.v8i16.p0(ptr %src, i32 2)1530// CHECK: store { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD3]], ptr [[__RET]]1531// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)1532// CHECK: ret void1533void test_vld3q_dup_f16(float16x8x3_t *dest, const float16_t *src) {1534 *dest = vld3q_dup_f16(src);1535}1536 1537// CHECK-LABEL: @test_vld3q_dup_f32(1538// CHECK: [[__RET:%.*]] = alloca %struct.float32x4x3_t, align {{16|8}}1539// CHECK-A64: [[VLD3:%.*]] = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3r.v4f32.p0(ptr %src)1540// CHECK-A32: [[VLD3:%.*]] = call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3dup.v4f32.p0(ptr %src, i32 4)1541// CHECK: store { <4 x float>, <4 x float>, <4 x float> } [[VLD3]], ptr [[__RET]]1542// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)1543// CHECK: ret void1544void test_vld3q_dup_f32(float32x4x3_t *dest, const float32_t *src) {1545 *dest = vld3q_dup_f32(src);1546}1547 1548// CHECK-LABEL: @test_vld3q_dup_p16(1549// CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x3_t, align {{16|8}}1550// CHECK-A64: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0(ptr %src)1551// CHECK-A32: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3dup.v8i16.p0(ptr %src, i32 2)1552// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3]], ptr [[__RET]]1553// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)1554// CHECK: ret void1555void test_vld3q_dup_p16(poly16x8x3_t *dest, const poly16_t *src) {1556 *dest = vld3q_dup_p16(src);1557}1558 1559// CHECK-LABEL: @test_vld3q_dup_p8(1560// CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x3_t, align {{16|8}}1561// CHECK-A64: [[VLD3:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0(ptr %src)1562// CHECK-A32: [[VLD3:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3dup.v16i8.p0(ptr %src, i32 1)1563// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3]], ptr [[__RET]]1564// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)1565// CHECK: ret void1566void test_vld3q_dup_p8(poly8x16x3_t *dest, const poly8_t *src) {1567 *dest = vld3q_dup_p8(src);1568}1569 1570// CHECK-LABEL: @test_vld3q_dup_s16(1571// CHECK: [[__RET:%.*]] = alloca %struct.int16x8x3_t, align {{16|8}}1572// CHECK-A64: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0(ptr %src)1573// CHECK-A32: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3dup.v8i16.p0(ptr %src, i32 2)1574// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3]], ptr [[__RET]]1575// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)1576// CHECK: ret void1577void test_vld3q_dup_s16(int16x8x3_t *dest, const int16_t *src) {1578 *dest = vld3q_dup_s16(src);1579}1580 1581// CHECK-LABEL: @test_vld3q_dup_s32(1582// CHECK: [[__RET:%.*]] = alloca %struct.int32x4x3_t, align {{16|8}}1583// CHECK-A64: [[VLD3:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3r.v4i32.p0(ptr %src)1584// CHECK-A32: [[VLD3:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3dup.v4i32.p0(ptr %src, i32 4)1585// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3]], ptr [[__RET]]1586// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)1587// CHECK: ret void1588void test_vld3q_dup_s32(int32x4x3_t *dest, const int32_t *src) {1589 *dest = vld3q_dup_s32(src);1590}1591 1592// CHECK-LABEL: @test_vld3q_dup_s8(1593// CHECK: [[__RET:%.*]] = alloca %struct.int8x16x3_t, align {{16|8}}1594// CHECK-A64: [[VLD3:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0(ptr %src)1595// CHECK-A32: [[VLD3:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3dup.v16i8.p0(ptr %src, i32 1)1596// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3]], ptr [[__RET]]1597// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)1598// CHECK: ret void1599void test_vld3q_dup_s8(int8x16x3_t *dest, const int8_t *src) {1600 *dest = vld3q_dup_s8(src);1601}1602 1603// CHECK-LABEL: @test_vld3q_dup_u16(1604// CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x3_t, align {{16|8}}1605// CHECK-A64: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0(ptr %src)1606// CHECK-A32: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3dup.v8i16.p0(ptr %src, i32 2)1607// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3]], ptr [[__RET]]1608// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)1609// CHECK: ret void1610void test_vld3q_dup_u16(uint16x8x3_t *dest, const uint16_t *src) {1611 *dest = vld3q_dup_u16(src);1612}1613 1614// CHECK-LABEL: @test_vld3q_dup_u32(1615// CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x3_t, align {{16|8}}1616// CHECK-A64: [[VLD3:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3r.v4i32.p0(ptr %src)1617// CHECK-A32: [[VLD3:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3dup.v4i32.p0(ptr %src, i32 4)1618// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3]], ptr [[__RET]]1619// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)1620// CHECK: ret void1621void test_vld3q_dup_u32(uint32x4x3_t *dest, const uint32_t *src) {1622 *dest = vld3q_dup_u32(src);1623}1624 1625// CHECK-LABEL: @test_vld3q_dup_u8(1626// CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x3_t, align {{16|8}}1627// CHECK-A64: [[VLD3:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0(ptr %src)1628// CHECK-A32: [[VLD3:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3dup.v16i8.p0(ptr %src, i32 1)1629// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3]], ptr [[__RET]]1630// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false)1631// CHECK: ret void1632void test_vld3q_dup_u8(uint8x16x3_t *dest, const uint8_t *src) {1633 *dest = vld3q_dup_u8(src);1634}1635 1636// CHECK-LABEL: @test_vld4q_dup_f16(1637// CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align {{16|8}}1638// CHECK-A64: [[VLD4:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0(ptr %src)1639// CHECK-A32: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4dup.v8i16.p0(ptr %src, i32 2)1640// CHECK: store { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD4]], ptr [[__RET]]1641// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1642// CHECK: ret void1643void test_vld4q_dup_f16(float16x8x4_t *dest, const float16_t *src) {1644 *dest = vld4q_dup_f16(src);1645}1646 1647// CHECK-LABEL: @test_vld4q_dup_f32(1648// CHECK: [[__RET:%.*]] = alloca %struct.float32x4x4_t, align {{16|8}}1649// CHECK-A64: [[VLD4:%.*]] = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4r.v4f32.p0(ptr %src)1650// CHECK-A32: [[VLD4:%.*]] = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4dup.v4f32.p0(ptr %src, i32 4)1651// CHECK: store { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD4]], ptr [[__RET]]1652// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1653// CHECK: ret void1654void test_vld4q_dup_f32(float32x4x4_t *dest, const float32_t *src) {1655 *dest = vld4q_dup_f32(src);1656}1657 1658// CHECK-LABEL: @test_vld4q_dup_p16(1659// CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x4_t, align {{16|8}}1660// CHECK-A64: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0(ptr %src)1661// CHECK-A32: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4dup.v8i16.p0(ptr %src, i32 2)1662// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4]], ptr [[__RET]]1663// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1664// CHECK: ret void1665void test_vld4q_dup_p16(poly16x8x4_t *dest, const poly16_t *src) {1666 *dest = vld4q_dup_p16(src);1667}1668 1669// CHECK-LABEL: @test_vld4q_dup_p8(1670// CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x4_t, align {{16|8}}1671// CHECK-A64: [[VLD4:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0(ptr %src)1672// CHECK-A32: [[VLD4:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4dup.v16i8.p0(ptr %src, i32 1)1673// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4]], ptr [[__RET]]1674// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1675// CHECK: ret void1676void test_vld4q_dup_p8(poly8x16x4_t *dest, const poly8_t *src) {1677 *dest = vld4q_dup_p8(src);1678}1679 1680// CHECK-LABEL: @test_vld4q_dup_s16(1681// CHECK: [[__RET:%.*]] = alloca %struct.int16x8x4_t, align {{16|8}}1682// CHECK-A64: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0(ptr %src)1683// CHECK-A32: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4dup.v8i16.p0(ptr %src, i32 2)1684// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4]], ptr [[__RET]]1685// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1686// CHECK: ret void1687void test_vld4q_dup_s16(int16x8x4_t *dest, const int16_t *src) {1688 *dest = vld4q_dup_s16(src);1689}1690 1691// CHECK-LABEL: @test_vld4q_dup_s32(1692// CHECK: [[__RET:%.*]] = alloca %struct.int32x4x4_t, align {{16|8}}1693// CHECK-A64: [[VLD4:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4r.v4i32.p0(ptr %src)1694// CHECK-A32: [[VLD4:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4dup.v4i32.p0(ptr %src, i32 4)1695// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4]], ptr [[__RET]]1696// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1697// CHECK: ret void1698void test_vld4q_dup_s32(int32x4x4_t *dest, const int32_t *src) {1699 *dest = vld4q_dup_s32(src);1700}1701 1702// CHECK-LABEL: @test_vld4q_dup_s8(1703// CHECK: [[__RET:%.*]] = alloca %struct.int8x16x4_t, align {{16|8}}1704// CHECK-A64: [[VLD4:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0(ptr %src)1705// CHECK-A32: [[VLD4:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4dup.v16i8.p0(ptr %src, i32 1)1706// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4]], ptr [[__RET]]1707// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1708// CHECK: ret void1709void test_vld4q_dup_s8(int8x16x4_t *dest, const int8_t *src) {1710 *dest = vld4q_dup_s8(src);1711}1712 1713// CHECK-LABEL: @test_vld4q_dup_u16(1714// CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x4_t, align {{16|8}}1715// CHECK-A64: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0(ptr %src)1716// CHECK-A32: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4dup.v8i16.p0(ptr %src, i32 2)1717// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4]], ptr [[__RET]]1718// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1719// CHECK: ret void1720void test_vld4q_dup_u16(uint16x8x4_t *dest, const uint16_t *src) {1721 *dest = vld4q_dup_u16(src);1722}1723 1724// CHECK-LABEL: @test_vld4q_dup_u32(1725// CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x4_t, align {{16|8}}1726// CHECK-A64: [[VLD4:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4r.v4i32.p0(ptr %src)1727// CHECK-A32: [[VLD4:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4dup.v4i32.p0(ptr %src, i32 4)1728// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4]], ptr [[__RET]]1729// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1730// CHECK: ret void1731void test_vld4q_dup_u32(uint32x4x4_t *dest, const uint32_t *src) {1732 *dest = vld4q_dup_u32(src);1733}1734 1735// CHECK-LABEL: @test_vld4q_dup_u8(1736// CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x4_t, align {{16|8}}1737// CHECK-A64: [[VLD4:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0(ptr %src)1738// CHECK-A32: [[VLD4:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4dup.v16i8.p0(ptr %src, i32 1)1739// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4]], ptr [[__RET]]1740// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} %dest, ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false)1741// CHECK: ret void1742void test_vld4q_dup_u8(uint8x16x4_t *dest, const uint8_t *src) {1743 *dest = vld4q_dup_u8(src);1744}1745