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1// REQUIRES: aarch64-registered-target2 3// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -S \4// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM5 6// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \7// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR8 9// RUN: %clang_cc1 -triple arm64-darwin -fms-compatibility -emit-llvm \10// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR11 12// From winnt.h13// op0=1 encodings, use with __sys14#define ARM64_SYSINSTR(op0, op1, crn, crm, op2) \15 ( ((op1 & 7) << 11) | \16 ((crn & 15) << 7) | \17 ((crm & 15) << 3) | \18 ((op2 & 7) << 0) )19 20//21// Sampling of instructions22//23#define ARM64_DC_CGDSW_EL1 ARM64_SYSINSTR(1,0, 7,10,6) // Clean of Data and Allocation Tags by Set/Way24#define ARM64_IC_IALLU_EL1 ARM64_SYSINSTR(1,0, 7, 5,0) // Instruction Cache Invalidate All to PoU25#define ARM64_AT_S1E2W ARM64_SYSINSTR(1,4, 7, 8,1) // Translate Stage1, EL2, write26#define ARM64_TLBI_VMALLE1 ARM64_SYSINSTR(1,0, 8, 7,0) // Invalidate stage 1 TLB [CP15_TLBIALL]27#define ARM64_CFP_RCTX ARM64_SYSINSTR(1,3, 7, 3,4) // Control Flow Prediction Restriction by Context28 29// From intrin.h30unsigned int __sys(int, __int64);31 32void check__sys(__int64 v) {33 __int64 ret;34 35 __sys(ARM64_DC_CGDSW_EL1, v);36// CHECK-ASM: msr S1_0_C7_C10_6, x837// CHECK-IR: %[[VAR:.*]] = load i64,38// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 %[[VAR]])39 40 __sys(ARM64_IC_IALLU_EL1, v);41// CHECK-ASM: msr S1_0_C7_C5_0, x842// CHECK-IR: %[[VAR:.*]] = load i64,43// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 %[[VAR]])44 45 __sys(ARM64_AT_S1E2W, v);46// CHECK-ASM: msr S1_4_C7_C8_1, x847// CHECK-IR: %[[VAR:.*]] = load i64,48// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 %[[VAR]])49 50 __sys(ARM64_TLBI_VMALLE1, v);51// CHECK-ASM: msr S1_0_C8_C7_0, x852// CHECK-IR: %[[VAR:.*]] = load i64,53// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 %[[VAR]])54 55 __sys(ARM64_CFP_RCTX, v);56// CHECK-ASM: msr S1_3_C7_C3_4, x857// CHECK-IR: %[[VAR:.*]] = load i64,58// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 %[[VAR]])59}60 61// CHECK-IR: ![[MD2]] = !{!"1:0:7:10:6"}62// CHECK-IR: ![[MD3]] = !{!"1:0:7:5:0"}63// CHECK-IR: ![[MD4]] = !{!"1:4:7:8:1"}64// CHECK-IR: ![[MD5]] = !{!"1:0:8:7:0"}65// CHECK-IR: ![[MD6]] = !{!"1:3:7:3:4"}66