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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -emit-llvm -o - %s | FileCheck %s3 4// REQUIRES: aarch64-registered-target || arm-registered-target5 6#include <arm_neon.h>7 8// CHECK-LABEL: define <2 x double> @rnd5(9// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {10// CHECK-NEXT: [[ENTRY:.*:]]11// CHECK-NEXT: [[__P0_ADDR_I:%.*]] = alloca <2 x double>, align 1612// CHECK-NEXT: [[__RET_I:%.*]] = alloca <2 x double>, align 1613// CHECK-NEXT: [[REF_TMP_I:%.*]] = alloca <16 x i8>, align 1614// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x double>, align 1615// CHECK-NEXT: store <2 x double> [[A]], ptr [[A_ADDR]], align 1616// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 1617// CHECK-NEXT: store <2 x double> [[TMP0]], ptr [[__P0_ADDR_I]], align 1618// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[__P0_ADDR_I]], align 1619// CHECK-NEXT: [[VRNDZ_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>20// CHECK-NEXT: [[VRNDZ1_I:%.*]] = call <2 x double> @llvm.trunc.v2f64(<2 x double> [[VRNDZ_I]])21// CHECK-NEXT: store <2 x double> [[VRNDZ1_I]], ptr [[REF_TMP_I]], align 1622// CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[REF_TMP_I]], align 1623// CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[__RET_I]], align 1624// CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[__RET_I]], align 1625// CHECK-NEXT: ret <2 x double> [[TMP3]]26//27float64x2_t rnd5(float64x2_t a) { return vrndq_f64(a); }28 29// CHECK-LABEL: define <2 x double> @rnd9(30// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {31// CHECK-NEXT: [[ENTRY:.*:]]32// CHECK-NEXT: [[__P0_ADDR_I:%.*]] = alloca <2 x double>, align 1633// CHECK-NEXT: [[__RET_I:%.*]] = alloca <2 x double>, align 1634// CHECK-NEXT: [[REF_TMP_I:%.*]] = alloca <16 x i8>, align 1635// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x double>, align 1636// CHECK-NEXT: store <2 x double> [[A]], ptr [[A_ADDR]], align 1637// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 1638// CHECK-NEXT: store <2 x double> [[TMP0]], ptr [[__P0_ADDR_I]], align 1639// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[__P0_ADDR_I]], align 1640// CHECK-NEXT: [[VRNDN_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>41// CHECK-NEXT: [[VRNDN1_I:%.*]] = call <2 x double> @llvm.roundeven.v2f64(<2 x double> [[VRNDN_I]])42// CHECK-NEXT: store <2 x double> [[VRNDN1_I]], ptr [[REF_TMP_I]], align 1643// CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[REF_TMP_I]], align 1644// CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[__RET_I]], align 1645// CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[__RET_I]], align 1646// CHECK-NEXT: ret <2 x double> [[TMP3]]47//48float64x2_t rnd9(float64x2_t a) { return vrndnq_f64(a); }49 50// CHECK-LABEL: define <2 x double> @rnd13(51// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {52// CHECK-NEXT: [[ENTRY:.*:]]53// CHECK-NEXT: [[__P0_ADDR_I:%.*]] = alloca <2 x double>, align 1654// CHECK-NEXT: [[__RET_I:%.*]] = alloca <2 x double>, align 1655// CHECK-NEXT: [[REF_TMP_I:%.*]] = alloca <16 x i8>, align 1656// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x double>, align 1657// CHECK-NEXT: store <2 x double> [[A]], ptr [[A_ADDR]], align 1658// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 1659// CHECK-NEXT: store <2 x double> [[TMP0]], ptr [[__P0_ADDR_I]], align 1660// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[__P0_ADDR_I]], align 1661// CHECK-NEXT: [[VRNDM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>62// CHECK-NEXT: [[VRNDM1_I:%.*]] = call <2 x double> @llvm.floor.v2f64(<2 x double> [[VRNDM_I]])63// CHECK-NEXT: store <2 x double> [[VRNDM1_I]], ptr [[REF_TMP_I]], align 1664// CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[REF_TMP_I]], align 1665// CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[__RET_I]], align 1666// CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[__RET_I]], align 1667// CHECK-NEXT: ret <2 x double> [[TMP3]]68//69float64x2_t rnd13(float64x2_t a) { return vrndmq_f64(a); }70 71// CHECK-LABEL: define <2 x double> @rnd18(72// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {73// CHECK-NEXT: [[ENTRY:.*:]]74// CHECK-NEXT: [[__P0_ADDR_I:%.*]] = alloca <2 x double>, align 1675// CHECK-NEXT: [[__RET_I:%.*]] = alloca <2 x double>, align 1676// CHECK-NEXT: [[REF_TMP_I:%.*]] = alloca <16 x i8>, align 1677// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x double>, align 1678// CHECK-NEXT: store <2 x double> [[A]], ptr [[A_ADDR]], align 1679// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 1680// CHECK-NEXT: store <2 x double> [[TMP0]], ptr [[__P0_ADDR_I]], align 1681// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[__P0_ADDR_I]], align 1682// CHECK-NEXT: [[VRNDP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>83// CHECK-NEXT: [[VRNDP1_I:%.*]] = call <2 x double> @llvm.ceil.v2f64(<2 x double> [[VRNDP_I]])84// CHECK-NEXT: store <2 x double> [[VRNDP1_I]], ptr [[REF_TMP_I]], align 1685// CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[REF_TMP_I]], align 1686// CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[__RET_I]], align 1687// CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[__RET_I]], align 1688// CHECK-NEXT: ret <2 x double> [[TMP3]]89//90float64x2_t rnd18(float64x2_t a) { return vrndpq_f64(a); }91 92// CHECK-LABEL: define <2 x double> @rnd22(93// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {94// CHECK-NEXT: [[ENTRY:.*:]]95// CHECK-NEXT: [[__P0_ADDR_I:%.*]] = alloca <2 x double>, align 1696// CHECK-NEXT: [[__RET_I:%.*]] = alloca <2 x double>, align 1697// CHECK-NEXT: [[REF_TMP_I:%.*]] = alloca <16 x i8>, align 1698// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x double>, align 1699// CHECK-NEXT: store <2 x double> [[A]], ptr [[A_ADDR]], align 16100// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 16101// CHECK-NEXT: store <2 x double> [[TMP0]], ptr [[__P0_ADDR_I]], align 16102// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[__P0_ADDR_I]], align 16103// CHECK-NEXT: [[VRNDA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>104// CHECK-NEXT: [[VRNDA1_I:%.*]] = call <2 x double> @llvm.round.v2f64(<2 x double> [[VRNDA_I]])105// CHECK-NEXT: store <2 x double> [[VRNDA1_I]], ptr [[REF_TMP_I]], align 16106// CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[REF_TMP_I]], align 16107// CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[__RET_I]], align 16108// CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[__RET_I]], align 16109// CHECK-NEXT: ret <2 x double> [[TMP3]]110//111float64x2_t rnd22(float64x2_t a) { return vrndaq_f64(a); }112 113// CHECK-LABEL: define <2 x double> @rnd25(114// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0]] {115// CHECK-NEXT: [[ENTRY:.*:]]116// CHECK-NEXT: [[__P0_ADDR_I:%.*]] = alloca <2 x double>, align 16117// CHECK-NEXT: [[__RET_I:%.*]] = alloca <2 x double>, align 16118// CHECK-NEXT: [[REF_TMP_I:%.*]] = alloca <16 x i8>, align 16119// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x double>, align 16120// CHECK-NEXT: store <2 x double> [[A]], ptr [[A_ADDR]], align 16121// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 16122// CHECK-NEXT: store <2 x double> [[TMP0]], ptr [[__P0_ADDR_I]], align 16123// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[__P0_ADDR_I]], align 16124// CHECK-NEXT: [[VRNDX_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>125// CHECK-NEXT: [[VRNDX1_I:%.*]] = call <2 x double> @llvm.rint.v2f64(<2 x double> [[VRNDX_I]])126// CHECK-NEXT: store <2 x double> [[VRNDX1_I]], ptr [[REF_TMP_I]], align 16127// CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[REF_TMP_I]], align 16128// CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[__RET_I]], align 16129// CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[__RET_I]], align 16130// CHECK-NEXT: ret <2 x double> [[TMP3]]131//132float64x2_t rnd25(float64x2_t a) { return vrndxq_f64(a); }133 134