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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm %s | opt -S -passes=mem2reg | FileCheck %s3// Test ARM64 SIMD vcreate intrinsics4 5// REQUIRES: aarch64-registered-target || arm-registered-target6 7#include <arm_neon.h>8 9// CHECK-LABEL: define <2 x float> @test_vcreate_f32(10// CHECK-SAME: i64 noundef [[A1:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-NEXT: [[ENTRY:.*:]]12// CHECK-NEXT: [[A1_ADDR:%.*]] = alloca i64, align 813// CHECK-NEXT: [[__RET:%.*]] = alloca <2 x float>, align 814// CHECK-NEXT: [[__PROMOTE:%.*]] = alloca i64, align 815// CHECK-NEXT: [[TMP:%.*]] = alloca <2 x float>, align 816// CHECK-NEXT: store i64 [[A1]], ptr [[A1_ADDR]], align 817// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A1_ADDR]], align 818// CHECK-NEXT: store i64 [[TMP0]], ptr [[__PROMOTE]], align 819// CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[__PROMOTE]], align 820// CHECK-NEXT: store <2 x float> [[TMP1]], ptr [[__RET]], align 821// CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[__RET]], align 822// CHECK-NEXT: store <2 x float> [[TMP2]], ptr [[TMP]], align 823// CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr [[TMP]], align 824// CHECK-NEXT: ret <2 x float> [[TMP3]]25//26float32x2_t test_vcreate_f32(uint64_t a1) {27 return vcreate_f32(a1);28}29