99 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm %s | opt -S -passes=mem2reg,sroa | FileCheck %s3 4// REQUIRES: aarch64-registered-target || arm-registered-target5 6#include <arm_neon.h>7 8// vdupq_n_f64 -> dup.2d v0, v0[0]9// CHECK-LABEL: define <2 x double> @test_vdupq_n_f64(10// CHECK-SAME: double noundef [[W:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-NEXT: [[ENTRY:.*:]]12// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x double> poison, double [[W]], i32 013// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double [[W]], i32 114// CHECK-NEXT: ret <2 x double> [[VECINIT1_I]]15//16float64x2_t test_vdupq_n_f64(float64_t w) {17 return vdupq_n_f64(w);18}19 20// might as well test this while we're here21// vdupq_n_f32 -> dup.4s v0, v0[0]22// CHECK-LABEL: define <4 x float> @test_vdupq_n_f32(23// CHECK-SAME: float noundef [[W:%.*]]) #[[ATTR0]] {24// CHECK-NEXT: [[ENTRY:.*:]]25// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[W]], i32 026// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[W]], i32 127// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[W]], i32 228// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[W]], i32 329// CHECK-NEXT: ret <4 x float> [[VECINIT3_I]]30//31float32x4_t test_vdupq_n_f32(float32_t w) {32 return vdupq_n_f32(w);33}34 35// vdupq_lane_f64 -> dup.2d v0, v0[0]36// CHECK-LABEL: define <2 x double> @test_vdupq_lane_f64(37// CHECK-SAME: <1 x double> noundef [[V:%.*]]) #[[ATTR0]] {38// CHECK-NEXT: [[ENTRY:.*:]]39// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[V]] to i6440// CHECK-NEXT: [[__S0_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 041// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__S0_SROA_0_0_VEC_INSERT]] to <8 x i8>42// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>43// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x double> [[TMP2]], <1 x double> [[TMP2]], <2 x i32> zeroinitializer44// CHECK-NEXT: ret <2 x double> [[LANE]]45//46float64x2_t test_vdupq_lane_f64(float64x1_t V) {47 return vdupq_lane_f64(V, 0);48}49 50// vmovq_n_f64 -> dup Vd.2d,X051// CHECK-LABEL: define <2 x double> @test_vmovq_n_f64(52// CHECK-SAME: double noundef [[W:%.*]]) #[[ATTR0]] {53// CHECK-NEXT: [[ENTRY:.*:]]54// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x double> poison, double [[W]], i32 055// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double [[W]], i32 156// CHECK-NEXT: ret <2 x double> [[VECINIT1_I]]57//58float64x2_t test_vmovq_n_f64(float64_t w) {59 return vmovq_n_f64(w);60}61 62// CHECK-LABEL: define <4 x half> @test_vmov_n_f16(63// CHECK-SAME: ptr noundef [[A1:%.*]]) #[[ATTR0]] {64// CHECK-NEXT: [[ENTRY:.*:]]65// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A1]], align 266// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x half> poison, half [[TMP0]], i32 067// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[TMP0]], i32 168// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[TMP0]], i32 269// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[TMP0]], i32 370// CHECK-NEXT: ret <4 x half> [[VECINIT3]]71//72float16x4_t test_vmov_n_f16(float16_t *a1) {73 return vmov_n_f16(*a1);74}75 76/*77float64x1_t test_vmov_n_f64(float64_t a1) {78 return vmov_n_f64(a1);79}80*/81 82// CHECK-LABEL: define <8 x half> @test_vmovq_n_f16(83// CHECK-SAME: ptr noundef [[A1:%.*]]) #[[ATTR0]] {84// CHECK-NEXT: [[ENTRY:.*:]]85// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A1]], align 286// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <8 x half> poison, half [[TMP0]], i32 087// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[TMP0]], i32 188// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[TMP0]], i32 289// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[TMP0]], i32 390// CHECK-NEXT: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[TMP0]], i32 491// CHECK-NEXT: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[TMP0]], i32 592// CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[TMP0]], i32 693// CHECK-NEXT: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[TMP0]], i32 794// CHECK-NEXT: ret <8 x half> [[VECINIT7]]95//96float16x8_t test_vmovq_n_f16(float16_t *a1) {97 return vmovq_n_f16(*a1);98}99