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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s -check-prefixes=ARM,AArch323// RUN: %clang_cc1 -ffreestanding -triple armv8a-none-eabi -target-feature +crc -target-feature +dsp -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s -check-prefixes=ARM,AArch324// RUN: %clang_cc1 -ffreestanding -Wno-error=implicit-function-declaration -triple aarch64-none-elf -target-feature +neon -target-feature +crc -target-feature +crypto -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s -check-prefixes=ARM,AArch645// RUN: %clang_cc1 -ffreestanding -triple aarch64-none-elf -target-feature +v8.3a -target-feature +crc -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s -check-prefixes=ARM,AArch64,AArch64836// RUN: %clang_cc1 -ffreestanding -triple aarch64-none-elf -target-feature +v8.5a -target-feature +crc -target-feature +rand -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s -check-prefixes=ARM,AArch64,AArch6483,AArch64857// RUN: %clang_cc1 -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -target-feature +crc -target-feature +rand -target-feature +d128 -O0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s -check-prefixes=ARM,AArch64,AArch6483,AArch6485,AArch6494D1288 9 10#include <arm_acle.h>11 12// REQUIRES: arm-registered-target,aarch64-registered-target13 14/* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */15/* 8.3 Memory Barriers */16 17// AArch32-LABEL: @test_dmb(18// AArch32-NEXT: entry:19// AArch32-NEXT: call void @llvm.arm.dmb(i32 1)20// AArch32-NEXT: ret void21//22// AArch64-LABEL: @test_dmb(23// AArch64-NEXT: entry:24// AArch64-NEXT: call void @llvm.aarch64.dmb(i32 1)25// AArch64-NEXT: ret void26//27void test_dmb(void) {28 __dmb(1);29}30 31// AArch32-LABEL: @test_dsb(32// AArch32-NEXT: entry:33// AArch32-NEXT: call void @llvm.arm.dsb(i32 2)34// AArch32-NEXT: ret void35//36// AArch64-LABEL: @test_dsb(37// AArch64-NEXT: entry:38// AArch64-NEXT: call void @llvm.aarch64.dsb(i32 2)39// AArch64-NEXT: ret void40//41void test_dsb(void) {42 __dsb(2);43}44 45// AArch32-LABEL: @test_isb(46// AArch32-NEXT: entry:47// AArch32-NEXT: call void @llvm.arm.isb(i32 3)48// AArch32-NEXT: ret void49//50// AArch64-LABEL: @test_isb(51// AArch64-NEXT: entry:52// AArch64-NEXT: call void @llvm.aarch64.isb(i32 3)53// AArch64-NEXT: ret void54//55void test_isb(void) {56 __isb(3);57}58 59/* 8.4 Hints */60// AArch32-LABEL: @test_yield(61// AArch32-NEXT: entry:62// AArch32-NEXT: call void @llvm.arm.hint(i32 1)63// AArch32-NEXT: ret void64//65// AArch64-LABEL: @test_yield(66// AArch64-NEXT: entry:67// AArch64-NEXT: call void @llvm.aarch64.hint(i32 1)68// AArch64-NEXT: ret void69//70void test_yield(void) {71 __yield();72}73 74// AArch32-LABEL: @test_wfe(75// AArch32-NEXT: entry:76// AArch32-NEXT: call void @llvm.arm.hint(i32 2)77// AArch32-NEXT: ret void78//79// AArch64-LABEL: @test_wfe(80// AArch64-NEXT: entry:81// AArch64-NEXT: call void @llvm.aarch64.hint(i32 2)82// AArch64-NEXT: ret void83//84void test_wfe(void) {85 __wfe();86}87 88// AArch32-LABEL: @test_wfi(89// AArch32-NEXT: entry:90// AArch32-NEXT: call void @llvm.arm.hint(i32 3)91// AArch32-NEXT: ret void92//93// AArch64-LABEL: @test_wfi(94// AArch64-NEXT: entry:95// AArch64-NEXT: call void @llvm.aarch64.hint(i32 3)96// AArch64-NEXT: ret void97//98void test_wfi(void) {99 __wfi();100}101 102// AArch32-LABEL: @test_sev(103// AArch32-NEXT: entry:104// AArch32-NEXT: call void @llvm.arm.hint(i32 4)105// AArch32-NEXT: ret void106//107// AArch64-LABEL: @test_sev(108// AArch64-NEXT: entry:109// AArch64-NEXT: call void @llvm.aarch64.hint(i32 4)110// AArch64-NEXT: ret void111//112void test_sev(void) {113 __sev();114}115 116// AArch32-LABEL: @test_sevl(117// AArch32-NEXT: entry:118// AArch32-NEXT: call void @llvm.arm.hint(i32 5)119// AArch32-NEXT: ret void120//121// AArch64-LABEL: @test_sevl(122// AArch64-NEXT: entry:123// AArch64-NEXT: call void @llvm.aarch64.hint(i32 5)124// AArch64-NEXT: ret void125//126void test_sevl(void) {127 __sevl();128}129 130#ifdef __ARM_32BIT_STATE131// AArch32-LABEL: @test_dbg(132// AArch32-NEXT: entry:133// AArch32-NEXT: call void @llvm.arm.dbg(i32 0)134// AArch32-NEXT: ret void135//136void test_dbg(void) {137 __dbg(0);138}139#endif140 141/* 8.5 Swap */142// ARM-LABEL: @test_swp(143// ARM-NEXT: entry:144// ARM-NEXT: [[TMP0:%.*]] = atomicrmw volatile xchg ptr [[P:%.*]], i32 [[X:%.*]] monotonic, align 4145// ARM-NEXT: ret void146//147void test_swp(uint32_t x, volatile void *p) {148 __swp(x, p);149}150 151/* 8.6 Memory prefetch intrinsics */152/* 8.6.1 Data prefetch */153// AArch32-LABEL: @test_pld(154// AArch32-NEXT: entry:155// AArch32-NEXT: call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 1)156// AArch32-NEXT: ret void157//158// AArch64-LABEL: @test_pld(159// AArch64-NEXT: entry:160// AArch64-NEXT: call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 1)161// AArch64-NEXT: ret void162//163void test_pld() {164 __pld(0);165}166 167// AArch32-LABEL: @test_pldx(168// AArch32-NEXT: entry:169// AArch32-NEXT: call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1)170// AArch32-NEXT: ret void171//172// AArch64-LABEL: @test_pldx(173// AArch64-NEXT: entry:174// AArch64-NEXT: call void @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1)175// AArch64-NEXT: ret void176//177void test_pldx() {178 __pldx(1, 2, 0, 0);179}180 181/* 8.6.2 Instruction prefetch */182// AArch32-LABEL: @test_pli(183// AArch32-NEXT: entry:184// AArch32-NEXT: call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)185// AArch32-NEXT: ret void186//187// AArch64-LABEL: @test_pli(188// AArch64-NEXT: entry:189// AArch64-NEXT: call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0)190// AArch64-NEXT: ret void191//192void test_pli() {193 __pli(0);194}195 196// AArch32-LABEL: @test_plix(197// AArch32-NEXT: entry:198// AArch32-NEXT: call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)199// AArch32-NEXT: ret void200//201// AArch64-LABEL: @test_plix(202// AArch64-NEXT: entry:203// AArch64-NEXT: call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 2, i32 0, i32 0)204// AArch64-NEXT: ret void205//206void test_plix() {207 __plix(2, 0, 0);208}209 210/* 8.7 NOP */211// AArch32-LABEL: @test_nop(212// AArch32-NEXT: entry:213// AArch32-NEXT: call void @llvm.arm.hint(i32 0)214// AArch32-NEXT: ret void215//216// AArch64-LABEL: @test_nop(217// AArch64-NEXT: entry:218// AArch64-NEXT: call void @llvm.aarch64.hint(i32 0)219// AArch64-NEXT: ret void220//221void test_nop(void) {222 __nop();223}224 225/* 9 DATA-PROCESSING INTRINSICS */226 227/* 9.2 Miscellaneous data-processing intrinsics */228// ARM-LABEL: @test_ror(229// ARM-NEXT: entry:230// ARM-NEXT: [[REM_I:%.*]] = urem i32 [[Y:%.*]], 32231// ARM-NEXT: [[CMP_I:%.*]] = icmp eq i32 [[REM_I]], 0232// ARM-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[IF_END_I:%.*]]233// ARM: if.then.i:234// ARM-NEXT: br label [[__ROR_EXIT:%.*]]235// ARM: if.end.i:236// ARM-NEXT: [[SHR_I:%.*]] = lshr i32 [[X:%.*]], [[REM_I]]237// ARM-NEXT: [[SUB_I:%.*]] = sub i32 32, [[REM_I]]238// ARM-NEXT: [[SHL_I:%.*]] = shl i32 [[X]], [[SUB_I]]239// ARM-NEXT: [[OR_I:%.*]] = or i32 [[SHR_I]], [[SHL_I]]240// ARM-NEXT: br label [[__ROR_EXIT]]241// ARM: __ror.exit:242// ARM-NEXT: [[RETVAL_I_0:%.*]] = phi i32 [ [[X]], [[IF_THEN_I]] ], [ [[OR_I]], [[IF_END_I]] ]243// ARM-NEXT: ret i32 [[RETVAL_I_0]]244//245uint32_t test_ror(uint32_t x, uint32_t y) {246 return __ror(x, y);247}248 249// AArch32-LABEL: @test_rorl(250// AArch32-NEXT: entry:251// AArch32-NEXT: [[REM_I_I:%.*]] = urem i32 [[Y:%.*]], 32252// AArch32-NEXT: [[CMP_I_I:%.*]] = icmp eq i32 [[REM_I_I]], 0253// AArch32-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[IF_END_I_I:%.*]]254// AArch32: if.then.i.i:255// AArch32-NEXT: br label [[__RORL_EXIT:%.*]]256// AArch32: if.end.i.i:257// AArch32-NEXT: [[SHR_I_I:%.*]] = lshr i32 [[X:%.*]], [[REM_I_I]]258// AArch32-NEXT: [[SUB_I_I:%.*]] = sub i32 32, [[REM_I_I]]259// AArch32-NEXT: [[SHL_I_I:%.*]] = shl i32 [[X]], [[SUB_I_I]]260// AArch32-NEXT: [[OR_I_I:%.*]] = or i32 [[SHR_I_I]], [[SHL_I_I]]261// AArch32-NEXT: br label [[__RORL_EXIT]]262// AArch32: __rorl.exit:263// AArch32-NEXT: [[RETVAL_I_I_0:%.*]] = phi i32 [ [[X]], [[IF_THEN_I_I]] ], [ [[OR_I_I]], [[IF_END_I_I]] ]264// AArch32-NEXT: ret i32 [[RETVAL_I_I_0]]265//266// AArch64-LABEL: @test_rorl(267// AArch64-NEXT: entry:268// AArch64-NEXT: [[REM_I:%.*]] = urem i32 [[Y:%.*]], 64269// AArch64-NEXT: [[CMP_I:%.*]] = icmp eq i32 [[REM_I]], 0270// AArch64-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[IF_END_I:%.*]]271// AArch64: if.then.i:272// AArch64-NEXT: br label [[__RORLL_EXIT:%.*]]273// AArch64: if.end.i:274// AArch64-NEXT: [[SH_PROM_I:%.*]] = zext i32 [[REM_I]] to i64275// AArch64-NEXT: [[SHR_I:%.*]] = lshr i64 [[X:%.*]], [[SH_PROM_I]]276// AArch64-NEXT: [[SUB_I:%.*]] = sub i32 64, [[REM_I]]277// AArch64-NEXT: [[SH_PROM1_I:%.*]] = zext i32 [[SUB_I]] to i64278// AArch64-NEXT: [[SHL_I:%.*]] = shl i64 [[X]], [[SH_PROM1_I]]279// AArch64-NEXT: [[OR_I:%.*]] = or i64 [[SHR_I]], [[SHL_I]]280// AArch64-NEXT: br label [[__RORLL_EXIT]]281// AArch64: __rorll.exit:282// AArch64-NEXT: [[RETVAL_I_0:%.*]] = phi i64 [ [[X]], [[IF_THEN_I]] ], [ [[OR_I]], [[IF_END_I]] ]283// AArch64-NEXT: ret i64 [[RETVAL_I_0]]284//285unsigned long test_rorl(unsigned long x, uint32_t y) {286 return __rorl(x, y);287}288 289// ARM-LABEL: @test_rorll(290// ARM-NEXT: entry:291// ARM-NEXT: [[REM_I:%.*]] = urem i32 [[Y:%.*]], 64292// ARM-NEXT: [[CMP_I:%.*]] = icmp eq i32 [[REM_I]], 0293// ARM-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[IF_END_I:%.*]]294// ARM: if.then.i:295// ARM-NEXT: br label [[__RORLL_EXIT:%.*]]296// ARM: if.end.i:297// ARM-NEXT: [[SH_PROM_I:%.*]] = zext i32 [[REM_I]] to i64298// ARM-NEXT: [[SHR_I:%.*]] = lshr i64 [[X:%.*]], [[SH_PROM_I]]299// ARM-NEXT: [[SUB_I:%.*]] = sub i32 64, [[REM_I]]300// ARM-NEXT: [[SH_PROM1_I:%.*]] = zext i32 [[SUB_I]] to i64301// ARM-NEXT: [[SHL_I:%.*]] = shl i64 [[X]], [[SH_PROM1_I]]302// ARM-NEXT: [[OR_I:%.*]] = or i64 [[SHR_I]], [[SHL_I]]303// ARM-NEXT: br label [[__RORLL_EXIT]]304// ARM: __rorll.exit:305// ARM-NEXT: [[RETVAL_I_0:%.*]] = phi i64 [ [[X]], [[IF_THEN_I]] ], [ [[OR_I]], [[IF_END_I]] ]306// ARM-NEXT: ret i64 [[RETVAL_I_0]]307//308uint64_t test_rorll(uint64_t x, uint32_t y) {309 return __rorll(x, y);310}311 312// ARM-LABEL: @test_clz(313// ARM-NEXT: entry:314// ARM-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[T:%.*]], i1 false)315// ARM-NEXT: ret i32 [[TMP0]]316//317unsigned test_clz(uint32_t t) {318 return __clz(t);319}320 321// AArch32-LABEL: @test_clzl(322// AArch32-NEXT: entry:323// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[T:%.*]], i1 false)324// AArch32-NEXT: ret i32 [[TMP0]]325//326// AArch64-LABEL: @test_clzl(327// AArch64-NEXT: entry:328// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1 false)329// AArch64-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32330// AArch64-NEXT: ret i32 [[CAST_I]]331//332unsigned test_clzl(unsigned long t) {333 return __clzl(t);334}335 336// ARM-LABEL: @test_clzll(337// ARM-NEXT: entry:338// ARM-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1 false)339// ARM-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32340// ARM-NEXT: ret i32 [[CAST_I]]341//342unsigned test_clzll(uint64_t t) {343 return __clzll(t);344}345 346// AArch32-LABEL: @test_cls(347// AArch32-NEXT: entry:348// AArch32-NEXT: [[CLS_I:%.*]] = call i32 @llvm.arm.cls(i32 [[T:%.*]])349// AArch32-NEXT: ret i32 [[CLS_I]]350//351// AArch64-LABEL: @test_cls(352// AArch64-NEXT: entry:353// AArch64-NEXT: [[CLS_I:%.*]] = call i32 @llvm.aarch64.cls(i32 [[T:%.*]])354// AArch64-NEXT: ret i32 [[CLS_I]]355//356unsigned test_cls(uint32_t t) {357 return __cls(t);358}359 360// AArch32-LABEL: @test_clsl(361// AArch32-NEXT: entry:362// AArch32-NEXT: [[CLS_I:%.*]] = call i32 @llvm.arm.cls(i32 [[T:%.*]])363// AArch32-NEXT: ret i32 [[CLS_I]]364//365// AArch64-LABEL: @test_clsl(366// AArch64-NEXT: entry:367// AArch64-NEXT: [[CLS_I:%.*]] = call i32 @llvm.aarch64.cls64(i64 [[T:%.*]])368// AArch64-NEXT: ret i32 [[CLS_I]]369//370unsigned test_clsl(unsigned long t) {371 return __clsl(t);372}373 374// AArch32-LABEL: @test_clsll(375// AArch32-NEXT: entry:376// AArch32-NEXT: [[CLS_I:%.*]] = call i32 @llvm.arm.cls64(i64 [[T:%.*]])377// AArch32-NEXT: ret i32 [[CLS_I]]378//379// AArch64-LABEL: @test_clsll(380// AArch64-NEXT: entry:381// AArch64-NEXT: [[CLS_I:%.*]] = call i32 @llvm.aarch64.cls64(i64 [[T:%.*]])382// AArch64-NEXT: ret i32 [[CLS_I]]383//384unsigned test_clsll(uint64_t t) {385 return __clsll(t);386}387 388// ARM-LABEL: @test_rev(389// ARM-NEXT: entry:390// ARM-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[T:%.*]])391// ARM-NEXT: ret i32 [[TMP0]]392//393uint32_t test_rev(uint32_t t) {394 return __rev(t);395}396 397// AArch32-LABEL: @test_revl(398// AArch32-NEXT: entry:399// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[T:%.*]])400// AArch32-NEXT: ret i32 [[TMP0]]401//402// AArch64-LABEL: @test_revl(403// AArch64-NEXT: entry:404// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.bswap.i64(i64 [[T:%.*]])405// AArch64-NEXT: ret i64 [[TMP0]]406//407long test_revl(long t) {408 return __revl(t);409}410 411// ARM-LABEL: @test_revll(412// ARM-NEXT: entry:413// ARM-NEXT: [[TMP0:%.*]] = call i64 @llvm.bswap.i64(i64 [[T:%.*]])414// ARM-NEXT: ret i64 [[TMP0]]415//416uint64_t test_revll(uint64_t t) {417 return __revll(t);418}419 420// ARM-LABEL: @test_rev16(421// ARM-NEXT: entry:422// ARM-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[T:%.*]])423// ARM-NEXT: [[REM_I_I:%.*]] = urem i32 16, 32424// ARM-NEXT: [[CMP_I_I:%.*]] = icmp eq i32 [[REM_I_I]], 0425// ARM-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[IF_END_I_I:%.*]]426// ARM: if.then.i.i:427// ARM-NEXT: br label [[__REV16_EXIT:%.*]]428// ARM: if.end.i.i:429// ARM-NEXT: [[SHR_I_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I]]430// ARM-NEXT: [[SUB_I_I:%.*]] = sub i32 32, [[REM_I_I]]431// ARM-NEXT: [[SHL_I_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I]]432// ARM-NEXT: [[OR_I_I:%.*]] = or i32 [[SHR_I_I]], [[SHL_I_I]]433// ARM-NEXT: br label [[__REV16_EXIT]]434// ARM: __rev16.exit:435// ARM-NEXT: [[RETVAL_I_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I]] ], [ [[OR_I_I]], [[IF_END_I_I]] ]436// ARM-NEXT: ret i32 [[RETVAL_I_I_0]]437//438uint32_t test_rev16(uint32_t t) {439 return __rev16(t);440}441 442// AArch32-LABEL: @test_rev16l(443// AArch32-NEXT: entry:444// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[T:%.*]])445// AArch32-NEXT: [[REM_I_I_I:%.*]] = urem i32 16, 32446// AArch32-NEXT: [[CMP_I_I_I:%.*]] = icmp eq i32 [[REM_I_I_I]], 0447// AArch32-NEXT: br i1 [[CMP_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[IF_END_I_I_I:%.*]]448// AArch32: if.then.i.i.i:449// AArch32-NEXT: br label [[__REV16L_EXIT:%.*]]450// AArch32: if.end.i.i.i:451// AArch32-NEXT: [[SHR_I_I_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I_I]]452// AArch32-NEXT: [[SUB_I_I_I:%.*]] = sub i32 32, [[REM_I_I_I]]453// AArch32-NEXT: [[SHL_I_I_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I_I]]454// AArch32-NEXT: [[OR_I_I_I:%.*]] = or i32 [[SHR_I_I_I]], [[SHL_I_I_I]]455// AArch32-NEXT: br label [[__REV16L_EXIT]]456// AArch32: __rev16l.exit:457// AArch32-NEXT: [[RETVAL_I_I_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I_I]] ], [ [[OR_I_I_I]], [[IF_END_I_I_I]] ]458// AArch32-NEXT: ret i32 [[RETVAL_I_I_I_0]]459//460// AArch64-LABEL: @test_rev16l(461// AArch64-NEXT: entry:462// AArch64-NEXT: [[SHR_I:%.*]] = lshr i64 [[T:%.*]], 32463// AArch64-NEXT: [[CONV_I:%.*]] = trunc i64 [[SHR_I]] to i32464// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I]])465// AArch64-NEXT: [[REM_I_I10_I:%.*]] = urem i32 16, 32466// AArch64-NEXT: [[CMP_I_I11_I:%.*]] = icmp eq i32 [[REM_I_I10_I]], 0467// AArch64-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I17_I:%.*]], label [[IF_END_I_I12_I:%.*]]468// AArch64: if.then.i.i17.i:469// AArch64-NEXT: br label [[__REV16_EXIT18_I:%.*]]470// AArch64: if.end.i.i12.i:471// AArch64-NEXT: [[SHR_I_I13_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I10_I]]472// AArch64-NEXT: [[SUB_I_I14_I:%.*]] = sub i32 32, [[REM_I_I10_I]]473// AArch64-NEXT: [[SHL_I_I15_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I14_I]]474// AArch64-NEXT: [[OR_I_I16_I:%.*]] = or i32 [[SHR_I_I13_I]], [[SHL_I_I15_I]]475// AArch64-NEXT: br label [[__REV16_EXIT18_I]]476// AArch64: __rev16.exit18.i:477// AArch64-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I17_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I12_I]] ]478// AArch64-NEXT: [[CONV1_I:%.*]] = zext i32 [[RETVAL_I_I6_I_0]] to i64479// AArch64-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32480// AArch64-NEXT: [[CONV2_I:%.*]] = trunc i64 [[T]] to i32481// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV2_I]])482// AArch64-NEXT: [[REM_I_I_I:%.*]] = urem i32 16, 32483// AArch64-NEXT: [[CMP_I_I_I:%.*]] = icmp eq i32 [[REM_I_I_I]], 0484// AArch64-NEXT: br i1 [[CMP_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[IF_END_I_I_I:%.*]]485// AArch64: if.then.i.i.i:486// AArch64-NEXT: br label [[__REV16LL_EXIT:%.*]]487// AArch64: if.end.i.i.i:488// AArch64-NEXT: [[SHR_I_I_I:%.*]] = lshr i32 [[TMP1]], [[REM_I_I_I]]489// AArch64-NEXT: [[SUB_I_I_I:%.*]] = sub i32 32, [[REM_I_I_I]]490// AArch64-NEXT: [[SHL_I_I_I:%.*]] = shl i32 [[TMP1]], [[SUB_I_I_I]]491// AArch64-NEXT: [[OR_I_I_I:%.*]] = or i32 [[SHR_I_I_I]], [[SHL_I_I_I]]492// AArch64-NEXT: br label [[__REV16LL_EXIT]]493// AArch64: __rev16ll.exit:494// AArch64-NEXT: [[RETVAL_I_I_I_0:%.*]] = phi i32 [ [[TMP1]], [[IF_THEN_I_I_I]] ], [ [[OR_I_I_I]], [[IF_END_I_I_I]] ]495// AArch64-NEXT: [[CONV4_I:%.*]] = zext i32 [[RETVAL_I_I_I_0]] to i64496// AArch64-NEXT: [[OR_I:%.*]] = or i64 [[SHL_I]], [[CONV4_I]]497// AArch64-NEXT: ret i64 [[OR_I]]498//499long test_rev16l(long t) {500 return __rev16l(t);501}502 503// ARM-LABEL: @test_rev16ll(504// ARM-NEXT: entry:505// ARM-NEXT: [[SHR_I:%.*]] = lshr i64 [[T:%.*]], 32506// ARM-NEXT: [[CONV_I:%.*]] = trunc i64 [[SHR_I]] to i32507// ARM-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I]])508// ARM-NEXT: [[REM_I_I10_I:%.*]] = urem i32 16, 32509// ARM-NEXT: [[CMP_I_I11_I:%.*]] = icmp eq i32 [[REM_I_I10_I]], 0510// ARM-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I17_I:%.*]], label [[IF_END_I_I12_I:%.*]]511// ARM: if.then.i.i17.i:512// ARM-NEXT: br label [[__REV16_EXIT18_I:%.*]]513// ARM: if.end.i.i12.i:514// ARM-NEXT: [[SHR_I_I13_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I10_I]]515// ARM-NEXT: [[SUB_I_I14_I:%.*]] = sub i32 32, [[REM_I_I10_I]]516// ARM-NEXT: [[SHL_I_I15_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I14_I]]517// ARM-NEXT: [[OR_I_I16_I:%.*]] = or i32 [[SHR_I_I13_I]], [[SHL_I_I15_I]]518// ARM-NEXT: br label [[__REV16_EXIT18_I]]519// ARM: __rev16.exit18.i:520// ARM-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I17_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I12_I]] ]521// ARM-NEXT: [[CONV1_I:%.*]] = zext i32 [[RETVAL_I_I6_I_0]] to i64522// ARM-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32523// ARM-NEXT: [[CONV2_I:%.*]] = trunc i64 [[T]] to i32524// ARM-NEXT: [[TMP1:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV2_I]])525// ARM-NEXT: [[REM_I_I_I:%.*]] = urem i32 16, 32526// ARM-NEXT: [[CMP_I_I_I:%.*]] = icmp eq i32 [[REM_I_I_I]], 0527// ARM-NEXT: br i1 [[CMP_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[IF_END_I_I_I:%.*]]528// ARM: if.then.i.i.i:529// ARM-NEXT: br label [[__REV16LL_EXIT:%.*]]530// ARM: if.end.i.i.i:531// ARM-NEXT: [[SHR_I_I_I:%.*]] = lshr i32 [[TMP1]], [[REM_I_I_I]]532// ARM-NEXT: [[SUB_I_I_I:%.*]] = sub i32 32, [[REM_I_I_I]]533// ARM-NEXT: [[SHL_I_I_I:%.*]] = shl i32 [[TMP1]], [[SUB_I_I_I]]534// ARM-NEXT: [[OR_I_I_I:%.*]] = or i32 [[SHR_I_I_I]], [[SHL_I_I_I]]535// ARM-NEXT: br label [[__REV16LL_EXIT]]536// ARM: __rev16ll.exit:537// ARM-NEXT: [[RETVAL_I_I_I_0:%.*]] = phi i32 [ [[TMP1]], [[IF_THEN_I_I_I]] ], [ [[OR_I_I_I]], [[IF_END_I_I_I]] ]538// ARM-NEXT: [[CONV4_I:%.*]] = zext i32 [[RETVAL_I_I_I_0]] to i64539// ARM-NEXT: [[OR_I:%.*]] = or i64 [[SHL_I]], [[CONV4_I]]540// ARM-NEXT: ret i64 [[OR_I]]541//542uint64_t test_rev16ll(uint64_t t) {543 return __rev16ll(t);544}545 546// ARM-LABEL: @test_revsh(547// ARM-NEXT: entry:548// ARM-NEXT: [[TMP0:%.*]] = call i16 @llvm.bswap.i16(i16 [[T:%.*]])549// ARM-NEXT: ret i16 [[TMP0]]550//551int16_t test_revsh(int16_t t) {552 return __revsh(t);553}554 555// ARM-LABEL: @test_rbit(556// ARM-NEXT: entry:557// ARM-NEXT: [[RBIT_I:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[T:%.*]])558// ARM-NEXT: ret i32 [[RBIT_I]]559//560uint32_t test_rbit(uint32_t t) {561 return __rbit(t);562}563 564// AArch32-LABEL: @test_rbitl(565// AArch32-NEXT: entry:566// AArch32-NEXT: [[RBIT_I_I:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[T:%.*]])567// AArch32-NEXT: ret i32 [[RBIT_I_I]]568//569// AArch64-LABEL: @test_rbitl(570// AArch64-NEXT: entry:571// AArch64-NEXT: [[RBIT_I:%.*]] = call i64 @llvm.bitreverse.i64(i64 [[T:%.*]])572// AArch64-NEXT: ret i64 [[RBIT_I]]573//574long test_rbitl(long t) {575 return __rbitl(t);576}577 578// AArch32-LABEL: @test_rbitll(579// AArch32-NEXT: entry:580// AArch32-NEXT: [[CONV_I:%.*]] = trunc i64 [[T:%.*]] to i32581// AArch32-NEXT: [[RBIT_I:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[CONV_I]])582// AArch32-NEXT: [[CONV1_I:%.*]] = zext i32 [[RBIT_I]] to i64583// AArch32-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32584// AArch32-NEXT: [[SHR_I:%.*]] = lshr i64 [[T]], 32585// AArch32-NEXT: [[CONV2_I:%.*]] = trunc i64 [[SHR_I]] to i32586// AArch32-NEXT: [[RBIT3_I:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[CONV2_I]])587// AArch32-NEXT: [[CONV4_I:%.*]] = zext i32 [[RBIT3_I]] to i64588// AArch32-NEXT: [[OR_I:%.*]] = or i64 [[SHL_I]], [[CONV4_I]]589// AArch32-NEXT: ret i64 [[OR_I]]590//591// AArch64-LABEL: @test_rbitll(592// AArch64-NEXT: entry:593// AArch64-NEXT: [[RBIT_I:%.*]] = call i64 @llvm.bitreverse.i64(i64 [[T:%.*]])594// AArch64-NEXT: ret i64 [[RBIT_I]]595//596uint64_t test_rbitll(uint64_t t) {597 return __rbitll(t);598}599 600/* 9.4 Saturating intrinsics */601#ifdef __ARM_FEATURE_SAT602/* 9.4.1 Width-specified saturation intrinsics */603// AArch32-LABEL: @test_ssat(604// AArch32-NEXT: entry:605// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.ssat(i32 [[T:%.*]], i32 1)606// AArch32-NEXT: ret i32 [[TMP0]]607//608int32_t test_ssat(int32_t t) {609 return __ssat(t, 1);610}611 612// AArch32-LABEL: @test_usat(613// AArch32-NEXT: entry:614// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usat(i32 [[T:%.*]], i32 2)615// AArch32-NEXT: ret i32 [[TMP0]]616//617uint32_t test_usat(int32_t t) {618 return __usat(t, 2);619}620#endif621 622/* 9.4.2 Saturating addition and subtraction intrinsics */623#ifdef __ARM_32BIT_STATE624// AArch32-LABEL: @test_qadd(625// AArch32-NEXT: entry:626// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd(i32 [[A:%.*]], i32 [[B:%.*]])627// AArch32-NEXT: ret i32 [[TMP0]]628//629#ifndef __ARM_FEATURE_DSP630__attribute__((target("dsp")))631#endif632int32_t test_qadd(int32_t a, int32_t b) {633 return __qadd(a, b);634}635 636// AArch32-LABEL: @test_qsub(637// AArch32-NEXT: entry:638// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qsub(i32 [[A:%.*]], i32 [[B:%.*]])639// AArch32-NEXT: ret i32 [[TMP0]]640//641#ifndef __ARM_FEATURE_DSP642__attribute__((target("dsp")))643#endif644int32_t test_qsub(int32_t a, int32_t b) {645 return __qsub(a, b);646}647 648extern int32_t f();649// AArch32-LABEL: @test_qdbl(650// AArch32-NEXT: entry:651// AArch32-NEXT: [[CALL:%.*]] = call i32 @f() #[[ATTR9:[0-9]+]]652// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd(i32 [[CALL]], i32 [[CALL]])653// AArch32-NEXT: ret i32 [[TMP0]]654//655#ifndef __ARM_FEATURE_DSP656__attribute__((target("dsp")))657#endif658int32_t test_qdbl() {659 return __qdbl(f());660}661#endif662 663/*664 * 9.3 16-bit multiplications665 */666#ifdef __ARM_32BIT_STATE667// AArch32-LABEL: @test_smulbb(668// AArch32-NEXT: entry:669// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smulbb(i32 [[A:%.*]], i32 [[B:%.*]])670// AArch32-NEXT: ret i32 [[TMP0]]671//672#ifndef __ARM_FEATURE_DSP673__attribute__((target("dsp")))674#endif675int32_t test_smulbb(int32_t a, int32_t b) {676 return __smulbb(a, b);677}678 679// AArch32-LABEL: @test_smulbt(680// AArch32-NEXT: entry:681// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smulbt(i32 [[A:%.*]], i32 [[B:%.*]])682// AArch32-NEXT: ret i32 [[TMP0]]683//684#ifndef __ARM_FEATURE_DSP685__attribute__((target("dsp")))686#endif687int32_t test_smulbt(int32_t a, int32_t b) {688 return __smulbt(a, b);689}690 691// AArch32-LABEL: @test_smultb(692// AArch32-NEXT: entry:693// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smultb(i32 [[A:%.*]], i32 [[B:%.*]])694// AArch32-NEXT: ret i32 [[TMP0]]695//696#ifndef __ARM_FEATURE_DSP697__attribute__((target("dsp")))698#endif699int32_t test_smultb(int32_t a, int32_t b) {700 return __smultb(a, b);701}702 703// AArch32-LABEL: @test_smultt(704// AArch32-NEXT: entry:705// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smultt(i32 [[A:%.*]], i32 [[B:%.*]])706// AArch32-NEXT: ret i32 [[TMP0]]707//708#ifndef __ARM_FEATURE_DSP709__attribute__((target("dsp")))710#endif711int32_t test_smultt(int32_t a, int32_t b) {712 return __smultt(a, b);713}714 715// AArch32-LABEL: @test_smulwb(716// AArch32-NEXT: entry:717// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smulwb(i32 [[A:%.*]], i32 [[B:%.*]])718// AArch32-NEXT: ret i32 [[TMP0]]719//720#ifndef __ARM_FEATURE_DSP721__attribute__((target("dsp")))722#endif723int32_t test_smulwb(int32_t a, int32_t b) {724 return __smulwb(a, b);725}726 727// AArch32-LABEL: @test_smulwt(728// AArch32-NEXT: entry:729// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smulwt(i32 [[A:%.*]], i32 [[B:%.*]])730// AArch32-NEXT: ret i32 [[TMP0]]731//732#ifndef __ARM_FEATURE_DSP733__attribute__((target("dsp")))734#endif735int32_t test_smulwt(int32_t a, int32_t b) {736 return __smulwt(a, b);737}738#endif739 740/* 9.4.3 Accumultating multiplications */741#ifdef __ARM_32BIT_STATE742// AArch32-LABEL: @test_smlabb(743// AArch32-NEXT: entry:744// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlabb(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]])745// AArch32-NEXT: ret i32 [[TMP0]]746//747#ifndef __ARM_FEATURE_DSP748__attribute__((target("dsp")))749#endif750int32_t test_smlabb(int32_t a, int32_t b, int32_t c) {751 return __smlabb(a, b, c);752}753 754// AArch32-LABEL: @test_smlabt(755// AArch32-NEXT: entry:756// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlabt(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]])757// AArch32-NEXT: ret i32 [[TMP0]]758//759#ifndef __ARM_FEATURE_DSP760__attribute__((target("dsp")))761#endif762int32_t test_smlabt(int32_t a, int32_t b, int32_t c) {763 return __smlabt(a, b, c);764}765 766// AArch32-LABEL: @test_smlatb(767// AArch32-NEXT: entry:768// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlatb(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]])769// AArch32-NEXT: ret i32 [[TMP0]]770//771#ifndef __ARM_FEATURE_DSP772__attribute__((target("dsp")))773#endif774int32_t test_smlatb(int32_t a, int32_t b, int32_t c) {775 return __smlatb(a, b, c);776}777 778// AArch32-LABEL: @test_smlatt(779// AArch32-NEXT: entry:780// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlatt(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]])781// AArch32-NEXT: ret i32 [[TMP0]]782//783#ifndef __ARM_FEATURE_DSP784__attribute__((target("dsp")))785#endif786int32_t test_smlatt(int32_t a, int32_t b, int32_t c) {787 return __smlatt(a, b, c);788}789 790// AArch32-LABEL: @test_smlawb(791// AArch32-NEXT: entry:792// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlawb(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]])793// AArch32-NEXT: ret i32 [[TMP0]]794//795#ifndef __ARM_FEATURE_DSP796__attribute__((target("dsp")))797#endif798int32_t test_smlawb(int32_t a, int32_t b, int32_t c) {799 return __smlawb(a, b, c);800}801 802// AArch32-LABEL: @test_smlawt(803// AArch32-NEXT: entry:804// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlawt(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]])805// AArch32-NEXT: ret i32 [[TMP0]]806//807#ifndef __ARM_FEATURE_DSP808__attribute__((target("dsp")))809#endif810int32_t test_smlawt(int32_t a, int32_t b, int32_t c) {811 return __smlawt(a, b, c);812}813#endif814 815/* 9.5.4 Parallel 16-bit saturation */816#if __ARM_FEATURE_SIMD32817// AArch32-LABEL: @test_ssat16(818// AArch32-NEXT: entry:819// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.ssat16(i32 [[A:%.*]], i32 15)820// AArch32-NEXT: ret i32 [[TMP0]]821//822int16x2_t test_ssat16(int16x2_t a) {823 return __ssat16(a, 15);824}825 826// AArch32-LABEL: @test_usat16(827// AArch32-NEXT: entry:828// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usat16(i32 [[A:%.*]], i32 15)829// AArch32-NEXT: ret i32 [[TMP0]]830//831uint16x2_t test_usat16(int16x2_t a) {832 return __usat16(a, 15);833}834#endif835 836/* 9.5.5 Packing and unpacking */837#if __ARM_FEATURE_SIMD32838// AArch32-LABEL: @test_sxtab16(839// AArch32-NEXT: entry:840// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sxtab16(i32 [[A:%.*]], i32 [[B:%.*]])841// AArch32-NEXT: ret i32 [[TMP0]]842//843int16x2_t test_sxtab16(int16x2_t a, int8x4_t b) {844 return __sxtab16(a, b);845}846 847// AArch32-LABEL: @test_sxtb16(848// AArch32-NEXT: entry:849// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sxtb16(i32 [[A:%.*]])850// AArch32-NEXT: ret i32 [[TMP0]]851//852int16x2_t test_sxtb16(int8x4_t a) {853 return __sxtb16(a);854}855 856// AArch32-LABEL: @test_uxtab16(857// AArch32-NEXT: entry:858// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uxtab16(i32 [[A:%.*]], i32 [[B:%.*]])859// AArch32-NEXT: ret i32 [[TMP0]]860//861int16x2_t test_uxtab16(int16x2_t a, int8x4_t b) {862 return __uxtab16(a, b);863}864 865// AArch32-LABEL: @test_uxtb16(866// AArch32-NEXT: entry:867// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uxtb16(i32 [[A:%.*]])868// AArch32-NEXT: ret i32 [[TMP0]]869//870int16x2_t test_uxtb16(int8x4_t a) {871 return __uxtb16(a);872}873#endif874 875/* 9.5.6 Parallel selection */876#if __ARM_FEATURE_SIMD32877// AArch32-LABEL: @test_sel(878// AArch32-NEXT: entry:879// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sel(i32 [[A:%.*]], i32 [[B:%.*]])880// AArch32-NEXT: ret i32 [[TMP0]]881//882uint8x4_t test_sel(uint8x4_t a, uint8x4_t b) {883 return __sel(a, b);884}885#endif886 887/* 9.5.7 Parallel 8-bit addition and subtraction */888#if __ARM_FEATURE_SIMD32889// AArch32-LABEL: @test_qadd8(890// AArch32-NEXT: entry:891// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd8(i32 [[A:%.*]], i32 [[B:%.*]])892// AArch32-NEXT: ret i32 [[TMP0]]893//894int16x2_t test_qadd8(int8x4_t a, int8x4_t b) {895 return __qadd8(a, b);896}897 898// AArch32-LABEL: @test_qsub8(899// AArch32-NEXT: entry:900// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qsub8(i32 [[A:%.*]], i32 [[B:%.*]])901// AArch32-NEXT: ret i32 [[TMP0]]902//903int8x4_t test_qsub8(int8x4_t a, int8x4_t b) {904 return __qsub8(a, b);905}906 907// AArch32-LABEL: @test_sadd8(908// AArch32-NEXT: entry:909// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sadd8(i32 [[A:%.*]], i32 [[B:%.*]])910// AArch32-NEXT: ret i32 [[TMP0]]911//912int8x4_t test_sadd8(int8x4_t a, int8x4_t b) {913 return __sadd8(a, b);914}915 916// AArch32-LABEL: @test_shadd8(917// AArch32-NEXT: entry:918// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shadd8(i32 [[A:%.*]], i32 [[B:%.*]])919// AArch32-NEXT: ret i32 [[TMP0]]920//921int8x4_t test_shadd8(int8x4_t a, int8x4_t b) {922 return __shadd8(a, b);923}924 925// AArch32-LABEL: @test_shsub8(926// AArch32-NEXT: entry:927// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shsub8(i32 [[A:%.*]], i32 [[B:%.*]])928// AArch32-NEXT: ret i32 [[TMP0]]929//930int8x4_t test_shsub8(int8x4_t a, int8x4_t b) {931 return __shsub8(a, b);932}933 934// AArch32-LABEL: @test_ssub8(935// AArch32-NEXT: entry:936// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.ssub8(i32 [[A:%.*]], i32 [[B:%.*]])937// AArch32-NEXT: ret i32 [[TMP0]]938//939int8x4_t test_ssub8(int8x4_t a, int8x4_t b) {940 return __ssub8(a, b);941}942 943// AArch32-LABEL: @test_uadd8(944// AArch32-NEXT: entry:945// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uadd8(i32 [[A:%.*]], i32 [[B:%.*]])946// AArch32-NEXT: ret i32 [[TMP0]]947//948uint8x4_t test_uadd8(uint8x4_t a, uint8x4_t b) {949 return __uadd8(a, b);950}951 952// AArch32-LABEL: @test_uhadd8(953// AArch32-NEXT: entry:954// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhadd8(i32 [[A:%.*]], i32 [[B:%.*]])955// AArch32-NEXT: ret i32 [[TMP0]]956//957uint8x4_t test_uhadd8(uint8x4_t a, uint8x4_t b) {958 return __uhadd8(a, b);959}960 961// AArch32-LABEL: @test_uhsub8(962// AArch32-NEXT: entry:963// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhsub8(i32 [[A:%.*]], i32 [[B:%.*]])964// AArch32-NEXT: ret i32 [[TMP0]]965//966uint8x4_t test_uhsub8(uint8x4_t a, uint8x4_t b) {967 return __uhsub8(a, b);968}969 970// AArch32-LABEL: @test_uqadd8(971// AArch32-NEXT: entry:972// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqadd8(i32 [[A:%.*]], i32 [[B:%.*]])973// AArch32-NEXT: ret i32 [[TMP0]]974//975uint8x4_t test_uqadd8(uint8x4_t a, uint8x4_t b) {976 return __uqadd8(a, b);977}978 979// AArch32-LABEL: @test_uqsub8(980// AArch32-NEXT: entry:981// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqsub8(i32 [[A:%.*]], i32 [[B:%.*]])982// AArch32-NEXT: ret i32 [[TMP0]]983//984uint8x4_t test_uqsub8(uint8x4_t a, uint8x4_t b) {985 return __uqsub8(a, b);986}987 988// AArch32-LABEL: @test_usub8(989// AArch32-NEXT: entry:990// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usub8(i32 [[A:%.*]], i32 [[B:%.*]])991// AArch32-NEXT: ret i32 [[TMP0]]992//993uint8x4_t test_usub8(uint8x4_t a, uint8x4_t b) {994 return __usub8(a, b);995}996#endif997 998/* 9.5.8 Sum of 8-bit absolute differences */999#if __ARM_FEATURE_SIMD321000// AArch32-LABEL: @test_usad8(1001// AArch32-NEXT: entry:1002// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usad8(i32 [[A:%.*]], i32 [[B:%.*]])1003// AArch32-NEXT: ret i32 [[TMP0]]1004//1005uint32_t test_usad8(uint8x4_t a, uint8x4_t b) {1006 return __usad8(a, b);1007}1008 1009// AArch32-LABEL: @test_usada8(1010// AArch32-NEXT: entry:1011// AArch32-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i321012// AArch32-NEXT: [[CONV1:%.*]] = zext i8 [[B:%.*]] to i321013// AArch32-NEXT: [[CONV2:%.*]] = zext i8 [[C:%.*]] to i321014// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usada8(i32 [[CONV]], i32 [[CONV1]], i32 [[CONV2]])1015// AArch32-NEXT: ret i32 [[TMP0]]1016//1017uint32_t test_usada8(uint8_t a, uint8_t b, uint8_t c) {1018 return __usada8(a, b, c);1019}1020#endif1021 1022/* 9.5.9 Parallel 16-bit addition and subtraction */1023#if __ARM_FEATURE_SIMD321024// AArch32-LABEL: @test_qadd16(1025// AArch32-NEXT: entry:1026// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd16(i32 [[A:%.*]], i32 [[B:%.*]])1027// AArch32-NEXT: ret i32 [[TMP0]]1028//1029int16x2_t test_qadd16(int16x2_t a, int16x2_t b) {1030 return __qadd16(a, b);1031}1032 1033// AArch32-LABEL: @test_qasx(1034// AArch32-NEXT: entry:1035// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qasx(i32 [[A:%.*]], i32 [[B:%.*]])1036// AArch32-NEXT: ret i32 [[TMP0]]1037//1038int16x2_t test_qasx(int16x2_t a, int16x2_t b) {1039 return __qasx(a, b);1040}1041 1042// AArch32-LABEL: @test_qsax(1043// AArch32-NEXT: entry:1044// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qsax(i32 [[A:%.*]], i32 [[B:%.*]])1045// AArch32-NEXT: ret i32 [[TMP0]]1046//1047int16x2_t test_qsax(int16x2_t a, int16x2_t b) {1048 return __qsax(a, b);1049}1050 1051// AArch32-LABEL: @test_qsub16(1052// AArch32-NEXT: entry:1053// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qsub16(i32 [[A:%.*]], i32 [[B:%.*]])1054// AArch32-NEXT: ret i32 [[TMP0]]1055//1056int16x2_t test_qsub16(int16x2_t a, int16x2_t b) {1057 return __qsub16(a, b);1058}1059 1060// AArch32-LABEL: @test_sadd16(1061// AArch32-NEXT: entry:1062// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sadd16(i32 [[A:%.*]], i32 [[B:%.*]])1063// AArch32-NEXT: ret i32 [[TMP0]]1064//1065int16x2_t test_sadd16(int16x2_t a, int16x2_t b) {1066 return __sadd16(a, b);1067}1068 1069// AArch32-LABEL: @test_sasx(1070// AArch32-NEXT: entry:1071// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sasx(i32 [[A:%.*]], i32 [[B:%.*]])1072// AArch32-NEXT: ret i32 [[TMP0]]1073//1074int16x2_t test_sasx(int16x2_t a, int16x2_t b) {1075 return __sasx(a, b);1076}1077 1078// AArch32-LABEL: @test_shadd16(1079// AArch32-NEXT: entry:1080// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shadd16(i32 [[A:%.*]], i32 [[B:%.*]])1081// AArch32-NEXT: ret i32 [[TMP0]]1082//1083int16x2_t test_shadd16(int16x2_t a, int16x2_t b) {1084 return __shadd16(a, b);1085}1086 1087// AArch32-LABEL: @test_shasx(1088// AArch32-NEXT: entry:1089// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shasx(i32 [[A:%.*]], i32 [[B:%.*]])1090// AArch32-NEXT: ret i32 [[TMP0]]1091//1092int16x2_t test_shasx(int16x2_t a, int16x2_t b) {1093 return __shasx(a, b);1094}1095 1096// AArch32-LABEL: @test_shsax(1097// AArch32-NEXT: entry:1098// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shsax(i32 [[A:%.*]], i32 [[B:%.*]])1099// AArch32-NEXT: ret i32 [[TMP0]]1100//1101int16x2_t test_shsax(int16x2_t a, int16x2_t b) {1102 return __shsax(a, b);1103}1104 1105// AArch32-LABEL: @test_shsub16(1106// AArch32-NEXT: entry:1107// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shsub16(i32 [[A:%.*]], i32 [[B:%.*]])1108// AArch32-NEXT: ret i32 [[TMP0]]1109//1110int16x2_t test_shsub16(int16x2_t a, int16x2_t b) {1111 return __shsub16(a, b);1112}1113 1114// AArch32-LABEL: @test_ssax(1115// AArch32-NEXT: entry:1116// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.ssax(i32 [[A:%.*]], i32 [[B:%.*]])1117// AArch32-NEXT: ret i32 [[TMP0]]1118//1119int16x2_t test_ssax(int16x2_t a, int16x2_t b) {1120 return __ssax(a, b);1121}1122 1123// AArch32-LABEL: @test_ssub16(1124// AArch32-NEXT: entry:1125// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.ssub16(i32 [[A:%.*]], i32 [[B:%.*]])1126// AArch32-NEXT: ret i32 [[TMP0]]1127//1128int16x2_t test_ssub16(int16x2_t a, int16x2_t b) {1129 return __ssub16(a, b);1130}1131 1132// AArch32-LABEL: @test_uadd16(1133// AArch32-NEXT: entry:1134// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uadd16(i32 [[A:%.*]], i32 [[B:%.*]])1135// AArch32-NEXT: ret i32 [[TMP0]]1136//1137uint16x2_t test_uadd16(uint16x2_t a, uint16x2_t b) {1138 return __uadd16(a, b);1139}1140 1141// AArch32-LABEL: @test_uasx(1142// AArch32-NEXT: entry:1143// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uasx(i32 [[A:%.*]], i32 [[B:%.*]])1144// AArch32-NEXT: ret i32 [[TMP0]]1145//1146uint16x2_t test_uasx(uint16x2_t a, uint16x2_t b) {1147 return __uasx(a, b);1148}1149 1150// AArch32-LABEL: @test_uhadd16(1151// AArch32-NEXT: entry:1152// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhadd16(i32 [[A:%.*]], i32 [[B:%.*]])1153// AArch32-NEXT: ret i32 [[TMP0]]1154//1155uint16x2_t test_uhadd16(uint16x2_t a, uint16x2_t b) {1156 return __uhadd16(a, b);1157}1158 1159// AArch32-LABEL: @test_uhasx(1160// AArch32-NEXT: entry:1161// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhasx(i32 [[A:%.*]], i32 [[B:%.*]])1162// AArch32-NEXT: ret i32 [[TMP0]]1163//1164uint16x2_t test_uhasx(uint16x2_t a, uint16x2_t b) {1165 return __uhasx(a, b);1166}1167 1168// AArch32-LABEL: @test_uhsax(1169// AArch32-NEXT: entry:1170// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhsax(i32 [[A:%.*]], i32 [[B:%.*]])1171// AArch32-NEXT: ret i32 [[TMP0]]1172//1173uint16x2_t test_uhsax(uint16x2_t a, uint16x2_t b) {1174 return __uhsax(a, b);1175}1176 1177// AArch32-LABEL: @test_uhsub16(1178// AArch32-NEXT: entry:1179// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhsub16(i32 [[A:%.*]], i32 [[B:%.*]])1180// AArch32-NEXT: ret i32 [[TMP0]]1181//1182uint16x2_t test_uhsub16(uint16x2_t a, uint16x2_t b) {1183 return __uhsub16(a, b);1184}1185 1186// AArch32-LABEL: @test_uqadd16(1187// AArch32-NEXT: entry:1188// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqadd16(i32 [[A:%.*]], i32 [[B:%.*]])1189// AArch32-NEXT: ret i32 [[TMP0]]1190//1191uint16x2_t test_uqadd16(uint16x2_t a, uint16x2_t b) {1192 return __uqadd16(a, b);1193}1194 1195// AArch32-LABEL: @test_uqasx(1196// AArch32-NEXT: entry:1197// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqasx(i32 [[A:%.*]], i32 [[B:%.*]])1198// AArch32-NEXT: ret i32 [[TMP0]]1199//1200uint16x2_t test_uqasx(uint16x2_t a, uint16x2_t b) {1201 return __uqasx(a, b);1202}1203 1204// AArch32-LABEL: @test_uqsax(1205// AArch32-NEXT: entry:1206// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqsax(i32 [[A:%.*]], i32 [[B:%.*]])1207// AArch32-NEXT: ret i32 [[TMP0]]1208//1209uint16x2_t test_uqsax(uint16x2_t a, uint16x2_t b) {1210 return __uqsax(a, b);1211}1212 1213// AArch32-LABEL: @test_uqsub16(1214// AArch32-NEXT: entry:1215// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqsub16(i32 [[A:%.*]], i32 [[B:%.*]])1216// AArch32-NEXT: ret i32 [[TMP0]]1217//1218uint16x2_t test_uqsub16(uint16x2_t a, uint16x2_t b) {1219 return __uqsub16(a, b);1220}1221 1222// AArch32-LABEL: @test_usax(1223// AArch32-NEXT: entry:1224// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usax(i32 [[A:%.*]], i32 [[B:%.*]])1225// AArch32-NEXT: ret i32 [[TMP0]]1226//1227uint16x2_t test_usax(uint16x2_t a, uint16x2_t b) {1228 return __usax(a, b);1229}1230 1231// AArch32-LABEL: @test_usub16(1232// AArch32-NEXT: entry:1233// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usub16(i32 [[A:%.*]], i32 [[B:%.*]])1234// AArch32-NEXT: ret i32 [[TMP0]]1235//1236uint16x2_t test_usub16(uint16x2_t a, uint16x2_t b) {1237 return __usub16(a, b);1238}1239#endif1240 1241/* 9.5.10 Parallel 16-bit multiplications */1242#if __ARM_FEATURE_SIMD321243// AArch32-LABEL: @test_smlad(1244// AArch32-NEXT: entry:1245// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlad(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]])1246// AArch32-NEXT: ret i32 [[TMP0]]1247//1248int32_t test_smlad(int16x2_t a, int16x2_t b, int32_t c) {1249 return __smlad(a, b, c);1250}1251 1252// AArch32-LABEL: @test_smladx(1253// AArch32-NEXT: entry:1254// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smladx(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]])1255// AArch32-NEXT: ret i32 [[TMP0]]1256//1257int32_t test_smladx(int16x2_t a, int16x2_t b, int32_t c) {1258 return __smladx(a, b, c);1259}1260 1261// AArch32-LABEL: @test_smlald(1262// AArch32-NEXT: entry:1263// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.arm.smlald(i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]])1264// AArch32-NEXT: ret i64 [[TMP0]]1265//1266int64_t test_smlald(int16x2_t a, int16x2_t b, int64_t c) {1267 return __smlald(a, b, c);1268}1269 1270// AArch32-LABEL: @test_smlaldx(1271// AArch32-NEXT: entry:1272// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]])1273// AArch32-NEXT: ret i64 [[TMP0]]1274//1275int64_t test_smlaldx(int16x2_t a, int16x2_t b, int64_t c) {1276 return __smlaldx(a, b, c);1277}1278 1279// AArch32-LABEL: @test_smlsd(1280// AArch32-NEXT: entry:1281// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlsd(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]])1282// AArch32-NEXT: ret i32 [[TMP0]]1283//1284int32_t test_smlsd(int16x2_t a, int16x2_t b, int32_t c) {1285 return __smlsd(a, b, c);1286}1287 1288// AArch32-LABEL: @test_smlsdx(1289// AArch32-NEXT: entry:1290// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlsdx(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]])1291// AArch32-NEXT: ret i32 [[TMP0]]1292//1293int32_t test_smlsdx(int16x2_t a, int16x2_t b, int32_t c) {1294 return __smlsdx(a, b, c);1295}1296 1297// AArch32-LABEL: @test_smlsld(1298// AArch32-NEXT: entry:1299// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.arm.smlsld(i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]])1300// AArch32-NEXT: ret i64 [[TMP0]]1301//1302int64_t test_smlsld(int16x2_t a, int16x2_t b, int64_t c) {1303 return __smlsld(a, b, c);1304}1305 1306// AArch32-LABEL: @test_smlsldx(1307// AArch32-NEXT: entry:1308// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.arm.smlsldx(i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]])1309// AArch32-NEXT: ret i64 [[TMP0]]1310//1311int64_t test_smlsldx(int16x2_t a, int16x2_t b, int64_t c) {1312 return __smlsldx(a, b, c);1313}1314 1315// AArch32-LABEL: @test_smuad(1316// AArch32-NEXT: entry:1317// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smuad(i32 [[A:%.*]], i32 [[B:%.*]])1318// AArch32-NEXT: ret i32 [[TMP0]]1319//1320int32_t test_smuad(int16x2_t a, int16x2_t b) {1321 return __smuad(a, b);1322}1323 1324// AArch32-LABEL: @test_smuadx(1325// AArch32-NEXT: entry:1326// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smuadx(i32 [[A:%.*]], i32 [[B:%.*]])1327// AArch32-NEXT: ret i32 [[TMP0]]1328//1329int32_t test_smuadx(int16x2_t a, int16x2_t b) {1330 return __smuadx(a, b);1331}1332 1333// AArch32-LABEL: @test_smusd(1334// AArch32-NEXT: entry:1335// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smusd(i32 [[A:%.*]], i32 [[B:%.*]])1336// AArch32-NEXT: ret i32 [[TMP0]]1337//1338int32_t test_smusd(int16x2_t a, int16x2_t b) {1339 return __smusd(a, b);1340}1341 1342// AArch32-LABEL: @test_smusdx(1343// AArch32-NEXT: entry:1344// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smusdx(i32 [[A:%.*]], i32 [[B:%.*]])1345// AArch32-NEXT: ret i32 [[TMP0]]1346//1347int32_t test_smusdx(int16x2_t a, int16x2_t b) {1348 return __smusdx(a, b);1349}1350#endif1351 1352/* 9.7 CRC32 intrinsics */1353// AArch32-LABEL: @test_crc32b(1354// AArch32-NEXT: entry:1355// AArch32-NEXT: [[TMP0:%.*]] = zext i8 [[B:%.*]] to i321356// AArch32-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.crc32b(i32 [[A:%.*]], i32 [[TMP0]])1357// AArch32-NEXT: ret i32 [[TMP1]]1358//1359// AArch64-LABEL: @test_crc32b(1360// AArch64-NEXT: entry:1361// AArch64-NEXT: [[TMP0:%.*]] = zext i8 [[B:%.*]] to i321362// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.aarch64.crc32b(i32 [[A:%.*]], i32 [[TMP0]])1363// AArch64-NEXT: ret i32 [[TMP1]]1364//1365#ifndef __ARM_FEATURE_CRC321366__attribute__((target("crc")))1367#endif1368uint32_t test_crc32b(uint32_t a, uint8_t b) {1369 return __crc32b(a, b);1370}1371 1372// AArch32-LABEL: @test_crc32h(1373// AArch32-NEXT: entry:1374// AArch32-NEXT: [[TMP0:%.*]] = zext i16 [[B:%.*]] to i321375// AArch32-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.crc32h(i32 [[A:%.*]], i32 [[TMP0]])1376// AArch32-NEXT: ret i32 [[TMP1]]1377//1378// AArch64-LABEL: @test_crc32h(1379// AArch64-NEXT: entry:1380// AArch64-NEXT: [[TMP0:%.*]] = zext i16 [[B:%.*]] to i321381// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.aarch64.crc32h(i32 [[A:%.*]], i32 [[TMP0]])1382// AArch64-NEXT: ret i32 [[TMP1]]1383//1384#ifndef __ARM_FEATURE_CRC321385__attribute__((target("crc")))1386#endif1387uint32_t test_crc32h(uint32_t a, uint16_t b) {1388 return __crc32h(a, b);1389}1390 1391// AArch32-LABEL: @test_crc32w(1392// AArch32-NEXT: entry:1393// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.crc32w(i32 [[A:%.*]], i32 [[B:%.*]])1394// AArch32-NEXT: ret i32 [[TMP0]]1395//1396// AArch64-LABEL: @test_crc32w(1397// AArch64-NEXT: entry:1398// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.aarch64.crc32w(i32 [[A:%.*]], i32 [[B:%.*]])1399// AArch64-NEXT: ret i32 [[TMP0]]1400//1401#ifndef __ARM_FEATURE_CRC321402__attribute__((target("crc")))1403#endif1404uint32_t test_crc32w(uint32_t a, uint32_t b) {1405 return __crc32w(a, b);1406}1407 1408// AArch32-LABEL: @test_crc32d(1409// AArch32-NEXT: entry:1410// AArch32-NEXT: [[TMP0:%.*]] = trunc i64 [[B:%.*]] to i321411// AArch32-NEXT: [[TMP1:%.*]] = lshr i64 [[B]], 321412// AArch32-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i321413// AArch32-NEXT: [[TMP3:%.*]] = call i32 @llvm.arm.crc32w(i32 [[A:%.*]], i32 [[TMP0]])1414// AArch32-NEXT: [[TMP4:%.*]] = call i32 @llvm.arm.crc32w(i32 [[TMP3]], i32 [[TMP2]])1415// AArch32-NEXT: ret i32 [[TMP4]]1416//1417// AArch64-LABEL: @test_crc32d(1418// AArch64-NEXT: entry:1419// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.aarch64.crc32x(i32 [[A:%.*]], i64 [[B:%.*]])1420// AArch64-NEXT: ret i32 [[TMP0]]1421//1422#ifndef __ARM_FEATURE_CRC321423__attribute__((target("crc")))1424#endif1425uint32_t test_crc32d(uint32_t a, uint64_t b) {1426 return __crc32d(a, b);1427}1428 1429// AArch32-LABEL: @test_crc32cb(1430// AArch32-NEXT: entry:1431// AArch32-NEXT: [[TMP0:%.*]] = zext i8 [[B:%.*]] to i321432// AArch32-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.crc32cb(i32 [[A:%.*]], i32 [[TMP0]])1433// AArch32-NEXT: ret i32 [[TMP1]]1434//1435// AArch64-LABEL: @test_crc32cb(1436// AArch64-NEXT: entry:1437// AArch64-NEXT: [[TMP0:%.*]] = zext i8 [[B:%.*]] to i321438// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.aarch64.crc32cb(i32 [[A:%.*]], i32 [[TMP0]])1439// AArch64-NEXT: ret i32 [[TMP1]]1440//1441#ifndef __ARM_FEATURE_CRC321442__attribute__((target("crc")))1443#endif1444uint32_t test_crc32cb(uint32_t a, uint8_t b) {1445 return __crc32cb(a, b);1446}1447 1448// AArch32-LABEL: @test_crc32ch(1449// AArch32-NEXT: entry:1450// AArch32-NEXT: [[TMP0:%.*]] = zext i16 [[B:%.*]] to i321451// AArch32-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.crc32ch(i32 [[A:%.*]], i32 [[TMP0]])1452// AArch32-NEXT: ret i32 [[TMP1]]1453//1454// AArch64-LABEL: @test_crc32ch(1455// AArch64-NEXT: entry:1456// AArch64-NEXT: [[TMP0:%.*]] = zext i16 [[B:%.*]] to i321457// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.aarch64.crc32ch(i32 [[A:%.*]], i32 [[TMP0]])1458// AArch64-NEXT: ret i32 [[TMP1]]1459//1460#ifndef __ARM_FEATURE_CRC321461__attribute__((target("crc")))1462#endif1463uint32_t test_crc32ch(uint32_t a, uint16_t b) {1464 return __crc32ch(a, b);1465}1466 1467// AArch32-LABEL: @test_crc32cw(1468// AArch32-NEXT: entry:1469// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.crc32cw(i32 [[A:%.*]], i32 [[B:%.*]])1470// AArch32-NEXT: ret i32 [[TMP0]]1471//1472// AArch64-LABEL: @test_crc32cw(1473// AArch64-NEXT: entry:1474// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.aarch64.crc32cw(i32 [[A:%.*]], i32 [[B:%.*]])1475// AArch64-NEXT: ret i32 [[TMP0]]1476//1477#ifndef __ARM_FEATURE_CRC321478__attribute__((target("crc")))1479#endif1480uint32_t test_crc32cw(uint32_t a, uint32_t b) {1481 return __crc32cw(a, b);1482}1483 1484// AArch32-LABEL: @test_crc32cd(1485// AArch32-NEXT: entry:1486// AArch32-NEXT: [[TMP0:%.*]] = trunc i64 [[B:%.*]] to i321487// AArch32-NEXT: [[TMP1:%.*]] = lshr i64 [[B]], 321488// AArch32-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i321489// AArch32-NEXT: [[TMP3:%.*]] = call i32 @llvm.arm.crc32cw(i32 [[A:%.*]], i32 [[TMP0]])1490// AArch32-NEXT: [[TMP4:%.*]] = call i32 @llvm.arm.crc32cw(i32 [[TMP3]], i32 [[TMP2]])1491// AArch32-NEXT: ret i32 [[TMP4]]1492//1493// AArch64-LABEL: @test_crc32cd(1494// AArch64-NEXT: entry:1495// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.aarch64.crc32cx(i32 [[A:%.*]], i64 [[B:%.*]])1496// AArch64-NEXT: ret i32 [[TMP0]]1497//1498#ifndef __ARM_FEATURE_CRC321499__attribute__((target("crc")))1500#endif1501uint32_t test_crc32cd(uint32_t a, uint64_t b) {1502 return __crc32cd(a, b);1503}1504 1505/* 10.1 Special register intrinsics */1506// AArch32-LABEL: @test_rsr(1507// AArch32-NEXT: entry:1508// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META5:![0-9]+]])1509// AArch32-NEXT: ret i32 [[TMP0]]1510//1511// AArch64-LABEL: @test_rsr(1512// AArch64-NEXT: entry:1513// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4:![0-9]+]])1514// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i321515// AArch64-NEXT: ret i32 [[TMP1]]1516//1517uint32_t test_rsr() {1518#ifdef __ARM_32BIT_STATE1519 return __arm_rsr("cp1:2:c3:c4:5");1520#else1521 return __arm_rsr("1:2:3:4:5");1522#endif1523}1524 1525// AArch32-LABEL: @test_rsr64(1526// AArch32-NEXT: entry:1527// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META6:![0-9]+]])1528// AArch32-NEXT: ret i64 [[TMP0]]1529//1530// AArch64-LABEL: @test_rsr64(1531// AArch64-NEXT: entry:1532// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]])1533// AArch64-NEXT: ret i64 [[TMP0]]1534//1535uint64_t test_rsr64() {1536#ifdef __ARM_32BIT_STATE1537 return __arm_rsr64("cp1:2:c3");1538#else1539 return __arm_rsr64("1:2:3:4:5");1540#endif1541}1542 1543#ifdef __ARM_FEATURE_SYSREG1281544// AArch6494D128-LABEL: @test_rsr128(1545// AArch6494D128-NEXT: entry:1546// AArch6494D128-NEXT: [[TMP0:%.*]] = call i128 @llvm.read_volatile_register.i128(metadata [[META4]])1547// AArch6494D128-NEXT: ret i128 [[TMP0]]1548//1549__uint128_t test_rsr128() {1550 return __arm_rsr128("1:2:3:4:5");1551}1552#endif1553 1554// AArch32-LABEL: @test_rsrp(1555// AArch32-NEXT: entry:1556// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META7:![0-9]+]])1557// AArch32-NEXT: [[TMP1:%.*]] = inttoptr i32 [[TMP0]] to ptr1558// AArch32-NEXT: ret ptr [[TMP1]]1559//1560// AArch64-LABEL: @test_rsrp(1561// AArch64-NEXT: entry:1562// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META5:![0-9]+]])1563// AArch64-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to ptr1564// AArch64-NEXT: ret ptr [[TMP1]]1565//1566void *test_rsrp() {1567 return __arm_rsrp("sysreg");1568}1569 1570// AArch32-LABEL: @test_wsr(1571// AArch32-NEXT: entry:1572// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META5]], i32 [[V:%.*]])1573// AArch32-NEXT: ret void1574//1575// AArch64-LABEL: @test_wsr(1576// AArch64-NEXT: entry:1577// AArch64-NEXT: [[TMP0:%.*]] = zext i32 [[V:%.*]] to i641578// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP0]])1579// AArch64-NEXT: ret void1580//1581void test_wsr(uint32_t v) {1582#ifdef __ARM_32BIT_STATE1583 __arm_wsr("cp1:2:c3:c4:5", v);1584#else1585 __arm_wsr("1:2:3:4:5", v);1586#endif1587}1588 1589// AArch32-LABEL: @test_wsr64(1590// AArch32-NEXT: entry:1591// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META6]], i64 [[V:%.*]])1592// AArch32-NEXT: ret void1593//1594// AArch64-LABEL: @test_wsr64(1595// AArch64-NEXT: entry:1596// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[V:%.*]])1597// AArch64-NEXT: ret void1598//1599void test_wsr64(uint64_t v) {1600#ifdef __ARM_32BIT_STATE1601 __arm_wsr64("cp1:2:c3", v);1602#else1603 __arm_wsr64("1:2:3:4:5", v);1604#endif1605}1606 1607#ifdef __ARM_FEATURE_SYSREG1281608// AArch6494D128-LABEL: @test_wsr128(1609// AArch6494D128-NEXT: entry:1610// AArch6494D128-NEXT: call void @llvm.write_register.i128(metadata [[META4]], i128 [[V:%.*]])1611// AArch6494D128-NEXT: ret void1612//1613void test_wsr128(__uint128_t v) {1614 __arm_wsr128("1:2:3:4:5", v);1615 1616}1617#endif1618 1619// AArch32-LABEL: @test_wsrp(1620// AArch32-NEXT: entry:1621// AArch32-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[V:%.*]] to i321622// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META7]], i32 [[TMP0]])1623// AArch32-NEXT: ret void1624//1625// AArch64-LABEL: @test_wsrp(1626// AArch64-NEXT: entry:1627// AArch64-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[V:%.*]] to i641628// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META5]], i64 [[TMP0]])1629// AArch64-NEXT: ret void1630//1631void test_wsrp(void *v) {1632 __arm_wsrp("sysreg", v);1633}1634 1635// AArch32-LABEL: @test_rsrf(1636// AArch32-NEXT: entry:1637// AArch32-NEXT: [[REF_TMP:%.*]] = alloca i32, align 41638// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META5]])1639// AArch32-NEXT: store i32 [[TMP0]], ptr [[REF_TMP]], align 41640// AArch32-NEXT: [[TMP1:%.*]] = load float, ptr [[REF_TMP]], align 41641// AArch32-NEXT: ret float [[TMP1]]1642//1643// AArch64-LABEL: @test_rsrf(1644// AArch64-NEXT: entry:1645// AArch64-NEXT: [[REF_TMP:%.*]] = alloca i32, align 41646// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]])1647// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i321648// AArch64-NEXT: store i32 [[TMP1]], ptr [[REF_TMP]], align 41649// AArch64-NEXT: [[TMP2:%.*]] = load float, ptr [[REF_TMP]], align 41650// AArch64-NEXT: ret float [[TMP2]]1651//1652float test_rsrf() {1653#ifdef __ARM_32BIT_STATE1654 return __arm_rsrf("cp1:2:c3:c4:5");1655#else1656 return __arm_rsrf("1:2:3:4:5");1657#endif1658}1659 1660// AArch32-LABEL: @test_rsrf64(1661// AArch32-NEXT: entry:1662// AArch32-NEXT: [[REF_TMP:%.*]] = alloca i64, align 81663// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META6]])1664// AArch32-NEXT: store i64 [[TMP0]], ptr [[REF_TMP]], align 81665// AArch32-NEXT: [[TMP1:%.*]] = load double, ptr [[REF_TMP]], align 81666// AArch32-NEXT: ret double [[TMP1]]1667//1668// AArch64-LABEL: @test_rsrf64(1669// AArch64-NEXT: entry:1670// AArch64-NEXT: [[REF_TMP:%.*]] = alloca i64, align 81671// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]])1672// AArch64-NEXT: store i64 [[TMP0]], ptr [[REF_TMP]], align 81673// AArch64-NEXT: [[TMP1:%.*]] = load double, ptr [[REF_TMP]], align 81674// AArch64-NEXT: ret double [[TMP1]]1675//1676double test_rsrf64() {1677#ifdef __ARM_32BIT_STATE1678 return __arm_rsrf64("cp1:2:c3");1679#else1680 return __arm_rsrf64("1:2:3:4:5");1681#endif1682}1683 1684// AArch32-LABEL: @test_wsrf(1685// AArch32-NEXT: entry:1686// AArch32-NEXT: [[V_ADDR:%.*]] = alloca float, align 41687// AArch32-NEXT: store float [[V:%.*]], ptr [[V_ADDR]], align 41688// AArch32-NEXT: [[TMP0:%.*]] = load i32, ptr [[V_ADDR]], align 41689// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META5]], i32 [[TMP0]])1690// AArch32-NEXT: ret void1691//1692// AArch64-LABEL: @test_wsrf(1693// AArch64-NEXT: entry:1694// AArch64-NEXT: [[V_ADDR:%.*]] = alloca float, align 41695// AArch64-NEXT: store float [[V:%.*]], ptr [[V_ADDR]], align 41696// AArch64-NEXT: [[TMP0:%.*]] = load i32, ptr [[V_ADDR]], align 41697// AArch64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i641698// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP1]])1699// AArch64-NEXT: ret void1700//1701void test_wsrf(float v) {1702#ifdef __ARM_32BIT_STATE1703 __arm_wsrf("cp1:2:c3:c4:5", v);1704#else1705 __arm_wsrf("1:2:3:4:5", v);1706#endif1707}1708 1709// AArch32-LABEL: @test_wsrf64(1710// AArch32-NEXT: entry:1711// AArch32-NEXT: [[V_ADDR:%.*]] = alloca double, align 81712// AArch32-NEXT: store double [[V:%.*]], ptr [[V_ADDR]], align 81713// AArch32-NEXT: [[TMP0:%.*]] = load i64, ptr [[V_ADDR]], align 81714// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META6]], i64 [[TMP0]])1715// AArch32-NEXT: ret void1716//1717// AArch64-LABEL: @test_wsrf64(1718// AArch64-NEXT: entry:1719// AArch64-NEXT: [[V_ADDR:%.*]] = alloca double, align 81720// AArch64-NEXT: store double [[V:%.*]], ptr [[V_ADDR]], align 81721// AArch64-NEXT: [[TMP0:%.*]] = load i64, ptr [[V_ADDR]], align 81722// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP0]])1723// AArch64-NEXT: ret void1724//1725void test_wsrf64(double v) {1726#ifdef __ARM_32BIT_STATE1727 __arm_wsrf64("cp1:2:c3", v);1728#else1729 __arm_wsrf64("1:2:3:4:5", v);1730#endif1731}1732 1733#if defined(__ARM_64BIT_STATE) && defined(__ARM_FEATURE_JCVT)1734// AArch6483-LABEL: @test_jcvt(1735// AArch6483-NEXT: entry:1736// AArch6483-NEXT: [[TMP0:%.*]] = call i32 @llvm.aarch64.fjcvtzs(double [[V:%.*]])1737// AArch6483-NEXT: ret i32 [[TMP0]]1738//1739int32_t test_jcvt(double v) {1740 return __jcvt(v);1741}1742#endif1743 1744#if defined(__ARM_FEATURE_DIRECTED_ROUNDING) && defined(__ARM_64BIT_STATE)1745 1746// AArch64-LABEL: @test_rintn(1747// AArch64-NEXT: entry:1748// AArch64-NEXT: call double @llvm.roundeven.f64(double [[TMP0:%.*]])1749double test_rintn(double a) {1750 return __rintn(a);1751}1752 1753// AArch64-LABEL: @test_rintnf(1754// AArch64-NEXT: entry:1755// AArch64-NEXT: call float @llvm.roundeven.f32(float [[TMP0:%.*]])1756float test_rintnf(float b) {1757 return __rintnf(b);1758}1759#endif1760 1761#if defined(__ARM_64BIT_STATE) && defined(__ARM_FEATURE_RNG)1762 1763// AArch6485-LABEL: @test_rndr(1764// AArch6485-NEXT: entry:1765// AArch6485-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndr()1766// AArch6485-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 01767// AArch6485-NEXT: [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 11768// AArch6485-NEXT: store i64 [[TMP1]], ptr [[__ADDR:%.*]], align 81769// AArch6485-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i321770// AArch6485-NEXT: ret i32 [[TMP3]]1771//1772int test_rndr(uint64_t *__addr) {1773 return __rndr(__addr);1774}1775 1776// AArch6485-LABEL: @test_rndrrs(1777// AArch6485-NEXT: entry:1778// AArch6485-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndrrs()1779// AArch6485-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 01780// AArch6485-NEXT: [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 11781// AArch6485-NEXT: store i64 [[TMP1]], ptr [[__ADDR:%.*]], align 81782// AArch6485-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i321783// AArch6485-NEXT: ret i32 [[TMP3]]1784//1785int test_rndrrs(uint64_t *__addr) {1786 return __rndrrs(__addr);1787}1788#endif1789 1790 1791