19470 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -triple thumbv7s-apple-darwin -target-abi apcs-gnu\3// RUN: -target-cpu swift \4// RUN: -target-feature +fullfp16 -ffreestanding \5// RUN: -flax-vector-conversions=none \6// RUN: -disable-O0-optnone -emit-llvm -o - %s \7// RUN: | opt -S -passes=mem2reg,sroa | FileCheck %s8 9// REQUIRES: aarch64-registered-target || arm-registered-target10 11#include <arm_neon.h>12 13// CHECK-LABEL: define <8 x i8> @test_vaba_s8(14// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] {15// CHECK-NEXT: [[ENTRY:.*:]]16// CHECK-NEXT: [[VABD_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> [[B]], <8 x i8> [[C]])17// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[VABD_V_I]]18// CHECK-NEXT: ret <8 x i8> [[ADD_I]]19//20int8x8_t test_vaba_s8(int8x8_t a, int8x8_t b, int8x8_t c) {21 return vaba_s8(a, b, c);22}23 24// CHECK-LABEL: define <4 x i16> @test_vaba_s16(25// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {26// CHECK-NEXT: [[ENTRY:.*:]]27// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>28// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>29// CHECK-NEXT: [[VABD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>30// CHECK-NEXT: [[VABD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>31// CHECK-NEXT: [[VABD_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> [[VABD_V_I]], <4 x i16> [[VABD_V1_I]])32// CHECK-NEXT: [[VABD_V3_I:%.*]] = bitcast <4 x i16> [[VABD_V2_I]] to <8 x i8>33// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I]] to <4 x i16>34// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[TMP2]]35// CHECK-NEXT: ret <4 x i16> [[ADD_I]]36//37int16x4_t test_vaba_s16(int16x4_t a, int16x4_t b, int16x4_t c) {38 return vaba_s16(a, b, c);39}40 41// CHECK-LABEL: define <2 x i32> @test_vaba_s32(42// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {43// CHECK-NEXT: [[ENTRY:.*:]]44// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>45// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>46// CHECK-NEXT: [[VABD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>47// CHECK-NEXT: [[VABD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>48// CHECK-NEXT: [[VABD_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> [[VABD_V_I]], <2 x i32> [[VABD_V1_I]])49// CHECK-NEXT: [[VABD_V3_I:%.*]] = bitcast <2 x i32> [[VABD_V2_I]] to <8 x i8>50// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I]] to <2 x i32>51// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[TMP2]]52// CHECK-NEXT: ret <2 x i32> [[ADD_I]]53//54int32x2_t test_vaba_s32(int32x2_t a, int32x2_t b, int32x2_t c) {55 return vaba_s32(a, b, c);56}57 58// CHECK-LABEL: define <8 x i8> @test_vaba_u8(59// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {60// CHECK-NEXT: [[ENTRY:.*:]]61// CHECK-NEXT: [[VABD_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> [[B]], <8 x i8> [[C]])62// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[VABD_V_I]]63// CHECK-NEXT: ret <8 x i8> [[ADD_I]]64//65uint8x8_t test_vaba_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c) {66 return vaba_u8(a, b, c);67}68 69// CHECK-LABEL: define <4 x i16> @test_vaba_u16(70// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {71// CHECK-NEXT: [[ENTRY:.*:]]72// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>73// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>74// CHECK-NEXT: [[VABD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>75// CHECK-NEXT: [[VABD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>76// CHECK-NEXT: [[VABD_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> [[VABD_V_I]], <4 x i16> [[VABD_V1_I]])77// CHECK-NEXT: [[VABD_V3_I:%.*]] = bitcast <4 x i16> [[VABD_V2_I]] to <8 x i8>78// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I]] to <4 x i16>79// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[TMP2]]80// CHECK-NEXT: ret <4 x i16> [[ADD_I]]81//82uint16x4_t test_vaba_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c) {83 return vaba_u16(a, b, c);84}85 86// CHECK-LABEL: define <2 x i32> @test_vaba_u32(87// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {88// CHECK-NEXT: [[ENTRY:.*:]]89// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>90// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>91// CHECK-NEXT: [[VABD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>92// CHECK-NEXT: [[VABD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>93// CHECK-NEXT: [[VABD_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> [[VABD_V_I]], <2 x i32> [[VABD_V1_I]])94// CHECK-NEXT: [[VABD_V3_I:%.*]] = bitcast <2 x i32> [[VABD_V2_I]] to <8 x i8>95// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I]] to <2 x i32>96// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[TMP2]]97// CHECK-NEXT: ret <2 x i32> [[ADD_I]]98//99uint32x2_t test_vaba_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c) {100 return vaba_u32(a, b, c);101}102 103// CHECK-LABEL: define <16 x i8> @test_vabaq_s8(104// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]], <16 x i8> noundef [[C:%.*]]) #[[ATTR0]] {105// CHECK-NEXT: [[ENTRY:.*:]]106// CHECK-NEXT: [[VABDQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> [[B]], <16 x i8> [[C]])107// CHECK-NEXT: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[VABDQ_V_I]]108// CHECK-NEXT: ret <16 x i8> [[ADD_I]]109//110int8x16_t test_vabaq_s8(int8x16_t a, int8x16_t b, int8x16_t c) {111 return vabaq_s8(a, b, c);112}113 114// CHECK-LABEL: define <8 x i16> @test_vabaq_s16(115// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <8 x i16> noundef [[C:%.*]]) #[[ATTR0]] {116// CHECK-NEXT: [[ENTRY:.*:]]117// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>118// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[C]] to <16 x i8>119// CHECK-NEXT: [[VABDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>120// CHECK-NEXT: [[VABDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>121// CHECK-NEXT: [[VABDQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> [[VABDQ_V_I]], <8 x i16> [[VABDQ_V1_I]])122// CHECK-NEXT: [[VABDQ_V3_I:%.*]] = bitcast <8 x i16> [[VABDQ_V2_I]] to <16 x i8>123// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VABDQ_V3_I]] to <8 x i16>124// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[TMP2]]125// CHECK-NEXT: ret <8 x i16> [[ADD_I]]126//127int16x8_t test_vabaq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {128 return vabaq_s16(a, b, c);129}130 131// CHECK-LABEL: define <4 x i32> @test_vabaq_s32(132// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <4 x i32> noundef [[C:%.*]]) #[[ATTR0]] {133// CHECK-NEXT: [[ENTRY:.*:]]134// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>135// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[C]] to <16 x i8>136// CHECK-NEXT: [[VABDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>137// CHECK-NEXT: [[VABDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>138// CHECK-NEXT: [[VABDQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> [[VABDQ_V_I]], <4 x i32> [[VABDQ_V1_I]])139// CHECK-NEXT: [[VABDQ_V3_I:%.*]] = bitcast <4 x i32> [[VABDQ_V2_I]] to <16 x i8>140// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VABDQ_V3_I]] to <4 x i32>141// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[TMP2]]142// CHECK-NEXT: ret <4 x i32> [[ADD_I]]143//144int32x4_t test_vabaq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {145 return vabaq_s32(a, b, c);146}147 148// CHECK-LABEL: define <16 x i8> @test_vabaq_u8(149// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]], <16 x i8> noundef [[C:%.*]]) #[[ATTR0]] {150// CHECK-NEXT: [[ENTRY:.*:]]151// CHECK-NEXT: [[VABDQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> [[B]], <16 x i8> [[C]])152// CHECK-NEXT: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[VABDQ_V_I]]153// CHECK-NEXT: ret <16 x i8> [[ADD_I]]154//155uint8x16_t test_vabaq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c) {156 return vabaq_u8(a, b, c);157}158 159// CHECK-LABEL: define <8 x i16> @test_vabaq_u16(160// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <8 x i16> noundef [[C:%.*]]) #[[ATTR0]] {161// CHECK-NEXT: [[ENTRY:.*:]]162// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>163// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[C]] to <16 x i8>164// CHECK-NEXT: [[VABDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>165// CHECK-NEXT: [[VABDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>166// CHECK-NEXT: [[VABDQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> [[VABDQ_V_I]], <8 x i16> [[VABDQ_V1_I]])167// CHECK-NEXT: [[VABDQ_V3_I:%.*]] = bitcast <8 x i16> [[VABDQ_V2_I]] to <16 x i8>168// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VABDQ_V3_I]] to <8 x i16>169// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[TMP2]]170// CHECK-NEXT: ret <8 x i16> [[ADD_I]]171//172uint16x8_t test_vabaq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c) {173 return vabaq_u16(a, b, c);174}175 176// CHECK-LABEL: define <4 x i32> @test_vabaq_u32(177// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <4 x i32> noundef [[C:%.*]]) #[[ATTR0]] {178// CHECK-NEXT: [[ENTRY:.*:]]179// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>180// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[C]] to <16 x i8>181// CHECK-NEXT: [[VABDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>182// CHECK-NEXT: [[VABDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>183// CHECK-NEXT: [[VABDQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> [[VABDQ_V_I]], <4 x i32> [[VABDQ_V1_I]])184// CHECK-NEXT: [[VABDQ_V3_I:%.*]] = bitcast <4 x i32> [[VABDQ_V2_I]] to <16 x i8>185// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VABDQ_V3_I]] to <4 x i32>186// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[TMP2]]187// CHECK-NEXT: ret <4 x i32> [[ADD_I]]188//189uint32x4_t test_vabaq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c) {190 return vabaq_u32(a, b, c);191}192 193// CHECK-LABEL: define <8 x i16> @test_vabal_s8(194// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {195// CHECK-NEXT: [[ENTRY:.*:]]196// CHECK-NEXT: [[VABD_V_I_I:%.*]] = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> [[B]], <8 x i8> [[C]])197// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <8 x i8> [[VABD_V_I_I]] to <8 x i16>198// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[VMOVL_I]]199// CHECK-NEXT: ret <8 x i16> [[ADD_I]]200//201int16x8_t test_vabal_s8(int16x8_t a, int8x8_t b, int8x8_t c) {202 return vabal_s8(a, b, c);203}204 205// CHECK-LABEL: define <4 x i32> @test_vabal_s16(206// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {207// CHECK-NEXT: [[ENTRY:.*:]]208// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>209// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>210// CHECK-NEXT: [[VABD_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>211// CHECK-NEXT: [[VABD_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>212// CHECK-NEXT: [[VABD_V2_I_I:%.*]] = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> [[VABD_V_I_I]], <4 x i16> [[VABD_V1_I_I]])213// CHECK-NEXT: [[VABD_V3_I_I:%.*]] = bitcast <4 x i16> [[VABD_V2_I_I]] to <8 x i8>214// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I_I]] to <4 x i16>215// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>216// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>217// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <4 x i16> [[TMP4]] to <4 x i32>218// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[VMOVL_I]]219// CHECK-NEXT: ret <4 x i32> [[ADD_I]]220//221int32x4_t test_vabal_s16(int32x4_t a, int16x4_t b, int16x4_t c) {222 return vabal_s16(a, b, c);223}224 225// CHECK-LABEL: define <2 x i64> @test_vabal_s32(226// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {227// CHECK-NEXT: [[ENTRY:.*:]]228// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>229// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>230// CHECK-NEXT: [[VABD_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>231// CHECK-NEXT: [[VABD_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>232// CHECK-NEXT: [[VABD_V2_I_I:%.*]] = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> [[VABD_V_I_I]], <2 x i32> [[VABD_V1_I_I]])233// CHECK-NEXT: [[VABD_V3_I_I:%.*]] = bitcast <2 x i32> [[VABD_V2_I_I]] to <8 x i8>234// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I_I]] to <2 x i32>235// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>236// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>237// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <2 x i32> [[TMP4]] to <2 x i64>238// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[VMOVL_I]]239// CHECK-NEXT: ret <2 x i64> [[ADD_I]]240//241int64x2_t test_vabal_s32(int64x2_t a, int32x2_t b, int32x2_t c) {242 return vabal_s32(a, b, c);243}244 245// CHECK-LABEL: define <8 x i16> @test_vabal_u8(246// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {247// CHECK-NEXT: [[ENTRY:.*:]]248// CHECK-NEXT: [[VABD_V_I_I:%.*]] = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> [[B]], <8 x i8> [[C]])249// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <8 x i8> [[VABD_V_I_I]] to <8 x i16>250// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[VMOVL_I]]251// CHECK-NEXT: ret <8 x i16> [[ADD_I]]252//253uint16x8_t test_vabal_u8(uint16x8_t a, uint8x8_t b, uint8x8_t c) {254 return vabal_u8(a, b, c);255}256 257// CHECK-LABEL: define <4 x i32> @test_vabal_u16(258// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {259// CHECK-NEXT: [[ENTRY:.*:]]260// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>261// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>262// CHECK-NEXT: [[VABD_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>263// CHECK-NEXT: [[VABD_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>264// CHECK-NEXT: [[VABD_V2_I_I:%.*]] = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> [[VABD_V_I_I]], <4 x i16> [[VABD_V1_I_I]])265// CHECK-NEXT: [[VABD_V3_I_I:%.*]] = bitcast <4 x i16> [[VABD_V2_I_I]] to <8 x i8>266// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I_I]] to <4 x i16>267// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>268// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>269// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <4 x i16> [[TMP4]] to <4 x i32>270// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[VMOVL_I]]271// CHECK-NEXT: ret <4 x i32> [[ADD_I]]272//273uint32x4_t test_vabal_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c) {274 return vabal_u16(a, b, c);275}276 277// CHECK-LABEL: define <2 x i64> @test_vabal_u32(278// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {279// CHECK-NEXT: [[ENTRY:.*:]]280// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>281// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>282// CHECK-NEXT: [[VABD_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>283// CHECK-NEXT: [[VABD_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>284// CHECK-NEXT: [[VABD_V2_I_I:%.*]] = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> [[VABD_V_I_I]], <2 x i32> [[VABD_V1_I_I]])285// CHECK-NEXT: [[VABD_V3_I_I:%.*]] = bitcast <2 x i32> [[VABD_V2_I_I]] to <8 x i8>286// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I_I]] to <2 x i32>287// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>288// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>289// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <2 x i32> [[TMP4]] to <2 x i64>290// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[VMOVL_I]]291// CHECK-NEXT: ret <2 x i64> [[ADD_I]]292//293uint64x2_t test_vabal_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c) {294 return vabal_u32(a, b, c);295}296 297// CHECK-LABEL: define <8 x i8> @test_vabd_s8(298// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {299// CHECK-NEXT: [[ENTRY:.*:]]300// CHECK-NEXT: [[VABD_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])301// CHECK-NEXT: ret <8 x i8> [[VABD_V_I]]302//303int8x8_t test_vabd_s8(int8x8_t a, int8x8_t b) {304 return vabd_s8(a, b);305}306 307// CHECK-LABEL: define <4 x i16> @test_vabd_s16(308// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {309// CHECK-NEXT: [[ENTRY:.*:]]310// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>311// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>312// CHECK-NEXT: [[VABD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>313// CHECK-NEXT: [[VABD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>314// CHECK-NEXT: [[VABD_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> [[VABD_V_I]], <4 x i16> [[VABD_V1_I]])315// CHECK-NEXT: [[VABD_V3_I:%.*]] = bitcast <4 x i16> [[VABD_V2_I]] to <8 x i8>316// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I]] to <4 x i16>317// CHECK-NEXT: ret <4 x i16> [[TMP2]]318//319int16x4_t test_vabd_s16(int16x4_t a, int16x4_t b) {320 return vabd_s16(a, b);321}322 323// CHECK-LABEL: define <2 x i32> @test_vabd_s32(324// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {325// CHECK-NEXT: [[ENTRY:.*:]]326// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>327// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>328// CHECK-NEXT: [[VABD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>329// CHECK-NEXT: [[VABD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>330// CHECK-NEXT: [[VABD_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> [[VABD_V_I]], <2 x i32> [[VABD_V1_I]])331// CHECK-NEXT: [[VABD_V3_I:%.*]] = bitcast <2 x i32> [[VABD_V2_I]] to <8 x i8>332// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I]] to <2 x i32>333// CHECK-NEXT: ret <2 x i32> [[TMP2]]334//335int32x2_t test_vabd_s32(int32x2_t a, int32x2_t b) {336 return vabd_s32(a, b);337}338 339// CHECK-LABEL: define <8 x i8> @test_vabd_u8(340// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {341// CHECK-NEXT: [[ENTRY:.*:]]342// CHECK-NEXT: [[VABD_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])343// CHECK-NEXT: ret <8 x i8> [[VABD_V_I]]344//345uint8x8_t test_vabd_u8(uint8x8_t a, uint8x8_t b) {346 return vabd_u8(a, b);347}348 349// CHECK-LABEL: define <4 x i16> @test_vabd_u16(350// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {351// CHECK-NEXT: [[ENTRY:.*:]]352// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>353// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>354// CHECK-NEXT: [[VABD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>355// CHECK-NEXT: [[VABD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>356// CHECK-NEXT: [[VABD_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> [[VABD_V_I]], <4 x i16> [[VABD_V1_I]])357// CHECK-NEXT: [[VABD_V3_I:%.*]] = bitcast <4 x i16> [[VABD_V2_I]] to <8 x i8>358// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I]] to <4 x i16>359// CHECK-NEXT: ret <4 x i16> [[TMP2]]360//361uint16x4_t test_vabd_u16(uint16x4_t a, uint16x4_t b) {362 return vabd_u16(a, b);363}364 365// CHECK-LABEL: define <2 x i32> @test_vabd_u32(366// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {367// CHECK-NEXT: [[ENTRY:.*:]]368// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>369// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>370// CHECK-NEXT: [[VABD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>371// CHECK-NEXT: [[VABD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>372// CHECK-NEXT: [[VABD_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> [[VABD_V_I]], <2 x i32> [[VABD_V1_I]])373// CHECK-NEXT: [[VABD_V3_I:%.*]] = bitcast <2 x i32> [[VABD_V2_I]] to <8 x i8>374// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I]] to <2 x i32>375// CHECK-NEXT: ret <2 x i32> [[TMP2]]376//377uint32x2_t test_vabd_u32(uint32x2_t a, uint32x2_t b) {378 return vabd_u32(a, b);379}380 381// CHECK-LABEL: define <2 x float> @test_vabd_f32(382// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {383// CHECK-NEXT: [[ENTRY:.*:]]384// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>385// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>386// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>387// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>388// CHECK-NEXT: [[VABD_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>389// CHECK-NEXT: [[VABD_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>390// CHECK-NEXT: [[VABD_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float> [[VABD_V_I]], <2 x float> [[VABD_V1_I]])391// CHECK-NEXT: [[VABD_V3_I:%.*]] = bitcast <2 x float> [[VABD_V2_I]] to <8 x i8>392// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VABD_V3_I]] to <2 x i32>393// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>394// CHECK-NEXT: ret <2 x float> [[TMP5]]395//396float32x2_t test_vabd_f32(float32x2_t a, float32x2_t b) {397 return vabd_f32(a, b);398}399 400// CHECK-LABEL: define <16 x i8> @test_vabdq_s8(401// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {402// CHECK-NEXT: [[ENTRY:.*:]]403// CHECK-NEXT: [[VABDQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])404// CHECK-NEXT: ret <16 x i8> [[VABDQ_V_I]]405//406int8x16_t test_vabdq_s8(int8x16_t a, int8x16_t b) {407 return vabdq_s8(a, b);408}409 410// CHECK-LABEL: define <8 x i16> @test_vabdq_s16(411// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {412// CHECK-NEXT: [[ENTRY:.*:]]413// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>414// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>415// CHECK-NEXT: [[VABDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>416// CHECK-NEXT: [[VABDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>417// CHECK-NEXT: [[VABDQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> [[VABDQ_V_I]], <8 x i16> [[VABDQ_V1_I]])418// CHECK-NEXT: [[VABDQ_V3_I:%.*]] = bitcast <8 x i16> [[VABDQ_V2_I]] to <16 x i8>419// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VABDQ_V3_I]] to <8 x i16>420// CHECK-NEXT: ret <8 x i16> [[TMP2]]421//422int16x8_t test_vabdq_s16(int16x8_t a, int16x8_t b) {423 return vabdq_s16(a, b);424}425 426// CHECK-LABEL: define <4 x i32> @test_vabdq_s32(427// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {428// CHECK-NEXT: [[ENTRY:.*:]]429// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>430// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>431// CHECK-NEXT: [[VABDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>432// CHECK-NEXT: [[VABDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>433// CHECK-NEXT: [[VABDQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> [[VABDQ_V_I]], <4 x i32> [[VABDQ_V1_I]])434// CHECK-NEXT: [[VABDQ_V3_I:%.*]] = bitcast <4 x i32> [[VABDQ_V2_I]] to <16 x i8>435// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VABDQ_V3_I]] to <4 x i32>436// CHECK-NEXT: ret <4 x i32> [[TMP2]]437//438int32x4_t test_vabdq_s32(int32x4_t a, int32x4_t b) {439 return vabdq_s32(a, b);440}441 442// CHECK-LABEL: define <16 x i8> @test_vabdq_u8(443// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {444// CHECK-NEXT: [[ENTRY:.*:]]445// CHECK-NEXT: [[VABDQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])446// CHECK-NEXT: ret <16 x i8> [[VABDQ_V_I]]447//448uint8x16_t test_vabdq_u8(uint8x16_t a, uint8x16_t b) {449 return vabdq_u8(a, b);450}451 452// CHECK-LABEL: define <8 x i16> @test_vabdq_u16(453// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {454// CHECK-NEXT: [[ENTRY:.*:]]455// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>456// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>457// CHECK-NEXT: [[VABDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>458// CHECK-NEXT: [[VABDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>459// CHECK-NEXT: [[VABDQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> [[VABDQ_V_I]], <8 x i16> [[VABDQ_V1_I]])460// CHECK-NEXT: [[VABDQ_V3_I:%.*]] = bitcast <8 x i16> [[VABDQ_V2_I]] to <16 x i8>461// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VABDQ_V3_I]] to <8 x i16>462// CHECK-NEXT: ret <8 x i16> [[TMP2]]463//464uint16x8_t test_vabdq_u16(uint16x8_t a, uint16x8_t b) {465 return vabdq_u16(a, b);466}467 468// CHECK-LABEL: define <4 x i32> @test_vabdq_u32(469// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {470// CHECK-NEXT: [[ENTRY:.*:]]471// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>472// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>473// CHECK-NEXT: [[VABDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>474// CHECK-NEXT: [[VABDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>475// CHECK-NEXT: [[VABDQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> [[VABDQ_V_I]], <4 x i32> [[VABDQ_V1_I]])476// CHECK-NEXT: [[VABDQ_V3_I:%.*]] = bitcast <4 x i32> [[VABDQ_V2_I]] to <16 x i8>477// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VABDQ_V3_I]] to <4 x i32>478// CHECK-NEXT: ret <4 x i32> [[TMP2]]479//480uint32x4_t test_vabdq_u32(uint32x4_t a, uint32x4_t b) {481 return vabdq_u32(a, b);482}483 484// CHECK-LABEL: define <4 x float> @test_vabdq_f32(485// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {486// CHECK-NEXT: [[ENTRY:.*:]]487// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>488// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>489// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>490// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>491// CHECK-NEXT: [[VABDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>492// CHECK-NEXT: [[VABDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>493// CHECK-NEXT: [[VABDQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> [[VABDQ_V_I]], <4 x float> [[VABDQ_V1_I]])494// CHECK-NEXT: [[VABDQ_V3_I:%.*]] = bitcast <4 x float> [[VABDQ_V2_I]] to <16 x i8>495// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[VABDQ_V3_I]] to <4 x i32>496// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>497// CHECK-NEXT: ret <4 x float> [[TMP5]]498//499float32x4_t test_vabdq_f32(float32x4_t a, float32x4_t b) {500 return vabdq_f32(a, b);501}502 503// CHECK-LABEL: define <8 x i16> @test_vabdl_s8(504// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {505// CHECK-NEXT: [[ENTRY:.*:]]506// CHECK-NEXT: [[VABD_V_I_I:%.*]] = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])507// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <8 x i8> [[VABD_V_I_I]] to <8 x i16>508// CHECK-NEXT: ret <8 x i16> [[VMOVL_I]]509//510int16x8_t test_vabdl_s8(int8x8_t a, int8x8_t b) {511 return vabdl_s8(a, b);512}513 514// CHECK-LABEL: define <4 x i32> @test_vabdl_s16(515// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {516// CHECK-NEXT: [[ENTRY:.*:]]517// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>518// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>519// CHECK-NEXT: [[VABD_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>520// CHECK-NEXT: [[VABD_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>521// CHECK-NEXT: [[VABD_V2_I_I:%.*]] = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> [[VABD_V_I_I]], <4 x i16> [[VABD_V1_I_I]])522// CHECK-NEXT: [[VABD_V3_I_I:%.*]] = bitcast <4 x i16> [[VABD_V2_I_I]] to <8 x i8>523// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I_I]] to <4 x i16>524// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>525// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>526// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <4 x i16> [[TMP4]] to <4 x i32>527// CHECK-NEXT: ret <4 x i32> [[VMOVL_I]]528//529int32x4_t test_vabdl_s16(int16x4_t a, int16x4_t b) {530 return vabdl_s16(a, b);531}532 533// CHECK-LABEL: define <2 x i64> @test_vabdl_s32(534// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {535// CHECK-NEXT: [[ENTRY:.*:]]536// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>537// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>538// CHECK-NEXT: [[VABD_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>539// CHECK-NEXT: [[VABD_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>540// CHECK-NEXT: [[VABD_V2_I_I:%.*]] = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> [[VABD_V_I_I]], <2 x i32> [[VABD_V1_I_I]])541// CHECK-NEXT: [[VABD_V3_I_I:%.*]] = bitcast <2 x i32> [[VABD_V2_I_I]] to <8 x i8>542// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I_I]] to <2 x i32>543// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>544// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>545// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <2 x i32> [[TMP4]] to <2 x i64>546// CHECK-NEXT: ret <2 x i64> [[VMOVL_I]]547//548int64x2_t test_vabdl_s32(int32x2_t a, int32x2_t b) {549 return vabdl_s32(a, b);550}551 552// CHECK-LABEL: define <8 x i16> @test_vabdl_u8(553// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {554// CHECK-NEXT: [[ENTRY:.*:]]555// CHECK-NEXT: [[VABD_V_I_I:%.*]] = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])556// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <8 x i8> [[VABD_V_I_I]] to <8 x i16>557// CHECK-NEXT: ret <8 x i16> [[VMOVL_I]]558//559uint16x8_t test_vabdl_u8(uint8x8_t a, uint8x8_t b) {560 return vabdl_u8(a, b);561}562 563// CHECK-LABEL: define <4 x i32> @test_vabdl_u16(564// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {565// CHECK-NEXT: [[ENTRY:.*:]]566// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>567// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>568// CHECK-NEXT: [[VABD_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>569// CHECK-NEXT: [[VABD_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>570// CHECK-NEXT: [[VABD_V2_I_I:%.*]] = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> [[VABD_V_I_I]], <4 x i16> [[VABD_V1_I_I]])571// CHECK-NEXT: [[VABD_V3_I_I:%.*]] = bitcast <4 x i16> [[VABD_V2_I_I]] to <8 x i8>572// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I_I]] to <4 x i16>573// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>574// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>575// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <4 x i16> [[TMP4]] to <4 x i32>576// CHECK-NEXT: ret <4 x i32> [[VMOVL_I]]577//578uint32x4_t test_vabdl_u16(uint16x4_t a, uint16x4_t b) {579 return vabdl_u16(a, b);580}581 582// CHECK-LABEL: define <2 x i64> @test_vabdl_u32(583// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {584// CHECK-NEXT: [[ENTRY:.*:]]585// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>586// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>587// CHECK-NEXT: [[VABD_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>588// CHECK-NEXT: [[VABD_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>589// CHECK-NEXT: [[VABD_V2_I_I:%.*]] = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> [[VABD_V_I_I]], <2 x i32> [[VABD_V1_I_I]])590// CHECK-NEXT: [[VABD_V3_I_I:%.*]] = bitcast <2 x i32> [[VABD_V2_I_I]] to <8 x i8>591// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VABD_V3_I_I]] to <2 x i32>592// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>593// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>594// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <2 x i32> [[TMP4]] to <2 x i64>595// CHECK-NEXT: ret <2 x i64> [[VMOVL_I]]596//597uint64x2_t test_vabdl_u32(uint32x2_t a, uint32x2_t b) {598 return vabdl_u32(a, b);599}600 601// CHECK-LABEL: define <8 x i8> @test_vabs_s8(602// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {603// CHECK-NEXT: [[ENTRY:.*:]]604// CHECK-NEXT: [[VABS_I:%.*]] = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> [[A]])605// CHECK-NEXT: ret <8 x i8> [[VABS_I]]606//607int8x8_t test_vabs_s8(int8x8_t a) {608 return vabs_s8(a);609}610 611// CHECK-LABEL: define <4 x i16> @test_vabs_s16(612// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {613// CHECK-NEXT: [[ENTRY:.*:]]614// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>615// CHECK-NEXT: [[VABS_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>616// CHECK-NEXT: [[VABS1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> [[VABS_I]])617// CHECK-NEXT: ret <4 x i16> [[VABS1_I]]618//619int16x4_t test_vabs_s16(int16x4_t a) {620 return vabs_s16(a);621}622 623// CHECK-LABEL: define <2 x i32> @test_vabs_s32(624// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {625// CHECK-NEXT: [[ENTRY:.*:]]626// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>627// CHECK-NEXT: [[VABS_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>628// CHECK-NEXT: [[VABS1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> [[VABS_I]])629// CHECK-NEXT: ret <2 x i32> [[VABS1_I]]630//631int32x2_t test_vabs_s32(int32x2_t a) {632 return vabs_s32(a);633}634 635// CHECK-LABEL: define <2 x float> @test_vabs_f32(636// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {637// CHECK-NEXT: [[ENTRY:.*:]]638// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>639// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>640// CHECK-NEXT: [[VABS_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>641// CHECK-NEXT: [[VABS1_I:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[VABS_I]])642// CHECK-NEXT: ret <2 x float> [[VABS1_I]]643//644float32x2_t test_vabs_f32(float32x2_t a) {645 return vabs_f32(a);646}647 648// CHECK-LABEL: define <16 x i8> @test_vabsq_s8(649// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {650// CHECK-NEXT: [[ENTRY:.*:]]651// CHECK-NEXT: [[VABS_I:%.*]] = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> [[A]])652// CHECK-NEXT: ret <16 x i8> [[VABS_I]]653//654int8x16_t test_vabsq_s8(int8x16_t a) {655 return vabsq_s8(a);656}657 658// CHECK-LABEL: define <8 x i16> @test_vabsq_s16(659// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {660// CHECK-NEXT: [[ENTRY:.*:]]661// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>662// CHECK-NEXT: [[VABS_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>663// CHECK-NEXT: [[VABS1_I:%.*]] = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> [[VABS_I]])664// CHECK-NEXT: ret <8 x i16> [[VABS1_I]]665//666int16x8_t test_vabsq_s16(int16x8_t a) {667 return vabsq_s16(a);668}669 670// CHECK-LABEL: define <4 x i32> @test_vabsq_s32(671// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {672// CHECK-NEXT: [[ENTRY:.*:]]673// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>674// CHECK-NEXT: [[VABS_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>675// CHECK-NEXT: [[VABS1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> [[VABS_I]])676// CHECK-NEXT: ret <4 x i32> [[VABS1_I]]677//678int32x4_t test_vabsq_s32(int32x4_t a) {679 return vabsq_s32(a);680}681 682// CHECK-LABEL: define <4 x float> @test_vabsq_f32(683// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {684// CHECK-NEXT: [[ENTRY:.*:]]685// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>686// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>687// CHECK-NEXT: [[VABS_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>688// CHECK-NEXT: [[VABS1_I:%.*]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> [[VABS_I]])689// CHECK-NEXT: ret <4 x float> [[VABS1_I]]690//691float32x4_t test_vabsq_f32(float32x4_t a) {692 return vabsq_f32(a);693}694 695// CHECK-LABEL: define <8 x i8> @test_vadd_s8(696// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {697// CHECK-NEXT: [[ENTRY:.*:]]698// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[B]]699// CHECK-NEXT: ret <8 x i8> [[ADD_I]]700//701int8x8_t test_vadd_s8(int8x8_t a, int8x8_t b) {702 return vadd_s8(a, b);703}704 705// CHECK-LABEL: define <4 x i16> @test_vadd_s16(706// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {707// CHECK-NEXT: [[ENTRY:.*:]]708// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[B]]709// CHECK-NEXT: ret <4 x i16> [[ADD_I]]710//711int16x4_t test_vadd_s16(int16x4_t a, int16x4_t b) {712 return vadd_s16(a, b);713}714 715// CHECK-LABEL: define <2 x i32> @test_vadd_s32(716// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {717// CHECK-NEXT: [[ENTRY:.*:]]718// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[B]]719// CHECK-NEXT: ret <2 x i32> [[ADD_I]]720//721int32x2_t test_vadd_s32(int32x2_t a, int32x2_t b) {722 return vadd_s32(a, b);723}724 725// CHECK-LABEL: define <1 x i64> @test_vadd_s64(726// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {727// CHECK-NEXT: [[ENTRY:.*:]]728// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[A]], [[B]]729// CHECK-NEXT: ret <1 x i64> [[ADD_I]]730//731int64x1_t test_vadd_s64(int64x1_t a, int64x1_t b) {732 return vadd_s64(a, b);733}734 735// CHECK-LABEL: define <2 x float> @test_vadd_f32(736// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {737// CHECK-NEXT: [[ENTRY:.*:]]738// CHECK-NEXT: [[ADD_I:%.*]] = fadd <2 x float> [[A]], [[B]]739// CHECK-NEXT: ret <2 x float> [[ADD_I]]740//741float32x2_t test_vadd_f32(float32x2_t a, float32x2_t b) {742 return vadd_f32(a, b);743}744 745// CHECK-LABEL: define <8 x i8> @test_vadd_u8(746// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {747// CHECK-NEXT: [[ENTRY:.*:]]748// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[B]]749// CHECK-NEXT: ret <8 x i8> [[ADD_I]]750//751uint8x8_t test_vadd_u8(uint8x8_t a, uint8x8_t b) {752 return vadd_u8(a, b);753}754 755// CHECK-LABEL: define <4 x i16> @test_vadd_u16(756// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {757// CHECK-NEXT: [[ENTRY:.*:]]758// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[B]]759// CHECK-NEXT: ret <4 x i16> [[ADD_I]]760//761uint16x4_t test_vadd_u16(uint16x4_t a, uint16x4_t b) {762 return vadd_u16(a, b);763}764 765// CHECK-LABEL: define <2 x i32> @test_vadd_u32(766// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {767// CHECK-NEXT: [[ENTRY:.*:]]768// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[B]]769// CHECK-NEXT: ret <2 x i32> [[ADD_I]]770//771uint32x2_t test_vadd_u32(uint32x2_t a, uint32x2_t b) {772 return vadd_u32(a, b);773}774 775// CHECK-LABEL: define <1 x i64> @test_vadd_u64(776// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {777// CHECK-NEXT: [[ENTRY:.*:]]778// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[A]], [[B]]779// CHECK-NEXT: ret <1 x i64> [[ADD_I]]780//781uint64x1_t test_vadd_u64(uint64x1_t a, uint64x1_t b) {782 return vadd_u64(a, b);783}784 785// CHECK-LABEL: define <16 x i8> @test_vaddq_s8(786// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {787// CHECK-NEXT: [[ENTRY:.*:]]788// CHECK-NEXT: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[B]]789// CHECK-NEXT: ret <16 x i8> [[ADD_I]]790//791int8x16_t test_vaddq_s8(int8x16_t a, int8x16_t b) {792 return vaddq_s8(a, b);793}794 795// CHECK-LABEL: define <8 x i16> @test_vaddq_s16(796// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {797// CHECK-NEXT: [[ENTRY:.*:]]798// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[B]]799// CHECK-NEXT: ret <8 x i16> [[ADD_I]]800//801int16x8_t test_vaddq_s16(int16x8_t a, int16x8_t b) {802 return vaddq_s16(a, b);803}804 805// CHECK-LABEL: define <4 x i32> @test_vaddq_s32(806// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {807// CHECK-NEXT: [[ENTRY:.*:]]808// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[B]]809// CHECK-NEXT: ret <4 x i32> [[ADD_I]]810//811int32x4_t test_vaddq_s32(int32x4_t a, int32x4_t b) {812 return vaddq_s32(a, b);813}814 815// CHECK-LABEL: define <2 x i64> @test_vaddq_s64(816// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {817// CHECK-NEXT: [[ENTRY:.*:]]818// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[B]]819// CHECK-NEXT: ret <2 x i64> [[ADD_I]]820//821int64x2_t test_vaddq_s64(int64x2_t a, int64x2_t b) {822 return vaddq_s64(a, b);823}824 825// CHECK-LABEL: define <4 x float> @test_vaddq_f32(826// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {827// CHECK-NEXT: [[ENTRY:.*:]]828// CHECK-NEXT: [[ADD_I:%.*]] = fadd <4 x float> [[A]], [[B]]829// CHECK-NEXT: ret <4 x float> [[ADD_I]]830//831float32x4_t test_vaddq_f32(float32x4_t a, float32x4_t b) {832 return vaddq_f32(a, b);833}834 835// CHECK-LABEL: define <16 x i8> @test_vaddq_u8(836// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {837// CHECK-NEXT: [[ENTRY:.*:]]838// CHECK-NEXT: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[B]]839// CHECK-NEXT: ret <16 x i8> [[ADD_I]]840//841uint8x16_t test_vaddq_u8(uint8x16_t a, uint8x16_t b) {842 return vaddq_u8(a, b);843}844 845// CHECK-LABEL: define <8 x i16> @test_vaddq_u16(846// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {847// CHECK-NEXT: [[ENTRY:.*:]]848// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[B]]849// CHECK-NEXT: ret <8 x i16> [[ADD_I]]850//851uint16x8_t test_vaddq_u16(uint16x8_t a, uint16x8_t b) {852 return vaddq_u16(a, b);853}854 855// CHECK-LABEL: define <4 x i32> @test_vaddq_u32(856// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {857// CHECK-NEXT: [[ENTRY:.*:]]858// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[B]]859// CHECK-NEXT: ret <4 x i32> [[ADD_I]]860//861uint32x4_t test_vaddq_u32(uint32x4_t a, uint32x4_t b) {862 return vaddq_u32(a, b);863}864 865// CHECK-LABEL: define <2 x i64> @test_vaddq_u64(866// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {867// CHECK-NEXT: [[ENTRY:.*:]]868// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[B]]869// CHECK-NEXT: ret <2 x i64> [[ADD_I]]870//871uint64x2_t test_vaddq_u64(uint64x2_t a, uint64x2_t b) {872 return vaddq_u64(a, b);873}874 875// CHECK-LABEL: define <8 x i8> @test_vaddhn_s16(876// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {877// CHECK-NEXT: [[ENTRY:.*:]]878// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>879// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>880// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>881// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>882// CHECK-NEXT: [[VADDHN_I:%.*]] = add <8 x i16> [[TMP2]], [[TMP3]]883// CHECK-NEXT: [[VADDHN1_I:%.*]] = lshr <8 x i16> [[VADDHN_I]], splat (i16 8)884// CHECK-NEXT: [[VADDHN2_I:%.*]] = trunc <8 x i16> [[VADDHN1_I]] to <8 x i8>885// CHECK-NEXT: ret <8 x i8> [[VADDHN2_I]]886//887int8x8_t test_vaddhn_s16(int16x8_t a, int16x8_t b) {888 return vaddhn_s16(a, b);889}890 891// CHECK-LABEL: define <4 x i16> @test_vaddhn_s32(892// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {893// CHECK-NEXT: [[ENTRY:.*:]]894// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>895// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>896// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>897// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>898// CHECK-NEXT: [[VADDHN_I:%.*]] = add <4 x i32> [[TMP2]], [[TMP3]]899// CHECK-NEXT: [[VADDHN1_I:%.*]] = lshr <4 x i32> [[VADDHN_I]], splat (i32 16)900// CHECK-NEXT: [[VADDHN2_I:%.*]] = trunc <4 x i32> [[VADDHN1_I]] to <4 x i16>901// CHECK-NEXT: ret <4 x i16> [[VADDHN2_I]]902//903int16x4_t test_vaddhn_s32(int32x4_t a, int32x4_t b) {904 return vaddhn_s32(a, b);905}906 907// CHECK-LABEL: define <2 x i32> @test_vaddhn_s64(908// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {909// CHECK-NEXT: [[ENTRY:.*:]]910// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>911// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>912// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>913// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>914// CHECK-NEXT: [[VADDHN_I:%.*]] = add <2 x i64> [[TMP2]], [[TMP3]]915// CHECK-NEXT: [[VADDHN1_I:%.*]] = lshr <2 x i64> [[VADDHN_I]], splat (i64 32)916// CHECK-NEXT: [[VADDHN2_I:%.*]] = trunc <2 x i64> [[VADDHN1_I]] to <2 x i32>917// CHECK-NEXT: ret <2 x i32> [[VADDHN2_I]]918//919int32x2_t test_vaddhn_s64(int64x2_t a, int64x2_t b) {920 return vaddhn_s64(a, b);921}922 923// CHECK-LABEL: define <8 x i8> @test_vaddhn_u16(924// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {925// CHECK-NEXT: [[ENTRY:.*:]]926// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>927// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>928// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>929// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>930// CHECK-NEXT: [[VADDHN_I:%.*]] = add <8 x i16> [[TMP2]], [[TMP3]]931// CHECK-NEXT: [[VADDHN1_I:%.*]] = lshr <8 x i16> [[VADDHN_I]], splat (i16 8)932// CHECK-NEXT: [[VADDHN2_I:%.*]] = trunc <8 x i16> [[VADDHN1_I]] to <8 x i8>933// CHECK-NEXT: ret <8 x i8> [[VADDHN2_I]]934//935uint8x8_t test_vaddhn_u16(uint16x8_t a, uint16x8_t b) {936 return vaddhn_u16(a, b);937}938 939// CHECK-LABEL: define <4 x i16> @test_vaddhn_u32(940// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {941// CHECK-NEXT: [[ENTRY:.*:]]942// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>943// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>944// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>945// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>946// CHECK-NEXT: [[VADDHN_I:%.*]] = add <4 x i32> [[TMP2]], [[TMP3]]947// CHECK-NEXT: [[VADDHN1_I:%.*]] = lshr <4 x i32> [[VADDHN_I]], splat (i32 16)948// CHECK-NEXT: [[VADDHN2_I:%.*]] = trunc <4 x i32> [[VADDHN1_I]] to <4 x i16>949// CHECK-NEXT: ret <4 x i16> [[VADDHN2_I]]950//951uint16x4_t test_vaddhn_u32(uint32x4_t a, uint32x4_t b) {952 return vaddhn_u32(a, b);953}954 955// CHECK-LABEL: define <2 x i32> @test_vaddhn_u64(956// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {957// CHECK-NEXT: [[ENTRY:.*:]]958// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>959// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>960// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>961// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>962// CHECK-NEXT: [[VADDHN_I:%.*]] = add <2 x i64> [[TMP2]], [[TMP3]]963// CHECK-NEXT: [[VADDHN1_I:%.*]] = lshr <2 x i64> [[VADDHN_I]], splat (i64 32)964// CHECK-NEXT: [[VADDHN2_I:%.*]] = trunc <2 x i64> [[VADDHN1_I]] to <2 x i32>965// CHECK-NEXT: ret <2 x i32> [[VADDHN2_I]]966//967uint32x2_t test_vaddhn_u64(uint64x2_t a, uint64x2_t b) {968 return vaddhn_u64(a, b);969}970 971// CHECK-LABEL: define <8 x i16> @test_vaddl_s8(972// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {973// CHECK-NEXT: [[ENTRY:.*:]]974// CHECK-NEXT: [[VMOVL_I6:%.*]] = sext <8 x i8> [[A]] to <8 x i16>975// CHECK-NEXT: [[VMOVL_I:%.*]] = sext <8 x i8> [[B]] to <8 x i16>976// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[VMOVL_I6]], [[VMOVL_I]]977// CHECK-NEXT: ret <8 x i16> [[ADD_I]]978//979int16x8_t test_vaddl_s8(int8x8_t a, int8x8_t b) {980 return vaddl_s8(a, b);981}982 983// CHECK-LABEL: define <4 x i32> @test_vaddl_s16(984// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {985// CHECK-NEXT: [[ENTRY:.*:]]986// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>987// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>988// CHECK-NEXT: [[VMOVL_I6:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>989// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>990// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>991// CHECK-NEXT: [[VMOVL_I:%.*]] = sext <4 x i16> [[TMP3]] to <4 x i32>992// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[VMOVL_I6]], [[VMOVL_I]]993// CHECK-NEXT: ret <4 x i32> [[ADD_I]]994//995int32x4_t test_vaddl_s16(int16x4_t a, int16x4_t b) {996 return vaddl_s16(a, b);997}998 999// CHECK-LABEL: define <2 x i64> @test_vaddl_s32(1000// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1001// CHECK-NEXT: [[ENTRY:.*:]]1002// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>1003// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>1004// CHECK-NEXT: [[VMOVL_I6:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>1005// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>1006// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>1007// CHECK-NEXT: [[VMOVL_I:%.*]] = sext <2 x i32> [[TMP3]] to <2 x i64>1008// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[VMOVL_I6]], [[VMOVL_I]]1009// CHECK-NEXT: ret <2 x i64> [[ADD_I]]1010//1011int64x2_t test_vaddl_s32(int32x2_t a, int32x2_t b) {1012 return vaddl_s32(a, b);1013}1014 1015// CHECK-LABEL: define <8 x i16> @test_vaddl_u8(1016// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1017// CHECK-NEXT: [[ENTRY:.*:]]1018// CHECK-NEXT: [[VMOVL_I6:%.*]] = zext <8 x i8> [[A]] to <8 x i16>1019// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <8 x i8> [[B]] to <8 x i16>1020// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[VMOVL_I6]], [[VMOVL_I]]1021// CHECK-NEXT: ret <8 x i16> [[ADD_I]]1022//1023uint16x8_t test_vaddl_u8(uint8x8_t a, uint8x8_t b) {1024 return vaddl_u8(a, b);1025}1026 1027// CHECK-LABEL: define <4 x i32> @test_vaddl_u16(1028// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1029// CHECK-NEXT: [[ENTRY:.*:]]1030// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>1031// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>1032// CHECK-NEXT: [[VMOVL_I6:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>1033// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>1034// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>1035// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <4 x i16> [[TMP3]] to <4 x i32>1036// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[VMOVL_I6]], [[VMOVL_I]]1037// CHECK-NEXT: ret <4 x i32> [[ADD_I]]1038//1039uint32x4_t test_vaddl_u16(uint16x4_t a, uint16x4_t b) {1040 return vaddl_u16(a, b);1041}1042 1043// CHECK-LABEL: define <2 x i64> @test_vaddl_u32(1044// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1045// CHECK-NEXT: [[ENTRY:.*:]]1046// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>1047// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>1048// CHECK-NEXT: [[VMOVL_I6:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>1049// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>1050// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>1051// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <2 x i32> [[TMP3]] to <2 x i64>1052// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[VMOVL_I6]], [[VMOVL_I]]1053// CHECK-NEXT: ret <2 x i64> [[ADD_I]]1054//1055uint64x2_t test_vaddl_u32(uint32x2_t a, uint32x2_t b) {1056 return vaddl_u32(a, b);1057}1058 1059// CHECK-LABEL: define <8 x i16> @test_vaddw_s8(1060// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1061// CHECK-NEXT: [[ENTRY:.*:]]1062// CHECK-NEXT: [[VMOVL_I:%.*]] = sext <8 x i8> [[B]] to <8 x i16>1063// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[VMOVL_I]]1064// CHECK-NEXT: ret <8 x i16> [[ADD_I]]1065//1066int16x8_t test_vaddw_s8(int16x8_t a, int8x8_t b) {1067 return vaddw_s8(a, b);1068}1069 1070// CHECK-LABEL: define <4 x i32> @test_vaddw_s16(1071// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1072// CHECK-NEXT: [[ENTRY:.*:]]1073// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>1074// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>1075// CHECK-NEXT: [[VMOVL_I:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>1076// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[VMOVL_I]]1077// CHECK-NEXT: ret <4 x i32> [[ADD_I]]1078//1079int32x4_t test_vaddw_s16(int32x4_t a, int16x4_t b) {1080 return vaddw_s16(a, b);1081}1082 1083// CHECK-LABEL: define <2 x i64> @test_vaddw_s32(1084// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1085// CHECK-NEXT: [[ENTRY:.*:]]1086// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>1087// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>1088// CHECK-NEXT: [[VMOVL_I:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>1089// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[VMOVL_I]]1090// CHECK-NEXT: ret <2 x i64> [[ADD_I]]1091//1092int64x2_t test_vaddw_s32(int64x2_t a, int32x2_t b) {1093 return vaddw_s32(a, b);1094}1095 1096// CHECK-LABEL: define <8 x i16> @test_vaddw_u8(1097// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1098// CHECK-NEXT: [[ENTRY:.*:]]1099// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <8 x i8> [[B]] to <8 x i16>1100// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[VMOVL_I]]1101// CHECK-NEXT: ret <8 x i16> [[ADD_I]]1102//1103uint16x8_t test_vaddw_u8(uint16x8_t a, uint8x8_t b) {1104 return vaddw_u8(a, b);1105}1106 1107// CHECK-LABEL: define <4 x i32> @test_vaddw_u16(1108// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1109// CHECK-NEXT: [[ENTRY:.*:]]1110// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>1111// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>1112// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>1113// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[VMOVL_I]]1114// CHECK-NEXT: ret <4 x i32> [[ADD_I]]1115//1116uint32x4_t test_vaddw_u16(uint32x4_t a, uint16x4_t b) {1117 return vaddw_u16(a, b);1118}1119 1120// CHECK-LABEL: define <2 x i64> @test_vaddw_u32(1121// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1122// CHECK-NEXT: [[ENTRY:.*:]]1123// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>1124// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>1125// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>1126// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[VMOVL_I]]1127// CHECK-NEXT: ret <2 x i64> [[ADD_I]]1128//1129uint64x2_t test_vaddw_u32(uint64x2_t a, uint32x2_t b) {1130 return vaddw_u32(a, b);1131}1132 1133// CHECK-LABEL: define <8 x i8> @test_vand_s8(1134// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1135// CHECK-NEXT: [[ENTRY:.*:]]1136// CHECK-NEXT: [[AND_I:%.*]] = and <8 x i8> [[A]], [[B]]1137// CHECK-NEXT: ret <8 x i8> [[AND_I]]1138//1139int8x8_t test_vand_s8(int8x8_t a, int8x8_t b) {1140 return vand_s8(a, b);1141}1142 1143// CHECK-LABEL: define <4 x i16> @test_vand_s16(1144// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1145// CHECK-NEXT: [[ENTRY:.*:]]1146// CHECK-NEXT: [[AND_I:%.*]] = and <4 x i16> [[A]], [[B]]1147// CHECK-NEXT: ret <4 x i16> [[AND_I]]1148//1149int16x4_t test_vand_s16(int16x4_t a, int16x4_t b) {1150 return vand_s16(a, b);1151}1152 1153// CHECK-LABEL: define <2 x i32> @test_vand_s32(1154// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1155// CHECK-NEXT: [[ENTRY:.*:]]1156// CHECK-NEXT: [[AND_I:%.*]] = and <2 x i32> [[A]], [[B]]1157// CHECK-NEXT: ret <2 x i32> [[AND_I]]1158//1159int32x2_t test_vand_s32(int32x2_t a, int32x2_t b) {1160 return vand_s32(a, b);1161}1162 1163// CHECK-LABEL: define <1 x i64> @test_vand_s64(1164// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {1165// CHECK-NEXT: [[ENTRY:.*:]]1166// CHECK-NEXT: [[AND_I:%.*]] = and <1 x i64> [[A]], [[B]]1167// CHECK-NEXT: ret <1 x i64> [[AND_I]]1168//1169int64x1_t test_vand_s64(int64x1_t a, int64x1_t b) {1170 return vand_s64(a, b);1171}1172 1173// CHECK-LABEL: define <8 x i8> @test_vand_u8(1174// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1175// CHECK-NEXT: [[ENTRY:.*:]]1176// CHECK-NEXT: [[AND_I:%.*]] = and <8 x i8> [[A]], [[B]]1177// CHECK-NEXT: ret <8 x i8> [[AND_I]]1178//1179uint8x8_t test_vand_u8(uint8x8_t a, uint8x8_t b) {1180 return vand_u8(a, b);1181}1182 1183// CHECK-LABEL: define <4 x i16> @test_vand_u16(1184// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1185// CHECK-NEXT: [[ENTRY:.*:]]1186// CHECK-NEXT: [[AND_I:%.*]] = and <4 x i16> [[A]], [[B]]1187// CHECK-NEXT: ret <4 x i16> [[AND_I]]1188//1189uint16x4_t test_vand_u16(uint16x4_t a, uint16x4_t b) {1190 return vand_u16(a, b);1191}1192 1193// CHECK-LABEL: define <2 x i32> @test_vand_u32(1194// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1195// CHECK-NEXT: [[ENTRY:.*:]]1196// CHECK-NEXT: [[AND_I:%.*]] = and <2 x i32> [[A]], [[B]]1197// CHECK-NEXT: ret <2 x i32> [[AND_I]]1198//1199uint32x2_t test_vand_u32(uint32x2_t a, uint32x2_t b) {1200 return vand_u32(a, b);1201}1202 1203// CHECK-LABEL: define <1 x i64> @test_vand_u64(1204// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {1205// CHECK-NEXT: [[ENTRY:.*:]]1206// CHECK-NEXT: [[AND_I:%.*]] = and <1 x i64> [[A]], [[B]]1207// CHECK-NEXT: ret <1 x i64> [[AND_I]]1208//1209uint64x1_t test_vand_u64(uint64x1_t a, uint64x1_t b) {1210 return vand_u64(a, b);1211}1212 1213// CHECK-LABEL: define <16 x i8> @test_vandq_s8(1214// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1215// CHECK-NEXT: [[ENTRY:.*:]]1216// CHECK-NEXT: [[AND_I:%.*]] = and <16 x i8> [[A]], [[B]]1217// CHECK-NEXT: ret <16 x i8> [[AND_I]]1218//1219int8x16_t test_vandq_s8(int8x16_t a, int8x16_t b) {1220 return vandq_s8(a, b);1221}1222 1223// CHECK-LABEL: define <8 x i16> @test_vandq_s16(1224// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1225// CHECK-NEXT: [[ENTRY:.*:]]1226// CHECK-NEXT: [[AND_I:%.*]] = and <8 x i16> [[A]], [[B]]1227// CHECK-NEXT: ret <8 x i16> [[AND_I]]1228//1229int16x8_t test_vandq_s16(int16x8_t a, int16x8_t b) {1230 return vandq_s16(a, b);1231}1232 1233// CHECK-LABEL: define <4 x i32> @test_vandq_s32(1234// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1235// CHECK-NEXT: [[ENTRY:.*:]]1236// CHECK-NEXT: [[AND_I:%.*]] = and <4 x i32> [[A]], [[B]]1237// CHECK-NEXT: ret <4 x i32> [[AND_I]]1238//1239int32x4_t test_vandq_s32(int32x4_t a, int32x4_t b) {1240 return vandq_s32(a, b);1241}1242 1243// CHECK-LABEL: define <2 x i64> @test_vandq_s64(1244// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {1245// CHECK-NEXT: [[ENTRY:.*:]]1246// CHECK-NEXT: [[AND_I:%.*]] = and <2 x i64> [[A]], [[B]]1247// CHECK-NEXT: ret <2 x i64> [[AND_I]]1248//1249int64x2_t test_vandq_s64(int64x2_t a, int64x2_t b) {1250 return vandq_s64(a, b);1251}1252 1253// CHECK-LABEL: define <16 x i8> @test_vandq_u8(1254// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1255// CHECK-NEXT: [[ENTRY:.*:]]1256// CHECK-NEXT: [[AND_I:%.*]] = and <16 x i8> [[A]], [[B]]1257// CHECK-NEXT: ret <16 x i8> [[AND_I]]1258//1259uint8x16_t test_vandq_u8(uint8x16_t a, uint8x16_t b) {1260 return vandq_u8(a, b);1261}1262 1263// CHECK-LABEL: define <8 x i16> @test_vandq_u16(1264// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1265// CHECK-NEXT: [[ENTRY:.*:]]1266// CHECK-NEXT: [[AND_I:%.*]] = and <8 x i16> [[A]], [[B]]1267// CHECK-NEXT: ret <8 x i16> [[AND_I]]1268//1269uint16x8_t test_vandq_u16(uint16x8_t a, uint16x8_t b) {1270 return vandq_u16(a, b);1271}1272 1273// CHECK-LABEL: define <4 x i32> @test_vandq_u32(1274// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1275// CHECK-NEXT: [[ENTRY:.*:]]1276// CHECK-NEXT: [[AND_I:%.*]] = and <4 x i32> [[A]], [[B]]1277// CHECK-NEXT: ret <4 x i32> [[AND_I]]1278//1279uint32x4_t test_vandq_u32(uint32x4_t a, uint32x4_t b) {1280 return vandq_u32(a, b);1281}1282 1283// CHECK-LABEL: define <2 x i64> @test_vandq_u64(1284// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {1285// CHECK-NEXT: [[ENTRY:.*:]]1286// CHECK-NEXT: [[AND_I:%.*]] = and <2 x i64> [[A]], [[B]]1287// CHECK-NEXT: ret <2 x i64> [[AND_I]]1288//1289uint64x2_t test_vandq_u64(uint64x2_t a, uint64x2_t b) {1290 return vandq_u64(a, b);1291}1292 1293// CHECK-LABEL: define <8 x i8> @test_vbic_s8(1294// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1295// CHECK-NEXT: [[ENTRY:.*:]]1296// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[B]], splat (i8 -1)1297// CHECK-NEXT: [[AND_I:%.*]] = and <8 x i8> [[A]], [[NOT_I]]1298// CHECK-NEXT: ret <8 x i8> [[AND_I]]1299//1300int8x8_t test_vbic_s8(int8x8_t a, int8x8_t b) {1301 return vbic_s8(a, b);1302}1303 1304// CHECK-LABEL: define <4 x i16> @test_vbic_s16(1305// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1306// CHECK-NEXT: [[ENTRY:.*:]]1307// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[B]], splat (i16 -1)1308// CHECK-NEXT: [[AND_I:%.*]] = and <4 x i16> [[A]], [[NOT_I]]1309// CHECK-NEXT: ret <4 x i16> [[AND_I]]1310//1311int16x4_t test_vbic_s16(int16x4_t a, int16x4_t b) {1312 return vbic_s16(a, b);1313}1314 1315// CHECK-LABEL: define <2 x i32> @test_vbic_s32(1316// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1317// CHECK-NEXT: [[ENTRY:.*:]]1318// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[B]], splat (i32 -1)1319// CHECK-NEXT: [[AND_I:%.*]] = and <2 x i32> [[A]], [[NOT_I]]1320// CHECK-NEXT: ret <2 x i32> [[AND_I]]1321//1322int32x2_t test_vbic_s32(int32x2_t a, int32x2_t b) {1323 return vbic_s32(a, b);1324}1325 1326// CHECK-LABEL: define <1 x i64> @test_vbic_s64(1327// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {1328// CHECK-NEXT: [[ENTRY:.*:]]1329// CHECK-NEXT: [[NOT_I:%.*]] = xor <1 x i64> [[B]], splat (i64 -1)1330// CHECK-NEXT: [[AND_I:%.*]] = and <1 x i64> [[A]], [[NOT_I]]1331// CHECK-NEXT: ret <1 x i64> [[AND_I]]1332//1333int64x1_t test_vbic_s64(int64x1_t a, int64x1_t b) {1334 return vbic_s64(a, b);1335}1336 1337// CHECK-LABEL: define <8 x i8> @test_vbic_u8(1338// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1339// CHECK-NEXT: [[ENTRY:.*:]]1340// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[B]], splat (i8 -1)1341// CHECK-NEXT: [[AND_I:%.*]] = and <8 x i8> [[A]], [[NOT_I]]1342// CHECK-NEXT: ret <8 x i8> [[AND_I]]1343//1344uint8x8_t test_vbic_u8(uint8x8_t a, uint8x8_t b) {1345 return vbic_u8(a, b);1346}1347 1348// CHECK-LABEL: define <4 x i16> @test_vbic_u16(1349// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1350// CHECK-NEXT: [[ENTRY:.*:]]1351// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[B]], splat (i16 -1)1352// CHECK-NEXT: [[AND_I:%.*]] = and <4 x i16> [[A]], [[NOT_I]]1353// CHECK-NEXT: ret <4 x i16> [[AND_I]]1354//1355uint16x4_t test_vbic_u16(uint16x4_t a, uint16x4_t b) {1356 return vbic_u16(a, b);1357}1358 1359// CHECK-LABEL: define <2 x i32> @test_vbic_u32(1360// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1361// CHECK-NEXT: [[ENTRY:.*:]]1362// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[B]], splat (i32 -1)1363// CHECK-NEXT: [[AND_I:%.*]] = and <2 x i32> [[A]], [[NOT_I]]1364// CHECK-NEXT: ret <2 x i32> [[AND_I]]1365//1366uint32x2_t test_vbic_u32(uint32x2_t a, uint32x2_t b) {1367 return vbic_u32(a, b);1368}1369 1370// CHECK-LABEL: define <1 x i64> @test_vbic_u64(1371// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {1372// CHECK-NEXT: [[ENTRY:.*:]]1373// CHECK-NEXT: [[NOT_I:%.*]] = xor <1 x i64> [[B]], splat (i64 -1)1374// CHECK-NEXT: [[AND_I:%.*]] = and <1 x i64> [[A]], [[NOT_I]]1375// CHECK-NEXT: ret <1 x i64> [[AND_I]]1376//1377uint64x1_t test_vbic_u64(uint64x1_t a, uint64x1_t b) {1378 return vbic_u64(a, b);1379}1380 1381// CHECK-LABEL: define <16 x i8> @test_vbicq_s8(1382// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1383// CHECK-NEXT: [[ENTRY:.*:]]1384// CHECK-NEXT: [[NOT_I:%.*]] = xor <16 x i8> [[B]], splat (i8 -1)1385// CHECK-NEXT: [[AND_I:%.*]] = and <16 x i8> [[A]], [[NOT_I]]1386// CHECK-NEXT: ret <16 x i8> [[AND_I]]1387//1388int8x16_t test_vbicq_s8(int8x16_t a, int8x16_t b) {1389 return vbicq_s8(a, b);1390}1391 1392// CHECK-LABEL: define <8 x i16> @test_vbicq_s16(1393// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1394// CHECK-NEXT: [[ENTRY:.*:]]1395// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i16> [[B]], splat (i16 -1)1396// CHECK-NEXT: [[AND_I:%.*]] = and <8 x i16> [[A]], [[NOT_I]]1397// CHECK-NEXT: ret <8 x i16> [[AND_I]]1398//1399int16x8_t test_vbicq_s16(int16x8_t a, int16x8_t b) {1400 return vbicq_s16(a, b);1401}1402 1403// CHECK-LABEL: define <4 x i32> @test_vbicq_s32(1404// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1405// CHECK-NEXT: [[ENTRY:.*:]]1406// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i32> [[B]], splat (i32 -1)1407// CHECK-NEXT: [[AND_I:%.*]] = and <4 x i32> [[A]], [[NOT_I]]1408// CHECK-NEXT: ret <4 x i32> [[AND_I]]1409//1410int32x4_t test_vbicq_s32(int32x4_t a, int32x4_t b) {1411 return vbicq_s32(a, b);1412}1413 1414// CHECK-LABEL: define <2 x i64> @test_vbicq_s64(1415// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {1416// CHECK-NEXT: [[ENTRY:.*:]]1417// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i64> [[B]], splat (i64 -1)1418// CHECK-NEXT: [[AND_I:%.*]] = and <2 x i64> [[A]], [[NOT_I]]1419// CHECK-NEXT: ret <2 x i64> [[AND_I]]1420//1421int64x2_t test_vbicq_s64(int64x2_t a, int64x2_t b) {1422 return vbicq_s64(a, b);1423}1424 1425// CHECK-LABEL: define <16 x i8> @test_vbicq_u8(1426// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1427// CHECK-NEXT: [[ENTRY:.*:]]1428// CHECK-NEXT: [[NOT_I:%.*]] = xor <16 x i8> [[B]], splat (i8 -1)1429// CHECK-NEXT: [[AND_I:%.*]] = and <16 x i8> [[A]], [[NOT_I]]1430// CHECK-NEXT: ret <16 x i8> [[AND_I]]1431//1432uint8x16_t test_vbicq_u8(uint8x16_t a, uint8x16_t b) {1433 return vbicq_u8(a, b);1434}1435 1436// CHECK-LABEL: define <8 x i16> @test_vbicq_u16(1437// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1438// CHECK-NEXT: [[ENTRY:.*:]]1439// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i16> [[B]], splat (i16 -1)1440// CHECK-NEXT: [[AND_I:%.*]] = and <8 x i16> [[A]], [[NOT_I]]1441// CHECK-NEXT: ret <8 x i16> [[AND_I]]1442//1443uint16x8_t test_vbicq_u16(uint16x8_t a, uint16x8_t b) {1444 return vbicq_u16(a, b);1445}1446 1447// CHECK-LABEL: define <4 x i32> @test_vbicq_u32(1448// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1449// CHECK-NEXT: [[ENTRY:.*:]]1450// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i32> [[B]], splat (i32 -1)1451// CHECK-NEXT: [[AND_I:%.*]] = and <4 x i32> [[A]], [[NOT_I]]1452// CHECK-NEXT: ret <4 x i32> [[AND_I]]1453//1454uint32x4_t test_vbicq_u32(uint32x4_t a, uint32x4_t b) {1455 return vbicq_u32(a, b);1456}1457 1458// CHECK-LABEL: define <2 x i64> @test_vbicq_u64(1459// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {1460// CHECK-NEXT: [[ENTRY:.*:]]1461// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i64> [[B]], splat (i64 -1)1462// CHECK-NEXT: [[AND_I:%.*]] = and <2 x i64> [[A]], [[NOT_I]]1463// CHECK-NEXT: ret <2 x i64> [[AND_I]]1464//1465uint64x2_t test_vbicq_u64(uint64x2_t a, uint64x2_t b) {1466 return vbicq_u64(a, b);1467}1468 1469// CHECK-LABEL: define <8 x i8> @test_vbsl_s8(1470// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {1471// CHECK-NEXT: [[ENTRY:.*:]]1472// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]], <8 x i8> [[C]])1473// CHECK-NEXT: ret <8 x i8> [[VBSL_V_I]]1474//1475int8x8_t test_vbsl_s8(uint8x8_t a, int8x8_t b, int8x8_t c) {1476 return vbsl_s8(a, b, c);1477}1478 1479// CHECK-LABEL: define <4 x i16> @test_vbsl_s16(1480// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {1481// CHECK-NEXT: [[ENTRY:.*:]]1482// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>1483// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>1484// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>1485// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])1486// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[VBSL_V_I]] to <4 x i16>1487// CHECK-NEXT: ret <4 x i16> [[TMP3]]1488//1489int16x4_t test_vbsl_s16(uint16x4_t a, int16x4_t b, int16x4_t c) {1490 return vbsl_s16(a, b, c);1491}1492 1493// CHECK-LABEL: define <2 x i32> @test_vbsl_s32(1494// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {1495// CHECK-NEXT: [[ENTRY:.*:]]1496// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>1497// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>1498// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>1499// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])1500// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[VBSL_V_I]] to <2 x i32>1501// CHECK-NEXT: ret <2 x i32> [[TMP3]]1502//1503int32x2_t test_vbsl_s32(uint32x2_t a, int32x2_t b, int32x2_t c) {1504 return vbsl_s32(a, b, c);1505}1506 1507// CHECK-LABEL: define <1 x i64> @test_vbsl_s64(1508// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]], <1 x i64> noundef [[C:%.*]]) #[[ATTR0]] {1509// CHECK-NEXT: [[ENTRY:.*:]]1510// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>1511// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>1512// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[C]] to <8 x i8>1513// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])1514// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[VBSL_V_I]] to i641515// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP3]], i32 01516// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]1517//1518int64x1_t test_vbsl_s64(uint64x1_t a, int64x1_t b, int64x1_t c) {1519 return vbsl_s64(a, b, c);1520}1521 1522// CHECK-LABEL: define <8 x i8> @test_vbsl_u8(1523// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {1524// CHECK-NEXT: [[ENTRY:.*:]]1525// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]], <8 x i8> [[C]])1526// CHECK-NEXT: ret <8 x i8> [[VBSL_V_I]]1527//1528uint8x8_t test_vbsl_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c) {1529 return vbsl_u8(a, b, c);1530}1531 1532// CHECK-LABEL: define <4 x i16> @test_vbsl_u16(1533// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {1534// CHECK-NEXT: [[ENTRY:.*:]]1535// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>1536// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>1537// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>1538// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])1539// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[VBSL_V_I]] to <4 x i16>1540// CHECK-NEXT: ret <4 x i16> [[TMP3]]1541//1542uint16x4_t test_vbsl_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c) {1543 return vbsl_u16(a, b, c);1544}1545 1546// CHECK-LABEL: define <2 x i32> @test_vbsl_u32(1547// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {1548// CHECK-NEXT: [[ENTRY:.*:]]1549// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>1550// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>1551// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>1552// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])1553// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[VBSL_V_I]] to <2 x i32>1554// CHECK-NEXT: ret <2 x i32> [[TMP3]]1555//1556uint32x2_t test_vbsl_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c) {1557 return vbsl_u32(a, b, c);1558}1559 1560// CHECK-LABEL: define <1 x i64> @test_vbsl_u64(1561// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]], <1 x i64> noundef [[C:%.*]]) #[[ATTR0]] {1562// CHECK-NEXT: [[ENTRY:.*:]]1563// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>1564// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>1565// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[C]] to <8 x i8>1566// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])1567// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[VBSL_V_I]] to i641568// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP3]], i32 01569// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]1570//1571uint64x1_t test_vbsl_u64(uint64x1_t a, uint64x1_t b, uint64x1_t c) {1572 return vbsl_u64(a, b, c);1573}1574 1575// CHECK-LABEL: define <2 x float> @test_vbsl_f32(1576// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[C:%.*]]) #[[ATTR0]] {1577// CHECK-NEXT: [[ENTRY:.*:]]1578// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>1579// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[C]] to <2 x i32>1580// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>1581// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>1582// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>1583// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[TMP2]], <8 x i8> [[TMP3]], <8 x i8> [[TMP4]])1584// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[VBSL_V_I]] to <2 x i32>1585// CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP5]] to <2 x float>1586// CHECK-NEXT: ret <2 x float> [[TMP6]]1587//1588float32x2_t test_vbsl_f32(uint32x2_t a, float32x2_t b, float32x2_t c) {1589 return vbsl_f32(a, b, c);1590}1591 1592// CHECK-LABEL: define <8 x i8> @test_vbsl_p8(1593// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {1594// CHECK-NEXT: [[ENTRY:.*:]]1595// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]], <8 x i8> [[C]])1596// CHECK-NEXT: ret <8 x i8> [[VBSL_V_I]]1597//1598poly8x8_t test_vbsl_p8(uint8x8_t a, poly8x8_t b, poly8x8_t c) {1599 return vbsl_p8(a, b, c);1600}1601 1602// CHECK-LABEL: define <4 x i16> @test_vbsl_p16(1603// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {1604// CHECK-NEXT: [[ENTRY:.*:]]1605// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>1606// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>1607// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>1608// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])1609// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[VBSL_V_I]] to <4 x i16>1610// CHECK-NEXT: ret <4 x i16> [[TMP3]]1611//1612poly16x4_t test_vbsl_p16(uint16x4_t a, poly16x4_t b, poly16x4_t c) {1613 return vbsl_p16(a, b, c);1614}1615 1616// CHECK-LABEL: define <16 x i8> @test_vbslq_s8(1617// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]], <16 x i8> noundef [[C:%.*]]) #[[ATTR0]] {1618// CHECK-NEXT: [[ENTRY:.*:]]1619// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]], <16 x i8> [[C]])1620// CHECK-NEXT: ret <16 x i8> [[VBSLQ_V_I]]1621//1622int8x16_t test_vbslq_s8(uint8x16_t a, int8x16_t b, int8x16_t c) {1623 return vbslq_s8(a, b, c);1624}1625 1626// CHECK-LABEL: define <8 x i16> @test_vbslq_s16(1627// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <8 x i16> noundef [[C:%.*]]) #[[ATTR0]] {1628// CHECK-NEXT: [[ENTRY:.*:]]1629// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>1630// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>1631// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[C]] to <16 x i8>1632// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], <16 x i8> [[TMP2]])1633// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[VBSLQ_V_I]] to <8 x i16>1634// CHECK-NEXT: ret <8 x i16> [[TMP3]]1635//1636int16x8_t test_vbslq_s16(uint16x8_t a, int16x8_t b, int16x8_t c) {1637 return vbslq_s16(a, b, c);1638}1639 1640// CHECK-LABEL: define <4 x i32> @test_vbslq_s32(1641// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <4 x i32> noundef [[C:%.*]]) #[[ATTR0]] {1642// CHECK-NEXT: [[ENTRY:.*:]]1643// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>1644// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>1645// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[C]] to <16 x i8>1646// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], <16 x i8> [[TMP2]])1647// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[VBSLQ_V_I]] to <4 x i32>1648// CHECK-NEXT: ret <4 x i32> [[TMP3]]1649//1650int32x4_t test_vbslq_s32(uint32x4_t a, int32x4_t b, int32x4_t c) {1651 return vbslq_s32(a, b, c);1652}1653 1654// CHECK-LABEL: define <2 x i64> @test_vbslq_s64(1655// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]], <2 x i64> noundef [[C:%.*]]) #[[ATTR0]] {1656// CHECK-NEXT: [[ENTRY:.*:]]1657// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>1658// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>1659// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[C]] to <16 x i8>1660// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], <16 x i8> [[TMP2]])1661// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[VBSLQ_V_I]] to <2 x i64>1662// CHECK-NEXT: ret <2 x i64> [[TMP3]]1663//1664int64x2_t test_vbslq_s64(uint64x2_t a, int64x2_t b, int64x2_t c) {1665 return vbslq_s64(a, b, c);1666}1667 1668// CHECK-LABEL: define <16 x i8> @test_vbslq_u8(1669// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]], <16 x i8> noundef [[C:%.*]]) #[[ATTR0]] {1670// CHECK-NEXT: [[ENTRY:.*:]]1671// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]], <16 x i8> [[C]])1672// CHECK-NEXT: ret <16 x i8> [[VBSLQ_V_I]]1673//1674uint8x16_t test_vbslq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c) {1675 return vbslq_u8(a, b, c);1676}1677 1678// CHECK-LABEL: define <8 x i16> @test_vbslq_u16(1679// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <8 x i16> noundef [[C:%.*]]) #[[ATTR0]] {1680// CHECK-NEXT: [[ENTRY:.*:]]1681// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>1682// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>1683// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[C]] to <16 x i8>1684// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], <16 x i8> [[TMP2]])1685// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[VBSLQ_V_I]] to <8 x i16>1686// CHECK-NEXT: ret <8 x i16> [[TMP3]]1687//1688uint16x8_t test_vbslq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c) {1689 return vbslq_u16(a, b, c);1690}1691 1692// CHECK-LABEL: define <4 x i32> @test_vbslq_u32(1693// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <4 x i32> noundef [[C:%.*]]) #[[ATTR0]] {1694// CHECK-NEXT: [[ENTRY:.*:]]1695// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>1696// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>1697// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[C]] to <16 x i8>1698// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], <16 x i8> [[TMP2]])1699// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[VBSLQ_V_I]] to <4 x i32>1700// CHECK-NEXT: ret <4 x i32> [[TMP3]]1701//1702uint32x4_t test_vbslq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c) {1703 return vbslq_u32(a, b, c);1704}1705 1706// CHECK-LABEL: define <2 x i64> @test_vbslq_u64(1707// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]], <2 x i64> noundef [[C:%.*]]) #[[ATTR0]] {1708// CHECK-NEXT: [[ENTRY:.*:]]1709// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>1710// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>1711// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[C]] to <16 x i8>1712// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], <16 x i8> [[TMP2]])1713// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[VBSLQ_V_I]] to <2 x i64>1714// CHECK-NEXT: ret <2 x i64> [[TMP3]]1715//1716uint64x2_t test_vbslq_u64(uint64x2_t a, uint64x2_t b, uint64x2_t c) {1717 return vbslq_u64(a, b, c);1718}1719 1720// CHECK-LABEL: define <4 x float> @test_vbslq_f32(1721// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]]) #[[ATTR0]] {1722// CHECK-NEXT: [[ENTRY:.*:]]1723// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>1724// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[C]] to <4 x i32>1725// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>1726// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>1727// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>1728// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[TMP2]], <16 x i8> [[TMP3]], <16 x i8> [[TMP4]])1729// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[VBSLQ_V_I]] to <4 x i32>1730// CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP5]] to <4 x float>1731// CHECK-NEXT: ret <4 x float> [[TMP6]]1732//1733float32x4_t test_vbslq_f32(uint32x4_t a, float32x4_t b, float32x4_t c) {1734 return vbslq_f32(a, b, c);1735}1736 1737// CHECK-LABEL: define <16 x i8> @test_vbslq_p8(1738// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]], <16 x i8> noundef [[C:%.*]]) #[[ATTR0]] {1739// CHECK-NEXT: [[ENTRY:.*:]]1740// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]], <16 x i8> [[C]])1741// CHECK-NEXT: ret <16 x i8> [[VBSLQ_V_I]]1742//1743poly8x16_t test_vbslq_p8(uint8x16_t a, poly8x16_t b, poly8x16_t c) {1744 return vbslq_p8(a, b, c);1745}1746 1747// CHECK-LABEL: define <8 x i16> @test_vbslq_p16(1748// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <8 x i16> noundef [[C:%.*]]) #[[ATTR0]] {1749// CHECK-NEXT: [[ENTRY:.*:]]1750// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>1751// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>1752// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[C]] to <16 x i8>1753// CHECK-NEXT: [[VBSLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], <16 x i8> [[TMP2]])1754// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[VBSLQ_V_I]] to <8 x i16>1755// CHECK-NEXT: ret <8 x i16> [[TMP3]]1756//1757poly16x8_t test_vbslq_p16(uint16x8_t a, poly16x8_t b, poly16x8_t c) {1758 return vbslq_p16(a, b, c);1759}1760 1761// CHECK-LABEL: define <2 x i32> @test_vcage_f32(1762// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {1763// CHECK-NEXT: [[ENTRY:.*:]]1764// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>1765// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>1766// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>1767// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>1768// CHECK-NEXT: [[VCAGE_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>1769// CHECK-NEXT: [[VCAGE_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>1770// CHECK-NEXT: [[VCAGE_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> [[VCAGE_V_I]], <2 x float> [[VCAGE_V1_I]])1771// CHECK-NEXT: ret <2 x i32> [[VCAGE_V2_I]]1772//1773uint32x2_t test_vcage_f32(float32x2_t a, float32x2_t b) {1774 return vcage_f32(a, b);1775}1776 1777// CHECK-LABEL: define <4 x i32> @test_vcageq_f32(1778// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {1779// CHECK-NEXT: [[ENTRY:.*:]]1780// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>1781// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>1782// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>1783// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>1784// CHECK-NEXT: [[VCAGEQ_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>1785// CHECK-NEXT: [[VCAGEQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>1786// CHECK-NEXT: [[VCAGEQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> [[VCAGEQ_V_I]], <4 x float> [[VCAGEQ_V1_I]])1787// CHECK-NEXT: ret <4 x i32> [[VCAGEQ_V2_I]]1788//1789uint32x4_t test_vcageq_f32(float32x4_t a, float32x4_t b) {1790 return vcageq_f32(a, b);1791}1792 1793// CHECK-LABEL: define <2 x i32> @test_vcagt_f32(1794// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {1795// CHECK-NEXT: [[ENTRY:.*:]]1796// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>1797// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>1798// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>1799// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>1800// CHECK-NEXT: [[VCAGT_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>1801// CHECK-NEXT: [[VCAGT_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>1802// CHECK-NEXT: [[VCAGT_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> [[VCAGT_V_I]], <2 x float> [[VCAGT_V1_I]])1803// CHECK-NEXT: ret <2 x i32> [[VCAGT_V2_I]]1804//1805uint32x2_t test_vcagt_f32(float32x2_t a, float32x2_t b) {1806 return vcagt_f32(a, b);1807}1808 1809// CHECK-LABEL: define <4 x i32> @test_vcagtq_f32(1810// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {1811// CHECK-NEXT: [[ENTRY:.*:]]1812// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>1813// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>1814// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>1815// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>1816// CHECK-NEXT: [[VCAGTQ_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>1817// CHECK-NEXT: [[VCAGTQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>1818// CHECK-NEXT: [[VCAGTQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> [[VCAGTQ_V_I]], <4 x float> [[VCAGTQ_V1_I]])1819// CHECK-NEXT: ret <4 x i32> [[VCAGTQ_V2_I]]1820//1821uint32x4_t test_vcagtq_f32(float32x4_t a, float32x4_t b) {1822 return vcagtq_f32(a, b);1823}1824 1825// CHECK-LABEL: define <2 x i32> @test_vcale_f32(1826// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {1827// CHECK-NEXT: [[ENTRY:.*:]]1828// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>1829// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>1830// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>1831// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>1832// CHECK-NEXT: [[VCALE_V_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>1833// CHECK-NEXT: [[VCALE_V1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>1834// CHECK-NEXT: [[VCALE_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> [[VCALE_V_I]], <2 x float> [[VCALE_V1_I]])1835// CHECK-NEXT: ret <2 x i32> [[VCALE_V2_I]]1836//1837uint32x2_t test_vcale_f32(float32x2_t a, float32x2_t b) {1838 return vcale_f32(a, b);1839}1840 1841// CHECK-LABEL: define <4 x i32> @test_vcaleq_f32(1842// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {1843// CHECK-NEXT: [[ENTRY:.*:]]1844// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>1845// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>1846// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>1847// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>1848// CHECK-NEXT: [[VCALEQ_V_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>1849// CHECK-NEXT: [[VCALEQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>1850// CHECK-NEXT: [[VCALEQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> [[VCALEQ_V_I]], <4 x float> [[VCALEQ_V1_I]])1851// CHECK-NEXT: ret <4 x i32> [[VCALEQ_V2_I]]1852//1853uint32x4_t test_vcaleq_f32(float32x4_t a, float32x4_t b) {1854 return vcaleq_f32(a, b);1855}1856 1857// CHECK-LABEL: define <2 x i32> @test_vcalt_f32(1858// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {1859// CHECK-NEXT: [[ENTRY:.*:]]1860// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>1861// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>1862// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>1863// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>1864// CHECK-NEXT: [[VCALT_V_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>1865// CHECK-NEXT: [[VCALT_V1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>1866// CHECK-NEXT: [[VCALT_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> [[VCALT_V_I]], <2 x float> [[VCALT_V1_I]])1867// CHECK-NEXT: ret <2 x i32> [[VCALT_V2_I]]1868//1869uint32x2_t test_vcalt_f32(float32x2_t a, float32x2_t b) {1870 return vcalt_f32(a, b);1871}1872 1873// CHECK-LABEL: define <4 x i32> @test_vcaltq_f32(1874// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {1875// CHECK-NEXT: [[ENTRY:.*:]]1876// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>1877// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>1878// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>1879// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>1880// CHECK-NEXT: [[VCALTQ_V_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>1881// CHECK-NEXT: [[VCALTQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>1882// CHECK-NEXT: [[VCALTQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> [[VCALTQ_V_I]], <4 x float> [[VCALTQ_V1_I]])1883// CHECK-NEXT: ret <4 x i32> [[VCALTQ_V2_I]]1884//1885uint32x4_t test_vcaltq_f32(float32x4_t a, float32x4_t b) {1886 return vcaltq_f32(a, b);1887}1888 1889// CHECK-LABEL: define <8 x i8> @test_vceq_s8(1890// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1891// CHECK-NEXT: [[ENTRY:.*:]]1892// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[A]], [[B]]1893// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>1894// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]1895//1896uint8x8_t test_vceq_s8(int8x8_t a, int8x8_t b) {1897 return vceq_s8(a, b);1898}1899 1900// CHECK-LABEL: define <4 x i16> @test_vceq_s16(1901// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1902// CHECK-NEXT: [[ENTRY:.*:]]1903// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[A]], [[B]]1904// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>1905// CHECK-NEXT: ret <4 x i16> [[SEXT_I]]1906//1907uint16x4_t test_vceq_s16(int16x4_t a, int16x4_t b) {1908 return vceq_s16(a, b);1909}1910 1911// CHECK-LABEL: define <2 x i32> @test_vceq_s32(1912// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1913// CHECK-NEXT: [[ENTRY:.*:]]1914// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[A]], [[B]]1915// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>1916// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]1917//1918uint32x2_t test_vceq_s32(int32x2_t a, int32x2_t b) {1919 return vceq_s32(a, b);1920}1921 1922// CHECK-LABEL: define <2 x i32> @test_vceq_f32(1923// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {1924// CHECK-NEXT: [[ENTRY:.*:]]1925// CHECK-NEXT: [[CMP_I:%.*]] = fcmp oeq <2 x float> [[A]], [[B]]1926// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>1927// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]1928//1929uint32x2_t test_vceq_f32(float32x2_t a, float32x2_t b) {1930 return vceq_f32(a, b);1931}1932 1933// CHECK-LABEL: define <8 x i8> @test_vceq_u8(1934// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1935// CHECK-NEXT: [[ENTRY:.*:]]1936// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[A]], [[B]]1937// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>1938// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]1939//1940uint8x8_t test_vceq_u8(uint8x8_t a, uint8x8_t b) {1941 return vceq_u8(a, b);1942}1943 1944// CHECK-LABEL: define <4 x i16> @test_vceq_u16(1945// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1946// CHECK-NEXT: [[ENTRY:.*:]]1947// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[A]], [[B]]1948// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>1949// CHECK-NEXT: ret <4 x i16> [[SEXT_I]]1950//1951uint16x4_t test_vceq_u16(uint16x4_t a, uint16x4_t b) {1952 return vceq_u16(a, b);1953}1954 1955// CHECK-LABEL: define <2 x i32> @test_vceq_u32(1956// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {1957// CHECK-NEXT: [[ENTRY:.*:]]1958// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[A]], [[B]]1959// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>1960// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]1961//1962uint32x2_t test_vceq_u32(uint32x2_t a, uint32x2_t b) {1963 return vceq_u32(a, b);1964}1965 1966// CHECK-LABEL: define <8 x i8> @test_vceq_p8(1967// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1968// CHECK-NEXT: [[ENTRY:.*:]]1969// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[A]], [[B]]1970// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>1971// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]1972//1973uint8x8_t test_vceq_p8(poly8x8_t a, poly8x8_t b) {1974 return vceq_p8(a, b);1975}1976 1977// CHECK-LABEL: define <16 x i8> @test_vceqq_s8(1978// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {1979// CHECK-NEXT: [[ENTRY:.*:]]1980// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <16 x i8> [[A]], [[B]]1981// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>1982// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]1983//1984uint8x16_t test_vceqq_s8(int8x16_t a, int8x16_t b) {1985 return vceqq_s8(a, b);1986}1987 1988// CHECK-LABEL: define <8 x i16> @test_vceqq_s16(1989// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {1990// CHECK-NEXT: [[ENTRY:.*:]]1991// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i16> [[A]], [[B]]1992// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>1993// CHECK-NEXT: ret <8 x i16> [[SEXT_I]]1994//1995uint16x8_t test_vceqq_s16(int16x8_t a, int16x8_t b) {1996 return vceqq_s16(a, b);1997}1998 1999// CHECK-LABEL: define <4 x i32> @test_vceqq_s32(2000// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2001// CHECK-NEXT: [[ENTRY:.*:]]2002// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i32> [[A]], [[B]]2003// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2004// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2005//2006uint32x4_t test_vceqq_s32(int32x4_t a, int32x4_t b) {2007 return vceqq_s32(a, b);2008}2009 2010// CHECK-LABEL: define <4 x i32> @test_vceqq_f32(2011// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {2012// CHECK-NEXT: [[ENTRY:.*:]]2013// CHECK-NEXT: [[CMP_I:%.*]] = fcmp oeq <4 x float> [[A]], [[B]]2014// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2015// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2016//2017uint32x4_t test_vceqq_f32(float32x4_t a, float32x4_t b) {2018 return vceqq_f32(a, b);2019}2020 2021// CHECK-LABEL: define <16 x i8> @test_vceqq_u8(2022// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2023// CHECK-NEXT: [[ENTRY:.*:]]2024// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <16 x i8> [[A]], [[B]]2025// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>2026// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]2027//2028uint8x16_t test_vceqq_u8(uint8x16_t a, uint8x16_t b) {2029 return vceqq_u8(a, b);2030}2031 2032// CHECK-LABEL: define <8 x i16> @test_vceqq_u16(2033// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2034// CHECK-NEXT: [[ENTRY:.*:]]2035// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i16> [[A]], [[B]]2036// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>2037// CHECK-NEXT: ret <8 x i16> [[SEXT_I]]2038//2039uint16x8_t test_vceqq_u16(uint16x8_t a, uint16x8_t b) {2040 return vceqq_u16(a, b);2041}2042 2043// CHECK-LABEL: define <4 x i32> @test_vceqq_u32(2044// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2045// CHECK-NEXT: [[ENTRY:.*:]]2046// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i32> [[A]], [[B]]2047// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2048// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2049//2050uint32x4_t test_vceqq_u32(uint32x4_t a, uint32x4_t b) {2051 return vceqq_u32(a, b);2052}2053 2054// CHECK-LABEL: define <16 x i8> @test_vceqq_p8(2055// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2056// CHECK-NEXT: [[ENTRY:.*:]]2057// CHECK-NEXT: [[CMP_I:%.*]] = icmp eq <16 x i8> [[A]], [[B]]2058// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>2059// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]2060//2061uint8x16_t test_vceqq_p8(poly8x16_t a, poly8x16_t b) {2062 return vceqq_p8(a, b);2063}2064 2065// CHECK-LABEL: define <8 x i8> @test_vcge_s8(2066// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2067// CHECK-NEXT: [[ENTRY:.*:]]2068// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <8 x i8> [[A]], [[B]]2069// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>2070// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]2071//2072uint8x8_t test_vcge_s8(int8x8_t a, int8x8_t b) {2073 return vcge_s8(a, b);2074}2075 2076// CHECK-LABEL: define <4 x i16> @test_vcge_s16(2077// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2078// CHECK-NEXT: [[ENTRY:.*:]]2079// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i16> [[A]], [[B]]2080// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>2081// CHECK-NEXT: ret <4 x i16> [[SEXT_I]]2082//2083uint16x4_t test_vcge_s16(int16x4_t a, int16x4_t b) {2084 return vcge_s16(a, b);2085}2086 2087// CHECK-LABEL: define <2 x i32> @test_vcge_s32(2088// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2089// CHECK-NEXT: [[ENTRY:.*:]]2090// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i32> [[A]], [[B]]2091// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2092// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2093//2094uint32x2_t test_vcge_s32(int32x2_t a, int32x2_t b) {2095 return vcge_s32(a, b);2096}2097 2098// CHECK-LABEL: define <2 x i32> @test_vcge_f32(2099// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {2100// CHECK-NEXT: [[ENTRY:.*:]]2101// CHECK-NEXT: [[CMP_I:%.*]] = fcmp oge <2 x float> [[A]], [[B]]2102// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2103// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2104//2105uint32x2_t test_vcge_f32(float32x2_t a, float32x2_t b) {2106 return vcge_f32(a, b);2107}2108 2109// CHECK-LABEL: define <8 x i8> @test_vcge_u8(2110// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2111// CHECK-NEXT: [[ENTRY:.*:]]2112// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <8 x i8> [[A]], [[B]]2113// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>2114// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]2115//2116uint8x8_t test_vcge_u8(uint8x8_t a, uint8x8_t b) {2117 return vcge_u8(a, b);2118}2119 2120// CHECK-LABEL: define <4 x i16> @test_vcge_u16(2121// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2122// CHECK-NEXT: [[ENTRY:.*:]]2123// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i16> [[A]], [[B]]2124// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>2125// CHECK-NEXT: ret <4 x i16> [[SEXT_I]]2126//2127uint16x4_t test_vcge_u16(uint16x4_t a, uint16x4_t b) {2128 return vcge_u16(a, b);2129}2130 2131// CHECK-LABEL: define <2 x i32> @test_vcge_u32(2132// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2133// CHECK-NEXT: [[ENTRY:.*:]]2134// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i32> [[A]], [[B]]2135// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2136// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2137//2138uint32x2_t test_vcge_u32(uint32x2_t a, uint32x2_t b) {2139 return vcge_u32(a, b);2140}2141 2142// CHECK-LABEL: define <16 x i8> @test_vcgeq_s8(2143// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2144// CHECK-NEXT: [[ENTRY:.*:]]2145// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <16 x i8> [[A]], [[B]]2146// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>2147// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]2148//2149uint8x16_t test_vcgeq_s8(int8x16_t a, int8x16_t b) {2150 return vcgeq_s8(a, b);2151}2152 2153// CHECK-LABEL: define <8 x i16> @test_vcgeq_s16(2154// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2155// CHECK-NEXT: [[ENTRY:.*:]]2156// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <8 x i16> [[A]], [[B]]2157// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>2158// CHECK-NEXT: ret <8 x i16> [[SEXT_I]]2159//2160uint16x8_t test_vcgeq_s16(int16x8_t a, int16x8_t b) {2161 return vcgeq_s16(a, b);2162}2163 2164// CHECK-LABEL: define <4 x i32> @test_vcgeq_s32(2165// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2166// CHECK-NEXT: [[ENTRY:.*:]]2167// CHECK-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i32> [[A]], [[B]]2168// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2169// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2170//2171uint32x4_t test_vcgeq_s32(int32x4_t a, int32x4_t b) {2172 return vcgeq_s32(a, b);2173}2174 2175// CHECK-LABEL: define <4 x i32> @test_vcgeq_f32(2176// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {2177// CHECK-NEXT: [[ENTRY:.*:]]2178// CHECK-NEXT: [[CMP_I:%.*]] = fcmp oge <4 x float> [[A]], [[B]]2179// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2180// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2181//2182uint32x4_t test_vcgeq_f32(float32x4_t a, float32x4_t b) {2183 return vcgeq_f32(a, b);2184}2185 2186// CHECK-LABEL: define <16 x i8> @test_vcgeq_u8(2187// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2188// CHECK-NEXT: [[ENTRY:.*:]]2189// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <16 x i8> [[A]], [[B]]2190// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>2191// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]2192//2193uint8x16_t test_vcgeq_u8(uint8x16_t a, uint8x16_t b) {2194 return vcgeq_u8(a, b);2195}2196 2197// CHECK-LABEL: define <8 x i16> @test_vcgeq_u16(2198// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2199// CHECK-NEXT: [[ENTRY:.*:]]2200// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <8 x i16> [[A]], [[B]]2201// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>2202// CHECK-NEXT: ret <8 x i16> [[SEXT_I]]2203//2204uint16x8_t test_vcgeq_u16(uint16x8_t a, uint16x8_t b) {2205 return vcgeq_u16(a, b);2206}2207 2208// CHECK-LABEL: define <4 x i32> @test_vcgeq_u32(2209// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2210// CHECK-NEXT: [[ENTRY:.*:]]2211// CHECK-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i32> [[A]], [[B]]2212// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2213// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2214//2215uint32x4_t test_vcgeq_u32(uint32x4_t a, uint32x4_t b) {2216 return vcgeq_u32(a, b);2217}2218 2219// CHECK-LABEL: define <8 x i8> @test_vcgt_s8(2220// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2221// CHECK-NEXT: [[ENTRY:.*:]]2222// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <8 x i8> [[A]], [[B]]2223// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>2224// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]2225//2226uint8x8_t test_vcgt_s8(int8x8_t a, int8x8_t b) {2227 return vcgt_s8(a, b);2228}2229 2230// CHECK-LABEL: define <4 x i16> @test_vcgt_s16(2231// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2232// CHECK-NEXT: [[ENTRY:.*:]]2233// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i16> [[A]], [[B]]2234// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>2235// CHECK-NEXT: ret <4 x i16> [[SEXT_I]]2236//2237uint16x4_t test_vcgt_s16(int16x4_t a, int16x4_t b) {2238 return vcgt_s16(a, b);2239}2240 2241// CHECK-LABEL: define <2 x i32> @test_vcgt_s32(2242// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2243// CHECK-NEXT: [[ENTRY:.*:]]2244// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i32> [[A]], [[B]]2245// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2246// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2247//2248uint32x2_t test_vcgt_s32(int32x2_t a, int32x2_t b) {2249 return vcgt_s32(a, b);2250}2251 2252// CHECK-LABEL: define <2 x i32> @test_vcgt_f32(2253// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {2254// CHECK-NEXT: [[ENTRY:.*:]]2255// CHECK-NEXT: [[CMP_I:%.*]] = fcmp ogt <2 x float> [[A]], [[B]]2256// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2257// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2258//2259uint32x2_t test_vcgt_f32(float32x2_t a, float32x2_t b) {2260 return vcgt_f32(a, b);2261}2262 2263// CHECK-LABEL: define <8 x i8> @test_vcgt_u8(2264// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2265// CHECK-NEXT: [[ENTRY:.*:]]2266// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <8 x i8> [[A]], [[B]]2267// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>2268// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]2269//2270uint8x8_t test_vcgt_u8(uint8x8_t a, uint8x8_t b) {2271 return vcgt_u8(a, b);2272}2273 2274// CHECK-LABEL: define <4 x i16> @test_vcgt_u16(2275// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2276// CHECK-NEXT: [[ENTRY:.*:]]2277// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i16> [[A]], [[B]]2278// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>2279// CHECK-NEXT: ret <4 x i16> [[SEXT_I]]2280//2281uint16x4_t test_vcgt_u16(uint16x4_t a, uint16x4_t b) {2282 return vcgt_u16(a, b);2283}2284 2285// CHECK-LABEL: define <2 x i32> @test_vcgt_u32(2286// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2287// CHECK-NEXT: [[ENTRY:.*:]]2288// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i32> [[A]], [[B]]2289// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2290// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2291//2292uint32x2_t test_vcgt_u32(uint32x2_t a, uint32x2_t b) {2293 return vcgt_u32(a, b);2294}2295 2296// CHECK-LABEL: define <16 x i8> @test_vcgtq_s8(2297// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2298// CHECK-NEXT: [[ENTRY:.*:]]2299// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <16 x i8> [[A]], [[B]]2300// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>2301// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]2302//2303uint8x16_t test_vcgtq_s8(int8x16_t a, int8x16_t b) {2304 return vcgtq_s8(a, b);2305}2306 2307// CHECK-LABEL: define <8 x i16> @test_vcgtq_s16(2308// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2309// CHECK-NEXT: [[ENTRY:.*:]]2310// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <8 x i16> [[A]], [[B]]2311// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>2312// CHECK-NEXT: ret <8 x i16> [[SEXT_I]]2313//2314uint16x8_t test_vcgtq_s16(int16x8_t a, int16x8_t b) {2315 return vcgtq_s16(a, b);2316}2317 2318// CHECK-LABEL: define <4 x i32> @test_vcgtq_s32(2319// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2320// CHECK-NEXT: [[ENTRY:.*:]]2321// CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i32> [[A]], [[B]]2322// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2323// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2324//2325uint32x4_t test_vcgtq_s32(int32x4_t a, int32x4_t b) {2326 return vcgtq_s32(a, b);2327}2328 2329// CHECK-LABEL: define <4 x i32> @test_vcgtq_f32(2330// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {2331// CHECK-NEXT: [[ENTRY:.*:]]2332// CHECK-NEXT: [[CMP_I:%.*]] = fcmp ogt <4 x float> [[A]], [[B]]2333// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2334// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2335//2336uint32x4_t test_vcgtq_f32(float32x4_t a, float32x4_t b) {2337 return vcgtq_f32(a, b);2338}2339 2340// CHECK-LABEL: define <16 x i8> @test_vcgtq_u8(2341// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2342// CHECK-NEXT: [[ENTRY:.*:]]2343// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <16 x i8> [[A]], [[B]]2344// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>2345// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]2346//2347uint8x16_t test_vcgtq_u8(uint8x16_t a, uint8x16_t b) {2348 return vcgtq_u8(a, b);2349}2350 2351// CHECK-LABEL: define <8 x i16> @test_vcgtq_u16(2352// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2353// CHECK-NEXT: [[ENTRY:.*:]]2354// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <8 x i16> [[A]], [[B]]2355// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>2356// CHECK-NEXT: ret <8 x i16> [[SEXT_I]]2357//2358uint16x8_t test_vcgtq_u16(uint16x8_t a, uint16x8_t b) {2359 return vcgtq_u16(a, b);2360}2361 2362// CHECK-LABEL: define <4 x i32> @test_vcgtq_u32(2363// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2364// CHECK-NEXT: [[ENTRY:.*:]]2365// CHECK-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i32> [[A]], [[B]]2366// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2367// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2368//2369uint32x4_t test_vcgtq_u32(uint32x4_t a, uint32x4_t b) {2370 return vcgtq_u32(a, b);2371}2372 2373// CHECK-LABEL: define <8 x i8> @test_vcle_s8(2374// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2375// CHECK-NEXT: [[ENTRY:.*:]]2376// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <8 x i8> [[A]], [[B]]2377// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>2378// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]2379//2380uint8x8_t test_vcle_s8(int8x8_t a, int8x8_t b) {2381 return vcle_s8(a, b);2382}2383 2384// CHECK-LABEL: define <4 x i16> @test_vcle_s16(2385// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2386// CHECK-NEXT: [[ENTRY:.*:]]2387// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i16> [[A]], [[B]]2388// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>2389// CHECK-NEXT: ret <4 x i16> [[SEXT_I]]2390//2391uint16x4_t test_vcle_s16(int16x4_t a, int16x4_t b) {2392 return vcle_s16(a, b);2393}2394 2395// CHECK-LABEL: define <2 x i32> @test_vcle_s32(2396// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2397// CHECK-NEXT: [[ENTRY:.*:]]2398// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i32> [[A]], [[B]]2399// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2400// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2401//2402uint32x2_t test_vcle_s32(int32x2_t a, int32x2_t b) {2403 return vcle_s32(a, b);2404}2405 2406// CHECK-LABEL: define <2 x i32> @test_vcle_f32(2407// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {2408// CHECK-NEXT: [[ENTRY:.*:]]2409// CHECK-NEXT: [[CMP_I:%.*]] = fcmp ole <2 x float> [[A]], [[B]]2410// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2411// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2412//2413uint32x2_t test_vcle_f32(float32x2_t a, float32x2_t b) {2414 return vcle_f32(a, b);2415}2416 2417// CHECK-LABEL: define <8 x i8> @test_vcle_u8(2418// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2419// CHECK-NEXT: [[ENTRY:.*:]]2420// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <8 x i8> [[A]], [[B]]2421// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>2422// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]2423//2424uint8x8_t test_vcle_u8(uint8x8_t a, uint8x8_t b) {2425 return vcle_u8(a, b);2426}2427 2428// CHECK-LABEL: define <4 x i16> @test_vcle_u16(2429// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2430// CHECK-NEXT: [[ENTRY:.*:]]2431// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i16> [[A]], [[B]]2432// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>2433// CHECK-NEXT: ret <4 x i16> [[SEXT_I]]2434//2435uint16x4_t test_vcle_u16(uint16x4_t a, uint16x4_t b) {2436 return vcle_u16(a, b);2437}2438 2439// CHECK-LABEL: define <2 x i32> @test_vcle_u32(2440// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2441// CHECK-NEXT: [[ENTRY:.*:]]2442// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i32> [[A]], [[B]]2443// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2444// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2445//2446uint32x2_t test_vcle_u32(uint32x2_t a, uint32x2_t b) {2447 return vcle_u32(a, b);2448}2449 2450// CHECK-LABEL: define <16 x i8> @test_vcleq_s8(2451// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2452// CHECK-NEXT: [[ENTRY:.*:]]2453// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <16 x i8> [[A]], [[B]]2454// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>2455// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]2456//2457uint8x16_t test_vcleq_s8(int8x16_t a, int8x16_t b) {2458 return vcleq_s8(a, b);2459}2460 2461// CHECK-LABEL: define <8 x i16> @test_vcleq_s16(2462// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2463// CHECK-NEXT: [[ENTRY:.*:]]2464// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <8 x i16> [[A]], [[B]]2465// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>2466// CHECK-NEXT: ret <8 x i16> [[SEXT_I]]2467//2468uint16x8_t test_vcleq_s16(int16x8_t a, int16x8_t b) {2469 return vcleq_s16(a, b);2470}2471 2472// CHECK-LABEL: define <4 x i32> @test_vcleq_s32(2473// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2474// CHECK-NEXT: [[ENTRY:.*:]]2475// CHECK-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i32> [[A]], [[B]]2476// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2477// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2478//2479uint32x4_t test_vcleq_s32(int32x4_t a, int32x4_t b) {2480 return vcleq_s32(a, b);2481}2482 2483// CHECK-LABEL: define <4 x i32> @test_vcleq_f32(2484// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {2485// CHECK-NEXT: [[ENTRY:.*:]]2486// CHECK-NEXT: [[CMP_I:%.*]] = fcmp ole <4 x float> [[A]], [[B]]2487// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2488// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2489//2490uint32x4_t test_vcleq_f32(float32x4_t a, float32x4_t b) {2491 return vcleq_f32(a, b);2492}2493 2494// CHECK-LABEL: define <16 x i8> @test_vcleq_u8(2495// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2496// CHECK-NEXT: [[ENTRY:.*:]]2497// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <16 x i8> [[A]], [[B]]2498// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>2499// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]2500//2501uint8x16_t test_vcleq_u8(uint8x16_t a, uint8x16_t b) {2502 return vcleq_u8(a, b);2503}2504 2505// CHECK-LABEL: define <8 x i16> @test_vcleq_u16(2506// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2507// CHECK-NEXT: [[ENTRY:.*:]]2508// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <8 x i16> [[A]], [[B]]2509// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>2510// CHECK-NEXT: ret <8 x i16> [[SEXT_I]]2511//2512uint16x8_t test_vcleq_u16(uint16x8_t a, uint16x8_t b) {2513 return vcleq_u16(a, b);2514}2515 2516// CHECK-LABEL: define <4 x i32> @test_vcleq_u32(2517// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2518// CHECK-NEXT: [[ENTRY:.*:]]2519// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i32> [[A]], [[B]]2520// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2521// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2522//2523uint32x4_t test_vcleq_u32(uint32x4_t a, uint32x4_t b) {2524 return vcleq_u32(a, b);2525}2526 2527// CHECK-LABEL: define <8 x i8> @test_vcls_s8(2528// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {2529// CHECK-NEXT: [[ENTRY:.*:]]2530// CHECK-NEXT: [[VCLS_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> [[A]])2531// CHECK-NEXT: ret <8 x i8> [[VCLS_V_I]]2532//2533int8x8_t test_vcls_s8(int8x8_t a) {2534 return vcls_s8(a);2535}2536 2537// CHECK-LABEL: define <4 x i16> @test_vcls_s16(2538// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {2539// CHECK-NEXT: [[ENTRY:.*:]]2540// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>2541// CHECK-NEXT: [[VCLS_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>2542// CHECK-NEXT: [[VCLS_V1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> [[VCLS_V_I]])2543// CHECK-NEXT: [[VCLS_V2_I:%.*]] = bitcast <4 x i16> [[VCLS_V1_I]] to <8 x i8>2544// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VCLS_V2_I]] to <4 x i16>2545// CHECK-NEXT: ret <4 x i16> [[TMP1]]2546//2547int16x4_t test_vcls_s16(int16x4_t a) {2548 return vcls_s16(a);2549}2550 2551// CHECK-LABEL: define <2 x i32> @test_vcls_s32(2552// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {2553// CHECK-NEXT: [[ENTRY:.*:]]2554// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>2555// CHECK-NEXT: [[VCLS_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>2556// CHECK-NEXT: [[VCLS_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> [[VCLS_V_I]])2557// CHECK-NEXT: [[VCLS_V2_I:%.*]] = bitcast <2 x i32> [[VCLS_V1_I]] to <8 x i8>2558// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VCLS_V2_I]] to <2 x i32>2559// CHECK-NEXT: ret <2 x i32> [[TMP1]]2560//2561int32x2_t test_vcls_s32(int32x2_t a) {2562 return vcls_s32(a);2563}2564 2565// CHECK-LABEL: define <8 x i8> @test_vcls_u8(2566// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {2567// CHECK-NEXT: [[ENTRY:.*:]]2568// CHECK-NEXT: [[VCLS_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> [[A]])2569// CHECK-NEXT: ret <8 x i8> [[VCLS_V_I]]2570//2571int8x8_t test_vcls_u8(uint8x8_t a) {2572 return vcls_u8(a);2573}2574 2575// CHECK-LABEL: define <4 x i16> @test_vcls_u16(2576// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {2577// CHECK-NEXT: [[ENTRY:.*:]]2578// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>2579// CHECK-NEXT: [[VCLS_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>2580// CHECK-NEXT: [[VCLS_V1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> [[VCLS_V_I]])2581// CHECK-NEXT: [[VCLS_V2_I:%.*]] = bitcast <4 x i16> [[VCLS_V1_I]] to <8 x i8>2582// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VCLS_V2_I]] to <4 x i16>2583// CHECK-NEXT: ret <4 x i16> [[TMP1]]2584//2585int16x4_t test_vcls_u16(uint16x4_t a) {2586 return vcls_u16(a);2587}2588 2589// CHECK-LABEL: define <2 x i32> @test_vcls_u32(2590// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {2591// CHECK-NEXT: [[ENTRY:.*:]]2592// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>2593// CHECK-NEXT: [[VCLS_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>2594// CHECK-NEXT: [[VCLS_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> [[VCLS_V_I]])2595// CHECK-NEXT: [[VCLS_V2_I:%.*]] = bitcast <2 x i32> [[VCLS_V1_I]] to <8 x i8>2596// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VCLS_V2_I]] to <2 x i32>2597// CHECK-NEXT: ret <2 x i32> [[TMP1]]2598//2599int32x2_t test_vcls_u32(uint32x2_t a) {2600 return vcls_u32(a);2601}2602 2603// CHECK-LABEL: define <16 x i8> @test_vclsq_s8(2604// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {2605// CHECK-NEXT: [[ENTRY:.*:]]2606// CHECK-NEXT: [[VCLSQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> [[A]])2607// CHECK-NEXT: ret <16 x i8> [[VCLSQ_V_I]]2608//2609int8x16_t test_vclsq_s8(int8x16_t a) {2610 return vclsq_s8(a);2611}2612 2613// CHECK-LABEL: define <8 x i16> @test_vclsq_s16(2614// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {2615// CHECK-NEXT: [[ENTRY:.*:]]2616// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>2617// CHECK-NEXT: [[VCLSQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>2618// CHECK-NEXT: [[VCLSQ_V1_I:%.*]] = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> [[VCLSQ_V_I]])2619// CHECK-NEXT: [[VCLSQ_V2_I:%.*]] = bitcast <8 x i16> [[VCLSQ_V1_I]] to <16 x i8>2620// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VCLSQ_V2_I]] to <8 x i16>2621// CHECK-NEXT: ret <8 x i16> [[TMP1]]2622//2623int16x8_t test_vclsq_s16(int16x8_t a) {2624 return vclsq_s16(a);2625}2626 2627// CHECK-LABEL: define <4 x i32> @test_vclsq_s32(2628// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {2629// CHECK-NEXT: [[ENTRY:.*:]]2630// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>2631// CHECK-NEXT: [[VCLSQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>2632// CHECK-NEXT: [[VCLSQ_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> [[VCLSQ_V_I]])2633// CHECK-NEXT: [[VCLSQ_V2_I:%.*]] = bitcast <4 x i32> [[VCLSQ_V1_I]] to <16 x i8>2634// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VCLSQ_V2_I]] to <4 x i32>2635// CHECK-NEXT: ret <4 x i32> [[TMP1]]2636//2637int32x4_t test_vclsq_s32(int32x4_t a) {2638 return vclsq_s32(a);2639}2640 2641// CHECK-LABEL: define <16 x i8> @test_vclsq_u8(2642// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {2643// CHECK-NEXT: [[ENTRY:.*:]]2644// CHECK-NEXT: [[VCLSQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> [[A]])2645// CHECK-NEXT: ret <16 x i8> [[VCLSQ_V_I]]2646//2647int8x16_t test_vclsq_u8(uint8x16_t a) {2648 return vclsq_u8(a);2649}2650 2651// CHECK-LABEL: define <8 x i16> @test_vclsq_u16(2652// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {2653// CHECK-NEXT: [[ENTRY:.*:]]2654// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>2655// CHECK-NEXT: [[VCLSQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>2656// CHECK-NEXT: [[VCLSQ_V1_I:%.*]] = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> [[VCLSQ_V_I]])2657// CHECK-NEXT: [[VCLSQ_V2_I:%.*]] = bitcast <8 x i16> [[VCLSQ_V1_I]] to <16 x i8>2658// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VCLSQ_V2_I]] to <8 x i16>2659// CHECK-NEXT: ret <8 x i16> [[TMP1]]2660//2661int16x8_t test_vclsq_u16(uint16x8_t a) {2662 return vclsq_u16(a);2663}2664 2665// CHECK-LABEL: define <4 x i32> @test_vclsq_u32(2666// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {2667// CHECK-NEXT: [[ENTRY:.*:]]2668// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>2669// CHECK-NEXT: [[VCLSQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>2670// CHECK-NEXT: [[VCLSQ_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> [[VCLSQ_V_I]])2671// CHECK-NEXT: [[VCLSQ_V2_I:%.*]] = bitcast <4 x i32> [[VCLSQ_V1_I]] to <16 x i8>2672// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VCLSQ_V2_I]] to <4 x i32>2673// CHECK-NEXT: ret <4 x i32> [[TMP1]]2674//2675int32x4_t test_vclsq_u32(uint32x4_t a) {2676 return vclsq_u32(a);2677}2678 2679// CHECK-LABEL: define <8 x i8> @test_vclt_s8(2680// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2681// CHECK-NEXT: [[ENTRY:.*:]]2682// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <8 x i8> [[A]], [[B]]2683// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>2684// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]2685//2686uint8x8_t test_vclt_s8(int8x8_t a, int8x8_t b) {2687 return vclt_s8(a, b);2688}2689 2690// CHECK-LABEL: define <4 x i16> @test_vclt_s16(2691// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2692// CHECK-NEXT: [[ENTRY:.*:]]2693// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i16> [[A]], [[B]]2694// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>2695// CHECK-NEXT: ret <4 x i16> [[SEXT_I]]2696//2697uint16x4_t test_vclt_s16(int16x4_t a, int16x4_t b) {2698 return vclt_s16(a, b);2699}2700 2701// CHECK-LABEL: define <2 x i32> @test_vclt_s32(2702// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2703// CHECK-NEXT: [[ENTRY:.*:]]2704// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i32> [[A]], [[B]]2705// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2706// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2707//2708uint32x2_t test_vclt_s32(int32x2_t a, int32x2_t b) {2709 return vclt_s32(a, b);2710}2711 2712// CHECK-LABEL: define <2 x i32> @test_vclt_f32(2713// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {2714// CHECK-NEXT: [[ENTRY:.*:]]2715// CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt <2 x float> [[A]], [[B]]2716// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2717// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2718//2719uint32x2_t test_vclt_f32(float32x2_t a, float32x2_t b) {2720 return vclt_f32(a, b);2721}2722 2723// CHECK-LABEL: define <8 x i8> @test_vclt_u8(2724// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2725// CHECK-NEXT: [[ENTRY:.*:]]2726// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <8 x i8> [[A]], [[B]]2727// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>2728// CHECK-NEXT: ret <8 x i8> [[SEXT_I]]2729//2730uint8x8_t test_vclt_u8(uint8x8_t a, uint8x8_t b) {2731 return vclt_u8(a, b);2732}2733 2734// CHECK-LABEL: define <4 x i16> @test_vclt_u16(2735// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2736// CHECK-NEXT: [[ENTRY:.*:]]2737// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i16> [[A]], [[B]]2738// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>2739// CHECK-NEXT: ret <4 x i16> [[SEXT_I]]2740//2741uint16x4_t test_vclt_u16(uint16x4_t a, uint16x4_t b) {2742 return vclt_u16(a, b);2743}2744 2745// CHECK-LABEL: define <2 x i32> @test_vclt_u32(2746// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2747// CHECK-NEXT: [[ENTRY:.*:]]2748// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i32> [[A]], [[B]]2749// CHECK-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>2750// CHECK-NEXT: ret <2 x i32> [[SEXT_I]]2751//2752uint32x2_t test_vclt_u32(uint32x2_t a, uint32x2_t b) {2753 return vclt_u32(a, b);2754}2755 2756// CHECK-LABEL: define <16 x i8> @test_vcltq_s8(2757// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2758// CHECK-NEXT: [[ENTRY:.*:]]2759// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <16 x i8> [[A]], [[B]]2760// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>2761// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]2762//2763uint8x16_t test_vcltq_s8(int8x16_t a, int8x16_t b) {2764 return vcltq_s8(a, b);2765}2766 2767// CHECK-LABEL: define <8 x i16> @test_vcltq_s16(2768// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2769// CHECK-NEXT: [[ENTRY:.*:]]2770// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <8 x i16> [[A]], [[B]]2771// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>2772// CHECK-NEXT: ret <8 x i16> [[SEXT_I]]2773//2774uint16x8_t test_vcltq_s16(int16x8_t a, int16x8_t b) {2775 return vcltq_s16(a, b);2776}2777 2778// CHECK-LABEL: define <4 x i32> @test_vcltq_s32(2779// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2780// CHECK-NEXT: [[ENTRY:.*:]]2781// CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i32> [[A]], [[B]]2782// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2783// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2784//2785uint32x4_t test_vcltq_s32(int32x4_t a, int32x4_t b) {2786 return vcltq_s32(a, b);2787}2788 2789// CHECK-LABEL: define <4 x i32> @test_vcltq_f32(2790// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {2791// CHECK-NEXT: [[ENTRY:.*:]]2792// CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt <4 x float> [[A]], [[B]]2793// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2794// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2795//2796uint32x4_t test_vcltq_f32(float32x4_t a, float32x4_t b) {2797 return vcltq_f32(a, b);2798}2799 2800// CHECK-LABEL: define <16 x i8> @test_vcltq_u8(2801// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {2802// CHECK-NEXT: [[ENTRY:.*:]]2803// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <16 x i8> [[A]], [[B]]2804// CHECK-NEXT: [[SEXT_I:%.*]] = sext <16 x i1> [[CMP_I]] to <16 x i8>2805// CHECK-NEXT: ret <16 x i8> [[SEXT_I]]2806//2807uint8x16_t test_vcltq_u8(uint8x16_t a, uint8x16_t b) {2808 return vcltq_u8(a, b);2809}2810 2811// CHECK-LABEL: define <8 x i16> @test_vcltq_u16(2812// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {2813// CHECK-NEXT: [[ENTRY:.*:]]2814// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <8 x i16> [[A]], [[B]]2815// CHECK-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>2816// CHECK-NEXT: ret <8 x i16> [[SEXT_I]]2817//2818uint16x8_t test_vcltq_u16(uint16x8_t a, uint16x8_t b) {2819 return vcltq_u16(a, b);2820}2821 2822// CHECK-LABEL: define <4 x i32> @test_vcltq_u32(2823// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {2824// CHECK-NEXT: [[ENTRY:.*:]]2825// CHECK-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i32> [[A]], [[B]]2826// CHECK-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>2827// CHECK-NEXT: ret <4 x i32> [[SEXT_I]]2828//2829uint32x4_t test_vcltq_u32(uint32x4_t a, uint32x4_t b) {2830 return vcltq_u32(a, b);2831}2832 2833// CHECK-LABEL: define <8 x i8> @test_vclz_s8(2834// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {2835// CHECK-NEXT: [[ENTRY:.*:]]2836// CHECK-NEXT: [[VCLZ_V_I:%.*]] = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> [[A]], i1 false)2837// CHECK-NEXT: ret <8 x i8> [[VCLZ_V_I]]2838//2839int8x8_t test_vclz_s8(int8x8_t a) {2840 return vclz_s8(a);2841}2842 2843// CHECK-LABEL: define <4 x i16> @test_vclz_s16(2844// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {2845// CHECK-NEXT: [[ENTRY:.*:]]2846// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>2847// CHECK-NEXT: [[VCLZ_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>2848// CHECK-NEXT: [[VCLZ_V1_I:%.*]] = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> [[VCLZ_V_I]], i1 false)2849// CHECK-NEXT: [[VCLZ_V2_I:%.*]] = bitcast <4 x i16> [[VCLZ_V1_I]] to <8 x i8>2850// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VCLZ_V2_I]] to <4 x i16>2851// CHECK-NEXT: ret <4 x i16> [[TMP1]]2852//2853int16x4_t test_vclz_s16(int16x4_t a) {2854 return vclz_s16(a);2855}2856 2857// CHECK-LABEL: define <2 x i32> @test_vclz_s32(2858// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {2859// CHECK-NEXT: [[ENTRY:.*:]]2860// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>2861// CHECK-NEXT: [[VCLZ_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>2862// CHECK-NEXT: [[VCLZ_V1_I:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[VCLZ_V_I]], i1 false)2863// CHECK-NEXT: [[VCLZ_V2_I:%.*]] = bitcast <2 x i32> [[VCLZ_V1_I]] to <8 x i8>2864// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VCLZ_V2_I]] to <2 x i32>2865// CHECK-NEXT: ret <2 x i32> [[TMP1]]2866//2867int32x2_t test_vclz_s32(int32x2_t a) {2868 return vclz_s32(a);2869}2870 2871// CHECK-LABEL: define <8 x i8> @test_vclz_u8(2872// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {2873// CHECK-NEXT: [[ENTRY:.*:]]2874// CHECK-NEXT: [[VCLZ_V_I:%.*]] = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> [[A]], i1 false)2875// CHECK-NEXT: ret <8 x i8> [[VCLZ_V_I]]2876//2877uint8x8_t test_vclz_u8(uint8x8_t a) {2878 return vclz_u8(a);2879}2880 2881// CHECK-LABEL: define <4 x i16> @test_vclz_u16(2882// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {2883// CHECK-NEXT: [[ENTRY:.*:]]2884// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>2885// CHECK-NEXT: [[VCLZ_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>2886// CHECK-NEXT: [[VCLZ_V1_I:%.*]] = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> [[VCLZ_V_I]], i1 false)2887// CHECK-NEXT: [[VCLZ_V2_I:%.*]] = bitcast <4 x i16> [[VCLZ_V1_I]] to <8 x i8>2888// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VCLZ_V2_I]] to <4 x i16>2889// CHECK-NEXT: ret <4 x i16> [[TMP1]]2890//2891uint16x4_t test_vclz_u16(uint16x4_t a) {2892 return vclz_u16(a);2893}2894 2895// CHECK-LABEL: define <2 x i32> @test_vclz_u32(2896// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {2897// CHECK-NEXT: [[ENTRY:.*:]]2898// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>2899// CHECK-NEXT: [[VCLZ_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>2900// CHECK-NEXT: [[VCLZ_V1_I:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[VCLZ_V_I]], i1 false)2901// CHECK-NEXT: [[VCLZ_V2_I:%.*]] = bitcast <2 x i32> [[VCLZ_V1_I]] to <8 x i8>2902// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VCLZ_V2_I]] to <2 x i32>2903// CHECK-NEXT: ret <2 x i32> [[TMP1]]2904//2905uint32x2_t test_vclz_u32(uint32x2_t a) {2906 return vclz_u32(a);2907}2908 2909// CHECK-LABEL: define <16 x i8> @test_vclzq_s8(2910// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {2911// CHECK-NEXT: [[ENTRY:.*:]]2912// CHECK-NEXT: [[VCLZQ_V_I:%.*]] = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> [[A]], i1 false)2913// CHECK-NEXT: ret <16 x i8> [[VCLZQ_V_I]]2914//2915int8x16_t test_vclzq_s8(int8x16_t a) {2916 return vclzq_s8(a);2917}2918 2919// CHECK-LABEL: define <8 x i16> @test_vclzq_s16(2920// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {2921// CHECK-NEXT: [[ENTRY:.*:]]2922// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>2923// CHECK-NEXT: [[VCLZQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>2924// CHECK-NEXT: [[VCLZQ_V1_I:%.*]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[VCLZQ_V_I]], i1 false)2925// CHECK-NEXT: [[VCLZQ_V2_I:%.*]] = bitcast <8 x i16> [[VCLZQ_V1_I]] to <16 x i8>2926// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VCLZQ_V2_I]] to <8 x i16>2927// CHECK-NEXT: ret <8 x i16> [[TMP1]]2928//2929int16x8_t test_vclzq_s16(int16x8_t a) {2930 return vclzq_s16(a);2931}2932 2933// CHECK-LABEL: define <4 x i32> @test_vclzq_s32(2934// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {2935// CHECK-NEXT: [[ENTRY:.*:]]2936// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>2937// CHECK-NEXT: [[VCLZQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>2938// CHECK-NEXT: [[VCLZQ_V1_I:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[VCLZQ_V_I]], i1 false)2939// CHECK-NEXT: [[VCLZQ_V2_I:%.*]] = bitcast <4 x i32> [[VCLZQ_V1_I]] to <16 x i8>2940// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VCLZQ_V2_I]] to <4 x i32>2941// CHECK-NEXT: ret <4 x i32> [[TMP1]]2942//2943int32x4_t test_vclzq_s32(int32x4_t a) {2944 return vclzq_s32(a);2945}2946 2947// CHECK-LABEL: define <16 x i8> @test_vclzq_u8(2948// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {2949// CHECK-NEXT: [[ENTRY:.*:]]2950// CHECK-NEXT: [[VCLZQ_V_I:%.*]] = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> [[A]], i1 false)2951// CHECK-NEXT: ret <16 x i8> [[VCLZQ_V_I]]2952//2953uint8x16_t test_vclzq_u8(uint8x16_t a) {2954 return vclzq_u8(a);2955}2956 2957// CHECK-LABEL: define <8 x i16> @test_vclzq_u16(2958// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {2959// CHECK-NEXT: [[ENTRY:.*:]]2960// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>2961// CHECK-NEXT: [[VCLZQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>2962// CHECK-NEXT: [[VCLZQ_V1_I:%.*]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[VCLZQ_V_I]], i1 false)2963// CHECK-NEXT: [[VCLZQ_V2_I:%.*]] = bitcast <8 x i16> [[VCLZQ_V1_I]] to <16 x i8>2964// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VCLZQ_V2_I]] to <8 x i16>2965// CHECK-NEXT: ret <8 x i16> [[TMP1]]2966//2967uint16x8_t test_vclzq_u16(uint16x8_t a) {2968 return vclzq_u16(a);2969}2970 2971// CHECK-LABEL: define <4 x i32> @test_vclzq_u32(2972// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {2973// CHECK-NEXT: [[ENTRY:.*:]]2974// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>2975// CHECK-NEXT: [[VCLZQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>2976// CHECK-NEXT: [[VCLZQ_V1_I:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[VCLZQ_V_I]], i1 false)2977// CHECK-NEXT: [[VCLZQ_V2_I:%.*]] = bitcast <4 x i32> [[VCLZQ_V1_I]] to <16 x i8>2978// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VCLZQ_V2_I]] to <4 x i32>2979// CHECK-NEXT: ret <4 x i32> [[TMP1]]2980//2981uint32x4_t test_vclzq_u32(uint32x4_t a) {2982 return vclzq_u32(a);2983}2984 2985// CHECK-LABEL: define <8 x i8> @test_vcnt_u8(2986// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {2987// CHECK-NEXT: [[ENTRY:.*:]]2988// CHECK-NEXT: [[VCNT_V_I:%.*]] = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> [[A]])2989// CHECK-NEXT: ret <8 x i8> [[VCNT_V_I]]2990//2991uint8x8_t test_vcnt_u8(uint8x8_t a) {2992 return vcnt_u8(a);2993}2994 2995// CHECK-LABEL: define <8 x i8> @test_vcnt_s8(2996// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {2997// CHECK-NEXT: [[ENTRY:.*:]]2998// CHECK-NEXT: [[VCNT_V_I:%.*]] = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> [[A]])2999// CHECK-NEXT: ret <8 x i8> [[VCNT_V_I]]3000//3001int8x8_t test_vcnt_s8(int8x8_t a) {3002 return vcnt_s8(a);3003}3004 3005// CHECK-LABEL: define <8 x i8> @test_vcnt_p8(3006// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {3007// CHECK-NEXT: [[ENTRY:.*:]]3008// CHECK-NEXT: [[VCNT_V_I:%.*]] = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> [[A]])3009// CHECK-NEXT: ret <8 x i8> [[VCNT_V_I]]3010//3011poly8x8_t test_vcnt_p8(poly8x8_t a) {3012 return vcnt_p8(a);3013}3014 3015// CHECK-LABEL: define <16 x i8> @test_vcntq_u8(3016// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {3017// CHECK-NEXT: [[ENTRY:.*:]]3018// CHECK-NEXT: [[VCNTQ_V_I:%.*]] = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> [[A]])3019// CHECK-NEXT: ret <16 x i8> [[VCNTQ_V_I]]3020//3021uint8x16_t test_vcntq_u8(uint8x16_t a) {3022 return vcntq_u8(a);3023}3024 3025// CHECK-LABEL: define <16 x i8> @test_vcntq_s8(3026// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {3027// CHECK-NEXT: [[ENTRY:.*:]]3028// CHECK-NEXT: [[VCNTQ_V_I:%.*]] = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> [[A]])3029// CHECK-NEXT: ret <16 x i8> [[VCNTQ_V_I]]3030//3031int8x16_t test_vcntq_s8(int8x16_t a) {3032 return vcntq_s8(a);3033}3034 3035// CHECK-LABEL: define <16 x i8> @test_vcntq_p8(3036// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {3037// CHECK-NEXT: [[ENTRY:.*:]]3038// CHECK-NEXT: [[VCNTQ_V_I:%.*]] = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> [[A]])3039// CHECK-NEXT: ret <16 x i8> [[VCNTQ_V_I]]3040//3041poly8x16_t test_vcntq_p8(poly8x16_t a) {3042 return vcntq_p8(a);3043}3044 3045// CHECK-LABEL: define <16 x i8> @test_vcombine_s8(3046// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {3047// CHECK-NEXT: [[ENTRY:.*:]]3048// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3049// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]3050//3051int8x16_t test_vcombine_s8(int8x8_t a, int8x8_t b) {3052 return vcombine_s8(a, b);3053}3054 3055// CHECK-LABEL: define <8 x i16> @test_vcombine_s16(3056// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {3057// CHECK-NEXT: [[ENTRY:.*:]]3058// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[B]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3059// CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]]3060//3061int16x8_t test_vcombine_s16(int16x4_t a, int16x4_t b) {3062 return vcombine_s16(a, b);3063}3064 3065// CHECK-LABEL: define <4 x i32> @test_vcombine_s32(3066// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {3067// CHECK-NEXT: [[ENTRY:.*:]]3068// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> [[B]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3069// CHECK-NEXT: ret <4 x i32> [[SHUFFLE_I]]3070//3071int32x4_t test_vcombine_s32(int32x2_t a, int32x2_t b) {3072 return vcombine_s32(a, b);3073}3074 3075// CHECK-LABEL: define <2 x i64> @test_vcombine_s64(3076// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {3077// CHECK-NEXT: [[ENTRY:.*:]]3078// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> [[A]], <1 x i64> [[B]], <2 x i32> <i32 0, i32 1>3079// CHECK-NEXT: ret <2 x i64> [[SHUFFLE_I]]3080//3081int64x2_t test_vcombine_s64(int64x1_t a, int64x1_t b) {3082 return vcombine_s64(a, b);3083}3084 3085// CHECK-LABEL: define <8 x half> @test_vcombine_f16(3086// CHECK-SAME: <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {3087// CHECK-NEXT: [[ENTRY:.*:]]3088// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> [[A]], <4 x half> [[B]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3089// CHECK-NEXT: ret <8 x half> [[SHUFFLE_I]]3090//3091float16x8_t test_vcombine_f16(float16x4_t a, float16x4_t b) {3092 return vcombine_f16(a, b);3093}3094 3095// CHECK-LABEL: define <4 x float> @test_vcombine_f32(3096// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {3097// CHECK-NEXT: [[ENTRY:.*:]]3098// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x float> [[A]], <2 x float> [[B]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3099// CHECK-NEXT: ret <4 x float> [[SHUFFLE_I]]3100//3101float32x4_t test_vcombine_f32(float32x2_t a, float32x2_t b) {3102 return vcombine_f32(a, b);3103}3104 3105// CHECK-LABEL: define <16 x i8> @test_vcombine_u8(3106// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {3107// CHECK-NEXT: [[ENTRY:.*:]]3108// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3109// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]3110//3111uint8x16_t test_vcombine_u8(uint8x8_t a, uint8x8_t b) {3112 return vcombine_u8(a, b);3113}3114 3115// CHECK-LABEL: define <8 x i16> @test_vcombine_u16(3116// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {3117// CHECK-NEXT: [[ENTRY:.*:]]3118// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[B]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3119// CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]]3120//3121uint16x8_t test_vcombine_u16(uint16x4_t a, uint16x4_t b) {3122 return vcombine_u16(a, b);3123}3124 3125// CHECK-LABEL: define <4 x i32> @test_vcombine_u32(3126// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {3127// CHECK-NEXT: [[ENTRY:.*:]]3128// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> [[B]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3129// CHECK-NEXT: ret <4 x i32> [[SHUFFLE_I]]3130//3131uint32x4_t test_vcombine_u32(uint32x2_t a, uint32x2_t b) {3132 return vcombine_u32(a, b);3133}3134 3135// CHECK-LABEL: define <2 x i64> @test_vcombine_u64(3136// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {3137// CHECK-NEXT: [[ENTRY:.*:]]3138// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> [[A]], <1 x i64> [[B]], <2 x i32> <i32 0, i32 1>3139// CHECK-NEXT: ret <2 x i64> [[SHUFFLE_I]]3140//3141uint64x2_t test_vcombine_u64(uint64x1_t a, uint64x1_t b) {3142 return vcombine_u64(a, b);3143}3144 3145// CHECK-LABEL: define <16 x i8> @test_vcombine_p8(3146// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {3147// CHECK-NEXT: [[ENTRY:.*:]]3148// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3149// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]3150//3151poly8x16_t test_vcombine_p8(poly8x8_t a, poly8x8_t b) {3152 return vcombine_p8(a, b);3153}3154 3155// CHECK-LABEL: define <8 x i16> @test_vcombine_p16(3156// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {3157// CHECK-NEXT: [[ENTRY:.*:]]3158// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[B]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3159// CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]]3160//3161poly16x8_t test_vcombine_p16(poly16x4_t a, poly16x4_t b) {3162 return vcombine_p16(a, b);3163}3164 3165// CHECK-LABEL: define <8 x i8> @test_vcreate_s8(3166// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3167// CHECK-NEXT: [[ENTRY:.*:]]3168// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <8 x i8>3169// CHECK-NEXT: [[VCLZ_V_I:%.*]] = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> [[TMP0]], i1 false)3170// CHECK-NEXT: ret <8 x i8> [[VCLZ_V_I]]3171//3172int8x8_t test_vcreate_s8(uint64_t a) {3173 return vclz_s8(vcreate_s8(a));3174}3175 3176// CHECK-LABEL: define <4 x i16> @test_vcreate_imm(3177// CHECK-SAME: ) #[[ATTR0]] {3178// CHECK-NEXT: [[ENTRY:.*:]]3179// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 0 to <4 x i16>3180// CHECK-NEXT: ret <4 x i16> [[TMP0]]3181//3182int16x4_t test_vcreate_imm(void) {3183 return vcreate_s16(0);3184}3185 3186// CHECK-LABEL: define <4 x i16> @test_vcreate_s16(3187// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3188// CHECK-NEXT: [[ENTRY:.*:]]3189// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <4 x i16>3190// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>3191// CHECK-NEXT: [[VCLZ_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>3192// CHECK-NEXT: [[VCLZ_V1_I:%.*]] = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> [[VCLZ_V_I]], i1 false)3193// CHECK-NEXT: [[VCLZ_V2_I:%.*]] = bitcast <4 x i16> [[VCLZ_V1_I]] to <8 x i8>3194// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VCLZ_V2_I]] to <4 x i16>3195// CHECK-NEXT: ret <4 x i16> [[TMP2]]3196//3197int16x4_t test_vcreate_s16(uint64_t a) {3198 return vclz_s16(vcreate_s16(a));3199}3200 3201// CHECK-LABEL: define <2 x i32> @test_vcreate_s32(3202// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3203// CHECK-NEXT: [[ENTRY:.*:]]3204// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <2 x i32>3205// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>3206// CHECK-NEXT: [[VCLZ_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>3207// CHECK-NEXT: [[VCLZ_V1_I:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[VCLZ_V_I]], i1 false)3208// CHECK-NEXT: [[VCLZ_V2_I:%.*]] = bitcast <2 x i32> [[VCLZ_V1_I]] to <8 x i8>3209// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VCLZ_V2_I]] to <2 x i32>3210// CHECK-NEXT: ret <2 x i32> [[TMP2]]3211//3212int32x2_t test_vcreate_s32(uint64_t a) {3213 return vclz_s32(vcreate_s32(a));3214}3215 3216// CHECK-LABEL: define <4 x half> @test_vcreate_f16(3217// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3218// CHECK-NEXT: [[ENTRY:.*:]]3219// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <4 x half>3220// CHECK-NEXT: ret <4 x half> [[TMP0]]3221//3222float16x4_t test_vcreate_f16(uint64_t a) {3223 return vcreate_f16(a);3224}3225 3226// CHECK-LABEL: define <2 x float> @test_vcreate_f32(3227// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3228// CHECK-NEXT: [[ENTRY:.*:]]3229// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <2 x float>3230// CHECK-NEXT: ret <2 x float> [[TMP0]]3231//3232float32x2_t test_vcreate_f32(uint64_t a) {3233 return vcreate_f32(a);3234}3235 3236// CHECK-LABEL: define <8 x i8> @test_vcreate_u8(3237// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3238// CHECK-NEXT: [[ENTRY:.*:]]3239// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <8 x i8>3240// CHECK-NEXT: [[VCLZ_V_I:%.*]] = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> [[TMP0]], i1 false)3241// CHECK-NEXT: ret <8 x i8> [[VCLZ_V_I]]3242//3243int8x8_t test_vcreate_u8(uint64_t a) {3244 return vclz_s8((int8x8_t)vcreate_u8(a));3245}3246 3247// CHECK-LABEL: define <4 x i16> @test_vcreate_u16(3248// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3249// CHECK-NEXT: [[ENTRY:.*:]]3250// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <4 x i16>3251// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>3252// CHECK-NEXT: [[VCLZ_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>3253// CHECK-NEXT: [[VCLZ_V1_I:%.*]] = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> [[VCLZ_V_I]], i1 false)3254// CHECK-NEXT: [[VCLZ_V2_I:%.*]] = bitcast <4 x i16> [[VCLZ_V1_I]] to <8 x i8>3255// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VCLZ_V2_I]] to <4 x i16>3256// CHECK-NEXT: ret <4 x i16> [[TMP2]]3257//3258int16x4_t test_vcreate_u16(uint64_t a) {3259 return vclz_s16((int16x4_t)vcreate_u16(a));3260}3261 3262// CHECK-LABEL: define <2 x i32> @test_vcreate_u32(3263// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3264// CHECK-NEXT: [[ENTRY:.*:]]3265// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <2 x i32>3266// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>3267// CHECK-NEXT: [[VCLZ_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>3268// CHECK-NEXT: [[VCLZ_V1_I:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[VCLZ_V_I]], i1 false)3269// CHECK-NEXT: [[VCLZ_V2_I:%.*]] = bitcast <2 x i32> [[VCLZ_V1_I]] to <8 x i8>3270// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VCLZ_V2_I]] to <2 x i32>3271// CHECK-NEXT: ret <2 x i32> [[TMP2]]3272//3273int32x2_t test_vcreate_u32(uint64_t a) {3274 return vclz_s32((int32x2_t)vcreate_u32(a));3275}3276 3277// CHECK-LABEL: define <1 x i64> @test_vcreate_u64(3278// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3279// CHECK-NEXT: [[ENTRY:.*:]]3280// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>3281// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[TMP0]], [[TMP0]]3282// CHECK-NEXT: ret <1 x i64> [[ADD_I]]3283//3284uint64x1_t test_vcreate_u64(uint64_t a) {3285 uint64x1_t tmp = vcreate_u64(a);3286 return vadd_u64(tmp, tmp);3287}3288 3289// CHECK-LABEL: define <8 x i8> @test_vcreate_p8(3290// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3291// CHECK-NEXT: [[ENTRY:.*:]]3292// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <8 x i8>3293// CHECK-NEXT: [[VCNT_V_I:%.*]] = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> [[TMP0]])3294// CHECK-NEXT: ret <8 x i8> [[VCNT_V_I]]3295//3296poly8x8_t test_vcreate_p8(uint64_t a) {3297 return vcnt_p8(vcreate_p8(a));3298}3299 3300// CHECK-LABEL: define <4 x i16> @test_vcreate_p16(3301// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3302// CHECK-NEXT: [[ENTRY:.*:]]3303// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <4 x i16>3304// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>3305// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>3306// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>3307// CHECK-NEXT: [[VBSL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]], <8 x i8> [[TMP3]])3308// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VBSL_V_I]] to <4 x i16>3309// CHECK-NEXT: ret <4 x i16> [[TMP4]]3310//3311poly16x4_t test_vcreate_p16(uint64_t a) {3312 poly16x4_t tmp = vcreate_p16(a);3313 return vbsl_p16((uint16x4_t)tmp, tmp, tmp);3314}3315 3316// CHECK-LABEL: define <1 x i64> @test_vcreate_s64(3317// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {3318// CHECK-NEXT: [[ENTRY:.*:]]3319// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>3320// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[TMP0]], [[TMP0]]3321// CHECK-NEXT: ret <1 x i64> [[ADD_I]]3322//3323int64x1_t test_vcreate_s64(uint64_t a) {3324 int64x1_t tmp = vcreate_s64(a);3325 return vadd_s64(tmp, tmp);3326}3327 3328// CHECK-LABEL: define <4 x half> @test_vcvt_f16_f32(3329// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {3330// CHECK-NEXT: [[ENTRY:.*:]]3331// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>3332// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>3333// CHECK-NEXT: [[VCVT_F16_F32_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>3334// CHECK-NEXT: [[VCVT_F16_F321_I:%.*]] = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> [[VCVT_F16_F32_I]])3335// CHECK-NEXT: [[VCVT_F16_F322_I:%.*]] = bitcast <4 x i16> [[VCVT_F16_F321_I]] to <8 x i8>3336// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VCVT_F16_F322_I]] to <4 x i16>3337// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <4 x half>3338// CHECK-NEXT: ret <4 x half> [[TMP3]]3339//3340float16x4_t test_vcvt_f16_f32(float32x4_t a) {3341 return vcvt_f16_f32(a);3342}3343 3344// CHECK-LABEL: define <2 x float> @test_vcvt_f32_s32(3345// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3346// CHECK-NEXT: [[ENTRY:.*:]]3347// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>3348// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>3349// CHECK-NEXT: [[VCVT_I:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x float>3350// CHECK-NEXT: ret <2 x float> [[VCVT_I]]3351//3352float32x2_t test_vcvt_f32_s32(int32x2_t a) {3353 return vcvt_f32_s32(a);3354}3355 3356// CHECK-LABEL: define <2 x float> @test_vcvt_f32_u32(3357// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3358// CHECK-NEXT: [[ENTRY:.*:]]3359// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>3360// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>3361// CHECK-NEXT: [[VCVT_I:%.*]] = uitofp <2 x i32> [[TMP1]] to <2 x float>3362// CHECK-NEXT: ret <2 x float> [[VCVT_I]]3363//3364float32x2_t test_vcvt_f32_u32(uint32x2_t a) {3365 return vcvt_f32_u32(a);3366}3367 3368// CHECK-LABEL: define <4 x float> @test_vcvtq_f32_s32(3369// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3370// CHECK-NEXT: [[ENTRY:.*:]]3371// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>3372// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>3373// CHECK-NEXT: [[VCVT_I:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>3374// CHECK-NEXT: ret <4 x float> [[VCVT_I]]3375//3376float32x4_t test_vcvtq_f32_s32(int32x4_t a) {3377 return vcvtq_f32_s32(a);3378}3379 3380// CHECK-LABEL: define <4 x float> @test_vcvtq_f32_u32(3381// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3382// CHECK-NEXT: [[ENTRY:.*:]]3383// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>3384// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>3385// CHECK-NEXT: [[VCVT_I:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x float>3386// CHECK-NEXT: ret <4 x float> [[VCVT_I]]3387//3388float32x4_t test_vcvtq_f32_u32(uint32x4_t a) {3389 return vcvtq_f32_u32(a);3390}3391 3392// CHECK-LABEL: define <4 x float> @test_vcvt_f32_f16(3393// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {3394// CHECK-NEXT: [[ENTRY:.*:]]3395// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>3396// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>3397// CHECK-NEXT: [[VCVT_F32_F16_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>3398// CHECK-NEXT: [[VCVT_F32_F161_I:%.*]] = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> [[VCVT_F32_F16_I]])3399// CHECK-NEXT: [[VCVT_F32_F162_I:%.*]] = bitcast <4 x float> [[VCVT_F32_F161_I]] to <16 x i8>3400// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VCVT_F32_F162_I]] to <4 x i32>3401// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float>3402// CHECK-NEXT: ret <4 x float> [[TMP3]]3403//3404float32x4_t test_vcvt_f32_f16(float16x4_t a) {3405 return vcvt_f32_f16(a);3406}3407 3408// CHECK-LABEL: define <2 x float> @test_vcvt_n_f32_s32(3409// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3410// CHECK-NEXT: [[ENTRY:.*:]]3411// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>3412// CHECK-NEXT: [[VCVT_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>3413// CHECK-NEXT: [[VCVT_N1:%.*]] = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> [[VCVT_N]], i32 1)3414// CHECK-NEXT: ret <2 x float> [[VCVT_N1]]3415//3416float32x2_t test_vcvt_n_f32_s32(int32x2_t a) {3417 return vcvt_n_f32_s32(a, 1);3418}3419 3420// CHECK-LABEL: define <2 x float> @test_vcvt_n_f32_u32(3421// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3422// CHECK-NEXT: [[ENTRY:.*:]]3423// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>3424// CHECK-NEXT: [[VCVT_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>3425// CHECK-NEXT: [[VCVT_N1:%.*]] = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> [[VCVT_N]], i32 1)3426// CHECK-NEXT: ret <2 x float> [[VCVT_N1]]3427//3428float32x2_t test_vcvt_n_f32_u32(uint32x2_t a) {3429 return vcvt_n_f32_u32(a, 1);3430}3431 3432// CHECK-LABEL: define <4 x float> @test_vcvtq_n_f32_s32(3433// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3434// CHECK-NEXT: [[ENTRY:.*:]]3435// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>3436// CHECK-NEXT: [[VCVT_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>3437// CHECK-NEXT: [[VCVT_N1:%.*]] = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> [[VCVT_N]], i32 3)3438// CHECK-NEXT: ret <4 x float> [[VCVT_N1]]3439//3440float32x4_t test_vcvtq_n_f32_s32(int32x4_t a) {3441 return vcvtq_n_f32_s32(a, 3);3442}3443 3444// CHECK-LABEL: define <4 x float> @test_vcvtq_n_f32_u32(3445// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3446// CHECK-NEXT: [[ENTRY:.*:]]3447// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>3448// CHECK-NEXT: [[VCVT_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>3449// CHECK-NEXT: [[VCVT_N1:%.*]] = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> [[VCVT_N]], i32 3)3450// CHECK-NEXT: ret <4 x float> [[VCVT_N1]]3451//3452float32x4_t test_vcvtq_n_f32_u32(uint32x4_t a) {3453 return vcvtq_n_f32_u32(a, 3);3454}3455 3456// CHECK-LABEL: define <2 x i32> @test_vcvt_n_s32_f32(3457// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {3458// CHECK-NEXT: [[ENTRY:.*:]]3459// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>3460// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>3461// CHECK-NEXT: [[VCVT_N:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>3462// CHECK-NEXT: [[VCVT_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> [[VCVT_N]], i32 1)3463// CHECK-NEXT: ret <2 x i32> [[VCVT_N1]]3464//3465int32x2_t test_vcvt_n_s32_f32(float32x2_t a) {3466 return vcvt_n_s32_f32(a, 1);3467}3468 3469// CHECK-LABEL: define <4 x i32> @test_vcvtq_n_s32_f32(3470// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {3471// CHECK-NEXT: [[ENTRY:.*:]]3472// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>3473// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>3474// CHECK-NEXT: [[VCVT_N:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>3475// CHECK-NEXT: [[VCVT_N1:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> [[VCVT_N]], i32 3)3476// CHECK-NEXT: ret <4 x i32> [[VCVT_N1]]3477//3478int32x4_t test_vcvtq_n_s32_f32(float32x4_t a) {3479 return vcvtq_n_s32_f32(a, 3);3480}3481 3482// CHECK-LABEL: define <2 x i32> @test_vcvt_n_u32_f32(3483// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {3484// CHECK-NEXT: [[ENTRY:.*:]]3485// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>3486// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>3487// CHECK-NEXT: [[VCVT_N:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>3488// CHECK-NEXT: [[VCVT_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> [[VCVT_N]], i32 1)3489// CHECK-NEXT: ret <2 x i32> [[VCVT_N1]]3490//3491uint32x2_t test_vcvt_n_u32_f32(float32x2_t a) {3492 return vcvt_n_u32_f32(a, 1);3493}3494 3495// CHECK-LABEL: define <4 x i32> @test_vcvtq_n_u32_f32(3496// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {3497// CHECK-NEXT: [[ENTRY:.*:]]3498// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>3499// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>3500// CHECK-NEXT: [[VCVT_N:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>3501// CHECK-NEXT: [[VCVT_N1:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> [[VCVT_N]], i32 3)3502// CHECK-NEXT: ret <4 x i32> [[VCVT_N1]]3503//3504uint32x4_t test_vcvtq_n_u32_f32(float32x4_t a) {3505 return vcvtq_n_u32_f32(a, 3);3506}3507 3508// CHECK-LABEL: define <2 x i32> @test_vcvt_s32_f32(3509// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {3510// CHECK-NEXT: [[ENTRY:.*:]]3511// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>3512// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>3513// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>3514// CHECK-NEXT: [[VCVT_I:%.*]] = fptosi <2 x float> [[TMP2]] to <2 x i32>3515// CHECK-NEXT: ret <2 x i32> [[VCVT_I]]3516//3517int32x2_t test_vcvt_s32_f32(float32x2_t a) {3518 return vcvt_s32_f32(a);3519}3520 3521// CHECK-LABEL: define <4 x i32> @test_vcvtq_s32_f32(3522// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {3523// CHECK-NEXT: [[ENTRY:.*:]]3524// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>3525// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>3526// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>3527// CHECK-NEXT: [[VCVT_I:%.*]] = fptosi <4 x float> [[TMP2]] to <4 x i32>3528// CHECK-NEXT: ret <4 x i32> [[VCVT_I]]3529//3530int32x4_t test_vcvtq_s32_f32(float32x4_t a) {3531 return vcvtq_s32_f32(a);3532}3533 3534// CHECK-LABEL: define <2 x i32> @test_vcvt_u32_f32(3535// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {3536// CHECK-NEXT: [[ENTRY:.*:]]3537// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>3538// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>3539// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>3540// CHECK-NEXT: [[VCVT_I:%.*]] = fptoui <2 x float> [[TMP2]] to <2 x i32>3541// CHECK-NEXT: ret <2 x i32> [[VCVT_I]]3542//3543uint32x2_t test_vcvt_u32_f32(float32x2_t a) {3544 return vcvt_u32_f32(a);3545}3546 3547// CHECK-LABEL: define <4 x i32> @test_vcvtq_u32_f32(3548// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {3549// CHECK-NEXT: [[ENTRY:.*:]]3550// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>3551// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>3552// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>3553// CHECK-NEXT: [[VCVT_I:%.*]] = fptoui <4 x float> [[TMP2]] to <4 x i32>3554// CHECK-NEXT: ret <4 x i32> [[VCVT_I]]3555//3556uint32x4_t test_vcvtq_u32_f32(float32x4_t a) {3557 return vcvtq_u32_f32(a);3558}3559 3560// CHECK-LABEL: define <8 x i8> @test_vdup_lane_u8(3561// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {3562// CHECK-NEXT: [[ENTRY:.*:]]3563// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>3564// CHECK-NEXT: ret <8 x i8> [[LANE]]3565//3566uint8x8_t test_vdup_lane_u8(uint8x8_t a) {3567 return vdup_lane_u8(a, 7);3568}3569 3570// CHECK-LABEL: define <4 x i16> @test_vdup_lane_u16(3571// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {3572// CHECK-NEXT: [[ENTRY:.*:]]3573// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>3574// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>3575// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>3576// CHECK-NEXT: ret <4 x i16> [[LANE]]3577//3578uint16x4_t test_vdup_lane_u16(uint16x4_t a) {3579 return vdup_lane_u16(a, 3);3580}3581 3582// CHECK-LABEL: define <2 x i32> @test_vdup_lane_u32(3583// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3584// CHECK-NEXT: [[ENTRY:.*:]]3585// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>3586// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>3587// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>3588// CHECK-NEXT: ret <2 x i32> [[LANE]]3589//3590uint32x2_t test_vdup_lane_u32(uint32x2_t a) {3591 return vdup_lane_u32(a, 1);3592}3593 3594// CHECK-LABEL: define <8 x i8> @test_vdup_lane_s8(3595// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {3596// CHECK-NEXT: [[ENTRY:.*:]]3597// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>3598// CHECK-NEXT: ret <8 x i8> [[LANE]]3599//3600int8x8_t test_vdup_lane_s8(int8x8_t a) {3601 return vdup_lane_s8(a, 7);3602}3603 3604// CHECK-LABEL: define <4 x i16> @test_vdup_lane_s16(3605// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {3606// CHECK-NEXT: [[ENTRY:.*:]]3607// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>3608// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>3609// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>3610// CHECK-NEXT: ret <4 x i16> [[LANE]]3611//3612int16x4_t test_vdup_lane_s16(int16x4_t a) {3613 return vdup_lane_s16(a, 3);3614}3615 3616// CHECK-LABEL: define <2 x i32> @test_vdup_lane_s32(3617// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3618// CHECK-NEXT: [[ENTRY:.*:]]3619// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>3620// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>3621// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>3622// CHECK-NEXT: ret <2 x i32> [[LANE]]3623//3624int32x2_t test_vdup_lane_s32(int32x2_t a) {3625 return vdup_lane_s32(a, 1);3626}3627 3628// CHECK-LABEL: define <8 x i8> @test_vdup_lane_p8(3629// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {3630// CHECK-NEXT: [[ENTRY:.*:]]3631// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>3632// CHECK-NEXT: ret <8 x i8> [[LANE]]3633//3634poly8x8_t test_vdup_lane_p8(poly8x8_t a) {3635 return vdup_lane_p8(a, 7);3636}3637 3638// CHECK-LABEL: define <4 x i16> @test_vdup_lane_p16(3639// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {3640// CHECK-NEXT: [[ENTRY:.*:]]3641// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>3642// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>3643// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>3644// CHECK-NEXT: ret <4 x i16> [[LANE]]3645//3646poly16x4_t test_vdup_lane_p16(poly16x4_t a) {3647 return vdup_lane_p16(a, 3);3648}3649 3650// CHECK-LABEL: define <2 x float> @test_vdup_lane_f32(3651// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {3652// CHECK-NEXT: [[ENTRY:.*:]]3653// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>3654// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>3655// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>3656// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <2 x i32> <i32 1, i32 1>3657// CHECK-NEXT: ret <2 x float> [[LANE]]3658//3659float32x2_t test_vdup_lane_f32(float32x2_t a) {3660 return vdup_lane_f32(a, 1);3661}3662 3663// CHECK-LABEL: define <16 x i8> @test_vdupq_lane_u8(3664// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {3665// CHECK-NEXT: [[ENTRY:.*:]]3666// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <16 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>3667// CHECK-NEXT: ret <16 x i8> [[LANE]]3668//3669uint8x16_t test_vdupq_lane_u8(uint8x8_t a) {3670 return vdupq_lane_u8(a, 7);3671}3672 3673// CHECK-LABEL: define <8 x i16> @test_vdupq_lane_u16(3674// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {3675// CHECK-NEXT: [[ENTRY:.*:]]3676// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>3677// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>3678// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>3679// CHECK-NEXT: ret <8 x i16> [[LANE]]3680//3681uint16x8_t test_vdupq_lane_u16(uint16x4_t a) {3682 return vdupq_lane_u16(a, 3);3683}3684 3685// CHECK-LABEL: define <4 x i32> @test_vdupq_lane_u32(3686// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3687// CHECK-NEXT: [[ENTRY:.*:]]3688// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>3689// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>3690// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>3691// CHECK-NEXT: ret <4 x i32> [[LANE]]3692//3693uint32x4_t test_vdupq_lane_u32(uint32x2_t a) {3694 return vdupq_lane_u32(a, 1);3695}3696 3697// CHECK-LABEL: define <16 x i8> @test_vdupq_lane_s8(3698// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {3699// CHECK-NEXT: [[ENTRY:.*:]]3700// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <16 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>3701// CHECK-NEXT: ret <16 x i8> [[LANE]]3702//3703int8x16_t test_vdupq_lane_s8(int8x8_t a) {3704 return vdupq_lane_s8(a, 7);3705}3706 3707// CHECK-LABEL: define <8 x i16> @test_vdupq_lane_s16(3708// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {3709// CHECK-NEXT: [[ENTRY:.*:]]3710// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>3711// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>3712// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>3713// CHECK-NEXT: ret <8 x i16> [[LANE]]3714//3715int16x8_t test_vdupq_lane_s16(int16x4_t a) {3716 return vdupq_lane_s16(a, 3);3717}3718 3719// CHECK-LABEL: define <4 x i32> @test_vdupq_lane_s32(3720// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {3721// CHECK-NEXT: [[ENTRY:.*:]]3722// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>3723// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>3724// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>3725// CHECK-NEXT: ret <4 x i32> [[LANE]]3726//3727int32x4_t test_vdupq_lane_s32(int32x2_t a) {3728 return vdupq_lane_s32(a, 1);3729}3730 3731// CHECK-LABEL: define <16 x i8> @test_vdupq_lane_p8(3732// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {3733// CHECK-NEXT: [[ENTRY:.*:]]3734// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <16 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>3735// CHECK-NEXT: ret <16 x i8> [[LANE]]3736//3737poly8x16_t test_vdupq_lane_p8(poly8x8_t a) {3738 return vdupq_lane_p8(a, 7);3739}3740 3741// CHECK-LABEL: define <8 x i16> @test_vdupq_lane_p16(3742// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {3743// CHECK-NEXT: [[ENTRY:.*:]]3744// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>3745// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>3746// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>3747// CHECK-NEXT: ret <8 x i16> [[LANE]]3748//3749poly16x8_t test_vdupq_lane_p16(poly16x4_t a) {3750 return vdupq_lane_p16(a, 3);3751}3752 3753// CHECK-LABEL: define <4 x float> @test_vdupq_lane_f32(3754// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {3755// CHECK-NEXT: [[ENTRY:.*:]]3756// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>3757// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>3758// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>3759// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>3760// CHECK-NEXT: ret <4 x float> [[LANE]]3761//3762float32x4_t test_vdupq_lane_f32(float32x2_t a) {3763 return vdupq_lane_f32(a, 1);3764}3765 3766// CHECK-LABEL: define <1 x i64> @test_vdup_lane_s64(3767// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {3768// CHECK-NEXT: [[ENTRY:.*:]]3769// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3770// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3771// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <1 x i32> zeroinitializer3772// CHECK-NEXT: ret <1 x i64> [[LANE]]3773//3774int64x1_t test_vdup_lane_s64(int64x1_t a) {3775 return vdup_lane_s64(a, 0);3776}3777 3778// CHECK-LABEL: define <1 x i64> @test_vdup_lane_u64(3779// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {3780// CHECK-NEXT: [[ENTRY:.*:]]3781// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3782// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3783// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <1 x i32> zeroinitializer3784// CHECK-NEXT: ret <1 x i64> [[LANE]]3785//3786uint64x1_t test_vdup_lane_u64(uint64x1_t a) {3787 return vdup_lane_u64(a, 0);3788}3789 3790// CHECK-LABEL: define <2 x i64> @test_vdupq_lane_s64(3791// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {3792// CHECK-NEXT: [[ENTRY:.*:]]3793// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3794// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3795// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <2 x i32> zeroinitializer3796// CHECK-NEXT: ret <2 x i64> [[LANE]]3797//3798int64x2_t test_vdupq_lane_s64(int64x1_t a) {3799 return vdupq_lane_s64(a, 0);3800}3801 3802// CHECK-LABEL: define <2 x i64> @test_vdupq_lane_u64(3803// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {3804// CHECK-NEXT: [[ENTRY:.*:]]3805// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>3806// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>3807// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <2 x i32> zeroinitializer3808// CHECK-NEXT: ret <2 x i64> [[LANE]]3809//3810uint64x2_t test_vdupq_lane_u64(uint64x1_t a) {3811 return vdupq_lane_u64(a, 0);3812}3813 3814// CHECK-LABEL: define <8 x i8> @test_vdup_n_u8(3815// CHECK-SAME: i8 noundef zeroext [[A:%.*]]) #[[ATTR0]] {3816// CHECK-NEXT: [[ENTRY:.*:]]3817// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i32 03818// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i8> [[VECINIT_I]], i8 [[A]], i32 13819// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i8> [[VECINIT1_I]], i8 [[A]], i32 23820// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i8> [[VECINIT2_I]], i8 [[A]], i32 33821// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i8> [[VECINIT3_I]], i8 [[A]], i32 43822// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i8> [[VECINIT4_I]], i8 [[A]], i32 53823// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i8> [[VECINIT5_I]], i8 [[A]], i32 63824// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i8> [[VECINIT6_I]], i8 [[A]], i32 73825// CHECK-NEXT: ret <8 x i8> [[VECINIT7_I]]3826//3827uint8x8_t test_vdup_n_u8(uint8_t a) {3828 return vdup_n_u8(a);3829}3830 3831// CHECK-LABEL: define <4 x i16> @test_vdup_n_u16(3832// CHECK-SAME: i16 noundef zeroext [[A:%.*]]) #[[ATTR0]] {3833// CHECK-NEXT: [[ENTRY:.*:]]3834// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i32 03835// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[A]], i32 13836// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[A]], i32 23837// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[A]], i32 33838// CHECK-NEXT: ret <4 x i16> [[VECINIT3_I]]3839//3840uint16x4_t test_vdup_n_u16(uint16_t a) {3841 return vdup_n_u16(a);3842}3843 3844// CHECK-LABEL: define <2 x i32> @test_vdup_n_u32(3845// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {3846// CHECK-NEXT: [[ENTRY:.*:]]3847// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i32 03848// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[A]], i32 13849// CHECK-NEXT: ret <2 x i32> [[VECINIT1_I]]3850//3851uint32x2_t test_vdup_n_u32(uint32_t a) {3852 return vdup_n_u32(a);3853}3854 3855// CHECK-LABEL: define <8 x i8> @test_vdup_n_s8(3856// CHECK-SAME: i8 noundef signext [[A:%.*]]) #[[ATTR0]] {3857// CHECK-NEXT: [[ENTRY:.*:]]3858// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i32 03859// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i8> [[VECINIT_I]], i8 [[A]], i32 13860// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i8> [[VECINIT1_I]], i8 [[A]], i32 23861// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i8> [[VECINIT2_I]], i8 [[A]], i32 33862// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i8> [[VECINIT3_I]], i8 [[A]], i32 43863// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i8> [[VECINIT4_I]], i8 [[A]], i32 53864// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i8> [[VECINIT5_I]], i8 [[A]], i32 63865// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i8> [[VECINIT6_I]], i8 [[A]], i32 73866// CHECK-NEXT: ret <8 x i8> [[VECINIT7_I]]3867//3868int8x8_t test_vdup_n_s8(int8_t a) {3869 return vdup_n_s8(a);3870}3871 3872// CHECK-LABEL: define <4 x i16> @test_vdup_n_s16(3873// CHECK-SAME: i16 noundef signext [[A:%.*]]) #[[ATTR0]] {3874// CHECK-NEXT: [[ENTRY:.*:]]3875// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i32 03876// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[A]], i32 13877// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[A]], i32 23878// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[A]], i32 33879// CHECK-NEXT: ret <4 x i16> [[VECINIT3_I]]3880//3881int16x4_t test_vdup_n_s16(int16_t a) {3882 return vdup_n_s16(a);3883}3884 3885// CHECK-LABEL: define <2 x i32> @test_vdup_n_s32(3886// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {3887// CHECK-NEXT: [[ENTRY:.*:]]3888// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i32 03889// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[A]], i32 13890// CHECK-NEXT: ret <2 x i32> [[VECINIT1_I]]3891//3892int32x2_t test_vdup_n_s32(int32_t a) {3893 return vdup_n_s32(a);3894}3895 3896// CHECK-LABEL: define <8 x i8> @test_vdup_n_p8(3897// CHECK-SAME: i8 noundef signext [[A:%.*]]) #[[ATTR0]] {3898// CHECK-NEXT: [[ENTRY:.*:]]3899// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i32 03900// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i8> [[VECINIT_I]], i8 [[A]], i32 13901// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i8> [[VECINIT1_I]], i8 [[A]], i32 23902// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i8> [[VECINIT2_I]], i8 [[A]], i32 33903// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i8> [[VECINIT3_I]], i8 [[A]], i32 43904// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i8> [[VECINIT4_I]], i8 [[A]], i32 53905// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i8> [[VECINIT5_I]], i8 [[A]], i32 63906// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i8> [[VECINIT6_I]], i8 [[A]], i32 73907// CHECK-NEXT: ret <8 x i8> [[VECINIT7_I]]3908//3909poly8x8_t test_vdup_n_p8(poly8_t a) {3910 return vdup_n_p8(a);3911}3912 3913// CHECK-LABEL: define <4 x i16> @test_vdup_n_p16(3914// CHECK-SAME: i16 noundef signext [[A:%.*]]) #[[ATTR0]] {3915// CHECK-NEXT: [[ENTRY:.*:]]3916// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i32 03917// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[A]], i32 13918// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[A]], i32 23919// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[A]], i32 33920// CHECK-NEXT: ret <4 x i16> [[VECINIT3_I]]3921//3922poly16x4_t test_vdup_n_p16(poly16_t a) {3923 return vdup_n_p16(a);3924}3925 3926// CHECK-LABEL: define <4 x half> @test_vdup_n_f16(3927// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {3928// CHECK-NEXT: [[ENTRY:.*:]]3929// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A]], align 23930// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x half> poison, half [[TMP0]], i32 03931// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[TMP0]], i32 13932// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[TMP0]], i32 23933// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[TMP0]], i32 33934// CHECK-NEXT: ret <4 x half> [[VECINIT3]]3935//3936float16x4_t test_vdup_n_f16(float16_t *a) {3937 return vdup_n_f16(*a);3938}3939 3940// CHECK-LABEL: define <2 x float> @test_vdup_n_f32(3941// CHECK-SAME: float noundef [[A:%.*]]) #[[ATTR0]] {3942// CHECK-NEXT: [[ENTRY:.*:]]3943// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x float> poison, float [[A]], i32 03944// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float [[A]], i32 13945// CHECK-NEXT: ret <2 x float> [[VECINIT1_I]]3946//3947float32x2_t test_vdup_n_f32(float32_t a) {3948 return vdup_n_f32(a);3949}3950 3951// CHECK-LABEL: define <16 x i8> @test_vdupq_n_u8(3952// CHECK-SAME: i8 noundef zeroext [[A:%.*]]) #[[ATTR0]] {3953// CHECK-NEXT: [[ENTRY:.*:]]3954// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> poison, i8 [[A]], i32 03955// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <16 x i8> [[VECINIT_I]], i8 [[A]], i32 13956// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <16 x i8> [[VECINIT1_I]], i8 [[A]], i32 23957// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <16 x i8> [[VECINIT2_I]], i8 [[A]], i32 33958// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <16 x i8> [[VECINIT3_I]], i8 [[A]], i32 43959// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <16 x i8> [[VECINIT4_I]], i8 [[A]], i32 53960// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <16 x i8> [[VECINIT5_I]], i8 [[A]], i32 63961// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <16 x i8> [[VECINIT6_I]], i8 [[A]], i32 73962// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <16 x i8> [[VECINIT7_I]], i8 [[A]], i32 83963// CHECK-NEXT: [[VECINIT9_I:%.*]] = insertelement <16 x i8> [[VECINIT8_I]], i8 [[A]], i32 93964// CHECK-NEXT: [[VECINIT10_I:%.*]] = insertelement <16 x i8> [[VECINIT9_I]], i8 [[A]], i32 103965// CHECK-NEXT: [[VECINIT11_I:%.*]] = insertelement <16 x i8> [[VECINIT10_I]], i8 [[A]], i32 113966// CHECK-NEXT: [[VECINIT12_I:%.*]] = insertelement <16 x i8> [[VECINIT11_I]], i8 [[A]], i32 123967// CHECK-NEXT: [[VECINIT13_I:%.*]] = insertelement <16 x i8> [[VECINIT12_I]], i8 [[A]], i32 133968// CHECK-NEXT: [[VECINIT14_I:%.*]] = insertelement <16 x i8> [[VECINIT13_I]], i8 [[A]], i32 143969// CHECK-NEXT: [[VECINIT15_I:%.*]] = insertelement <16 x i8> [[VECINIT14_I]], i8 [[A]], i32 153970// CHECK-NEXT: ret <16 x i8> [[VECINIT15_I]]3971//3972uint8x16_t test_vdupq_n_u8(uint8_t a) {3973 return vdupq_n_u8(a);3974}3975 3976// CHECK-LABEL: define <8 x i16> @test_vdupq_n_u16(3977// CHECK-SAME: i16 noundef zeroext [[A:%.*]]) #[[ATTR0]] {3978// CHECK-NEXT: [[ENTRY:.*:]]3979// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[A]], i32 03980// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[A]], i32 13981// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[A]], i32 23982// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[A]], i32 33983// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[A]], i32 43984// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[A]], i32 53985// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[A]], i32 63986// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[A]], i32 73987// CHECK-NEXT: ret <8 x i16> [[VECINIT7_I]]3988//3989uint16x8_t test_vdupq_n_u16(uint16_t a) {3990 return vdupq_n_u16(a);3991}3992 3993// CHECK-LABEL: define <4 x i32> @test_vdupq_n_u32(3994// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {3995// CHECK-NEXT: [[ENTRY:.*:]]3996// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 03997// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[A]], i32 13998// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[A]], i32 23999// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[A]], i32 34000// CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]]4001//4002uint32x4_t test_vdupq_n_u32(uint32_t a) {4003 return vdupq_n_u32(a);4004}4005 4006// CHECK-LABEL: define <16 x i8> @test_vdupq_n_s8(4007// CHECK-SAME: i8 noundef signext [[A:%.*]]) #[[ATTR0]] {4008// CHECK-NEXT: [[ENTRY:.*:]]4009// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> poison, i8 [[A]], i32 04010// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <16 x i8> [[VECINIT_I]], i8 [[A]], i32 14011// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <16 x i8> [[VECINIT1_I]], i8 [[A]], i32 24012// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <16 x i8> [[VECINIT2_I]], i8 [[A]], i32 34013// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <16 x i8> [[VECINIT3_I]], i8 [[A]], i32 44014// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <16 x i8> [[VECINIT4_I]], i8 [[A]], i32 54015// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <16 x i8> [[VECINIT5_I]], i8 [[A]], i32 64016// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <16 x i8> [[VECINIT6_I]], i8 [[A]], i32 74017// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <16 x i8> [[VECINIT7_I]], i8 [[A]], i32 84018// CHECK-NEXT: [[VECINIT9_I:%.*]] = insertelement <16 x i8> [[VECINIT8_I]], i8 [[A]], i32 94019// CHECK-NEXT: [[VECINIT10_I:%.*]] = insertelement <16 x i8> [[VECINIT9_I]], i8 [[A]], i32 104020// CHECK-NEXT: [[VECINIT11_I:%.*]] = insertelement <16 x i8> [[VECINIT10_I]], i8 [[A]], i32 114021// CHECK-NEXT: [[VECINIT12_I:%.*]] = insertelement <16 x i8> [[VECINIT11_I]], i8 [[A]], i32 124022// CHECK-NEXT: [[VECINIT13_I:%.*]] = insertelement <16 x i8> [[VECINIT12_I]], i8 [[A]], i32 134023// CHECK-NEXT: [[VECINIT14_I:%.*]] = insertelement <16 x i8> [[VECINIT13_I]], i8 [[A]], i32 144024// CHECK-NEXT: [[VECINIT15_I:%.*]] = insertelement <16 x i8> [[VECINIT14_I]], i8 [[A]], i32 154025// CHECK-NEXT: ret <16 x i8> [[VECINIT15_I]]4026//4027int8x16_t test_vdupq_n_s8(int8_t a) {4028 return vdupq_n_s8(a);4029}4030 4031// CHECK-LABEL: define <8 x i16> @test_vdupq_n_s16(4032// CHECK-SAME: i16 noundef signext [[A:%.*]]) #[[ATTR0]] {4033// CHECK-NEXT: [[ENTRY:.*:]]4034// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[A]], i32 04035// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[A]], i32 14036// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[A]], i32 24037// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[A]], i32 34038// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[A]], i32 44039// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[A]], i32 54040// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[A]], i32 64041// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[A]], i32 74042// CHECK-NEXT: ret <8 x i16> [[VECINIT7_I]]4043//4044int16x8_t test_vdupq_n_s16(int16_t a) {4045 return vdupq_n_s16(a);4046}4047 4048// CHECK-LABEL: define <4 x i32> @test_vdupq_n_s32(4049// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {4050// CHECK-NEXT: [[ENTRY:.*:]]4051// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 04052// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[A]], i32 14053// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[A]], i32 24054// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[A]], i32 34055// CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]]4056//4057int32x4_t test_vdupq_n_s32(int32_t a) {4058 return vdupq_n_s32(a);4059}4060 4061// CHECK-LABEL: define <16 x i8> @test_vdupq_n_p8(4062// CHECK-SAME: i8 noundef signext [[A:%.*]]) #[[ATTR0]] {4063// CHECK-NEXT: [[ENTRY:.*:]]4064// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> poison, i8 [[A]], i32 04065// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <16 x i8> [[VECINIT_I]], i8 [[A]], i32 14066// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <16 x i8> [[VECINIT1_I]], i8 [[A]], i32 24067// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <16 x i8> [[VECINIT2_I]], i8 [[A]], i32 34068// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <16 x i8> [[VECINIT3_I]], i8 [[A]], i32 44069// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <16 x i8> [[VECINIT4_I]], i8 [[A]], i32 54070// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <16 x i8> [[VECINIT5_I]], i8 [[A]], i32 64071// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <16 x i8> [[VECINIT6_I]], i8 [[A]], i32 74072// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <16 x i8> [[VECINIT7_I]], i8 [[A]], i32 84073// CHECK-NEXT: [[VECINIT9_I:%.*]] = insertelement <16 x i8> [[VECINIT8_I]], i8 [[A]], i32 94074// CHECK-NEXT: [[VECINIT10_I:%.*]] = insertelement <16 x i8> [[VECINIT9_I]], i8 [[A]], i32 104075// CHECK-NEXT: [[VECINIT11_I:%.*]] = insertelement <16 x i8> [[VECINIT10_I]], i8 [[A]], i32 114076// CHECK-NEXT: [[VECINIT12_I:%.*]] = insertelement <16 x i8> [[VECINIT11_I]], i8 [[A]], i32 124077// CHECK-NEXT: [[VECINIT13_I:%.*]] = insertelement <16 x i8> [[VECINIT12_I]], i8 [[A]], i32 134078// CHECK-NEXT: [[VECINIT14_I:%.*]] = insertelement <16 x i8> [[VECINIT13_I]], i8 [[A]], i32 144079// CHECK-NEXT: [[VECINIT15_I:%.*]] = insertelement <16 x i8> [[VECINIT14_I]], i8 [[A]], i32 154080// CHECK-NEXT: ret <16 x i8> [[VECINIT15_I]]4081//4082poly8x16_t test_vdupq_n_p8(poly8_t a) {4083 return vdupq_n_p8(a);4084}4085 4086// CHECK-LABEL: define <8 x i16> @test_vdupq_n_p16(4087// CHECK-SAME: i16 noundef signext [[A:%.*]]) #[[ATTR0]] {4088// CHECK-NEXT: [[ENTRY:.*:]]4089// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[A]], i32 04090// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[A]], i32 14091// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[A]], i32 24092// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[A]], i32 34093// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[A]], i32 44094// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[A]], i32 54095// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[A]], i32 64096// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[A]], i32 74097// CHECK-NEXT: ret <8 x i16> [[VECINIT7_I]]4098//4099poly16x8_t test_vdupq_n_p16(poly16_t a) {4100 return vdupq_n_p16(a);4101}4102 4103// CHECK-LABEL: define <8 x half> @test_vdupq_n_f16(4104// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {4105// CHECK-NEXT: [[ENTRY:.*:]]4106// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A]], align 24107// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <8 x half> poison, half [[TMP0]], i32 04108// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[TMP0]], i32 14109// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[TMP0]], i32 24110// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[TMP0]], i32 34111// CHECK-NEXT: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[TMP0]], i32 44112// CHECK-NEXT: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[TMP0]], i32 54113// CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[TMP0]], i32 64114// CHECK-NEXT: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[TMP0]], i32 74115// CHECK-NEXT: ret <8 x half> [[VECINIT7]]4116//4117float16x8_t test_vdupq_n_f16(float16_t *a) {4118 return vdupq_n_f16(*a);4119}4120 4121// CHECK-LABEL: define <4 x float> @test_vdupq_n_f32(4122// CHECK-SAME: float noundef [[A:%.*]]) #[[ATTR0]] {4123// CHECK-NEXT: [[ENTRY:.*:]]4124// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[A]], i32 04125// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[A]], i32 14126// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[A]], i32 24127// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[A]], i32 34128// CHECK-NEXT: ret <4 x float> [[VECINIT3_I]]4129//4130float32x4_t test_vdupq_n_f32(float32_t a) {4131 return vdupq_n_f32(a);4132}4133 4134// CHECK-LABEL: define <1 x i64> @test_vdup_n_s64(4135// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {4136// CHECK-NEXT: [[ENTRY:.*:]]4137// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <1 x i64> poison, i64 [[A]], i32 04138// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[VECINIT_I]], [[VECINIT_I]]4139// CHECK-NEXT: ret <1 x i64> [[ADD_I]]4140//4141int64x1_t test_vdup_n_s64(int64_t a) {4142 int64x1_t tmp = vdup_n_s64(a);4143 return vadd_s64(tmp, tmp);4144}4145 4146// CHECK-LABEL: define <1 x i64> @test_vdup_n_u64(4147// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {4148// CHECK-NEXT: [[ENTRY:.*:]]4149// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <1 x i64> poison, i64 [[A]], i32 04150// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[VECINIT_I]], [[VECINIT_I]]4151// CHECK-NEXT: ret <1 x i64> [[ADD_I]]4152//4153int64x1_t test_vdup_n_u64(uint64_t a) {4154 int64x1_t tmp = (int64x1_t)vdup_n_u64(a);4155 return vadd_s64(tmp, tmp);4156}4157 4158// CHECK-LABEL: define <2 x i64> @test_vdupq_n_s64(4159// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {4160// CHECK-NEXT: [[ENTRY:.*:]]4161// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 [[A]], i32 04162// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 [[A]], i32 14163// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[VECINIT1_I]], [[VECINIT1_I]]4164// CHECK-NEXT: ret <2 x i64> [[ADD_I]]4165//4166int64x2_t test_vdupq_n_s64(int64_t a) {4167 int64x2_t tmp = vdupq_n_s64(a);4168 return vaddq_s64(tmp, tmp);4169}4170 4171// CHECK-LABEL: define <2 x i64> @test_vdupq_n_u64(4172// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {4173// CHECK-NEXT: [[ENTRY:.*:]]4174// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 [[A]], i32 04175// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 [[A]], i32 14176// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[VECINIT1_I]], [[VECINIT1_I]]4177// CHECK-NEXT: ret <2 x i64> [[ADD_I]]4178//4179uint64x2_t test_vdupq_n_u64(uint64_t a) {4180 uint64x2_t tmp = vdupq_n_u64(a);4181 return vaddq_u64(tmp, tmp);4182}4183 4184// CHECK-LABEL: define <8 x i8> @test_veor_s8(4185// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {4186// CHECK-NEXT: [[ENTRY:.*:]]4187// CHECK-NEXT: [[XOR_I:%.*]] = xor <8 x i8> [[A]], [[B]]4188// CHECK-NEXT: ret <8 x i8> [[XOR_I]]4189//4190int8x8_t test_veor_s8(int8x8_t a, int8x8_t b) {4191 return veor_s8(a, b);4192}4193 4194// CHECK-LABEL: define <4 x i16> @test_veor_s16(4195// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {4196// CHECK-NEXT: [[ENTRY:.*:]]4197// CHECK-NEXT: [[XOR_I:%.*]] = xor <4 x i16> [[A]], [[B]]4198// CHECK-NEXT: ret <4 x i16> [[XOR_I]]4199//4200int16x4_t test_veor_s16(int16x4_t a, int16x4_t b) {4201 return veor_s16(a, b);4202}4203 4204// CHECK-LABEL: define <2 x i32> @test_veor_s32(4205// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {4206// CHECK-NEXT: [[ENTRY:.*:]]4207// CHECK-NEXT: [[XOR_I:%.*]] = xor <2 x i32> [[A]], [[B]]4208// CHECK-NEXT: ret <2 x i32> [[XOR_I]]4209//4210int32x2_t test_veor_s32(int32x2_t a, int32x2_t b) {4211 return veor_s32(a, b);4212}4213 4214// CHECK-LABEL: define <1 x i64> @test_veor_s64(4215// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {4216// CHECK-NEXT: [[ENTRY:.*:]]4217// CHECK-NEXT: [[XOR_I:%.*]] = xor <1 x i64> [[A]], [[B]]4218// CHECK-NEXT: ret <1 x i64> [[XOR_I]]4219//4220int64x1_t test_veor_s64(int64x1_t a, int64x1_t b) {4221 return veor_s64(a, b);4222}4223 4224// CHECK-LABEL: define <8 x i8> @test_veor_u8(4225// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {4226// CHECK-NEXT: [[ENTRY:.*:]]4227// CHECK-NEXT: [[XOR_I:%.*]] = xor <8 x i8> [[A]], [[B]]4228// CHECK-NEXT: ret <8 x i8> [[XOR_I]]4229//4230uint8x8_t test_veor_u8(uint8x8_t a, uint8x8_t b) {4231 return veor_u8(a, b);4232}4233 4234// CHECK-LABEL: define <4 x i16> @test_veor_u16(4235// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {4236// CHECK-NEXT: [[ENTRY:.*:]]4237// CHECK-NEXT: [[XOR_I:%.*]] = xor <4 x i16> [[A]], [[B]]4238// CHECK-NEXT: ret <4 x i16> [[XOR_I]]4239//4240uint16x4_t test_veor_u16(uint16x4_t a, uint16x4_t b) {4241 return veor_u16(a, b);4242}4243 4244// CHECK-LABEL: define <2 x i32> @test_veor_u32(4245// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {4246// CHECK-NEXT: [[ENTRY:.*:]]4247// CHECK-NEXT: [[XOR_I:%.*]] = xor <2 x i32> [[A]], [[B]]4248// CHECK-NEXT: ret <2 x i32> [[XOR_I]]4249//4250uint32x2_t test_veor_u32(uint32x2_t a, uint32x2_t b) {4251 return veor_u32(a, b);4252}4253 4254// CHECK-LABEL: define <1 x i64> @test_veor_u64(4255// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {4256// CHECK-NEXT: [[ENTRY:.*:]]4257// CHECK-NEXT: [[XOR_I:%.*]] = xor <1 x i64> [[A]], [[B]]4258// CHECK-NEXT: ret <1 x i64> [[XOR_I]]4259//4260uint64x1_t test_veor_u64(uint64x1_t a, uint64x1_t b) {4261 return veor_u64(a, b);4262}4263 4264// CHECK-LABEL: define <16 x i8> @test_veorq_s8(4265// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {4266// CHECK-NEXT: [[ENTRY:.*:]]4267// CHECK-NEXT: [[XOR_I:%.*]] = xor <16 x i8> [[A]], [[B]]4268// CHECK-NEXT: ret <16 x i8> [[XOR_I]]4269//4270int8x16_t test_veorq_s8(int8x16_t a, int8x16_t b) {4271 return veorq_s8(a, b);4272}4273 4274// CHECK-LABEL: define <8 x i16> @test_veorq_s16(4275// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {4276// CHECK-NEXT: [[ENTRY:.*:]]4277// CHECK-NEXT: [[XOR_I:%.*]] = xor <8 x i16> [[A]], [[B]]4278// CHECK-NEXT: ret <8 x i16> [[XOR_I]]4279//4280int16x8_t test_veorq_s16(int16x8_t a, int16x8_t b) {4281 return veorq_s16(a, b);4282}4283 4284// CHECK-LABEL: define <4 x i32> @test_veorq_s32(4285// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {4286// CHECK-NEXT: [[ENTRY:.*:]]4287// CHECK-NEXT: [[XOR_I:%.*]] = xor <4 x i32> [[A]], [[B]]4288// CHECK-NEXT: ret <4 x i32> [[XOR_I]]4289//4290int32x4_t test_veorq_s32(int32x4_t a, int32x4_t b) {4291 return veorq_s32(a, b);4292}4293 4294// CHECK-LABEL: define <2 x i64> @test_veorq_s64(4295// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {4296// CHECK-NEXT: [[ENTRY:.*:]]4297// CHECK-NEXT: [[XOR_I:%.*]] = xor <2 x i64> [[A]], [[B]]4298// CHECK-NEXT: ret <2 x i64> [[XOR_I]]4299//4300int64x2_t test_veorq_s64(int64x2_t a, int64x2_t b) {4301 return veorq_s64(a, b);4302}4303 4304// CHECK-LABEL: define <16 x i8> @test_veorq_u8(4305// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {4306// CHECK-NEXT: [[ENTRY:.*:]]4307// CHECK-NEXT: [[XOR_I:%.*]] = xor <16 x i8> [[A]], [[B]]4308// CHECK-NEXT: ret <16 x i8> [[XOR_I]]4309//4310uint8x16_t test_veorq_u8(uint8x16_t a, uint8x16_t b) {4311 return veorq_u8(a, b);4312}4313 4314// CHECK-LABEL: define <8 x i16> @test_veorq_u16(4315// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {4316// CHECK-NEXT: [[ENTRY:.*:]]4317// CHECK-NEXT: [[XOR_I:%.*]] = xor <8 x i16> [[A]], [[B]]4318// CHECK-NEXT: ret <8 x i16> [[XOR_I]]4319//4320uint16x8_t test_veorq_u16(uint16x8_t a, uint16x8_t b) {4321 return veorq_u16(a, b);4322}4323 4324// CHECK-LABEL: define <4 x i32> @test_veorq_u32(4325// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {4326// CHECK-NEXT: [[ENTRY:.*:]]4327// CHECK-NEXT: [[XOR_I:%.*]] = xor <4 x i32> [[A]], [[B]]4328// CHECK-NEXT: ret <4 x i32> [[XOR_I]]4329//4330uint32x4_t test_veorq_u32(uint32x4_t a, uint32x4_t b) {4331 return veorq_u32(a, b);4332}4333 4334// CHECK-LABEL: define <2 x i64> @test_veorq_u64(4335// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {4336// CHECK-NEXT: [[ENTRY:.*:]]4337// CHECK-NEXT: [[XOR_I:%.*]] = xor <2 x i64> [[A]], [[B]]4338// CHECK-NEXT: ret <2 x i64> [[XOR_I]]4339//4340uint64x2_t test_veorq_u64(uint64x2_t a, uint64x2_t b) {4341 return veorq_u64(a, b);4342}4343 4344// CHECK-LABEL: define <8 x i8> @test_vext_s8(4345// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {4346// CHECK-NEXT: [[ENTRY:.*:]]4347// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>4348// CHECK-NEXT: ret <8 x i8> [[VEXT]]4349//4350int8x8_t test_vext_s8(int8x8_t a, int8x8_t b) {4351 return vext_s8(a, b, 7);4352}4353 4354// CHECK-LABEL: define <8 x i8> @test_vext_u8(4355// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {4356// CHECK-NEXT: [[ENTRY:.*:]]4357// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>4358// CHECK-NEXT: ret <8 x i8> [[VEXT]]4359//4360uint8x8_t test_vext_u8(uint8x8_t a, uint8x8_t b) {4361 return vext_u8(a, b, 7);4362}4363 4364// CHECK-LABEL: define <8 x i8> @test_vext_p8(4365// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {4366// CHECK-NEXT: [[ENTRY:.*:]]4367// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[B]], <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>4368// CHECK-NEXT: ret <8 x i8> [[VEXT]]4369//4370poly8x8_t test_vext_p8(poly8x8_t a, poly8x8_t b) {4371 return vext_p8(a, b, 7);4372}4373 4374// CHECK-LABEL: define <4 x i16> @test_vext_s16(4375// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {4376// CHECK-NEXT: [[ENTRY:.*:]]4377// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>4378// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>4379// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>4380// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>4381// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP3]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>4382// CHECK-NEXT: ret <4 x i16> [[VEXT]]4383//4384int16x4_t test_vext_s16(int16x4_t a, int16x4_t b) {4385 return vext_s16(a, b, 3);4386}4387 4388// CHECK-LABEL: define <4 x i16> @test_vext_u16(4389// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {4390// CHECK-NEXT: [[ENTRY:.*:]]4391// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>4392// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>4393// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>4394// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>4395// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP3]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>4396// CHECK-NEXT: ret <4 x i16> [[VEXT]]4397//4398uint16x4_t test_vext_u16(uint16x4_t a, uint16x4_t b) {4399 return vext_u16(a, b, 3);4400}4401 4402// CHECK-LABEL: define <4 x i16> @test_vext_p16(4403// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {4404// CHECK-NEXT: [[ENTRY:.*:]]4405// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>4406// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>4407// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>4408// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>4409// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP3]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>4410// CHECK-NEXT: ret <4 x i16> [[VEXT]]4411//4412poly16x4_t test_vext_p16(poly16x4_t a, poly16x4_t b) {4413 return vext_p16(a, b, 3);4414}4415 4416// CHECK-LABEL: define <2 x i32> @test_vext_s32(4417// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {4418// CHECK-NEXT: [[ENTRY:.*:]]4419// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>4420// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>4421// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>4422// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>4423// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> <i32 1, i32 2>4424// CHECK-NEXT: ret <2 x i32> [[VEXT]]4425//4426int32x2_t test_vext_s32(int32x2_t a, int32x2_t b) {4427 return vext_s32(a, b, 1);4428}4429 4430// CHECK-LABEL: define <2 x i32> @test_vext_u32(4431// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {4432// CHECK-NEXT: [[ENTRY:.*:]]4433// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>4434// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>4435// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>4436// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>4437// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> <i32 1, i32 2>4438// CHECK-NEXT: ret <2 x i32> [[VEXT]]4439//4440uint32x2_t test_vext_u32(uint32x2_t a, uint32x2_t b) {4441 return vext_u32(a, b, 1);4442}4443 4444// CHECK-LABEL: define <1 x i64> @test_vext_s64(4445// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {4446// CHECK-NEXT: [[ENTRY:.*:]]4447// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>4448// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>4449// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>4450// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>4451// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <1 x i64> [[TMP2]], <1 x i64> [[TMP3]], <1 x i32> zeroinitializer4452// CHECK-NEXT: ret <1 x i64> [[VEXT]]4453//4454int64x1_t test_vext_s64(int64x1_t a, int64x1_t b) {4455 return vext_s64(a, b, 0);4456}4457 4458// CHECK-LABEL: define <1 x i64> @test_vext_u64(4459// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {4460// CHECK-NEXT: [[ENTRY:.*:]]4461// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>4462// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>4463// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>4464// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>4465// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <1 x i64> [[TMP2]], <1 x i64> [[TMP3]], <1 x i32> zeroinitializer4466// CHECK-NEXT: ret <1 x i64> [[VEXT]]4467//4468uint64x1_t test_vext_u64(uint64x1_t a, uint64x1_t b) {4469 return vext_u64(a, b, 0);4470}4471 4472// CHECK-LABEL: define <2 x float> @test_vext_f32(4473// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {4474// CHECK-NEXT: [[ENTRY:.*:]]4475// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>4476// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>4477// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>4478// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>4479// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>4480// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>4481// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> [[TMP5]], <2 x i32> <i32 1, i32 2>4482// CHECK-NEXT: ret <2 x float> [[VEXT]]4483//4484float32x2_t test_vext_f32(float32x2_t a, float32x2_t b) {4485 return vext_f32(a, b, 1);4486}4487 4488// CHECK-LABEL: define <16 x i8> @test_vextq_s8(4489// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {4490// CHECK-NEXT: [[ENTRY:.*:]]4491// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>4492// CHECK-NEXT: ret <16 x i8> [[VEXT]]4493//4494int8x16_t test_vextq_s8(int8x16_t a, int8x16_t b) {4495 return vextq_s8(a, b, 15);4496}4497 4498// CHECK-LABEL: define <16 x i8> @test_vextq_u8(4499// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {4500// CHECK-NEXT: [[ENTRY:.*:]]4501// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>4502// CHECK-NEXT: ret <16 x i8> [[VEXT]]4503//4504uint8x16_t test_vextq_u8(uint8x16_t a, uint8x16_t b) {4505 return vextq_u8(a, b, 15);4506}4507 4508// CHECK-LABEL: define <16 x i8> @test_vextq_p8(4509// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {4510// CHECK-NEXT: [[ENTRY:.*:]]4511// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[B]], <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>4512// CHECK-NEXT: ret <16 x i8> [[VEXT]]4513//4514poly8x16_t test_vextq_p8(poly8x16_t a, poly8x16_t b) {4515 return vextq_p8(a, b, 15);4516}4517 4518// CHECK-LABEL: define <8 x i16> @test_vextq_s16(4519// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {4520// CHECK-NEXT: [[ENTRY:.*:]]4521// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>4522// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>4523// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>4524// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>4525// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>4526// CHECK-NEXT: ret <8 x i16> [[VEXT]]4527//4528int16x8_t test_vextq_s16(int16x8_t a, int16x8_t b) {4529 return vextq_s16(a, b, 7);4530}4531 4532// CHECK-LABEL: define <8 x i16> @test_vextq_u16(4533// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {4534// CHECK-NEXT: [[ENTRY:.*:]]4535// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>4536// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>4537// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>4538// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>4539// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>4540// CHECK-NEXT: ret <8 x i16> [[VEXT]]4541//4542uint16x8_t test_vextq_u16(uint16x8_t a, uint16x8_t b) {4543 return vextq_u16(a, b, 7);4544}4545 4546// CHECK-LABEL: define <8 x i16> @test_vextq_p16(4547// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {4548// CHECK-NEXT: [[ENTRY:.*:]]4549// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>4550// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>4551// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>4552// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>4553// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>4554// CHECK-NEXT: ret <8 x i16> [[VEXT]]4555//4556poly16x8_t test_vextq_p16(poly16x8_t a, poly16x8_t b) {4557 return vextq_p16(a, b, 7);4558}4559 4560// CHECK-LABEL: define <4 x i32> @test_vextq_s32(4561// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {4562// CHECK-NEXT: [[ENTRY:.*:]]4563// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>4564// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>4565// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>4566// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>4567// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>4568// CHECK-NEXT: ret <4 x i32> [[VEXT]]4569//4570int32x4_t test_vextq_s32(int32x4_t a, int32x4_t b) {4571 return vextq_s32(a, b, 3);4572}4573 4574// CHECK-LABEL: define <4 x i32> @test_vextq_u32(4575// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {4576// CHECK-NEXT: [[ENTRY:.*:]]4577// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>4578// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>4579// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>4580// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>4581// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>4582// CHECK-NEXT: ret <4 x i32> [[VEXT]]4583//4584uint32x4_t test_vextq_u32(uint32x4_t a, uint32x4_t b) {4585 return vextq_u32(a, b, 3);4586}4587 4588// CHECK-LABEL: define <2 x i64> @test_vextq_s64(4589// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {4590// CHECK-NEXT: [[ENTRY:.*:]]4591// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>4592// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>4593// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>4594// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>4595// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> [[TMP3]], <2 x i32> <i32 1, i32 2>4596// CHECK-NEXT: ret <2 x i64> [[VEXT]]4597//4598int64x2_t test_vextq_s64(int64x2_t a, int64x2_t b) {4599 return vextq_s64(a, b, 1);4600}4601 4602// CHECK-LABEL: define <2 x i64> @test_vextq_u64(4603// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {4604// CHECK-NEXT: [[ENTRY:.*:]]4605// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>4606// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>4607// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>4608// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>4609// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> [[TMP3]], <2 x i32> <i32 1, i32 2>4610// CHECK-NEXT: ret <2 x i64> [[VEXT]]4611//4612uint64x2_t test_vextq_u64(uint64x2_t a, uint64x2_t b) {4613 return vextq_u64(a, b, 1);4614}4615 4616// CHECK-LABEL: define <4 x float> @test_vextq_f32(4617// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {4618// CHECK-NEXT: [[ENTRY:.*:]]4619// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>4620// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>4621// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>4622// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>4623// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>4624// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>4625// CHECK-NEXT: [[VEXT:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>4626// CHECK-NEXT: ret <4 x float> [[VEXT]]4627//4628float32x4_t test_vextq_f32(float32x4_t a, float32x4_t b) {4629 return vextq_f32(a, b, 3);4630}4631 4632// CHECK-LABEL: define <2 x float> @test_vfma_f32(4633// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[C:%.*]]) #[[ATTR0]] {4634// CHECK-NEXT: [[ENTRY:.*:]]4635// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>4636// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>4637// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[C]] to <2 x i32>4638// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>4639// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>4640// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>4641// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>4642// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x float>4643// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x float>4644// CHECK-NEXT: [[TMP9:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[TMP7]], <2 x float> [[TMP8]], <2 x float> [[TMP6]])4645// CHECK-NEXT: ret <2 x float> [[TMP9]]4646//4647float32x2_t test_vfma_f32(float32x2_t a, float32x2_t b, float32x2_t c) {4648 return vfma_f32(a, b, c);4649}4650 4651// CHECK-LABEL: define <4 x float> @test_vfmaq_f32(4652// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]]) #[[ATTR0]] {4653// CHECK-NEXT: [[ENTRY:.*:]]4654// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>4655// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>4656// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x float> [[C]] to <4 x i32>4657// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>4658// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>4659// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to <16 x i8>4660// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>4661// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <4 x float>4662// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>4663// CHECK-NEXT: [[TMP9:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP7]], <4 x float> [[TMP8]], <4 x float> [[TMP6]])4664// CHECK-NEXT: ret <4 x float> [[TMP9]]4665//4666float32x4_t test_vfmaq_f32(float32x4_t a, float32x4_t b, float32x4_t c) {4667 return vfmaq_f32(a, b, c);4668}4669 4670// CHECK-LABEL: define <2 x float> @test_vfms_f32(4671// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[C:%.*]]) #[[ATTR0]] {4672// CHECK-NEXT: [[ENTRY:.*:]]4673// CHECK-NEXT: [[FNEG_I:%.*]] = fneg <2 x float> [[B]]4674// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>4675// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[FNEG_I]] to <2 x i32>4676// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[C]] to <2 x i32>4677// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>4678// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>4679// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>4680// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>4681// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x float>4682// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x float>4683// CHECK-NEXT: [[TMP9:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[TMP7]], <2 x float> [[TMP8]], <2 x float> [[TMP6]])4684// CHECK-NEXT: ret <2 x float> [[TMP9]]4685//4686float32x2_t test_vfms_f32(float32x2_t a, float32x2_t b, float32x2_t c) {4687 return vfms_f32(a, b, c);4688}4689 4690// CHECK-LABEL: define <4 x float> @test_vfmsq_f32(4691// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]]) #[[ATTR0]] {4692// CHECK-NEXT: [[ENTRY:.*:]]4693// CHECK-NEXT: [[FNEG_I:%.*]] = fneg <4 x float> [[B]]4694// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>4695// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[FNEG_I]] to <4 x i32>4696// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x float> [[C]] to <4 x i32>4697// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>4698// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>4699// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to <16 x i8>4700// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>4701// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <4 x float>4702// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>4703// CHECK-NEXT: [[TMP9:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP7]], <4 x float> [[TMP8]], <4 x float> [[TMP6]])4704// CHECK-NEXT: ret <4 x float> [[TMP9]]4705//4706float32x4_t test_vfmsq_f32(float32x4_t a, float32x4_t b, float32x4_t c) {4707 return vfmsq_f32(a, b, c);4708}4709 4710// CHECK-LABEL: define <8 x i8> @test_vget_high_s8(4711// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {4712// CHECK-NEXT: [[ENTRY:.*:]]4713// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4714// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]4715//4716int8x8_t test_vget_high_s8(int8x16_t a) {4717 return vget_high_s8(a);4718}4719 4720// CHECK-LABEL: define <4 x i16> @test_vget_high_s16(4721// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {4722// CHECK-NEXT: [[ENTRY:.*:]]4723// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>4724// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]4725//4726int16x4_t test_vget_high_s16(int16x8_t a) {4727 return vget_high_s16(a);4728}4729 4730// CHECK-LABEL: define <2 x i32> @test_vget_high_s32(4731// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {4732// CHECK-NEXT: [[ENTRY:.*:]]4733// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3>4734// CHECK-NEXT: ret <2 x i32> [[SHUFFLE_I]]4735//4736int32x2_t test_vget_high_s32(int32x4_t a) {4737 return vget_high_s32(a);4738}4739 4740// CHECK-LABEL: define <1 x i64> @test_vget_high_s64(4741// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {4742// CHECK-NEXT: [[ENTRY:.*:]]4743// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[A]], <2 x i64> [[A]], <1 x i32> <i32 1>4744// CHECK-NEXT: ret <1 x i64> [[SHUFFLE_I]]4745//4746int64x1_t test_vget_high_s64(int64x2_t a) {4747 return vget_high_s64(a);4748}4749 4750// CHECK-LABEL: define <4 x half> @test_vget_high_f16(4751// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {4752// CHECK-NEXT: [[ENTRY:.*:]]4753// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> [[A]], <8 x half> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>4754// CHECK-NEXT: ret <4 x half> [[SHUFFLE_I]]4755//4756float16x4_t test_vget_high_f16(float16x8_t a) {4757 return vget_high_f16(a);4758}4759 4760// CHECK-LABEL: define <2 x float> @test_vget_high_f32(4761// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {4762// CHECK-NEXT: [[ENTRY:.*:]]4763// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> [[A]], <4 x float> [[A]], <2 x i32> <i32 2, i32 3>4764// CHECK-NEXT: ret <2 x float> [[SHUFFLE_I]]4765//4766float32x2_t test_vget_high_f32(float32x4_t a) {4767 return vget_high_f32(a);4768}4769 4770// CHECK-LABEL: define <8 x i8> @test_vget_high_u8(4771// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {4772// CHECK-NEXT: [[ENTRY:.*:]]4773// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4774// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]4775//4776uint8x8_t test_vget_high_u8(uint8x16_t a) {4777 return vget_high_u8(a);4778}4779 4780// CHECK-LABEL: define <4 x i16> @test_vget_high_u16(4781// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {4782// CHECK-NEXT: [[ENTRY:.*:]]4783// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>4784// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]4785//4786uint16x4_t test_vget_high_u16(uint16x8_t a) {4787 return vget_high_u16(a);4788}4789 4790// CHECK-LABEL: define <2 x i32> @test_vget_high_u32(4791// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {4792// CHECK-NEXT: [[ENTRY:.*:]]4793// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3>4794// CHECK-NEXT: ret <2 x i32> [[SHUFFLE_I]]4795//4796uint32x2_t test_vget_high_u32(uint32x4_t a) {4797 return vget_high_u32(a);4798}4799 4800// CHECK-LABEL: define <1 x i64> @test_vget_high_u64(4801// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {4802// CHECK-NEXT: [[ENTRY:.*:]]4803// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[A]], <2 x i64> [[A]], <1 x i32> <i32 1>4804// CHECK-NEXT: ret <1 x i64> [[SHUFFLE_I]]4805//4806uint64x1_t test_vget_high_u64(uint64x2_t a) {4807 return vget_high_u64(a);4808}4809 4810// CHECK-LABEL: define <8 x i8> @test_vget_high_p8(4811// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {4812// CHECK-NEXT: [[ENTRY:.*:]]4813// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4814// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]4815//4816poly8x8_t test_vget_high_p8(poly8x16_t a) {4817 return vget_high_p8(a);4818}4819 4820// CHECK-LABEL: define <4 x i16> @test_vget_high_p16(4821// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {4822// CHECK-NEXT: [[ENTRY:.*:]]4823// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>4824// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]4825//4826poly16x4_t test_vget_high_p16(poly16x8_t a) {4827 return vget_high_p16(a);4828}4829 4830// CHECK-LABEL: define zeroext i8 @test_vget_lane_u8(4831// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {4832// CHECK-NEXT: [[ENTRY:.*:]]4833// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 74834// CHECK-NEXT: ret i8 [[VGET_LANE]]4835//4836uint8_t test_vget_lane_u8(uint8x8_t a) {4837 return vget_lane_u8(a, 7);4838}4839 4840// CHECK-LABEL: define zeroext i16 @test_vget_lane_u16(4841// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {4842// CHECK-NEXT: [[ENTRY:.*:]]4843// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 34844// CHECK-NEXT: ret i16 [[VGET_LANE]]4845//4846uint16_t test_vget_lane_u16(uint16x4_t a) {4847 return vget_lane_u16(a, 3);4848}4849 4850// CHECK-LABEL: define i32 @test_vget_lane_u32(4851// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {4852// CHECK-NEXT: [[ENTRY:.*:]]4853// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <2 x i32> [[A]], i32 14854// CHECK-NEXT: ret i32 [[VGET_LANE]]4855//4856uint32_t test_vget_lane_u32(uint32x2_t a) {4857 return vget_lane_u32(a, 1);4858}4859 4860// CHECK-LABEL: define signext i8 @test_vget_lane_s8(4861// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {4862// CHECK-NEXT: [[ENTRY:.*:]]4863// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 74864// CHECK-NEXT: ret i8 [[VGET_LANE]]4865//4866int8_t test_vget_lane_s8(int8x8_t a) {4867 return vget_lane_s8(a, 7);4868}4869 4870// CHECK-LABEL: define signext i16 @test_vget_lane_s16(4871// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {4872// CHECK-NEXT: [[ENTRY:.*:]]4873// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 34874// CHECK-NEXT: ret i16 [[VGET_LANE]]4875//4876int16_t test_vget_lane_s16(int16x4_t a) {4877 return vget_lane_s16(a, 3);4878}4879 4880// CHECK-LABEL: define i32 @test_vget_lane_s32(4881// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {4882// CHECK-NEXT: [[ENTRY:.*:]]4883// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <2 x i32> [[A]], i32 14884// CHECK-NEXT: ret i32 [[VGET_LANE]]4885//4886int32_t test_vget_lane_s32(int32x2_t a) {4887 return vget_lane_s32(a, 1);4888}4889 4890// CHECK-LABEL: define signext i8 @test_vget_lane_p8(4891// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {4892// CHECK-NEXT: [[ENTRY:.*:]]4893// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 74894// CHECK-NEXT: ret i8 [[VGET_LANE]]4895//4896poly8_t test_vget_lane_p8(poly8x8_t a) {4897 return vget_lane_p8(a, 7);4898}4899 4900// CHECK-LABEL: define signext i16 @test_vget_lane_p16(4901// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {4902// CHECK-NEXT: [[ENTRY:.*:]]4903// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 34904// CHECK-NEXT: ret i16 [[VGET_LANE]]4905//4906poly16_t test_vget_lane_p16(poly16x4_t a) {4907 return vget_lane_p16(a, 3);4908}4909 4910// CHECK-LABEL: define float @test_vget_lane_f32(4911// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {4912// CHECK-NEXT: [[ENTRY:.*:]]4913// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <2 x float> [[A]], i32 14914// CHECK-NEXT: ret float [[VGET_LANE]]4915//4916float32_t test_vget_lane_f32(float32x2_t a) {4917 return vget_lane_f32(a, 1);4918}4919 4920// CHECK-LABEL: define float @test_vget_lane_f16(4921// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {4922// CHECK-NEXT: [[ENTRY:.*:]]4923// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>4924// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP0]], i32 14925// CHECK-NEXT: [[TMP1:%.*]] = bitcast i16 [[VGET_LANE]] to half4926// CHECK-NEXT: [[CONV:%.*]] = fpext half [[TMP1]] to float4927// CHECK-NEXT: ret float [[CONV]]4928//4929float32_t test_vget_lane_f16(float16x4_t a) {4930 return vget_lane_f16(a, 1);4931}4932 4933// CHECK-LABEL: define zeroext i8 @test_vgetq_lane_u8(4934// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {4935// CHECK-NEXT: [[ENTRY:.*:]]4936// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 154937// CHECK-NEXT: ret i8 [[VGET_LANE]]4938//4939uint8_t test_vgetq_lane_u8(uint8x16_t a) {4940 return vgetq_lane_u8(a, 15);4941}4942 4943// CHECK-LABEL: define zeroext i16 @test_vgetq_lane_u16(4944// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {4945// CHECK-NEXT: [[ENTRY:.*:]]4946// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 74947// CHECK-NEXT: ret i16 [[VGET_LANE]]4948//4949uint16_t test_vgetq_lane_u16(uint16x8_t a) {4950 return vgetq_lane_u16(a, 7);4951}4952 4953// CHECK-LABEL: define i32 @test_vgetq_lane_u32(4954// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {4955// CHECK-NEXT: [[ENTRY:.*:]]4956// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x i32> [[A]], i32 34957// CHECK-NEXT: ret i32 [[VGET_LANE]]4958//4959uint32_t test_vgetq_lane_u32(uint32x4_t a) {4960 return vgetq_lane_u32(a, 3);4961}4962 4963// CHECK-LABEL: define signext i8 @test_vgetq_lane_s8(4964// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {4965// CHECK-NEXT: [[ENTRY:.*:]]4966// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 154967// CHECK-NEXT: ret i8 [[VGET_LANE]]4968//4969int8_t test_vgetq_lane_s8(int8x16_t a) {4970 return vgetq_lane_s8(a, 15);4971}4972 4973// CHECK-LABEL: define signext i16 @test_vgetq_lane_s16(4974// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {4975// CHECK-NEXT: [[ENTRY:.*:]]4976// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 74977// CHECK-NEXT: ret i16 [[VGET_LANE]]4978//4979int16_t test_vgetq_lane_s16(int16x8_t a) {4980 return vgetq_lane_s16(a, 7);4981}4982 4983// CHECK-LABEL: define i32 @test_vgetq_lane_s32(4984// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {4985// CHECK-NEXT: [[ENTRY:.*:]]4986// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x i32> [[A]], i32 34987// CHECK-NEXT: ret i32 [[VGET_LANE]]4988//4989int32_t test_vgetq_lane_s32(int32x4_t a) {4990 return vgetq_lane_s32(a, 3);4991}4992 4993// CHECK-LABEL: define signext i8 @test_vgetq_lane_p8(4994// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {4995// CHECK-NEXT: [[ENTRY:.*:]]4996// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 154997// CHECK-NEXT: ret i8 [[VGET_LANE]]4998//4999poly8_t test_vgetq_lane_p8(poly8x16_t a) {5000 return vgetq_lane_p8(a, 15);5001}5002 5003// CHECK-LABEL: define signext i16 @test_vgetq_lane_p16(5004// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {5005// CHECK-NEXT: [[ENTRY:.*:]]5006// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 75007// CHECK-NEXT: ret i16 [[VGET_LANE]]5008//5009poly16_t test_vgetq_lane_p16(poly16x8_t a) {5010 return vgetq_lane_p16(a, 7);5011}5012 5013// CHECK-LABEL: define float @test_vgetq_lane_f32(5014// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {5015// CHECK-NEXT: [[ENTRY:.*:]]5016// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x float> [[A]], i32 35017// CHECK-NEXT: ret float [[VGET_LANE]]5018//5019float32_t test_vgetq_lane_f32(float32x4_t a) {5020 return vgetq_lane_f32(a, 3);5021}5022 5023// CHECK-LABEL: define float @test_vgetq_lane_f16(5024// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {5025// CHECK-NEXT: [[ENTRY:.*:]]5026// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>5027// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x i16> [[TMP0]], i32 35028// CHECK-NEXT: [[TMP1:%.*]] = bitcast i16 [[VGET_LANE]] to half5029// CHECK-NEXT: [[CONV:%.*]] = fpext half [[TMP1]] to float5030// CHECK-NEXT: ret float [[CONV]]5031//5032float32_t test_vgetq_lane_f16(float16x8_t a) {5033 return vgetq_lane_f16(a, 3);5034}5035 5036// CHECK-LABEL: define i64 @test_vget_lane_s64(5037// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {5038// CHECK-NEXT: [[ENTRY:.*:]]5039// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[A]], i32 05040// CHECK-NEXT: ret i64 [[VGET_LANE]]5041//5042int64_t test_vget_lane_s64(int64x1_t a) {5043 return vget_lane_s64(a, 0);5044}5045 5046// CHECK-LABEL: define i64 @test_vget_lane_u64(5047// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {5048// CHECK-NEXT: [[ENTRY:.*:]]5049// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[A]], i32 05050// CHECK-NEXT: ret i64 [[VGET_LANE]]5051//5052uint64_t test_vget_lane_u64(uint64x1_t a) {5053 return vget_lane_u64(a, 0);5054}5055 5056// CHECK-LABEL: define i64 @test_vgetq_lane_s64(5057// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {5058// CHECK-NEXT: [[ENTRY:.*:]]5059// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <2 x i64> [[A]], i32 15060// CHECK-NEXT: ret i64 [[VGET_LANE]]5061//5062int64_t test_vgetq_lane_s64(int64x2_t a) {5063 return vgetq_lane_s64(a, 1);5064}5065 5066// CHECK-LABEL: define i64 @test_vgetq_lane_u64(5067// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {5068// CHECK-NEXT: [[ENTRY:.*:]]5069// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <2 x i64> [[A]], i32 15070// CHECK-NEXT: ret i64 [[VGET_LANE]]5071//5072uint64_t test_vgetq_lane_u64(uint64x2_t a) {5073 return vgetq_lane_u64(a, 1);5074}5075 5076// CHECK-LABEL: define <8 x i8> @test_vget_low_s8(5077// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {5078// CHECK-NEXT: [[ENTRY:.*:]]5079// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5080// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]5081//5082int8x8_t test_vget_low_s8(int8x16_t a) {5083 return vget_low_s8(a);5084}5085 5086// CHECK-LABEL: define <4 x i16> @test_vget_low_s16(5087// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {5088// CHECK-NEXT: [[ENTRY:.*:]]5089// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>5090// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]5091//5092int16x4_t test_vget_low_s16(int16x8_t a) {5093 return vget_low_s16(a);5094}5095 5096// CHECK-LABEL: define <2 x i32> @test_vget_low_s32(5097// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {5098// CHECK-NEXT: [[ENTRY:.*:]]5099// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 0, i32 1>5100// CHECK-NEXT: ret <2 x i32> [[SHUFFLE_I]]5101//5102int32x2_t test_vget_low_s32(int32x4_t a) {5103 return vget_low_s32(a);5104}5105 5106// CHECK-LABEL: define <1 x i64> @test_vget_low_s64(5107// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {5108// CHECK-NEXT: [[ENTRY:.*:]]5109// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[A]], <2 x i64> [[A]], <1 x i32> zeroinitializer5110// CHECK-NEXT: ret <1 x i64> [[SHUFFLE_I]]5111//5112int64x1_t test_vget_low_s64(int64x2_t a) {5113 return vget_low_s64(a);5114}5115 5116// CHECK-LABEL: define <4 x half> @test_vget_low_f16(5117// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {5118// CHECK-NEXT: [[ENTRY:.*:]]5119// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> [[A]], <8 x half> [[A]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>5120// CHECK-NEXT: ret <4 x half> [[SHUFFLE_I]]5121//5122float16x4_t test_vget_low_f16(float16x8_t a) {5123 return vget_low_f16(a);5124}5125 5126// CHECK-LABEL: define <2 x float> @test_vget_low_f32(5127// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {5128// CHECK-NEXT: [[ENTRY:.*:]]5129// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> [[A]], <4 x float> [[A]], <2 x i32> <i32 0, i32 1>5130// CHECK-NEXT: ret <2 x float> [[SHUFFLE_I]]5131//5132float32x2_t test_vget_low_f32(float32x4_t a) {5133 return vget_low_f32(a);5134}5135 5136// CHECK-LABEL: define <8 x i8> @test_vget_low_u8(5137// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {5138// CHECK-NEXT: [[ENTRY:.*:]]5139// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5140// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]5141//5142uint8x8_t test_vget_low_u8(uint8x16_t a) {5143 return vget_low_u8(a);5144}5145 5146// CHECK-LABEL: define <4 x i16> @test_vget_low_u16(5147// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {5148// CHECK-NEXT: [[ENTRY:.*:]]5149// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>5150// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]5151//5152uint16x4_t test_vget_low_u16(uint16x8_t a) {5153 return vget_low_u16(a);5154}5155 5156// CHECK-LABEL: define <2 x i32> @test_vget_low_u32(5157// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {5158// CHECK-NEXT: [[ENTRY:.*:]]5159// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 0, i32 1>5160// CHECK-NEXT: ret <2 x i32> [[SHUFFLE_I]]5161//5162uint32x2_t test_vget_low_u32(uint32x4_t a) {5163 return vget_low_u32(a);5164}5165 5166// CHECK-LABEL: define <1 x i64> @test_vget_low_u64(5167// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {5168// CHECK-NEXT: [[ENTRY:.*:]]5169// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[A]], <2 x i64> [[A]], <1 x i32> zeroinitializer5170// CHECK-NEXT: ret <1 x i64> [[SHUFFLE_I]]5171//5172uint64x1_t test_vget_low_u64(uint64x2_t a) {5173 return vget_low_u64(a);5174}5175 5176// CHECK-LABEL: define <8 x i8> @test_vget_low_p8(5177// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {5178// CHECK-NEXT: [[ENTRY:.*:]]5179// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5180// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]5181//5182poly8x8_t test_vget_low_p8(poly8x16_t a) {5183 return vget_low_p8(a);5184}5185 5186// CHECK-LABEL: define <4 x i16> @test_vget_low_p16(5187// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {5188// CHECK-NEXT: [[ENTRY:.*:]]5189// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>5190// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]5191//5192poly16x4_t test_vget_low_p16(poly16x8_t a) {5193 return vget_low_p16(a);5194}5195 5196// CHECK-LABEL: define <8 x i8> @test_vhadd_s8(5197// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {5198// CHECK-NEXT: [[ENTRY:.*:]]5199// CHECK-NEXT: [[VHADD_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])5200// CHECK-NEXT: ret <8 x i8> [[VHADD_V_I]]5201//5202int8x8_t test_vhadd_s8(int8x8_t a, int8x8_t b) {5203 return vhadd_s8(a, b);5204}5205 5206// CHECK-LABEL: define <4 x i16> @test_vhadd_s16(5207// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {5208// CHECK-NEXT: [[ENTRY:.*:]]5209// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>5210// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>5211// CHECK-NEXT: [[VHADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>5212// CHECK-NEXT: [[VHADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>5213// CHECK-NEXT: [[VHADD_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> [[VHADD_V_I]], <4 x i16> [[VHADD_V1_I]])5214// CHECK-NEXT: [[VHADD_V3_I:%.*]] = bitcast <4 x i16> [[VHADD_V2_I]] to <8 x i8>5215// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VHADD_V3_I]] to <4 x i16>5216// CHECK-NEXT: ret <4 x i16> [[TMP2]]5217//5218int16x4_t test_vhadd_s16(int16x4_t a, int16x4_t b) {5219 return vhadd_s16(a, b);5220}5221 5222// CHECK-LABEL: define <2 x i32> @test_vhadd_s32(5223// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {5224// CHECK-NEXT: [[ENTRY:.*:]]5225// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>5226// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>5227// CHECK-NEXT: [[VHADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>5228// CHECK-NEXT: [[VHADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>5229// CHECK-NEXT: [[VHADD_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> [[VHADD_V_I]], <2 x i32> [[VHADD_V1_I]])5230// CHECK-NEXT: [[VHADD_V3_I:%.*]] = bitcast <2 x i32> [[VHADD_V2_I]] to <8 x i8>5231// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VHADD_V3_I]] to <2 x i32>5232// CHECK-NEXT: ret <2 x i32> [[TMP2]]5233//5234int32x2_t test_vhadd_s32(int32x2_t a, int32x2_t b) {5235 return vhadd_s32(a, b);5236}5237 5238// CHECK-LABEL: define <8 x i8> @test_vhadd_u8(5239// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {5240// CHECK-NEXT: [[ENTRY:.*:]]5241// CHECK-NEXT: [[VHADD_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])5242// CHECK-NEXT: ret <8 x i8> [[VHADD_V_I]]5243//5244uint8x8_t test_vhadd_u8(uint8x8_t a, uint8x8_t b) {5245 return vhadd_u8(a, b);5246}5247 5248// CHECK-LABEL: define <4 x i16> @test_vhadd_u16(5249// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {5250// CHECK-NEXT: [[ENTRY:.*:]]5251// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>5252// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>5253// CHECK-NEXT: [[VHADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>5254// CHECK-NEXT: [[VHADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>5255// CHECK-NEXT: [[VHADD_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> [[VHADD_V_I]], <4 x i16> [[VHADD_V1_I]])5256// CHECK-NEXT: [[VHADD_V3_I:%.*]] = bitcast <4 x i16> [[VHADD_V2_I]] to <8 x i8>5257// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VHADD_V3_I]] to <4 x i16>5258// CHECK-NEXT: ret <4 x i16> [[TMP2]]5259//5260uint16x4_t test_vhadd_u16(uint16x4_t a, uint16x4_t b) {5261 return vhadd_u16(a, b);5262}5263 5264// CHECK-LABEL: define <2 x i32> @test_vhadd_u32(5265// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {5266// CHECK-NEXT: [[ENTRY:.*:]]5267// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>5268// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>5269// CHECK-NEXT: [[VHADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>5270// CHECK-NEXT: [[VHADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>5271// CHECK-NEXT: [[VHADD_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> [[VHADD_V_I]], <2 x i32> [[VHADD_V1_I]])5272// CHECK-NEXT: [[VHADD_V3_I:%.*]] = bitcast <2 x i32> [[VHADD_V2_I]] to <8 x i8>5273// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VHADD_V3_I]] to <2 x i32>5274// CHECK-NEXT: ret <2 x i32> [[TMP2]]5275//5276uint32x2_t test_vhadd_u32(uint32x2_t a, uint32x2_t b) {5277 return vhadd_u32(a, b);5278}5279 5280// CHECK-LABEL: define <16 x i8> @test_vhaddq_s8(5281// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {5282// CHECK-NEXT: [[ENTRY:.*:]]5283// CHECK-NEXT: [[VHADDQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])5284// CHECK-NEXT: ret <16 x i8> [[VHADDQ_V_I]]5285//5286int8x16_t test_vhaddq_s8(int8x16_t a, int8x16_t b) {5287 return vhaddq_s8(a, b);5288}5289 5290// CHECK-LABEL: define <8 x i16> @test_vhaddq_s16(5291// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {5292// CHECK-NEXT: [[ENTRY:.*:]]5293// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>5294// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>5295// CHECK-NEXT: [[VHADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>5296// CHECK-NEXT: [[VHADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>5297// CHECK-NEXT: [[VHADDQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> [[VHADDQ_V_I]], <8 x i16> [[VHADDQ_V1_I]])5298// CHECK-NEXT: [[VHADDQ_V3_I:%.*]] = bitcast <8 x i16> [[VHADDQ_V2_I]] to <16 x i8>5299// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VHADDQ_V3_I]] to <8 x i16>5300// CHECK-NEXT: ret <8 x i16> [[TMP2]]5301//5302int16x8_t test_vhaddq_s16(int16x8_t a, int16x8_t b) {5303 return vhaddq_s16(a, b);5304}5305 5306// CHECK-LABEL: define <4 x i32> @test_vhaddq_s32(5307// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {5308// CHECK-NEXT: [[ENTRY:.*:]]5309// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>5310// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>5311// CHECK-NEXT: [[VHADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>5312// CHECK-NEXT: [[VHADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>5313// CHECK-NEXT: [[VHADDQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> [[VHADDQ_V_I]], <4 x i32> [[VHADDQ_V1_I]])5314// CHECK-NEXT: [[VHADDQ_V3_I:%.*]] = bitcast <4 x i32> [[VHADDQ_V2_I]] to <16 x i8>5315// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VHADDQ_V3_I]] to <4 x i32>5316// CHECK-NEXT: ret <4 x i32> [[TMP2]]5317//5318int32x4_t test_vhaddq_s32(int32x4_t a, int32x4_t b) {5319 return vhaddq_s32(a, b);5320}5321 5322// CHECK-LABEL: define <16 x i8> @test_vhaddq_u8(5323// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {5324// CHECK-NEXT: [[ENTRY:.*:]]5325// CHECK-NEXT: [[VHADDQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])5326// CHECK-NEXT: ret <16 x i8> [[VHADDQ_V_I]]5327//5328uint8x16_t test_vhaddq_u8(uint8x16_t a, uint8x16_t b) {5329 return vhaddq_u8(a, b);5330}5331 5332// CHECK-LABEL: define <8 x i16> @test_vhaddq_u16(5333// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {5334// CHECK-NEXT: [[ENTRY:.*:]]5335// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>5336// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>5337// CHECK-NEXT: [[VHADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>5338// CHECK-NEXT: [[VHADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>5339// CHECK-NEXT: [[VHADDQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> [[VHADDQ_V_I]], <8 x i16> [[VHADDQ_V1_I]])5340// CHECK-NEXT: [[VHADDQ_V3_I:%.*]] = bitcast <8 x i16> [[VHADDQ_V2_I]] to <16 x i8>5341// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VHADDQ_V3_I]] to <8 x i16>5342// CHECK-NEXT: ret <8 x i16> [[TMP2]]5343//5344uint16x8_t test_vhaddq_u16(uint16x8_t a, uint16x8_t b) {5345 return vhaddq_u16(a, b);5346}5347 5348// CHECK-LABEL: define <4 x i32> @test_vhaddq_u32(5349// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {5350// CHECK-NEXT: [[ENTRY:.*:]]5351// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>5352// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>5353// CHECK-NEXT: [[VHADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>5354// CHECK-NEXT: [[VHADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>5355// CHECK-NEXT: [[VHADDQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> [[VHADDQ_V_I]], <4 x i32> [[VHADDQ_V1_I]])5356// CHECK-NEXT: [[VHADDQ_V3_I:%.*]] = bitcast <4 x i32> [[VHADDQ_V2_I]] to <16 x i8>5357// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VHADDQ_V3_I]] to <4 x i32>5358// CHECK-NEXT: ret <4 x i32> [[TMP2]]5359//5360uint32x4_t test_vhaddq_u32(uint32x4_t a, uint32x4_t b) {5361 return vhaddq_u32(a, b);5362}5363 5364// CHECK-LABEL: define <8 x i8> @test_vhsub_s8(5365// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {5366// CHECK-NEXT: [[ENTRY:.*:]]5367// CHECK-NEXT: [[VHSUB_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])5368// CHECK-NEXT: ret <8 x i8> [[VHSUB_V_I]]5369//5370int8x8_t test_vhsub_s8(int8x8_t a, int8x8_t b) {5371 return vhsub_s8(a, b);5372}5373 5374// CHECK-LABEL: define <4 x i16> @test_vhsub_s16(5375// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {5376// CHECK-NEXT: [[ENTRY:.*:]]5377// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>5378// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>5379// CHECK-NEXT: [[VHSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>5380// CHECK-NEXT: [[VHSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>5381// CHECK-NEXT: [[VHSUB_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> [[VHSUB_V_I]], <4 x i16> [[VHSUB_V1_I]])5382// CHECK-NEXT: [[VHSUB_V3_I:%.*]] = bitcast <4 x i16> [[VHSUB_V2_I]] to <8 x i8>5383// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VHSUB_V3_I]] to <4 x i16>5384// CHECK-NEXT: ret <4 x i16> [[TMP2]]5385//5386int16x4_t test_vhsub_s16(int16x4_t a, int16x4_t b) {5387 return vhsub_s16(a, b);5388}5389 5390// CHECK-LABEL: define <2 x i32> @test_vhsub_s32(5391// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {5392// CHECK-NEXT: [[ENTRY:.*:]]5393// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>5394// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>5395// CHECK-NEXT: [[VHSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>5396// CHECK-NEXT: [[VHSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>5397// CHECK-NEXT: [[VHSUB_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> [[VHSUB_V_I]], <2 x i32> [[VHSUB_V1_I]])5398// CHECK-NEXT: [[VHSUB_V3_I:%.*]] = bitcast <2 x i32> [[VHSUB_V2_I]] to <8 x i8>5399// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VHSUB_V3_I]] to <2 x i32>5400// CHECK-NEXT: ret <2 x i32> [[TMP2]]5401//5402int32x2_t test_vhsub_s32(int32x2_t a, int32x2_t b) {5403 return vhsub_s32(a, b);5404}5405 5406// CHECK-LABEL: define <8 x i8> @test_vhsub_u8(5407// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {5408// CHECK-NEXT: [[ENTRY:.*:]]5409// CHECK-NEXT: [[VHSUB_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])5410// CHECK-NEXT: ret <8 x i8> [[VHSUB_V_I]]5411//5412uint8x8_t test_vhsub_u8(uint8x8_t a, uint8x8_t b) {5413 return vhsub_u8(a, b);5414}5415 5416// CHECK-LABEL: define <4 x i16> @test_vhsub_u16(5417// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {5418// CHECK-NEXT: [[ENTRY:.*:]]5419// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>5420// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>5421// CHECK-NEXT: [[VHSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>5422// CHECK-NEXT: [[VHSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>5423// CHECK-NEXT: [[VHSUB_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> [[VHSUB_V_I]], <4 x i16> [[VHSUB_V1_I]])5424// CHECK-NEXT: [[VHSUB_V3_I:%.*]] = bitcast <4 x i16> [[VHSUB_V2_I]] to <8 x i8>5425// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VHSUB_V3_I]] to <4 x i16>5426// CHECK-NEXT: ret <4 x i16> [[TMP2]]5427//5428uint16x4_t test_vhsub_u16(uint16x4_t a, uint16x4_t b) {5429 return vhsub_u16(a, b);5430}5431 5432// CHECK-LABEL: define <2 x i32> @test_vhsub_u32(5433// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {5434// CHECK-NEXT: [[ENTRY:.*:]]5435// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>5436// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>5437// CHECK-NEXT: [[VHSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>5438// CHECK-NEXT: [[VHSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>5439// CHECK-NEXT: [[VHSUB_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> [[VHSUB_V_I]], <2 x i32> [[VHSUB_V1_I]])5440// CHECK-NEXT: [[VHSUB_V3_I:%.*]] = bitcast <2 x i32> [[VHSUB_V2_I]] to <8 x i8>5441// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VHSUB_V3_I]] to <2 x i32>5442// CHECK-NEXT: ret <2 x i32> [[TMP2]]5443//5444uint32x2_t test_vhsub_u32(uint32x2_t a, uint32x2_t b) {5445 return vhsub_u32(a, b);5446}5447 5448// CHECK-LABEL: define <16 x i8> @test_vhsubq_s8(5449// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {5450// CHECK-NEXT: [[ENTRY:.*:]]5451// CHECK-NEXT: [[VHSUBQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])5452// CHECK-NEXT: ret <16 x i8> [[VHSUBQ_V_I]]5453//5454int8x16_t test_vhsubq_s8(int8x16_t a, int8x16_t b) {5455 return vhsubq_s8(a, b);5456}5457 5458// CHECK-LABEL: define <8 x i16> @test_vhsubq_s16(5459// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {5460// CHECK-NEXT: [[ENTRY:.*:]]5461// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>5462// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>5463// CHECK-NEXT: [[VHSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>5464// CHECK-NEXT: [[VHSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>5465// CHECK-NEXT: [[VHSUBQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> [[VHSUBQ_V_I]], <8 x i16> [[VHSUBQ_V1_I]])5466// CHECK-NEXT: [[VHSUBQ_V3_I:%.*]] = bitcast <8 x i16> [[VHSUBQ_V2_I]] to <16 x i8>5467// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VHSUBQ_V3_I]] to <8 x i16>5468// CHECK-NEXT: ret <8 x i16> [[TMP2]]5469//5470int16x8_t test_vhsubq_s16(int16x8_t a, int16x8_t b) {5471 return vhsubq_s16(a, b);5472}5473 5474// CHECK-LABEL: define <4 x i32> @test_vhsubq_s32(5475// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {5476// CHECK-NEXT: [[ENTRY:.*:]]5477// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>5478// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>5479// CHECK-NEXT: [[VHSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>5480// CHECK-NEXT: [[VHSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>5481// CHECK-NEXT: [[VHSUBQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> [[VHSUBQ_V_I]], <4 x i32> [[VHSUBQ_V1_I]])5482// CHECK-NEXT: [[VHSUBQ_V3_I:%.*]] = bitcast <4 x i32> [[VHSUBQ_V2_I]] to <16 x i8>5483// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VHSUBQ_V3_I]] to <4 x i32>5484// CHECK-NEXT: ret <4 x i32> [[TMP2]]5485//5486int32x4_t test_vhsubq_s32(int32x4_t a, int32x4_t b) {5487 return vhsubq_s32(a, b);5488}5489 5490// CHECK-LABEL: define <16 x i8> @test_vhsubq_u8(5491// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {5492// CHECK-NEXT: [[ENTRY:.*:]]5493// CHECK-NEXT: [[VHSUBQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])5494// CHECK-NEXT: ret <16 x i8> [[VHSUBQ_V_I]]5495//5496uint8x16_t test_vhsubq_u8(uint8x16_t a, uint8x16_t b) {5497 return vhsubq_u8(a, b);5498}5499 5500// CHECK-LABEL: define <8 x i16> @test_vhsubq_u16(5501// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {5502// CHECK-NEXT: [[ENTRY:.*:]]5503// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>5504// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>5505// CHECK-NEXT: [[VHSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>5506// CHECK-NEXT: [[VHSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>5507// CHECK-NEXT: [[VHSUBQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> [[VHSUBQ_V_I]], <8 x i16> [[VHSUBQ_V1_I]])5508// CHECK-NEXT: [[VHSUBQ_V3_I:%.*]] = bitcast <8 x i16> [[VHSUBQ_V2_I]] to <16 x i8>5509// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VHSUBQ_V3_I]] to <8 x i16>5510// CHECK-NEXT: ret <8 x i16> [[TMP2]]5511//5512uint16x8_t test_vhsubq_u16(uint16x8_t a, uint16x8_t b) {5513 return vhsubq_u16(a, b);5514}5515 5516// CHECK-LABEL: define <4 x i32> @test_vhsubq_u32(5517// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {5518// CHECK-NEXT: [[ENTRY:.*:]]5519// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>5520// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>5521// CHECK-NEXT: [[VHSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>5522// CHECK-NEXT: [[VHSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>5523// CHECK-NEXT: [[VHSUBQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> [[VHSUBQ_V_I]], <4 x i32> [[VHSUBQ_V1_I]])5524// CHECK-NEXT: [[VHSUBQ_V3_I:%.*]] = bitcast <4 x i32> [[VHSUBQ_V2_I]] to <16 x i8>5525// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VHSUBQ_V3_I]] to <4 x i32>5526// CHECK-NEXT: ret <4 x i32> [[TMP2]]5527//5528uint32x4_t test_vhsubq_u32(uint32x4_t a, uint32x4_t b) {5529 return vhsubq_u32(a, b);5530}5531 5532// CHECK-LABEL: define <16 x i8> @test_vld1q_u8(5533// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5534// CHECK-NEXT: [[ENTRY:.*:]]5535// CHECK-NEXT: [[VLD1:%.*]] = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr [[A]], i32 1)5536// CHECK-NEXT: ret <16 x i8> [[VLD1]]5537//5538uint8x16_t test_vld1q_u8(uint8_t const * a) {5539 return vld1q_u8(a);5540}5541 5542// CHECK-LABEL: define <8 x i16> @test_vld1q_u16(5543// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5544// CHECK-NEXT: [[ENTRY:.*:]]5545// CHECK-NEXT: [[VLD1:%.*]] = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr [[A]], i32 2)5546// CHECK-NEXT: ret <8 x i16> [[VLD1]]5547//5548uint16x8_t test_vld1q_u16(uint16_t const * a) {5549 return vld1q_u16(a);5550}5551 5552// CHECK-LABEL: define <4 x i32> @test_vld1q_u32(5553// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5554// CHECK-NEXT: [[ENTRY:.*:]]5555// CHECK-NEXT: [[VLD1:%.*]] = call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr [[A]], i32 4)5556// CHECK-NEXT: ret <4 x i32> [[VLD1]]5557//5558uint32x4_t test_vld1q_u32(uint32_t const * a) {5559 return vld1q_u32(a);5560}5561 5562// CHECK-LABEL: define <2 x i64> @test_vld1q_u64(5563// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5564// CHECK-NEXT: [[ENTRY:.*:]]5565// CHECK-NEXT: [[VLD1:%.*]] = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr [[A]], i32 4)5566// CHECK-NEXT: ret <2 x i64> [[VLD1]]5567//5568uint64x2_t test_vld1q_u64(uint64_t const * a) {5569 return vld1q_u64(a);5570}5571 5572// CHECK-LABEL: define <16 x i8> @test_vld1q_s8(5573// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5574// CHECK-NEXT: [[ENTRY:.*:]]5575// CHECK-NEXT: [[VLD1:%.*]] = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr [[A]], i32 1)5576// CHECK-NEXT: ret <16 x i8> [[VLD1]]5577//5578int8x16_t test_vld1q_s8(int8_t const * a) {5579 return vld1q_s8(a);5580}5581 5582// CHECK-LABEL: define <8 x i16> @test_vld1q_s16(5583// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5584// CHECK-NEXT: [[ENTRY:.*:]]5585// CHECK-NEXT: [[VLD1:%.*]] = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr [[A]], i32 2)5586// CHECK-NEXT: ret <8 x i16> [[VLD1]]5587//5588int16x8_t test_vld1q_s16(int16_t const * a) {5589 return vld1q_s16(a);5590}5591 5592// CHECK-LABEL: define <4 x i32> @test_vld1q_s32(5593// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5594// CHECK-NEXT: [[ENTRY:.*:]]5595// CHECK-NEXT: [[VLD1:%.*]] = call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0(ptr [[A]], i32 4)5596// CHECK-NEXT: ret <4 x i32> [[VLD1]]5597//5598int32x4_t test_vld1q_s32(int32_t const * a) {5599 return vld1q_s32(a);5600}5601 5602// CHECK-LABEL: define <2 x i64> @test_vld1q_s64(5603// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5604// CHECK-NEXT: [[ENTRY:.*:]]5605// CHECK-NEXT: [[VLD1:%.*]] = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr [[A]], i32 4)5606// CHECK-NEXT: ret <2 x i64> [[VLD1]]5607//5608int64x2_t test_vld1q_s64(int64_t const * a) {5609 return vld1q_s64(a);5610}5611 5612// CHECK-LABEL: define <8 x half> @test_vld1q_f16(5613// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5614// CHECK-NEXT: [[ENTRY:.*:]]5615// CHECK-NEXT: [[VLD1:%.*]] = call <8 x half> @llvm.arm.neon.vld1.v8f16.p0(ptr [[A]], i32 2)5616// CHECK-NEXT: ret <8 x half> [[VLD1]]5617//5618float16x8_t test_vld1q_f16(float16_t const * a) {5619 return vld1q_f16(a);5620}5621 5622// CHECK-LABEL: define <4 x float> @test_vld1q_f32(5623// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5624// CHECK-NEXT: [[ENTRY:.*:]]5625// CHECK-NEXT: [[VLD1:%.*]] = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr [[A]], i32 4)5626// CHECK-NEXT: ret <4 x float> [[VLD1]]5627//5628float32x4_t test_vld1q_f32(float32_t const * a) {5629 return vld1q_f32(a);5630}5631 5632// CHECK-LABEL: define <16 x i8> @test_vld1q_p8(5633// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5634// CHECK-NEXT: [[ENTRY:.*:]]5635// CHECK-NEXT: [[VLD1:%.*]] = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr [[A]], i32 1)5636// CHECK-NEXT: ret <16 x i8> [[VLD1]]5637//5638poly8x16_t test_vld1q_p8(poly8_t const * a) {5639 return vld1q_p8(a);5640}5641 5642// CHECK-LABEL: define <8 x i16> @test_vld1q_p16(5643// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5644// CHECK-NEXT: [[ENTRY:.*:]]5645// CHECK-NEXT: [[VLD1:%.*]] = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0(ptr [[A]], i32 2)5646// CHECK-NEXT: ret <8 x i16> [[VLD1]]5647//5648poly16x8_t test_vld1q_p16(poly16_t const * a) {5649 return vld1q_p16(a);5650}5651 5652// CHECK-LABEL: define <8 x i8> @test_vld1_u8(5653// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5654// CHECK-NEXT: [[ENTRY:.*:]]5655// CHECK-NEXT: [[VLD1:%.*]] = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr [[A]], i32 1)5656// CHECK-NEXT: ret <8 x i8> [[VLD1]]5657//5658uint8x8_t test_vld1_u8(uint8_t const * a) {5659 return vld1_u8(a);5660}5661 5662// CHECK-LABEL: define <4 x i16> @test_vld1_u16(5663// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5664// CHECK-NEXT: [[ENTRY:.*:]]5665// CHECK-NEXT: [[VLD1:%.*]] = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0(ptr [[A]], i32 2)5666// CHECK-NEXT: ret <4 x i16> [[VLD1]]5667//5668uint16x4_t test_vld1_u16(uint16_t const * a) {5669 return vld1_u16(a);5670}5671 5672// CHECK-LABEL: define <2 x i32> @test_vld1_u32(5673// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5674// CHECK-NEXT: [[ENTRY:.*:]]5675// CHECK-NEXT: [[VLD1:%.*]] = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0(ptr [[A]], i32 4)5676// CHECK-NEXT: ret <2 x i32> [[VLD1]]5677//5678uint32x2_t test_vld1_u32(uint32_t const * a) {5679 return vld1_u32(a);5680}5681 5682// CHECK-LABEL: define <1 x i64> @test_vld1_u64(5683// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5684// CHECK-NEXT: [[ENTRY:.*:]]5685// CHECK-NEXT: [[VLD1:%.*]] = call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr [[A]], i32 4)5686// CHECK-NEXT: ret <1 x i64> [[VLD1]]5687//5688uint64x1_t test_vld1_u64(uint64_t const * a) {5689 return vld1_u64(a);5690}5691 5692// CHECK-LABEL: define <8 x i8> @test_vld1_s8(5693// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5694// CHECK-NEXT: [[ENTRY:.*:]]5695// CHECK-NEXT: [[VLD1:%.*]] = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr [[A]], i32 1)5696// CHECK-NEXT: ret <8 x i8> [[VLD1]]5697//5698int8x8_t test_vld1_s8(int8_t const * a) {5699 return vld1_s8(a);5700}5701 5702// CHECK-LABEL: define <4 x i16> @test_vld1_s16(5703// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5704// CHECK-NEXT: [[ENTRY:.*:]]5705// CHECK-NEXT: [[VLD1:%.*]] = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0(ptr [[A]], i32 2)5706// CHECK-NEXT: ret <4 x i16> [[VLD1]]5707//5708int16x4_t test_vld1_s16(int16_t const * a) {5709 return vld1_s16(a);5710}5711 5712// CHECK-LABEL: define <2 x i32> @test_vld1_s32(5713// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5714// CHECK-NEXT: [[ENTRY:.*:]]5715// CHECK-NEXT: [[VLD1:%.*]] = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0(ptr [[A]], i32 4)5716// CHECK-NEXT: ret <2 x i32> [[VLD1]]5717//5718int32x2_t test_vld1_s32(int32_t const * a) {5719 return vld1_s32(a);5720}5721 5722// CHECK-LABEL: define <1 x i64> @test_vld1_s64(5723// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5724// CHECK-NEXT: [[ENTRY:.*:]]5725// CHECK-NEXT: [[VLD1:%.*]] = call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr [[A]], i32 4)5726// CHECK-NEXT: ret <1 x i64> [[VLD1]]5727//5728int64x1_t test_vld1_s64(int64_t const * a) {5729 return vld1_s64(a);5730}5731 5732// CHECK-LABEL: define <4 x half> @test_vld1_f16(5733// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5734// CHECK-NEXT: [[ENTRY:.*:]]5735// CHECK-NEXT: [[VLD1:%.*]] = call <4 x half> @llvm.arm.neon.vld1.v4f16.p0(ptr [[A]], i32 2)5736// CHECK-NEXT: ret <4 x half> [[VLD1]]5737//5738float16x4_t test_vld1_f16(float16_t const * a) {5739 return vld1_f16(a);5740}5741 5742// CHECK-LABEL: define <2 x float> @test_vld1_f32(5743// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5744// CHECK-NEXT: [[ENTRY:.*:]]5745// CHECK-NEXT: [[VLD1:%.*]] = call <2 x float> @llvm.arm.neon.vld1.v2f32.p0(ptr [[A]], i32 4)5746// CHECK-NEXT: ret <2 x float> [[VLD1]]5747//5748float32x2_t test_vld1_f32(float32_t const * a) {5749 return vld1_f32(a);5750}5751 5752// CHECK-LABEL: define <8 x i8> @test_vld1_p8(5753// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5754// CHECK-NEXT: [[ENTRY:.*:]]5755// CHECK-NEXT: [[VLD1:%.*]] = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0(ptr [[A]], i32 1)5756// CHECK-NEXT: ret <8 x i8> [[VLD1]]5757//5758poly8x8_t test_vld1_p8(poly8_t const * a) {5759 return vld1_p8(a);5760}5761 5762// CHECK-LABEL: define <4 x i16> @test_vld1_p16(5763// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5764// CHECK-NEXT: [[ENTRY:.*:]]5765// CHECK-NEXT: [[VLD1:%.*]] = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0(ptr [[A]], i32 2)5766// CHECK-NEXT: ret <4 x i16> [[VLD1]]5767//5768poly16x4_t test_vld1_p16(poly16_t const * a) {5769 return vld1_p16(a);5770}5771 5772// CHECK-LABEL: define <16 x i8> @test_vld1q_dup_u8(5773// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5774// CHECK-NEXT: [[ENTRY:.*:]]5775// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 15776// CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i32 05777// CHECK-NEXT: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> zeroinitializer5778// CHECK-NEXT: ret <16 x i8> [[LANE]]5779//5780uint8x16_t test_vld1q_dup_u8(uint8_t const * a) {5781 return vld1q_dup_u8(a);5782}5783 5784// CHECK-LABEL: define <8 x i16> @test_vld1q_dup_u16(5785// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5786// CHECK-NEXT: [[ENTRY:.*:]]5787// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 25788// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP0]], i32 05789// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> [[TMP1]], <8 x i32> zeroinitializer5790// CHECK-NEXT: ret <8 x i16> [[LANE]]5791//5792uint16x8_t test_vld1q_dup_u16(uint16_t const * a) {5793 return vld1q_dup_u16(a);5794}5795 5796// CHECK-LABEL: define <4 x i32> @test_vld1q_dup_u32(5797// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5798// CHECK-NEXT: [[ENTRY:.*:]]5799// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 45800// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 05801// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP1]], <4 x i32> zeroinitializer5802// CHECK-NEXT: ret <4 x i32> [[LANE]]5803//5804uint32x4_t test_vld1q_dup_u32(uint32_t const * a) {5805 return vld1q_dup_u32(a);5806}5807 5808// CHECK-LABEL: define <2 x i64> @test_vld1q_dup_u64(5809// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5810// CHECK-NEXT: [[ENTRY:.*:]]5811// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 45812// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i32 05813// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP1]], <2 x i32> zeroinitializer5814// CHECK-NEXT: ret <2 x i64> [[LANE]]5815//5816uint64x2_t test_vld1q_dup_u64(uint64_t const * a) {5817 return vld1q_dup_u64(a);5818}5819 5820// CHECK-LABEL: define <16 x i8> @test_vld1q_dup_s8(5821// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5822// CHECK-NEXT: [[ENTRY:.*:]]5823// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 15824// CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i32 05825// CHECK-NEXT: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> zeroinitializer5826// CHECK-NEXT: ret <16 x i8> [[LANE]]5827//5828int8x16_t test_vld1q_dup_s8(int8_t const * a) {5829 return vld1q_dup_s8(a);5830}5831 5832// CHECK-LABEL: define <8 x i16> @test_vld1q_dup_s16(5833// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5834// CHECK-NEXT: [[ENTRY:.*:]]5835// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 25836// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP0]], i32 05837// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> [[TMP1]], <8 x i32> zeroinitializer5838// CHECK-NEXT: ret <8 x i16> [[LANE]]5839//5840int16x8_t test_vld1q_dup_s16(int16_t const * a) {5841 return vld1q_dup_s16(a);5842}5843 5844// CHECK-LABEL: define <4 x i32> @test_vld1q_dup_s32(5845// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5846// CHECK-NEXT: [[ENTRY:.*:]]5847// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 45848// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 05849// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP1]], <4 x i32> zeroinitializer5850// CHECK-NEXT: ret <4 x i32> [[LANE]]5851//5852int32x4_t test_vld1q_dup_s32(int32_t const * a) {5853 return vld1q_dup_s32(a);5854}5855 5856// CHECK-LABEL: define <2 x i64> @test_vld1q_dup_s64(5857// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5858// CHECK-NEXT: [[ENTRY:.*:]]5859// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 45860// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i32 05861// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP1]], <2 x i32> zeroinitializer5862// CHECK-NEXT: ret <2 x i64> [[LANE]]5863//5864int64x2_t test_vld1q_dup_s64(int64_t const * a) {5865 return vld1q_dup_s64(a);5866}5867 5868// CHECK-LABEL: define <8 x half> @test_vld1q_dup_f16(5869// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5870// CHECK-NEXT: [[ENTRY:.*:]]5871// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A]], align 25872// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x half> poison, half [[TMP0]], i32 05873// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x half> [[TMP1]], <8 x half> [[TMP1]], <8 x i32> zeroinitializer5874// CHECK-NEXT: ret <8 x half> [[LANE]]5875//5876float16x8_t test_vld1q_dup_f16(float16_t const * a) {5877 return vld1q_dup_f16(a);5878}5879 5880// CHECK-LABEL: define <4 x float> @test_vld1q_dup_f32(5881// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5882// CHECK-NEXT: [[ENTRY:.*:]]5883// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[A]], align 45884// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[TMP0]], i32 05885// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> zeroinitializer5886// CHECK-NEXT: ret <4 x float> [[LANE]]5887//5888float32x4_t test_vld1q_dup_f32(float32_t const * a) {5889 return vld1q_dup_f32(a);5890}5891 5892// CHECK-LABEL: define <16 x i8> @test_vld1q_dup_p8(5893// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5894// CHECK-NEXT: [[ENTRY:.*:]]5895// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 15896// CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i32 05897// CHECK-NEXT: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> zeroinitializer5898// CHECK-NEXT: ret <16 x i8> [[LANE]]5899//5900poly8x16_t test_vld1q_dup_p8(poly8_t const * a) {5901 return vld1q_dup_p8(a);5902}5903 5904// CHECK-LABEL: define <8 x i16> @test_vld1q_dup_p16(5905// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5906// CHECK-NEXT: [[ENTRY:.*:]]5907// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 25908// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP0]], i32 05909// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> [[TMP1]], <8 x i32> zeroinitializer5910// CHECK-NEXT: ret <8 x i16> [[LANE]]5911//5912poly16x8_t test_vld1q_dup_p16(poly16_t const * a) {5913 return vld1q_dup_p16(a);5914}5915 5916// CHECK-LABEL: define <8 x i8> @test_vld1_dup_u8(5917// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5918// CHECK-NEXT: [[ENTRY:.*:]]5919// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 15920// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i32 05921// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP1]], <8 x i32> zeroinitializer5922// CHECK-NEXT: ret <8 x i8> [[LANE]]5923//5924uint8x8_t test_vld1_dup_u8(uint8_t const * a) {5925 return vld1_dup_u8(a);5926}5927 5928// CHECK-LABEL: define <4 x i16> @test_vld1_dup_u16(5929// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5930// CHECK-NEXT: [[ENTRY:.*:]]5931// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 25932// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i32 05933// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> zeroinitializer5934// CHECK-NEXT: ret <4 x i16> [[LANE]]5935//5936uint16x4_t test_vld1_dup_u16(uint16_t const * a) {5937 return vld1_dup_u16(a);5938}5939 5940// CHECK-LABEL: define <2 x i32> @test_vld1_dup_u32(5941// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5942// CHECK-NEXT: [[ENTRY:.*:]]5943// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 45944// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 05945// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> zeroinitializer5946// CHECK-NEXT: ret <2 x i32> [[LANE]]5947//5948uint32x2_t test_vld1_dup_u32(uint32_t const * a) {5949 return vld1_dup_u32(a);5950}5951 5952// CHECK-LABEL: define <1 x i64> @test_vld1_dup_u64(5953// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5954// CHECK-NEXT: [[ENTRY:.*:]]5955// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 45956// CHECK-NEXT: [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i32 05957// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <1 x i32> zeroinitializer5958// CHECK-NEXT: ret <1 x i64> [[LANE]]5959//5960uint64x1_t test_vld1_dup_u64(uint64_t const * a) {5961 return vld1_dup_u64(a);5962}5963 5964// CHECK-LABEL: define <8 x i8> @test_vld1_dup_s8(5965// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5966// CHECK-NEXT: [[ENTRY:.*:]]5967// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 15968// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i32 05969// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP1]], <8 x i32> zeroinitializer5970// CHECK-NEXT: ret <8 x i8> [[LANE]]5971//5972int8x8_t test_vld1_dup_s8(int8_t const * a) {5973 return vld1_dup_s8(a);5974}5975 5976// CHECK-LABEL: define <4 x i16> @test_vld1_dup_s16(5977// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5978// CHECK-NEXT: [[ENTRY:.*:]]5979// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 25980// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i32 05981// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> zeroinitializer5982// CHECK-NEXT: ret <4 x i16> [[LANE]]5983//5984int16x4_t test_vld1_dup_s16(int16_t const * a) {5985 return vld1_dup_s16(a);5986}5987 5988// CHECK-LABEL: define <2 x i32> @test_vld1_dup_s32(5989// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {5990// CHECK-NEXT: [[ENTRY:.*:]]5991// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 45992// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 05993// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> zeroinitializer5994// CHECK-NEXT: ret <2 x i32> [[LANE]]5995//5996int32x2_t test_vld1_dup_s32(int32_t const * a) {5997 return vld1_dup_s32(a);5998}5999 6000// CHECK-LABEL: define <1 x i64> @test_vld1_dup_s64(6001// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {6002// CHECK-NEXT: [[ENTRY:.*:]]6003// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 46004// CHECK-NEXT: [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i32 06005// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <1 x i32> zeroinitializer6006// CHECK-NEXT: ret <1 x i64> [[LANE]]6007//6008int64x1_t test_vld1_dup_s64(int64_t const * a) {6009 return vld1_dup_s64(a);6010}6011 6012// CHECK-LABEL: define <4 x half> @test_vld1_dup_f16(6013// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {6014// CHECK-NEXT: [[ENTRY:.*:]]6015// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A]], align 26016// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x half> poison, half [[TMP0]], i32 06017// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x half> [[TMP1]], <4 x half> [[TMP1]], <4 x i32> zeroinitializer6018// CHECK-NEXT: ret <4 x half> [[LANE]]6019//6020float16x4_t test_vld1_dup_f16(float16_t const * a) {6021 return vld1_dup_f16(a);6022}6023 6024// CHECK-LABEL: define <2 x float> @test_vld1_dup_f32(6025// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {6026// CHECK-NEXT: [[ENTRY:.*:]]6027// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[A]], align 46028// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 06029// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> zeroinitializer6030// CHECK-NEXT: ret <2 x float> [[LANE]]6031//6032float32x2_t test_vld1_dup_f32(float32_t const * a) {6033 return vld1_dup_f32(a);6034}6035 6036// CHECK-LABEL: define <8 x i8> @test_vld1_dup_p8(6037// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {6038// CHECK-NEXT: [[ENTRY:.*:]]6039// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 16040// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i32 06041// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP1]], <8 x i32> zeroinitializer6042// CHECK-NEXT: ret <8 x i8> [[LANE]]6043//6044poly8x8_t test_vld1_dup_p8(poly8_t const * a) {6045 return vld1_dup_p8(a);6046}6047 6048// CHECK-LABEL: define <4 x i16> @test_vld1_dup_p16(6049// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {6050// CHECK-NEXT: [[ENTRY:.*:]]6051// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 26052// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i32 06053// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> zeroinitializer6054// CHECK-NEXT: ret <4 x i16> [[LANE]]6055//6056poly16x4_t test_vld1_dup_p16(poly16_t const * a) {6057 return vld1_dup_p16(a);6058}6059 6060// CHECK-LABEL: define <16 x i8> @test_vld1q_lane_u8(6061// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {6062// CHECK-NEXT: [[ENTRY:.*:]]6063// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 16064// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i32 156065// CHECK-NEXT: ret <16 x i8> [[VLD1_LANE]]6066//6067uint8x16_t test_vld1q_lane_u8(uint8_t const * a, uint8x16_t b) {6068 return vld1q_lane_u8(a, b, 15);6069}6070 6071// CHECK-LABEL: define <8 x i16> @test_vld1q_lane_u16(6072// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {6073// CHECK-NEXT: [[ENTRY:.*:]]6074// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>6075// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>6076// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 26077// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[TMP2]], i32 76078// CHECK-NEXT: ret <8 x i16> [[VLD1_LANE]]6079//6080uint16x8_t test_vld1q_lane_u16(uint16_t const * a, uint16x8_t b) {6081 return vld1q_lane_u16(a, b, 7);6082}6083 6084// CHECK-LABEL: define <4 x i32> @test_vld1q_lane_u32(6085// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {6086// CHECK-NEXT: [[ENTRY:.*:]]6087// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>6088// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>6089// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 46090// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP2]], i32 36091// CHECK-NEXT: ret <4 x i32> [[VLD1_LANE]]6092//6093uint32x4_t test_vld1q_lane_u32(uint32_t const * a, uint32x4_t b) {6094 return vld1q_lane_u32(a, b, 3);6095}6096 6097// CHECK-LABEL: define <2 x i64> @test_vld1q_lane_u64(6098// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {6099// CHECK-NEXT: [[ENTRY:.*:]]6100// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>6101// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>6102// CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP1]], <1 x i32> zeroinitializer6103// CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr [[A]], i32 4)6104// CHECK-NEXT: [[VLD1Q_LANE:%.*]] = shufflevector <1 x i64> [[TMP2]], <1 x i64> [[TMP3]], <2 x i32> <i32 0, i32 1>6105// CHECK-NEXT: ret <2 x i64> [[VLD1Q_LANE]]6106//6107uint64x2_t test_vld1q_lane_u64(uint64_t const * a, uint64x2_t b) {6108 return vld1q_lane_u64(a, b, 1);6109}6110 6111// CHECK-LABEL: define <16 x i8> @test_vld1q_lane_s8(6112// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {6113// CHECK-NEXT: [[ENTRY:.*:]]6114// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 16115// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i32 156116// CHECK-NEXT: ret <16 x i8> [[VLD1_LANE]]6117//6118int8x16_t test_vld1q_lane_s8(int8_t const * a, int8x16_t b) {6119 return vld1q_lane_s8(a, b, 15);6120}6121 6122// CHECK-LABEL: define <8 x i16> @test_vld1q_lane_s16(6123// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {6124// CHECK-NEXT: [[ENTRY:.*:]]6125// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>6126// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>6127// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 26128// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[TMP2]], i32 76129// CHECK-NEXT: ret <8 x i16> [[VLD1_LANE]]6130//6131int16x8_t test_vld1q_lane_s16(int16_t const * a, int16x8_t b) {6132 return vld1q_lane_s16(a, b, 7);6133}6134 6135// CHECK-LABEL: define <4 x i32> @test_vld1q_lane_s32(6136// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {6137// CHECK-NEXT: [[ENTRY:.*:]]6138// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>6139// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>6140// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 46141// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP2]], i32 36142// CHECK-NEXT: ret <4 x i32> [[VLD1_LANE]]6143//6144int32x4_t test_vld1q_lane_s32(int32_t const * a, int32x4_t b) {6145 return vld1q_lane_s32(a, b, 3);6146}6147 6148// CHECK-LABEL: define <2 x i64> @test_vld1q_lane_s64(6149// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {6150// CHECK-NEXT: [[ENTRY:.*:]]6151// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>6152// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>6153// CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP1]], <1 x i32> zeroinitializer6154// CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0(ptr [[A]], i32 4)6155// CHECK-NEXT: [[VLD1Q_LANE:%.*]] = shufflevector <1 x i64> [[TMP2]], <1 x i64> [[TMP3]], <2 x i32> <i32 0, i32 1>6156// CHECK-NEXT: ret <2 x i64> [[VLD1Q_LANE]]6157//6158int64x2_t test_vld1q_lane_s64(int64_t const * a, int64x2_t b) {6159 return vld1q_lane_s64(a, b, 1);6160}6161 6162// CHECK-LABEL: define <8 x half> @test_vld1q_lane_f16(6163// CHECK-SAME: ptr noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {6164// CHECK-NEXT: [[ENTRY:.*:]]6165// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[B]] to <8 x i16>6166// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>6167// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>6168// CHECK-NEXT: [[TMP3:%.*]] = load half, ptr [[A]], align 26169// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x half> [[TMP2]], half [[TMP3]], i32 76170// CHECK-NEXT: ret <8 x half> [[VLD1_LANE]]6171//6172float16x8_t test_vld1q_lane_f16(float16_t const * a, float16x8_t b) {6173 return vld1q_lane_f16(a, b, 7);6174}6175 6176// CHECK-LABEL: define <4 x float> @test_vld1q_lane_f32(6177// CHECK-SAME: ptr noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {6178// CHECK-NEXT: [[ENTRY:.*:]]6179// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>6180// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>6181// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>6182// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[A]], align 46183// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x float> [[TMP2]], float [[TMP3]], i32 36184// CHECK-NEXT: ret <4 x float> [[VLD1_LANE]]6185//6186float32x4_t test_vld1q_lane_f32(float32_t const * a, float32x4_t b) {6187 return vld1q_lane_f32(a, b, 3);6188}6189 6190// CHECK-LABEL: define <16 x i8> @test_vld1q_lane_p8(6191// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {6192// CHECK-NEXT: [[ENTRY:.*:]]6193// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 16194// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i32 156195// CHECK-NEXT: ret <16 x i8> [[VLD1_LANE]]6196//6197poly8x16_t test_vld1q_lane_p8(poly8_t const * a, poly8x16_t b) {6198 return vld1q_lane_p8(a, b, 15);6199}6200 6201// CHECK-LABEL: define <8 x i16> @test_vld1q_lane_p16(6202// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {6203// CHECK-NEXT: [[ENTRY:.*:]]6204// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>6205// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>6206// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 26207// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[TMP2]], i32 76208// CHECK-NEXT: ret <8 x i16> [[VLD1_LANE]]6209//6210poly16x8_t test_vld1q_lane_p16(poly16_t const * a, poly16x8_t b) {6211 return vld1q_lane_p16(a, b, 7);6212}6213 6214// CHECK-LABEL: define <8 x i8> @test_vld1_lane_u8(6215// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {6216// CHECK-NEXT: [[ENTRY:.*:]]6217// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 16218// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i32 76219// CHECK-NEXT: ret <8 x i8> [[VLD1_LANE]]6220//6221uint8x8_t test_vld1_lane_u8(uint8_t const * a, uint8x8_t b) {6222 return vld1_lane_u8(a, b, 7);6223}6224 6225// CHECK-LABEL: define <4 x i16> @test_vld1_lane_u16(6226// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {6227// CHECK-NEXT: [[ENTRY:.*:]]6228// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>6229// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>6230// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 26231// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[TMP2]], i32 36232// CHECK-NEXT: ret <4 x i16> [[VLD1_LANE]]6233//6234uint16x4_t test_vld1_lane_u16(uint16_t const * a, uint16x4_t b) {6235 return vld1_lane_u16(a, b, 3);6236}6237 6238// CHECK-LABEL: define <2 x i32> @test_vld1_lane_u32(6239// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {6240// CHECK-NEXT: [[ENTRY:.*:]]6241// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>6242// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>6243// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 46244// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[TMP2]], i32 16245// CHECK-NEXT: ret <2 x i32> [[VLD1_LANE]]6246//6247uint32x2_t test_vld1_lane_u32(uint32_t const * a, uint32x2_t b) {6248 return vld1_lane_u32(a, b, 1);6249}6250 6251// CHECK-LABEL: define <1 x i64> @test_vld1_lane_u64(6252// CHECK-SAME: ptr noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {6253// CHECK-NEXT: [[ENTRY:.*:]]6254// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>6255// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>6256// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[A]], align 46257// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <1 x i64> [[TMP1]], i64 [[TMP2]], i32 06258// CHECK-NEXT: ret <1 x i64> [[VLD1_LANE]]6259//6260uint64x1_t test_vld1_lane_u64(uint64_t const * a, uint64x1_t b) {6261 return vld1_lane_u64(a, b, 0);6262}6263 6264// CHECK-LABEL: define <8 x i8> @test_vld1_lane_s8(6265// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {6266// CHECK-NEXT: [[ENTRY:.*:]]6267// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 16268// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i32 76269// CHECK-NEXT: ret <8 x i8> [[VLD1_LANE]]6270//6271int8x8_t test_vld1_lane_s8(int8_t const * a, int8x8_t b) {6272 return vld1_lane_s8(a, b, 7);6273}6274 6275// CHECK-LABEL: define <4 x i16> @test_vld1_lane_s16(6276// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {6277// CHECK-NEXT: [[ENTRY:.*:]]6278// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>6279// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>6280// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 26281// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[TMP2]], i32 36282// CHECK-NEXT: ret <4 x i16> [[VLD1_LANE]]6283//6284int16x4_t test_vld1_lane_s16(int16_t const * a, int16x4_t b) {6285 return vld1_lane_s16(a, b, 3);6286}6287 6288// CHECK-LABEL: define <2 x i32> @test_vld1_lane_s32(6289// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {6290// CHECK-NEXT: [[ENTRY:.*:]]6291// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>6292// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>6293// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 46294// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[TMP2]], i32 16295// CHECK-NEXT: ret <2 x i32> [[VLD1_LANE]]6296//6297int32x2_t test_vld1_lane_s32(int32_t const * a, int32x2_t b) {6298 return vld1_lane_s32(a, b, 1);6299}6300 6301// CHECK-LABEL: define <1 x i64> @test_vld1_lane_s64(6302// CHECK-SAME: ptr noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {6303// CHECK-NEXT: [[ENTRY:.*:]]6304// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>6305// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>6306// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[A]], align 46307// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <1 x i64> [[TMP1]], i64 [[TMP2]], i32 06308// CHECK-NEXT: ret <1 x i64> [[VLD1_LANE]]6309//6310int64x1_t test_vld1_lane_s64(int64_t const * a, int64x1_t b) {6311 return vld1_lane_s64(a, b, 0);6312}6313 6314// CHECK-LABEL: define <4 x half> @test_vld1_lane_f16(6315// CHECK-SAME: ptr noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {6316// CHECK-NEXT: [[ENTRY:.*:]]6317// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[B]] to <4 x i16>6318// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>6319// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>6320// CHECK-NEXT: [[TMP3:%.*]] = load half, ptr [[A]], align 26321// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x half> [[TMP2]], half [[TMP3]], i32 36322// CHECK-NEXT: ret <4 x half> [[VLD1_LANE]]6323//6324float16x4_t test_vld1_lane_f16(float16_t const * a, float16x4_t b) {6325 return vld1_lane_f16(a, b, 3);6326}6327 6328// CHECK-LABEL: define <2 x float> @test_vld1_lane_f32(6329// CHECK-SAME: ptr noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {6330// CHECK-NEXT: [[ENTRY:.*:]]6331// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>6332// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>6333// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>6334// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[A]], align 46335// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <2 x float> [[TMP2]], float [[TMP3]], i32 16336// CHECK-NEXT: ret <2 x float> [[VLD1_LANE]]6337//6338float32x2_t test_vld1_lane_f32(float32_t const * a, float32x2_t b) {6339 return vld1_lane_f32(a, b, 1);6340}6341 6342// CHECK-LABEL: define <8 x i8> @test_vld1_lane_p8(6343// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {6344// CHECK-NEXT: [[ENTRY:.*:]]6345// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 16346// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i32 76347// CHECK-NEXT: ret <8 x i8> [[VLD1_LANE]]6348//6349poly8x8_t test_vld1_lane_p8(poly8_t const * a, poly8x8_t b) {6350 return vld1_lane_p8(a, b, 7);6351}6352 6353// CHECK-LABEL: define <4 x i16> @test_vld1_lane_p16(6354// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {6355// CHECK-NEXT: [[ENTRY:.*:]]6356// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>6357// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>6358// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 26359// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[TMP2]], i32 36360// CHECK-NEXT: ret <4 x i16> [[VLD1_LANE]]6361//6362poly16x4_t test_vld1_lane_p16(poly16_t const * a, poly16x4_t b) {6363 return vld1_lane_p16(a, b, 3);6364}6365 6366// CHECK-LABEL: define void @test_vld2q_u8(6367// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X16X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6368// CHECK-NEXT: [[ENTRY:.*:]]6369// CHECK-NEXT: [[VLD2Q_V:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2.v16i8.p0(ptr [[A]], i32 1)6370// CHECK-NEXT: [[VLD2Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[VLD2Q_V]], 06371// CHECK-NEXT: [[VLD2Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[VLD2Q_V]], 16372// CHECK-NEXT: store <16 x i8> [[VLD2Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166373// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166374// CHECK-NEXT: store <16 x i8> [[VLD2Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166375// CHECK-NEXT: ret void6376//6377uint8x16x2_t test_vld2q_u8(uint8_t const * a) {6378 return vld2q_u8(a);6379}6380 6381// CHECK-LABEL: define void @test_vld2q_u16(6382// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6383// CHECK-NEXT: [[ENTRY:.*:]]6384// CHECK-NEXT: [[VLD2Q_V:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2.v8i16.p0(ptr [[A]], i32 2)6385// CHECK-NEXT: [[VLD2Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_V]], 06386// CHECK-NEXT: [[VLD2Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_V]], 16387// CHECK-NEXT: store <8 x i16> [[VLD2Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166388// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166389// CHECK-NEXT: store <8 x i16> [[VLD2Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166390// CHECK-NEXT: ret void6391//6392uint16x8x2_t test_vld2q_u16(uint16_t const * a) {6393 return vld2q_u16(a);6394}6395 6396// CHECK-LABEL: define void @test_vld2q_u32(6397// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X4X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6398// CHECK-NEXT: [[ENTRY:.*:]]6399// CHECK-NEXT: [[VLD2Q_V:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0(ptr [[A]], i32 4)6400// CHECK-NEXT: [[VLD2Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2Q_V]], 06401// CHECK-NEXT: [[VLD2Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2Q_V]], 16402// CHECK-NEXT: store <4 x i32> [[VLD2Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166403// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166404// CHECK-NEXT: store <4 x i32> [[VLD2Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166405// CHECK-NEXT: ret void6406//6407uint32x4x2_t test_vld2q_u32(uint32_t const * a) {6408 return vld2q_u32(a);6409}6410 6411// CHECK-LABEL: define void @test_vld2q_s8(6412// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X16X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6413// CHECK-NEXT: [[ENTRY:.*:]]6414// CHECK-NEXT: [[VLD2Q_V:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2.v16i8.p0(ptr [[A]], i32 1)6415// CHECK-NEXT: [[VLD2Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[VLD2Q_V]], 06416// CHECK-NEXT: [[VLD2Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[VLD2Q_V]], 16417// CHECK-NEXT: store <16 x i8> [[VLD2Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166418// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166419// CHECK-NEXT: store <16 x i8> [[VLD2Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166420// CHECK-NEXT: ret void6421//6422int8x16x2_t test_vld2q_s8(int8_t const * a) {6423 return vld2q_s8(a);6424}6425 6426// CHECK-LABEL: define void @test_vld2q_s16(6427// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6428// CHECK-NEXT: [[ENTRY:.*:]]6429// CHECK-NEXT: [[VLD2Q_V:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2.v8i16.p0(ptr [[A]], i32 2)6430// CHECK-NEXT: [[VLD2Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_V]], 06431// CHECK-NEXT: [[VLD2Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_V]], 16432// CHECK-NEXT: store <8 x i16> [[VLD2Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166433// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166434// CHECK-NEXT: store <8 x i16> [[VLD2Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166435// CHECK-NEXT: ret void6436//6437int16x8x2_t test_vld2q_s16(int16_t const * a) {6438 return vld2q_s16(a);6439}6440 6441// CHECK-LABEL: define void @test_vld2q_s32(6442// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X4X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6443// CHECK-NEXT: [[ENTRY:.*:]]6444// CHECK-NEXT: [[VLD2Q_V:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0(ptr [[A]], i32 4)6445// CHECK-NEXT: [[VLD2Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2Q_V]], 06446// CHECK-NEXT: [[VLD2Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2Q_V]], 16447// CHECK-NEXT: store <4 x i32> [[VLD2Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166448// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166449// CHECK-NEXT: store <4 x i32> [[VLD2Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166450// CHECK-NEXT: ret void6451//6452int32x4x2_t test_vld2q_s32(int32_t const * a) {6453 return vld2q_s32(a);6454}6455 6456// CHECK-LABEL: define void @test_vld2q_f16(6457// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6458// CHECK-NEXT: [[ENTRY:.*:]]6459// CHECK-NEXT: [[VLD2Q_V:%.*]] = call { <8 x half>, <8 x half> } @llvm.arm.neon.vld2.v8f16.p0(ptr [[A]], i32 2)6460// CHECK-NEXT: [[VLD2Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half> } [[VLD2Q_V]], 06461// CHECK-NEXT: [[VLD2Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half> } [[VLD2Q_V]], 16462// CHECK-NEXT: store <8 x half> [[VLD2Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166463// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166464// CHECK-NEXT: store <8 x half> [[VLD2Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166465// CHECK-NEXT: ret void6466//6467float16x8x2_t test_vld2q_f16(float16_t const * a) {6468 return vld2q_f16(a);6469}6470 6471// CHECK-LABEL: define void @test_vld2q_f32(6472// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X4X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6473// CHECK-NEXT: [[ENTRY:.*:]]6474// CHECK-NEXT: [[VLD2Q_V:%.*]] = call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0(ptr [[A]], i32 4)6475// CHECK-NEXT: [[VLD2Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float> } [[VLD2Q_V]], 06476// CHECK-NEXT: [[VLD2Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float> } [[VLD2Q_V]], 16477// CHECK-NEXT: store <4 x float> [[VLD2Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166478// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166479// CHECK-NEXT: store <4 x float> [[VLD2Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166480// CHECK-NEXT: ret void6481//6482float32x4x2_t test_vld2q_f32(float32_t const * a) {6483 return vld2q_f32(a);6484}6485 6486// CHECK-LABEL: define void @test_vld2q_p8(6487// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X16X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6488// CHECK-NEXT: [[ENTRY:.*:]]6489// CHECK-NEXT: [[VLD2Q_V:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2.v16i8.p0(ptr [[A]], i32 1)6490// CHECK-NEXT: [[VLD2Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[VLD2Q_V]], 06491// CHECK-NEXT: [[VLD2Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[VLD2Q_V]], 16492// CHECK-NEXT: store <16 x i8> [[VLD2Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166493// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166494// CHECK-NEXT: store <16 x i8> [[VLD2Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166495// CHECK-NEXT: ret void6496//6497poly8x16x2_t test_vld2q_p8(poly8_t const * a) {6498 return vld2q_p8(a);6499}6500 6501// CHECK-LABEL: define void @test_vld2q_p16(6502// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6503// CHECK-NEXT: [[ENTRY:.*:]]6504// CHECK-NEXT: [[VLD2Q_V:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2.v8i16.p0(ptr [[A]], i32 2)6505// CHECK-NEXT: [[VLD2Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_V]], 06506// CHECK-NEXT: [[VLD2Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_V]], 16507// CHECK-NEXT: store <8 x i16> [[VLD2Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166508// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166509// CHECK-NEXT: store <8 x i16> [[VLD2Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166510// CHECK-NEXT: ret void6511//6512poly16x8x2_t test_vld2q_p16(poly16_t const * a) {6513 return vld2q_p16(a);6514}6515 6516// CHECK-LABEL: define void @test_vld2_u8(6517// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X8X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6518// CHECK-NEXT: [[ENTRY:.*:]]6519// CHECK-NEXT: [[VLD2_V:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2.v8i8.p0(ptr [[A]], i32 1)6520// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_V]], 06521// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_V]], 16522// CHECK-NEXT: store <8 x i8> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86523// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86524// CHECK-NEXT: store <8 x i8> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86525// CHECK-NEXT: ret void6526//6527uint8x8x2_t test_vld2_u8(uint8_t const * a) {6528 return vld2_u8(a);6529}6530 6531// CHECK-LABEL: define void @test_vld2_u16(6532// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6533// CHECK-NEXT: [[ENTRY:.*:]]6534// CHECK-NEXT: [[VLD2_V:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2.v4i16.p0(ptr [[A]], i32 2)6535// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_V]], 06536// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_V]], 16537// CHECK-NEXT: store <4 x i16> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86538// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86539// CHECK-NEXT: store <4 x i16> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86540// CHECK-NEXT: ret void6541//6542uint16x4x2_t test_vld2_u16(uint16_t const * a) {6543 return vld2_u16(a);6544}6545 6546// CHECK-LABEL: define void @test_vld2_u32(6547// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X2X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6548// CHECK-NEXT: [[ENTRY:.*:]]6549// CHECK-NEXT: [[VLD2_V:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2.v2i32.p0(ptr [[A]], i32 4)6550// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[VLD2_V]], 06551// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[VLD2_V]], 16552// CHECK-NEXT: store <2 x i32> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86553// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86554// CHECK-NEXT: store <2 x i32> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86555// CHECK-NEXT: ret void6556//6557uint32x2x2_t test_vld2_u32(uint32_t const * a) {6558 return vld2_u32(a);6559}6560 6561// CHECK-LABEL: define void @test_vld2_u64(6562// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT64X1X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6563// CHECK-NEXT: [[ENTRY:.*:]]6564// CHECK-NEXT: [[VLD2_V:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.arm.neon.vld2.v1i64.p0(ptr [[A]], i32 4)6565// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64> } [[VLD2_V]], 06566// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64> } [[VLD2_V]], 16567// CHECK-NEXT: store <1 x i64> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86568// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86569// CHECK-NEXT: store <1 x i64> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86570// CHECK-NEXT: ret void6571//6572uint64x1x2_t test_vld2_u64(uint64_t const * a) {6573 return vld2_u64(a);6574}6575 6576// CHECK-LABEL: define void @test_vld2_s8(6577// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X8X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6578// CHECK-NEXT: [[ENTRY:.*:]]6579// CHECK-NEXT: [[VLD2_V:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2.v8i8.p0(ptr [[A]], i32 1)6580// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_V]], 06581// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_V]], 16582// CHECK-NEXT: store <8 x i8> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86583// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86584// CHECK-NEXT: store <8 x i8> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86585// CHECK-NEXT: ret void6586//6587int8x8x2_t test_vld2_s8(int8_t const * a) {6588 return vld2_s8(a);6589}6590 6591// CHECK-LABEL: define void @test_vld2_s16(6592// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6593// CHECK-NEXT: [[ENTRY:.*:]]6594// CHECK-NEXT: [[VLD2_V:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2.v4i16.p0(ptr [[A]], i32 2)6595// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_V]], 06596// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_V]], 16597// CHECK-NEXT: store <4 x i16> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86598// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86599// CHECK-NEXT: store <4 x i16> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86600// CHECK-NEXT: ret void6601//6602int16x4x2_t test_vld2_s16(int16_t const * a) {6603 return vld2_s16(a);6604}6605 6606// CHECK-LABEL: define void @test_vld2_s32(6607// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X2X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6608// CHECK-NEXT: [[ENTRY:.*:]]6609// CHECK-NEXT: [[VLD2_V:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2.v2i32.p0(ptr [[A]], i32 4)6610// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[VLD2_V]], 06611// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[VLD2_V]], 16612// CHECK-NEXT: store <2 x i32> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86613// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86614// CHECK-NEXT: store <2 x i32> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86615// CHECK-NEXT: ret void6616//6617int32x2x2_t test_vld2_s32(int32_t const * a) {6618 return vld2_s32(a);6619}6620 6621// CHECK-LABEL: define void @test_vld2_s64(6622// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT64X1X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6623// CHECK-NEXT: [[ENTRY:.*:]]6624// CHECK-NEXT: [[VLD2_V:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.arm.neon.vld2.v1i64.p0(ptr [[A]], i32 4)6625// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64> } [[VLD2_V]], 06626// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64> } [[VLD2_V]], 16627// CHECK-NEXT: store <1 x i64> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86628// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86629// CHECK-NEXT: store <1 x i64> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86630// CHECK-NEXT: ret void6631//6632int64x1x2_t test_vld2_s64(int64_t const * a) {6633 return vld2_s64(a);6634}6635 6636// CHECK-LABEL: define void @test_vld2_f16(6637// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6638// CHECK-NEXT: [[ENTRY:.*:]]6639// CHECK-NEXT: [[VLD2_V:%.*]] = call { <4 x half>, <4 x half> } @llvm.arm.neon.vld2.v4f16.p0(ptr [[A]], i32 2)6640// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half> } [[VLD2_V]], 06641// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half> } [[VLD2_V]], 16642// CHECK-NEXT: store <4 x half> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86643// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86644// CHECK-NEXT: store <4 x half> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86645// CHECK-NEXT: ret void6646//6647float16x4x2_t test_vld2_f16(float16_t const * a) {6648 return vld2_f16(a);6649}6650 6651// CHECK-LABEL: define void @test_vld2_f32(6652// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X2X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6653// CHECK-NEXT: [[ENTRY:.*:]]6654// CHECK-NEXT: [[VLD2_V:%.*]] = call { <2 x float>, <2 x float> } @llvm.arm.neon.vld2.v2f32.p0(ptr [[A]], i32 4)6655// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float> } [[VLD2_V]], 06656// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float> } [[VLD2_V]], 16657// CHECK-NEXT: store <2 x float> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86658// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86659// CHECK-NEXT: store <2 x float> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86660// CHECK-NEXT: ret void6661//6662float32x2x2_t test_vld2_f32(float32_t const * a) {6663 return vld2_f32(a);6664}6665 6666// CHECK-LABEL: define void @test_vld2_p8(6667// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X8X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6668// CHECK-NEXT: [[ENTRY:.*:]]6669// CHECK-NEXT: [[VLD2_V:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2.v8i8.p0(ptr [[A]], i32 1)6670// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_V]], 06671// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_V]], 16672// CHECK-NEXT: store <8 x i8> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86673// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86674// CHECK-NEXT: store <8 x i8> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86675// CHECK-NEXT: ret void6676//6677poly8x8x2_t test_vld2_p8(poly8_t const * a) {6678 return vld2_p8(a);6679}6680 6681// CHECK-LABEL: define void @test_vld2_p16(6682// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {6683// CHECK-NEXT: [[ENTRY:.*:]]6684// CHECK-NEXT: [[VLD2_V:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2.v4i16.p0(ptr [[A]], i32 2)6685// CHECK-NEXT: [[VLD2_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_V]], 06686// CHECK-NEXT: [[VLD2_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_V]], 16687// CHECK-NEXT: store <4 x i16> [[VLD2_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86688// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86689// CHECK-NEXT: store <4 x i16> [[VLD2_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86690// CHECK-NEXT: ret void6691//6692poly16x4x2_t test_vld2_p16(poly16_t const * a) {6693 return vld2_p16(a);6694}6695 6696// CHECK-LABEL: define void @test_vld2q_lane_u16(6697// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6698// CHECK-NEXT: [[ENTRY:.*:]]6699// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 06700// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 06701// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 16702// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 16703// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 26704// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 06705// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 36706// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 16707// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>6708// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>6709// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>6710// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>6711// CHECK-NEXT: [[VLD2Q_LANE_V:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2lane.v8i16.p0(ptr [[A]], <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], i32 7, i32 2)6712// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_LANE_V]], 06713// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_LANE_V]], 16714// CHECK-NEXT: store <8 x i16> [[VLD2Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166715// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166716// CHECK-NEXT: store <8 x i16> [[VLD2Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166717// CHECK-NEXT: ret void6718//6719uint16x8x2_t test_vld2q_lane_u16(uint16_t const * a, uint16x8x2_t b) {6720 return vld2q_lane_u16(a, b, 7);6721}6722 6723// CHECK-LABEL: define void @test_vld2q_lane_u32(6724// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X4X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6725// CHECK-NEXT: [[ENTRY:.*:]]6726// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 06727// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 06728// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 16729// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 16730// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 26731// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 06732// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 36733// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 16734// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>6735// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>6736// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>6737// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>6738// CHECK-NEXT: [[VLD2Q_LANE_V:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32.p0(ptr [[A]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], i32 3, i32 4)6739// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2Q_LANE_V]], 06740// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2Q_LANE_V]], 16741// CHECK-NEXT: store <4 x i32> [[VLD2Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166742// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166743// CHECK-NEXT: store <4 x i32> [[VLD2Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166744// CHECK-NEXT: ret void6745//6746uint32x4x2_t test_vld2q_lane_u32(uint32_t const * a, uint32x4x2_t b) {6747 return vld2q_lane_u32(a, b, 3);6748}6749 6750// CHECK-LABEL: define void @test_vld2q_lane_s16(6751// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6752// CHECK-NEXT: [[ENTRY:.*:]]6753// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 06754// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 06755// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 16756// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 16757// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 26758// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 06759// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 36760// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 16761// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>6762// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>6763// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>6764// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>6765// CHECK-NEXT: [[VLD2Q_LANE_V:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2lane.v8i16.p0(ptr [[A]], <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], i32 7, i32 2)6766// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_LANE_V]], 06767// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_LANE_V]], 16768// CHECK-NEXT: store <8 x i16> [[VLD2Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166769// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166770// CHECK-NEXT: store <8 x i16> [[VLD2Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166771// CHECK-NEXT: ret void6772//6773int16x8x2_t test_vld2q_lane_s16(int16_t const * a, int16x8x2_t b) {6774 return vld2q_lane_s16(a, b, 7);6775}6776 6777// CHECK-LABEL: define void @test_vld2q_lane_s32(6778// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X4X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6779// CHECK-NEXT: [[ENTRY:.*:]]6780// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 06781// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 06782// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 16783// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 16784// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 26785// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 06786// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 36787// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 16788// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>6789// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>6790// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>6791// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>6792// CHECK-NEXT: [[VLD2Q_LANE_V:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32.p0(ptr [[A]], <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], i32 3, i32 4)6793// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2Q_LANE_V]], 06794// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[VLD2Q_LANE_V]], 16795// CHECK-NEXT: store <4 x i32> [[VLD2Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166796// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166797// CHECK-NEXT: store <4 x i32> [[VLD2Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166798// CHECK-NEXT: ret void6799//6800int32x4x2_t test_vld2q_lane_s32(int32_t const * a, int32x4x2_t b) {6801 return vld2q_lane_s32(a, b, 3);6802}6803 6804// CHECK-LABEL: define void @test_vld2q_lane_f16(6805// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6806// CHECK-NEXT: [[ENTRY:.*:]]6807// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 06808// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 06809// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 16810// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 16811// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 26812// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 06813// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 36814// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 16815// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>6816// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>6817// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>6818// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>6819// CHECK-NEXT: [[VLD2Q_LANE_V:%.*]] = call { <8 x half>, <8 x half> } @llvm.arm.neon.vld2lane.v8f16.p0(ptr [[A]], <8 x half> [[TMP2]], <8 x half> [[TMP3]], i32 7, i32 2)6820// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half> } [[VLD2Q_LANE_V]], 06821// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half> } [[VLD2Q_LANE_V]], 16822// CHECK-NEXT: store <8 x half> [[VLD2Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166823// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166824// CHECK-NEXT: store <8 x half> [[VLD2Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166825// CHECK-NEXT: ret void6826//6827float16x8x2_t test_vld2q_lane_f16(float16_t const * a, float16x8x2_t b) {6828 return vld2q_lane_f16(a, b, 7);6829}6830 6831// CHECK-LABEL: define void @test_vld2q_lane_f32(6832// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X4X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6833// CHECK-NEXT: [[ENTRY:.*:]]6834// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 06835// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 06836// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 16837// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 16838// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 26839// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 06840// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 36841// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 16842// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>6843// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>6844// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>6845// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>6846// CHECK-NEXT: [[VLD2Q_LANE_V:%.*]] = call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2lane.v4f32.p0(ptr [[A]], <4 x float> [[TMP2]], <4 x float> [[TMP3]], i32 3, i32 4)6847// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float> } [[VLD2Q_LANE_V]], 06848// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float> } [[VLD2Q_LANE_V]], 16849// CHECK-NEXT: store <4 x float> [[VLD2Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166850// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166851// CHECK-NEXT: store <4 x float> [[VLD2Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166852// CHECK-NEXT: ret void6853//6854float32x4x2_t test_vld2q_lane_f32(float32_t const * a, float32x4x2_t b) {6855 return vld2q_lane_f32(a, b, 3);6856}6857 6858// CHECK-LABEL: define void @test_vld2q_lane_p16(6859// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X8X2_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6860// CHECK-NEXT: [[ENTRY:.*:]]6861// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 06862// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 06863// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 16864// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 16865// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 26866// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 06867// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 36868// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 16869// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>6870// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>6871// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>6872// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>6873// CHECK-NEXT: [[VLD2Q_LANE_V:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2lane.v8i16.p0(ptr [[A]], <8 x i16> [[TMP2]], <8 x i16> [[TMP3]], i32 7, i32 2)6874// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_LANE_V]], 06875// CHECK-NEXT: [[VLD2Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16> } [[VLD2Q_LANE_V]], 16876// CHECK-NEXT: store <8 x i16> [[VLD2Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 166877// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 166878// CHECK-NEXT: store <8 x i16> [[VLD2Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 166879// CHECK-NEXT: ret void6880//6881poly16x8x2_t test_vld2q_lane_p16(poly16_t const * a, poly16x8x2_t b) {6882 return vld2q_lane_p16(a, b, 7);6883}6884 6885// CHECK-LABEL: define void @test_vld2_lane_u8(6886// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X8X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [2 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6887// CHECK-NEXT: [[ENTRY:.*:]]6888// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 06889// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>6890// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 16891// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>6892// CHECK-NEXT: [[VLD2_LANE_V:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2lane.v8i8.p0(ptr [[A]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], i32 7, i32 1)6893// CHECK-NEXT: [[VLD2_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_LANE_V]], 06894// CHECK-NEXT: [[VLD2_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_LANE_V]], 16895// CHECK-NEXT: store <8 x i8> [[VLD2_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86896// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86897// CHECK-NEXT: store <8 x i8> [[VLD2_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86898// CHECK-NEXT: ret void6899//6900uint8x8x2_t test_vld2_lane_u8(uint8_t const * a, uint8x8x2_t b) {6901 return vld2_lane_u8(a, b, 7);6902}6903 6904// CHECK-LABEL: define void @test_vld2_lane_u16(6905// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [2 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6906// CHECK-NEXT: [[ENTRY:.*:]]6907// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 06908// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>6909// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 16910// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>6911// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>6912// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>6913// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>6914// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>6915// CHECK-NEXT: [[VLD2_LANE_V:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2lane.v4i16.p0(ptr [[A]], <4 x i16> [[TMP4]], <4 x i16> [[TMP5]], i32 3, i32 2)6916// CHECK-NEXT: [[VLD2_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_LANE_V]], 06917// CHECK-NEXT: [[VLD2_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_LANE_V]], 16918// CHECK-NEXT: store <4 x i16> [[VLD2_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86919// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86920// CHECK-NEXT: store <4 x i16> [[VLD2_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86921// CHECK-NEXT: ret void6922//6923uint16x4x2_t test_vld2_lane_u16(uint16_t const * a, uint16x4x2_t b) {6924 return vld2_lane_u16(a, b, 3);6925}6926 6927// CHECK-LABEL: define void @test_vld2_lane_u32(6928// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X2X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [2 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6929// CHECK-NEXT: [[ENTRY:.*:]]6930// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 06931// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>6932// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 16933// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>6934// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>6935// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>6936// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>6937// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>6938// CHECK-NEXT: [[VLD2_LANE_V:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2lane.v2i32.p0(ptr [[A]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], i32 1, i32 4)6939// CHECK-NEXT: [[VLD2_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[VLD2_LANE_V]], 06940// CHECK-NEXT: [[VLD2_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[VLD2_LANE_V]], 16941// CHECK-NEXT: store <2 x i32> [[VLD2_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86942// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86943// CHECK-NEXT: store <2 x i32> [[VLD2_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86944// CHECK-NEXT: ret void6945//6946uint32x2x2_t test_vld2_lane_u32(uint32_t const * a, uint32x2x2_t b) {6947 return vld2_lane_u32(a, b, 1);6948}6949 6950// CHECK-LABEL: define void @test_vld2_lane_s8(6951// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X8X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [2 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6952// CHECK-NEXT: [[ENTRY:.*:]]6953// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 06954// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>6955// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 16956// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>6957// CHECK-NEXT: [[VLD2_LANE_V:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2lane.v8i8.p0(ptr [[A]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], i32 7, i32 1)6958// CHECK-NEXT: [[VLD2_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_LANE_V]], 06959// CHECK-NEXT: [[VLD2_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_LANE_V]], 16960// CHECK-NEXT: store <8 x i8> [[VLD2_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86961// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86962// CHECK-NEXT: store <8 x i8> [[VLD2_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86963// CHECK-NEXT: ret void6964//6965int8x8x2_t test_vld2_lane_s8(int8_t const * a, int8x8x2_t b) {6966 return vld2_lane_s8(a, b, 7);6967}6968 6969// CHECK-LABEL: define void @test_vld2_lane_s16(6970// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [2 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6971// CHECK-NEXT: [[ENTRY:.*:]]6972// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 06973// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>6974// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 16975// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>6976// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>6977// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>6978// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>6979// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>6980// CHECK-NEXT: [[VLD2_LANE_V:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2lane.v4i16.p0(ptr [[A]], <4 x i16> [[TMP4]], <4 x i16> [[TMP5]], i32 3, i32 2)6981// CHECK-NEXT: [[VLD2_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_LANE_V]], 06982// CHECK-NEXT: [[VLD2_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_LANE_V]], 16983// CHECK-NEXT: store <4 x i16> [[VLD2_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 86984// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 86985// CHECK-NEXT: store <4 x i16> [[VLD2_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 86986// CHECK-NEXT: ret void6987//6988int16x4x2_t test_vld2_lane_s16(int16_t const * a, int16x4x2_t b) {6989 return vld2_lane_s16(a, b, 3);6990}6991 6992// CHECK-LABEL: define void @test_vld2_lane_s32(6993// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X2X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [2 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {6994// CHECK-NEXT: [[ENTRY:.*:]]6995// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 06996// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>6997// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 16998// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>6999// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>7000// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>7001// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>7002// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>7003// CHECK-NEXT: [[VLD2_LANE_V:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2lane.v2i32.p0(ptr [[A]], <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], i32 1, i32 4)7004// CHECK-NEXT: [[VLD2_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[VLD2_LANE_V]], 07005// CHECK-NEXT: [[VLD2_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32> } [[VLD2_LANE_V]], 17006// CHECK-NEXT: store <2 x i32> [[VLD2_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87007// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87008// CHECK-NEXT: store <2 x i32> [[VLD2_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87009// CHECK-NEXT: ret void7010//7011int32x2x2_t test_vld2_lane_s32(int32_t const * a, int32x2x2_t b) {7012 return vld2_lane_s32(a, b, 1);7013}7014 7015// CHECK-LABEL: define void @test_vld2_lane_f16(7016// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [2 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7017// CHECK-NEXT: [[ENTRY:.*:]]7018// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 07019// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x half>7020// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 17021// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x half>7022// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[TMP0]] to <8 x i8>7023// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x half> [[TMP1]] to <8 x i8>7024// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>7025// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x half>7026// CHECK-NEXT: [[VLD2_LANE_V:%.*]] = call { <4 x half>, <4 x half> } @llvm.arm.neon.vld2lane.v4f16.p0(ptr [[A]], <4 x half> [[TMP4]], <4 x half> [[TMP5]], i32 3, i32 2)7027// CHECK-NEXT: [[VLD2_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half> } [[VLD2_LANE_V]], 07028// CHECK-NEXT: [[VLD2_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half> } [[VLD2_LANE_V]], 17029// CHECK-NEXT: store <4 x half> [[VLD2_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87030// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87031// CHECK-NEXT: store <4 x half> [[VLD2_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87032// CHECK-NEXT: ret void7033//7034float16x4x2_t test_vld2_lane_f16(float16_t const * a, float16x4x2_t b) {7035 return vld2_lane_f16(a, b, 3);7036}7037 7038// CHECK-LABEL: define void @test_vld2_lane_f32(7039// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X2X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [2 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7040// CHECK-NEXT: [[ENTRY:.*:]]7041// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 07042// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <2 x float>7043// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 17044// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <2 x float>7045// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[TMP0]] to <8 x i8>7046// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[TMP1]] to <8 x i8>7047// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>7048// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>7049// CHECK-NEXT: [[VLD2_LANE_V:%.*]] = call { <2 x float>, <2 x float> } @llvm.arm.neon.vld2lane.v2f32.p0(ptr [[A]], <2 x float> [[TMP4]], <2 x float> [[TMP5]], i32 1, i32 4)7050// CHECK-NEXT: [[VLD2_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float> } [[VLD2_LANE_V]], 07051// CHECK-NEXT: [[VLD2_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float> } [[VLD2_LANE_V]], 17052// CHECK-NEXT: store <2 x float> [[VLD2_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87053// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87054// CHECK-NEXT: store <2 x float> [[VLD2_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87055// CHECK-NEXT: ret void7056//7057float32x2x2_t test_vld2_lane_f32(float32_t const * a, float32x2x2_t b) {7058 return vld2_lane_f32(a, b, 1);7059}7060 7061// CHECK-LABEL: define void @test_vld2_lane_p8(7062// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X8X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [2 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7063// CHECK-NEXT: [[ENTRY:.*:]]7064// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 07065// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>7066// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 17067// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>7068// CHECK-NEXT: [[VLD2_LANE_V:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2lane.v8i8.p0(ptr [[A]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], i32 7, i32 1)7069// CHECK-NEXT: [[VLD2_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_LANE_V]], 07070// CHECK-NEXT: [[VLD2_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD2_LANE_V]], 17071// CHECK-NEXT: store <8 x i8> [[VLD2_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87072// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87073// CHECK-NEXT: store <8 x i8> [[VLD2_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87074// CHECK-NEXT: ret void7075//7076poly8x8x2_t test_vld2_lane_p8(poly8_t const * a, poly8x8x2_t b) {7077 return vld2_lane_p8(a, b, 7);7078}7079 7080// CHECK-LABEL: define void @test_vld2_lane_p16(7081// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X4X2_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [2 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7082// CHECK-NEXT: [[ENTRY:.*:]]7083// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 07084// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>7085// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x i64] [[B_COERCE]], 17086// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>7087// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>7088// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>7089// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>7090// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>7091// CHECK-NEXT: [[VLD2_LANE_V:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2lane.v4i16.p0(ptr [[A]], <4 x i16> [[TMP4]], <4 x i16> [[TMP5]], i32 3, i32 2)7092// CHECK-NEXT: [[VLD2_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_LANE_V]], 07093// CHECK-NEXT: [[VLD2_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16> } [[VLD2_LANE_V]], 17094// CHECK-NEXT: store <4 x i16> [[VLD2_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87095// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87096// CHECK-NEXT: store <4 x i16> [[VLD2_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87097// CHECK-NEXT: ret void7098//7099poly16x4x2_t test_vld2_lane_p16(poly16_t const * a, poly16x4x2_t b) {7100 return vld2_lane_p16(a, b, 3);7101}7102 7103// CHECK-LABEL: define void @test_vld3q_u8(7104// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X16X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7105// CHECK-NEXT: [[ENTRY:.*:]]7106// CHECK-NEXT: [[VLD3Q_V:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr [[A]], i32 1)7107// CHECK-NEXT: [[VLD3Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3Q_V]], 07108// CHECK-NEXT: [[VLD3Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3Q_V]], 17109// CHECK-NEXT: [[VLD3Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3Q_V]], 27110// CHECK-NEXT: store <16 x i8> [[VLD3Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167111// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167112// CHECK-NEXT: store <16 x i8> [[VLD3Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167113// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327114// CHECK-NEXT: store <16 x i8> [[VLD3Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167115// CHECK-NEXT: ret void7116//7117uint8x16x3_t test_vld3q_u8(uint8_t const * a) {7118 return vld3q_u8(a);7119}7120 7121// CHECK-LABEL: define void @test_vld3q_u16(7122// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X8X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7123// CHECK-NEXT: [[ENTRY:.*:]]7124// CHECK-NEXT: [[VLD3Q_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3.v8i16.p0(ptr [[A]], i32 2)7125// CHECK-NEXT: [[VLD3Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_V]], 07126// CHECK-NEXT: [[VLD3Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_V]], 17127// CHECK-NEXT: [[VLD3Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_V]], 27128// CHECK-NEXT: store <8 x i16> [[VLD3Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167129// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167130// CHECK-NEXT: store <8 x i16> [[VLD3Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167131// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327132// CHECK-NEXT: store <8 x i16> [[VLD3Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167133// CHECK-NEXT: ret void7134//7135uint16x8x3_t test_vld3q_u16(uint16_t const * a) {7136 return vld3q_u16(a);7137}7138 7139// CHECK-LABEL: define void @test_vld3q_u32(7140// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X4X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7141// CHECK-NEXT: [[ENTRY:.*:]]7142// CHECK-NEXT: [[VLD3Q_V:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3.v4i32.p0(ptr [[A]], i32 4)7143// CHECK-NEXT: [[VLD3Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_V]], 07144// CHECK-NEXT: [[VLD3Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_V]], 17145// CHECK-NEXT: [[VLD3Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_V]], 27146// CHECK-NEXT: store <4 x i32> [[VLD3Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167147// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167148// CHECK-NEXT: store <4 x i32> [[VLD3Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167149// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327150// CHECK-NEXT: store <4 x i32> [[VLD3Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167151// CHECK-NEXT: ret void7152//7153uint32x4x3_t test_vld3q_u32(uint32_t const * a) {7154 return vld3q_u32(a);7155}7156 7157// CHECK-LABEL: define void @test_vld3q_s8(7158// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X16X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7159// CHECK-NEXT: [[ENTRY:.*:]]7160// CHECK-NEXT: [[VLD3Q_V:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr [[A]], i32 1)7161// CHECK-NEXT: [[VLD3Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3Q_V]], 07162// CHECK-NEXT: [[VLD3Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3Q_V]], 17163// CHECK-NEXT: [[VLD3Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3Q_V]], 27164// CHECK-NEXT: store <16 x i8> [[VLD3Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167165// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167166// CHECK-NEXT: store <16 x i8> [[VLD3Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167167// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327168// CHECK-NEXT: store <16 x i8> [[VLD3Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167169// CHECK-NEXT: ret void7170//7171int8x16x3_t test_vld3q_s8(int8_t const * a) {7172 return vld3q_s8(a);7173}7174 7175// CHECK-LABEL: define void @test_vld3q_s16(7176// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X8X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7177// CHECK-NEXT: [[ENTRY:.*:]]7178// CHECK-NEXT: [[VLD3Q_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3.v8i16.p0(ptr [[A]], i32 2)7179// CHECK-NEXT: [[VLD3Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_V]], 07180// CHECK-NEXT: [[VLD3Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_V]], 17181// CHECK-NEXT: [[VLD3Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_V]], 27182// CHECK-NEXT: store <8 x i16> [[VLD3Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167183// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167184// CHECK-NEXT: store <8 x i16> [[VLD3Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167185// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327186// CHECK-NEXT: store <8 x i16> [[VLD3Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167187// CHECK-NEXT: ret void7188//7189int16x8x3_t test_vld3q_s16(int16_t const * a) {7190 return vld3q_s16(a);7191}7192 7193// CHECK-LABEL: define void @test_vld3q_s32(7194// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X4X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7195// CHECK-NEXT: [[ENTRY:.*:]]7196// CHECK-NEXT: [[VLD3Q_V:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3.v4i32.p0(ptr [[A]], i32 4)7197// CHECK-NEXT: [[VLD3Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_V]], 07198// CHECK-NEXT: [[VLD3Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_V]], 17199// CHECK-NEXT: [[VLD3Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_V]], 27200// CHECK-NEXT: store <4 x i32> [[VLD3Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167201// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167202// CHECK-NEXT: store <4 x i32> [[VLD3Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167203// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327204// CHECK-NEXT: store <4 x i32> [[VLD3Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167205// CHECK-NEXT: ret void7206//7207int32x4x3_t test_vld3q_s32(int32_t const * a) {7208 return vld3q_s32(a);7209}7210 7211// CHECK-LABEL: define void @test_vld3q_f16(7212// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X8X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7213// CHECK-NEXT: [[ENTRY:.*:]]7214// CHECK-NEXT: [[VLD3Q_V:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3.v8f16.p0(ptr [[A]], i32 2)7215// CHECK-NEXT: [[VLD3Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half> } [[VLD3Q_V]], 07216// CHECK-NEXT: [[VLD3Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half> } [[VLD3Q_V]], 17217// CHECK-NEXT: [[VLD3Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half> } [[VLD3Q_V]], 27218// CHECK-NEXT: store <8 x half> [[VLD3Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167219// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167220// CHECK-NEXT: store <8 x half> [[VLD3Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167221// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327222// CHECK-NEXT: store <8 x half> [[VLD3Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167223// CHECK-NEXT: ret void7224//7225float16x8x3_t test_vld3q_f16(float16_t const * a) {7226 return vld3q_f16(a);7227}7228 7229// CHECK-LABEL: define void @test_vld3q_f32(7230// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X4X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7231// CHECK-NEXT: [[ENTRY:.*:]]7232// CHECK-NEXT: [[VLD3Q_V:%.*]] = call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3.v4f32.p0(ptr [[A]], i32 4)7233// CHECK-NEXT: [[VLD3Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float> } [[VLD3Q_V]], 07234// CHECK-NEXT: [[VLD3Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float> } [[VLD3Q_V]], 17235// CHECK-NEXT: [[VLD3Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float> } [[VLD3Q_V]], 27236// CHECK-NEXT: store <4 x float> [[VLD3Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167237// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167238// CHECK-NEXT: store <4 x float> [[VLD3Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167239// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327240// CHECK-NEXT: store <4 x float> [[VLD3Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167241// CHECK-NEXT: ret void7242//7243float32x4x3_t test_vld3q_f32(float32_t const * a) {7244 return vld3q_f32(a);7245}7246 7247// CHECK-LABEL: define void @test_vld3q_p8(7248// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X16X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7249// CHECK-NEXT: [[ENTRY:.*:]]7250// CHECK-NEXT: [[VLD3Q_V:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr [[A]], i32 1)7251// CHECK-NEXT: [[VLD3Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3Q_V]], 07252// CHECK-NEXT: [[VLD3Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3Q_V]], 17253// CHECK-NEXT: [[VLD3Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD3Q_V]], 27254// CHECK-NEXT: store <16 x i8> [[VLD3Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167255// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167256// CHECK-NEXT: store <16 x i8> [[VLD3Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167257// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327258// CHECK-NEXT: store <16 x i8> [[VLD3Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167259// CHECK-NEXT: ret void7260//7261poly8x16x3_t test_vld3q_p8(poly8_t const * a) {7262 return vld3q_p8(a);7263}7264 7265// CHECK-LABEL: define void @test_vld3q_p16(7266// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X8X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7267// CHECK-NEXT: [[ENTRY:.*:]]7268// CHECK-NEXT: [[VLD3Q_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3.v8i16.p0(ptr [[A]], i32 2)7269// CHECK-NEXT: [[VLD3Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_V]], 07270// CHECK-NEXT: [[VLD3Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_V]], 17271// CHECK-NEXT: [[VLD3Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_V]], 27272// CHECK-NEXT: store <8 x i16> [[VLD3Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167273// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167274// CHECK-NEXT: store <8 x i16> [[VLD3Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167275// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327276// CHECK-NEXT: store <8 x i16> [[VLD3Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167277// CHECK-NEXT: ret void7278//7279poly16x8x3_t test_vld3q_p16(poly16_t const * a) {7280 return vld3q_p16(a);7281}7282 7283// CHECK-LABEL: define void @test_vld3_u8(7284// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X8X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7285// CHECK-NEXT: [[ENTRY:.*:]]7286// CHECK-NEXT: [[VLD3_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3.v8i8.p0(ptr [[A]], i32 1)7287// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_V]], 07288// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_V]], 17289// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_V]], 27290// CHECK-NEXT: store <8 x i8> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87291// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87292// CHECK-NEXT: store <8 x i8> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87293// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167294// CHECK-NEXT: store <8 x i8> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87295// CHECK-NEXT: ret void7296//7297uint8x8x3_t test_vld3_u8(uint8_t const * a) {7298 return vld3_u8(a);7299}7300 7301// CHECK-LABEL: define void @test_vld3_u16(7302// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X4X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7303// CHECK-NEXT: [[ENTRY:.*:]]7304// CHECK-NEXT: [[VLD3_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16.p0(ptr [[A]], i32 2)7305// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_V]], 07306// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_V]], 17307// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_V]], 27308// CHECK-NEXT: store <4 x i16> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87309// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87310// CHECK-NEXT: store <4 x i16> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87311// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167312// CHECK-NEXT: store <4 x i16> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87313// CHECK-NEXT: ret void7314//7315uint16x4x3_t test_vld3_u16(uint16_t const * a) {7316 return vld3_u16(a);7317}7318 7319// CHECK-LABEL: define void @test_vld3_u32(7320// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X2X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7321// CHECK-NEXT: [[ENTRY:.*:]]7322// CHECK-NEXT: [[VLD3_V:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3.v2i32.p0(ptr [[A]], i32 4)7323// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_V]], 07324// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_V]], 17325// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_V]], 27326// CHECK-NEXT: store <2 x i32> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87327// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87328// CHECK-NEXT: store <2 x i32> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87329// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167330// CHECK-NEXT: store <2 x i32> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87331// CHECK-NEXT: ret void7332//7333uint32x2x3_t test_vld3_u32(uint32_t const * a) {7334 return vld3_u32(a);7335}7336 7337// CHECK-LABEL: define void @test_vld3_u64(7338// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT64X1X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7339// CHECK-NEXT: [[ENTRY:.*:]]7340// CHECK-NEXT: [[VLD3_V:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld3.v1i64.p0(ptr [[A]], i32 4)7341// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD3_V]], 07342// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD3_V]], 17343// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD3_V]], 27344// CHECK-NEXT: store <1 x i64> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87345// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87346// CHECK-NEXT: store <1 x i64> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87347// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167348// CHECK-NEXT: store <1 x i64> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87349// CHECK-NEXT: ret void7350//7351uint64x1x3_t test_vld3_u64(uint64_t const * a) {7352 return vld3_u64(a);7353}7354 7355// CHECK-LABEL: define void @test_vld3_s8(7356// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X8X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7357// CHECK-NEXT: [[ENTRY:.*:]]7358// CHECK-NEXT: [[VLD3_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3.v8i8.p0(ptr [[A]], i32 1)7359// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_V]], 07360// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_V]], 17361// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_V]], 27362// CHECK-NEXT: store <8 x i8> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87363// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87364// CHECK-NEXT: store <8 x i8> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87365// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167366// CHECK-NEXT: store <8 x i8> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87367// CHECK-NEXT: ret void7368//7369int8x8x3_t test_vld3_s8(int8_t const * a) {7370 return vld3_s8(a);7371}7372 7373// CHECK-LABEL: define void @test_vld3_s16(7374// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X4X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7375// CHECK-NEXT: [[ENTRY:.*:]]7376// CHECK-NEXT: [[VLD3_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16.p0(ptr [[A]], i32 2)7377// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_V]], 07378// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_V]], 17379// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_V]], 27380// CHECK-NEXT: store <4 x i16> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87381// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87382// CHECK-NEXT: store <4 x i16> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87383// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167384// CHECK-NEXT: store <4 x i16> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87385// CHECK-NEXT: ret void7386//7387int16x4x3_t test_vld3_s16(int16_t const * a) {7388 return vld3_s16(a);7389}7390 7391// CHECK-LABEL: define void @test_vld3_s32(7392// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X2X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7393// CHECK-NEXT: [[ENTRY:.*:]]7394// CHECK-NEXT: [[VLD3_V:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3.v2i32.p0(ptr [[A]], i32 4)7395// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_V]], 07396// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_V]], 17397// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_V]], 27398// CHECK-NEXT: store <2 x i32> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87399// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87400// CHECK-NEXT: store <2 x i32> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87401// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167402// CHECK-NEXT: store <2 x i32> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87403// CHECK-NEXT: ret void7404//7405int32x2x3_t test_vld3_s32(int32_t const * a) {7406 return vld3_s32(a);7407}7408 7409// CHECK-LABEL: define void @test_vld3_s64(7410// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT64X1X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7411// CHECK-NEXT: [[ENTRY:.*:]]7412// CHECK-NEXT: [[VLD3_V:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld3.v1i64.p0(ptr [[A]], i32 4)7413// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD3_V]], 07414// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD3_V]], 17415// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD3_V]], 27416// CHECK-NEXT: store <1 x i64> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87417// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87418// CHECK-NEXT: store <1 x i64> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87419// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167420// CHECK-NEXT: store <1 x i64> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87421// CHECK-NEXT: ret void7422//7423int64x1x3_t test_vld3_s64(int64_t const * a) {7424 return vld3_s64(a);7425}7426 7427// CHECK-LABEL: define void @test_vld3_f16(7428// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X4X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7429// CHECK-NEXT: [[ENTRY:.*:]]7430// CHECK-NEXT: [[VLD3_V:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3.v4f16.p0(ptr [[A]], i32 2)7431// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half> } [[VLD3_V]], 07432// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half> } [[VLD3_V]], 17433// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half> } [[VLD3_V]], 27434// CHECK-NEXT: store <4 x half> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87435// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87436// CHECK-NEXT: store <4 x half> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87437// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167438// CHECK-NEXT: store <4 x half> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87439// CHECK-NEXT: ret void7440//7441float16x4x3_t test_vld3_f16(float16_t const * a) {7442 return vld3_f16(a);7443}7444 7445// CHECK-LABEL: define void @test_vld3_f32(7446// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X2X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7447// CHECK-NEXT: [[ENTRY:.*:]]7448// CHECK-NEXT: [[VLD3_V:%.*]] = call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld3.v2f32.p0(ptr [[A]], i32 4)7449// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float> } [[VLD3_V]], 07450// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float> } [[VLD3_V]], 17451// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float> } [[VLD3_V]], 27452// CHECK-NEXT: store <2 x float> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87453// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87454// CHECK-NEXT: store <2 x float> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87455// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167456// CHECK-NEXT: store <2 x float> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87457// CHECK-NEXT: ret void7458//7459float32x2x3_t test_vld3_f32(float32_t const * a) {7460 return vld3_f32(a);7461}7462 7463// CHECK-LABEL: define void @test_vld3_p8(7464// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X8X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7465// CHECK-NEXT: [[ENTRY:.*:]]7466// CHECK-NEXT: [[VLD3_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3.v8i8.p0(ptr [[A]], i32 1)7467// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_V]], 07468// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_V]], 17469// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_V]], 27470// CHECK-NEXT: store <8 x i8> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87471// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87472// CHECK-NEXT: store <8 x i8> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87473// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167474// CHECK-NEXT: store <8 x i8> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87475// CHECK-NEXT: ret void7476//7477poly8x8x3_t test_vld3_p8(poly8_t const * a) {7478 return vld3_p8(a);7479}7480 7481// CHECK-LABEL: define void @test_vld3_p16(7482// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X4X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {7483// CHECK-NEXT: [[ENTRY:.*:]]7484// CHECK-NEXT: [[VLD3_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16.p0(ptr [[A]], i32 2)7485// CHECK-NEXT: [[VLD3_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_V]], 07486// CHECK-NEXT: [[VLD3_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_V]], 17487// CHECK-NEXT: [[VLD3_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_V]], 27488// CHECK-NEXT: store <4 x i16> [[VLD3_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87489// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87490// CHECK-NEXT: store <4 x i16> [[VLD3_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87491// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167492// CHECK-NEXT: store <4 x i16> [[VLD3_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87493// CHECK-NEXT: ret void7494//7495poly16x4x3_t test_vld3_p16(poly16_t const * a) {7496 return vld3_p16(a);7497}7498 7499// CHECK-LABEL: define void @test_vld3q_lane_u16(7500// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X8X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [6 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7501// CHECK-NEXT: [[ENTRY:.*:]]7502// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 07503// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 07504// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 17505// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 17506// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 27507// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 07508// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 37509// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 17510// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 47511// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 07512// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 57513// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 17514// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>7515// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>7516// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>7517// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>7518// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>7519// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>7520// CHECK-NEXT: [[VLD3Q_LANE_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0(ptr [[A]], <8 x i16> [[TMP3]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], i32 7, i32 2)7521// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_LANE_V]], 07522// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_LANE_V]], 17523// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_LANE_V]], 27524// CHECK-NEXT: store <8 x i16> [[VLD3Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167525// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167526// CHECK-NEXT: store <8 x i16> [[VLD3Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167527// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327528// CHECK-NEXT: store <8 x i16> [[VLD3Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167529// CHECK-NEXT: ret void7530//7531uint16x8x3_t test_vld3q_lane_u16(uint16_t const * a, uint16x8x3_t b) {7532 return vld3q_lane_u16(a, b, 7);7533}7534 7535// CHECK-LABEL: define void @test_vld3q_lane_u32(7536// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X4X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [6 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7537// CHECK-NEXT: [[ENTRY:.*:]]7538// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 07539// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 07540// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 17541// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 17542// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 27543// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 07544// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 37545// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 17546// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 47547// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 07548// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 57549// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 17550// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>7551// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>7552// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>7553// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>7554// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>7555// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>7556// CHECK-NEXT: [[VLD3Q_LANE_V:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3lane.v4i32.p0(ptr [[A]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], i32 3, i32 4)7557// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_LANE_V]], 07558// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_LANE_V]], 17559// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_LANE_V]], 27560// CHECK-NEXT: store <4 x i32> [[VLD3Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167561// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167562// CHECK-NEXT: store <4 x i32> [[VLD3Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167563// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327564// CHECK-NEXT: store <4 x i32> [[VLD3Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167565// CHECK-NEXT: ret void7566//7567uint32x4x3_t test_vld3q_lane_u32(uint32_t const * a, uint32x4x3_t b) {7568 return vld3q_lane_u32(a, b, 3);7569}7570 7571// CHECK-LABEL: define void @test_vld3q_lane_s16(7572// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X8X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [6 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7573// CHECK-NEXT: [[ENTRY:.*:]]7574// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 07575// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 07576// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 17577// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 17578// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 27579// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 07580// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 37581// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 17582// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 47583// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 07584// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 57585// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 17586// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>7587// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>7588// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>7589// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>7590// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>7591// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>7592// CHECK-NEXT: [[VLD3Q_LANE_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0(ptr [[A]], <8 x i16> [[TMP3]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], i32 7, i32 2)7593// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_LANE_V]], 07594// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_LANE_V]], 17595// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_LANE_V]], 27596// CHECK-NEXT: store <8 x i16> [[VLD3Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167597// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167598// CHECK-NEXT: store <8 x i16> [[VLD3Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167599// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327600// CHECK-NEXT: store <8 x i16> [[VLD3Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167601// CHECK-NEXT: ret void7602//7603int16x8x3_t test_vld3q_lane_s16(int16_t const * a, int16x8x3_t b) {7604 return vld3q_lane_s16(a, b, 7);7605}7606 7607// CHECK-LABEL: define void @test_vld3q_lane_s32(7608// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X4X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [6 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7609// CHECK-NEXT: [[ENTRY:.*:]]7610// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 07611// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 07612// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 17613// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 17614// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 27615// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 07616// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 37617// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 17618// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 47619// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 07620// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 57621// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 17622// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>7623// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>7624// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>7625// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>7626// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>7627// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>7628// CHECK-NEXT: [[VLD3Q_LANE_V:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3lane.v4i32.p0(ptr [[A]], <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], i32 3, i32 4)7629// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_LANE_V]], 07630// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_LANE_V]], 17631// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD3Q_LANE_V]], 27632// CHECK-NEXT: store <4 x i32> [[VLD3Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167633// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167634// CHECK-NEXT: store <4 x i32> [[VLD3Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167635// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327636// CHECK-NEXT: store <4 x i32> [[VLD3Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167637// CHECK-NEXT: ret void7638//7639int32x4x3_t test_vld3q_lane_s32(int32_t const * a, int32x4x3_t b) {7640 return vld3q_lane_s32(a, b, 3);7641}7642 7643// CHECK-LABEL: define void @test_vld3q_lane_f16(7644// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X8X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [6 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7645// CHECK-NEXT: [[ENTRY:.*:]]7646// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 07647// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 07648// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 17649// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 17650// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 27651// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 07652// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 37653// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 17654// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 47655// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 07656// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 57657// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 17658// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>7659// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>7660// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>7661// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>7662// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>7663// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>7664// CHECK-NEXT: [[VLD3Q_LANE_V:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3lane.v8f16.p0(ptr [[A]], <8 x half> [[TMP3]], <8 x half> [[TMP4]], <8 x half> [[TMP5]], i32 7, i32 2)7665// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half> } [[VLD3Q_LANE_V]], 07666// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half> } [[VLD3Q_LANE_V]], 17667// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half> } [[VLD3Q_LANE_V]], 27668// CHECK-NEXT: store <8 x half> [[VLD3Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167669// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167670// CHECK-NEXT: store <8 x half> [[VLD3Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167671// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327672// CHECK-NEXT: store <8 x half> [[VLD3Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167673// CHECK-NEXT: ret void7674//7675float16x8x3_t test_vld3q_lane_f16(float16_t const * a, float16x8x3_t b) {7676 return vld3q_lane_f16(a, b, 7);7677}7678 7679// CHECK-LABEL: define void @test_vld3q_lane_f32(7680// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X4X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [6 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7681// CHECK-NEXT: [[ENTRY:.*:]]7682// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 07683// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 07684// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 17685// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 17686// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 27687// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 07688// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 37689// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 17690// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 47691// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 07692// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 57693// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 17694// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>7695// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>7696// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>7697// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>7698// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>7699// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>7700// CHECK-NEXT: [[VLD3Q_LANE_V:%.*]] = call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3lane.v4f32.p0(ptr [[A]], <4 x float> [[TMP3]], <4 x float> [[TMP4]], <4 x float> [[TMP5]], i32 3, i32 4)7701// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float> } [[VLD3Q_LANE_V]], 07702// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float> } [[VLD3Q_LANE_V]], 17703// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float> } [[VLD3Q_LANE_V]], 27704// CHECK-NEXT: store <4 x float> [[VLD3Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167705// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167706// CHECK-NEXT: store <4 x float> [[VLD3Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167707// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327708// CHECK-NEXT: store <4 x float> [[VLD3Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167709// CHECK-NEXT: ret void7710//7711float32x4x3_t test_vld3q_lane_f32(float32_t const * a, float32x4x3_t b) {7712 return vld3q_lane_f32(a, b, 3);7713}7714 7715// CHECK-LABEL: define void @test_vld3q_lane_p16(7716// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X8X3_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [6 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7717// CHECK-NEXT: [[ENTRY:.*:]]7718// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 07719// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 07720// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 17721// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 17722// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 27723// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 07724// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 37725// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 17726// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 47727// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 07728// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [6 x i64] [[B_COERCE]], 57729// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 17730// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>7731// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>7732// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>7733// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>7734// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>7735// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>7736// CHECK-NEXT: [[VLD3Q_LANE_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0(ptr [[A]], <8 x i16> [[TMP3]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], i32 7, i32 2)7737// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_LANE_V]], 07738// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_LANE_V]], 17739// CHECK-NEXT: [[VLD3Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3Q_LANE_V]], 27740// CHECK-NEXT: store <8 x i16> [[VLD3Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 167741// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167742// CHECK-NEXT: store <8 x i16> [[VLD3Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 167743// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 327744// CHECK-NEXT: store <8 x i16> [[VLD3Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 167745// CHECK-NEXT: ret void7746//7747poly16x8x3_t test_vld3q_lane_p16(poly16_t const * a, poly16x8x3_t b) {7748 return vld3q_lane_p16(a, b, 7);7749}7750 7751// CHECK-LABEL: define void @test_vld3_lane_u8(7752// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X8X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [3 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7753// CHECK-NEXT: [[ENTRY:.*:]]7754// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 07755// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>7756// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 17757// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>7758// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 27759// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>7760// CHECK-NEXT: [[VLD3_LANE_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3lane.v8i8.p0(ptr [[A]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]], i32 7, i32 1)7761// CHECK-NEXT: [[VLD3_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_LANE_V]], 07762// CHECK-NEXT: [[VLD3_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_LANE_V]], 17763// CHECK-NEXT: [[VLD3_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_LANE_V]], 27764// CHECK-NEXT: store <8 x i8> [[VLD3_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87765// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87766// CHECK-NEXT: store <8 x i8> [[VLD3_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87767// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167768// CHECK-NEXT: store <8 x i8> [[VLD3_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87769// CHECK-NEXT: ret void7770//7771uint8x8x3_t test_vld3_lane_u8(uint8_t const * a, uint8x8x3_t b) {7772 return vld3_lane_u8(a, b, 7);7773}7774 7775// CHECK-LABEL: define void @test_vld3_lane_u16(7776// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X4X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [3 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7777// CHECK-NEXT: [[ENTRY:.*:]]7778// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 07779// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>7780// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 17781// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>7782// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 27783// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <4 x i16>7784// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>7785// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>7786// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>7787// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>7788// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>7789// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16>7790// CHECK-NEXT: [[VLD3_LANE_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3lane.v4i16.p0(ptr [[A]], <4 x i16> [[TMP6]], <4 x i16> [[TMP7]], <4 x i16> [[TMP8]], i32 3, i32 2)7791// CHECK-NEXT: [[VLD3_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE_V]], 07792// CHECK-NEXT: [[VLD3_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE_V]], 17793// CHECK-NEXT: [[VLD3_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE_V]], 27794// CHECK-NEXT: store <4 x i16> [[VLD3_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87795// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87796// CHECK-NEXT: store <4 x i16> [[VLD3_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87797// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167798// CHECK-NEXT: store <4 x i16> [[VLD3_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87799// CHECK-NEXT: ret void7800//7801uint16x4x3_t test_vld3_lane_u16(uint16_t const * a, uint16x4x3_t b) {7802 return vld3_lane_u16(a, b, 3);7803}7804 7805// CHECK-LABEL: define void @test_vld3_lane_u32(7806// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X2X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [3 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7807// CHECK-NEXT: [[ENTRY:.*:]]7808// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 07809// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>7810// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 17811// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>7812// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 27813// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <2 x i32>7814// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>7815// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>7816// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>7817// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>7818// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x i32>7819// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x i32>7820// CHECK-NEXT: [[VLD3_LANE_V:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3lane.v2i32.p0(ptr [[A]], <2 x i32> [[TMP6]], <2 x i32> [[TMP7]], <2 x i32> [[TMP8]], i32 1, i32 4)7821// CHECK-NEXT: [[VLD3_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_LANE_V]], 07822// CHECK-NEXT: [[VLD3_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_LANE_V]], 17823// CHECK-NEXT: [[VLD3_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_LANE_V]], 27824// CHECK-NEXT: store <2 x i32> [[VLD3_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87825// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87826// CHECK-NEXT: store <2 x i32> [[VLD3_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87827// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167828// CHECK-NEXT: store <2 x i32> [[VLD3_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87829// CHECK-NEXT: ret void7830//7831uint32x2x3_t test_vld3_lane_u32(uint32_t const * a, uint32x2x3_t b) {7832 return vld3_lane_u32(a, b, 1);7833}7834 7835// CHECK-LABEL: define void @test_vld3_lane_s8(7836// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X8X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [3 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7837// CHECK-NEXT: [[ENTRY:.*:]]7838// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 07839// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>7840// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 17841// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>7842// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 27843// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>7844// CHECK-NEXT: [[VLD3_LANE_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3lane.v8i8.p0(ptr [[A]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]], i32 7, i32 1)7845// CHECK-NEXT: [[VLD3_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_LANE_V]], 07846// CHECK-NEXT: [[VLD3_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_LANE_V]], 17847// CHECK-NEXT: [[VLD3_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_LANE_V]], 27848// CHECK-NEXT: store <8 x i8> [[VLD3_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87849// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87850// CHECK-NEXT: store <8 x i8> [[VLD3_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87851// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167852// CHECK-NEXT: store <8 x i8> [[VLD3_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87853// CHECK-NEXT: ret void7854//7855int8x8x3_t test_vld3_lane_s8(int8_t const * a, int8x8x3_t b) {7856 return vld3_lane_s8(a, b, 7);7857}7858 7859// CHECK-LABEL: define void @test_vld3_lane_s16(7860// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X4X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [3 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7861// CHECK-NEXT: [[ENTRY:.*:]]7862// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 07863// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>7864// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 17865// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>7866// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 27867// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <4 x i16>7868// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>7869// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>7870// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>7871// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>7872// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>7873// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16>7874// CHECK-NEXT: [[VLD3_LANE_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3lane.v4i16.p0(ptr [[A]], <4 x i16> [[TMP6]], <4 x i16> [[TMP7]], <4 x i16> [[TMP8]], i32 3, i32 2)7875// CHECK-NEXT: [[VLD3_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE_V]], 07876// CHECK-NEXT: [[VLD3_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE_V]], 17877// CHECK-NEXT: [[VLD3_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE_V]], 27878// CHECK-NEXT: store <4 x i16> [[VLD3_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87879// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87880// CHECK-NEXT: store <4 x i16> [[VLD3_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87881// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167882// CHECK-NEXT: store <4 x i16> [[VLD3_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87883// CHECK-NEXT: ret void7884//7885int16x4x3_t test_vld3_lane_s16(int16_t const * a, int16x4x3_t b) {7886 return vld3_lane_s16(a, b, 3);7887}7888 7889// CHECK-LABEL: define void @test_vld3_lane_s32(7890// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X2X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [3 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7891// CHECK-NEXT: [[ENTRY:.*:]]7892// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 07893// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>7894// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 17895// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>7896// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 27897// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <2 x i32>7898// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>7899// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>7900// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>7901// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>7902// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x i32>7903// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x i32>7904// CHECK-NEXT: [[VLD3_LANE_V:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3lane.v2i32.p0(ptr [[A]], <2 x i32> [[TMP6]], <2 x i32> [[TMP7]], <2 x i32> [[TMP8]], i32 1, i32 4)7905// CHECK-NEXT: [[VLD3_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_LANE_V]], 07906// CHECK-NEXT: [[VLD3_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_LANE_V]], 17907// CHECK-NEXT: [[VLD3_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD3_LANE_V]], 27908// CHECK-NEXT: store <2 x i32> [[VLD3_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87909// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87910// CHECK-NEXT: store <2 x i32> [[VLD3_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87911// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167912// CHECK-NEXT: store <2 x i32> [[VLD3_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87913// CHECK-NEXT: ret void7914//7915int32x2x3_t test_vld3_lane_s32(int32_t const * a, int32x2x3_t b) {7916 return vld3_lane_s32(a, b, 1);7917}7918 7919// CHECK-LABEL: define void @test_vld3_lane_f16(7920// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X4X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [3 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7921// CHECK-NEXT: [[ENTRY:.*:]]7922// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 07923// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x half>7924// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 17925// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x half>7926// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 27927// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <4 x half>7928// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x half> [[TMP0]] to <8 x i8>7929// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x half> [[TMP1]] to <8 x i8>7930// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x half> [[TMP2]] to <8 x i8>7931// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x half>7932// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>7933// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half>7934// CHECK-NEXT: [[VLD3_LANE_V:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3lane.v4f16.p0(ptr [[A]], <4 x half> [[TMP6]], <4 x half> [[TMP7]], <4 x half> [[TMP8]], i32 3, i32 2)7935// CHECK-NEXT: [[VLD3_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half> } [[VLD3_LANE_V]], 07936// CHECK-NEXT: [[VLD3_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half> } [[VLD3_LANE_V]], 17937// CHECK-NEXT: [[VLD3_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half> } [[VLD3_LANE_V]], 27938// CHECK-NEXT: store <4 x half> [[VLD3_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87939// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87940// CHECK-NEXT: store <4 x half> [[VLD3_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87941// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167942// CHECK-NEXT: store <4 x half> [[VLD3_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87943// CHECK-NEXT: ret void7944//7945float16x4x3_t test_vld3_lane_f16(float16_t const * a, float16x4x3_t b) {7946 return vld3_lane_f16(a, b, 3);7947}7948 7949// CHECK-LABEL: define void @test_vld3_lane_f32(7950// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X2X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [3 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7951// CHECK-NEXT: [[ENTRY:.*:]]7952// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 07953// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <2 x float>7954// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 17955// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <2 x float>7956// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 27957// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <2 x float>7958// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[TMP0]] to <8 x i8>7959// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x float> [[TMP1]] to <8 x i8>7960// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x float> [[TMP2]] to <8 x i8>7961// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>7962// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x float>7963// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x float>7964// CHECK-NEXT: [[VLD3_LANE_V:%.*]] = call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld3lane.v2f32.p0(ptr [[A]], <2 x float> [[TMP6]], <2 x float> [[TMP7]], <2 x float> [[TMP8]], i32 1, i32 4)7965// CHECK-NEXT: [[VLD3_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float> } [[VLD3_LANE_V]], 07966// CHECK-NEXT: [[VLD3_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float> } [[VLD3_LANE_V]], 17967// CHECK-NEXT: [[VLD3_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float> } [[VLD3_LANE_V]], 27968// CHECK-NEXT: store <2 x float> [[VLD3_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87969// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87970// CHECK-NEXT: store <2 x float> [[VLD3_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87971// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167972// CHECK-NEXT: store <2 x float> [[VLD3_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87973// CHECK-NEXT: ret void7974//7975float32x2x3_t test_vld3_lane_f32(float32_t const * a, float32x2x3_t b) {7976 return vld3_lane_f32(a, b, 1);7977}7978 7979// CHECK-LABEL: define void @test_vld3_lane_p8(7980// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X8X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [3 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {7981// CHECK-NEXT: [[ENTRY:.*:]]7982// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 07983// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>7984// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 17985// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>7986// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 27987// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>7988// CHECK-NEXT: [[VLD3_LANE_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3lane.v8i8.p0(ptr [[A]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]], i32 7, i32 1)7989// CHECK-NEXT: [[VLD3_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_LANE_V]], 07990// CHECK-NEXT: [[VLD3_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_LANE_V]], 17991// CHECK-NEXT: [[VLD3_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD3_LANE_V]], 27992// CHECK-NEXT: store <8 x i8> [[VLD3_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 87993// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 87994// CHECK-NEXT: store <8 x i8> [[VLD3_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 87995// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 167996// CHECK-NEXT: store <8 x i8> [[VLD3_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 87997// CHECK-NEXT: ret void7998//7999poly8x8x3_t test_vld3_lane_p8(poly8_t const * a, poly8x8x3_t b) {8000 return vld3_lane_p8(a, b, 7);8001}8002 8003// CHECK-LABEL: define void @test_vld3_lane_p16(8004// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X4X3_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [3 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8005// CHECK-NEXT: [[ENTRY:.*:]]8006// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 08007// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>8008// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 18009// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>8010// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x i64] [[B_COERCE]], 28011// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <4 x i16>8012// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>8013// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>8014// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>8015// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>8016// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>8017// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16>8018// CHECK-NEXT: [[VLD3_LANE_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3lane.v4i16.p0(ptr [[A]], <4 x i16> [[TMP6]], <4 x i16> [[TMP7]], <4 x i16> [[TMP8]], i32 3, i32 2)8019// CHECK-NEXT: [[VLD3_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE_V]], 08020// CHECK-NEXT: [[VLD3_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE_V]], 18021// CHECK-NEXT: [[VLD3_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE_V]], 28022// CHECK-NEXT: store <4 x i16> [[VLD3_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88023// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88024// CHECK-NEXT: store <4 x i16> [[VLD3_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88025// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168026// CHECK-NEXT: store <4 x i16> [[VLD3_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88027// CHECK-NEXT: ret void8028//8029poly16x4x3_t test_vld3_lane_p16(poly16_t const * a, poly16x4x3_t b) {8030 return vld3_lane_p16(a, b, 3);8031}8032 8033// CHECK-LABEL: define void @test_vld4q_u8(8034// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X16X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8035// CHECK-NEXT: [[ENTRY:.*:]]8036// CHECK-NEXT: [[VLD4Q_V:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8.p0(ptr [[A]], i32 1)8037// CHECK-NEXT: [[VLD4Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 08038// CHECK-NEXT: [[VLD4Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 18039// CHECK-NEXT: [[VLD4Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 28040// CHECK-NEXT: [[VLD4Q_V_FCA_3_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 38041// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168042// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168043// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168044// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328045// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168046// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488047// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168048// CHECK-NEXT: ret void8049//8050uint8x16x4_t test_vld4q_u8(uint8_t const * a) {8051 return vld4q_u8(a);8052}8053 8054// CHECK-LABEL: define void @test_vld4q_u16(8055// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X8X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8056// CHECK-NEXT: [[ENTRY:.*:]]8057// CHECK-NEXT: [[VLD4Q_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4.v8i16.p0(ptr [[A]], i32 2)8058// CHECK-NEXT: [[VLD4Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 08059// CHECK-NEXT: [[VLD4Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 18060// CHECK-NEXT: [[VLD4Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 28061// CHECK-NEXT: [[VLD4Q_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 38062// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168063// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168064// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168065// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328066// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168067// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488068// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168069// CHECK-NEXT: ret void8070//8071uint16x8x4_t test_vld4q_u16(uint16_t const * a) {8072 return vld4q_u16(a);8073}8074 8075// CHECK-LABEL: define void @test_vld4q_u32(8076// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X4X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8077// CHECK-NEXT: [[ENTRY:.*:]]8078// CHECK-NEXT: [[VLD4Q_V:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4.v4i32.p0(ptr [[A]], i32 4)8079// CHECK-NEXT: [[VLD4Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_V]], 08080// CHECK-NEXT: [[VLD4Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_V]], 18081// CHECK-NEXT: [[VLD4Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_V]], 28082// CHECK-NEXT: [[VLD4Q_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_V]], 38083// CHECK-NEXT: store <4 x i32> [[VLD4Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168084// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168085// CHECK-NEXT: store <4 x i32> [[VLD4Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168086// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328087// CHECK-NEXT: store <4 x i32> [[VLD4Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168088// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488089// CHECK-NEXT: store <4 x i32> [[VLD4Q_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168090// CHECK-NEXT: ret void8091//8092uint32x4x4_t test_vld4q_u32(uint32_t const * a) {8093 return vld4q_u32(a);8094}8095 8096// CHECK-LABEL: define void @test_vld4q_s8(8097// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X16X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8098// CHECK-NEXT: [[ENTRY:.*:]]8099// CHECK-NEXT: [[VLD4Q_V:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8.p0(ptr [[A]], i32 1)8100// CHECK-NEXT: [[VLD4Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 08101// CHECK-NEXT: [[VLD4Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 18102// CHECK-NEXT: [[VLD4Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 28103// CHECK-NEXT: [[VLD4Q_V_FCA_3_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 38104// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168105// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168106// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168107// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328108// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168109// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488110// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168111// CHECK-NEXT: ret void8112//8113int8x16x4_t test_vld4q_s8(int8_t const * a) {8114 return vld4q_s8(a);8115}8116 8117// CHECK-LABEL: define void @test_vld4q_s16(8118// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X8X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8119// CHECK-NEXT: [[ENTRY:.*:]]8120// CHECK-NEXT: [[VLD4Q_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4.v8i16.p0(ptr [[A]], i32 2)8121// CHECK-NEXT: [[VLD4Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 08122// CHECK-NEXT: [[VLD4Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 18123// CHECK-NEXT: [[VLD4Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 28124// CHECK-NEXT: [[VLD4Q_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 38125// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168126// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168127// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168128// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328129// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168130// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488131// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168132// CHECK-NEXT: ret void8133//8134int16x8x4_t test_vld4q_s16(int16_t const * a) {8135 return vld4q_s16(a);8136}8137 8138// CHECK-LABEL: define void @test_vld4q_s32(8139// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X4X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8140// CHECK-NEXT: [[ENTRY:.*:]]8141// CHECK-NEXT: [[VLD4Q_V:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4.v4i32.p0(ptr [[A]], i32 4)8142// CHECK-NEXT: [[VLD4Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_V]], 08143// CHECK-NEXT: [[VLD4Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_V]], 18144// CHECK-NEXT: [[VLD4Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_V]], 28145// CHECK-NEXT: [[VLD4Q_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_V]], 38146// CHECK-NEXT: store <4 x i32> [[VLD4Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168147// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168148// CHECK-NEXT: store <4 x i32> [[VLD4Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168149// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328150// CHECK-NEXT: store <4 x i32> [[VLD4Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168151// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488152// CHECK-NEXT: store <4 x i32> [[VLD4Q_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168153// CHECK-NEXT: ret void8154//8155int32x4x4_t test_vld4q_s32(int32_t const * a) {8156 return vld4q_s32(a);8157}8158 8159// CHECK-LABEL: define void @test_vld4q_f16(8160// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X8X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8161// CHECK-NEXT: [[ENTRY:.*:]]8162// CHECK-NEXT: [[VLD4Q_V:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4.v8f16.p0(ptr [[A]], i32 2)8163// CHECK-NEXT: [[VLD4Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4Q_V]], 08164// CHECK-NEXT: [[VLD4Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4Q_V]], 18165// CHECK-NEXT: [[VLD4Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4Q_V]], 28166// CHECK-NEXT: [[VLD4Q_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4Q_V]], 38167// CHECK-NEXT: store <8 x half> [[VLD4Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168168// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168169// CHECK-NEXT: store <8 x half> [[VLD4Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168170// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328171// CHECK-NEXT: store <8 x half> [[VLD4Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168172// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488173// CHECK-NEXT: store <8 x half> [[VLD4Q_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168174// CHECK-NEXT: ret void8175//8176float16x8x4_t test_vld4q_f16(float16_t const * a) {8177 return vld4q_f16(a);8178}8179 8180// CHECK-LABEL: define void @test_vld4q_f32(8181// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X4X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8182// CHECK-NEXT: [[ENTRY:.*:]]8183// CHECK-NEXT: [[VLD4Q_V:%.*]] = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32.p0(ptr [[A]], i32 4)8184// CHECK-NEXT: [[VLD4Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD4Q_V]], 08185// CHECK-NEXT: [[VLD4Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD4Q_V]], 18186// CHECK-NEXT: [[VLD4Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD4Q_V]], 28187// CHECK-NEXT: [[VLD4Q_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD4Q_V]], 38188// CHECK-NEXT: store <4 x float> [[VLD4Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168189// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168190// CHECK-NEXT: store <4 x float> [[VLD4Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168191// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328192// CHECK-NEXT: store <4 x float> [[VLD4Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168193// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488194// CHECK-NEXT: store <4 x float> [[VLD4Q_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168195// CHECK-NEXT: ret void8196//8197float32x4x4_t test_vld4q_f32(float32_t const * a) {8198 return vld4q_f32(a);8199}8200 8201// CHECK-LABEL: define void @test_vld4q_p8(8202// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X16X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8203// CHECK-NEXT: [[ENTRY:.*:]]8204// CHECK-NEXT: [[VLD4Q_V:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8.p0(ptr [[A]], i32 1)8205// CHECK-NEXT: [[VLD4Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 08206// CHECK-NEXT: [[VLD4Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 18207// CHECK-NEXT: [[VLD4Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 28208// CHECK-NEXT: [[VLD4Q_V_FCA_3_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD4Q_V]], 38209// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168210// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168211// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168212// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328213// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168214// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488215// CHECK-NEXT: store <16 x i8> [[VLD4Q_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168216// CHECK-NEXT: ret void8217//8218poly8x16x4_t test_vld4q_p8(poly8_t const * a) {8219 return vld4q_p8(a);8220}8221 8222// CHECK-LABEL: define void @test_vld4q_p16(8223// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X8X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8224// CHECK-NEXT: [[ENTRY:.*:]]8225// CHECK-NEXT: [[VLD4Q_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4.v8i16.p0(ptr [[A]], i32 2)8226// CHECK-NEXT: [[VLD4Q_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 08227// CHECK-NEXT: [[VLD4Q_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 18228// CHECK-NEXT: [[VLD4Q_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 28229// CHECK-NEXT: [[VLD4Q_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_V]], 38230// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168231// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168232// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168233// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328234// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168235// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488236// CHECK-NEXT: store <8 x i16> [[VLD4Q_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168237// CHECK-NEXT: ret void8238//8239poly16x8x4_t test_vld4q_p16(poly16_t const * a) {8240 return vld4q_p16(a);8241}8242 8243// CHECK-LABEL: define void @test_vld4_u8(8244// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X8X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8245// CHECK-NEXT: [[ENTRY:.*:]]8246// CHECK-NEXT: [[VLD4_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4.v8i8.p0(ptr [[A]], i32 1)8247// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 08248// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 18249// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 28250// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 38251// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88252// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88253// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88254// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168255// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88256// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248257// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88258// CHECK-NEXT: ret void8259//8260uint8x8x4_t test_vld4_u8(uint8_t const * a) {8261 return vld4_u8(a);8262}8263 8264// CHECK-LABEL: define void @test_vld4_u16(8265// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X4X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8266// CHECK-NEXT: [[ENTRY:.*:]]8267// CHECK-NEXT: [[VLD4_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4.v4i16.p0(ptr [[A]], i32 2)8268// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 08269// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 18270// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 28271// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 38272// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88273// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88274// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88275// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168276// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88277// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248278// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88279// CHECK-NEXT: ret void8280//8281uint16x4x4_t test_vld4_u16(uint16_t const * a) {8282 return vld4_u16(a);8283}8284 8285// CHECK-LABEL: define void @test_vld4_u32(8286// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X2X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8287// CHECK-NEXT: [[ENTRY:.*:]]8288// CHECK-NEXT: [[VLD4_V:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4.v2i32.p0(ptr [[A]], i32 4)8289// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_V]], 08290// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_V]], 18291// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_V]], 28292// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_V]], 38293// CHECK-NEXT: store <2 x i32> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88294// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88295// CHECK-NEXT: store <2 x i32> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88296// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168297// CHECK-NEXT: store <2 x i32> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88298// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248299// CHECK-NEXT: store <2 x i32> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88300// CHECK-NEXT: ret void8301//8302uint32x2x4_t test_vld4_u32(uint32_t const * a) {8303 return vld4_u32(a);8304}8305 8306// CHECK-LABEL: define void @test_vld4_u64(8307// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT64X1X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8308// CHECK-NEXT: [[ENTRY:.*:]]8309// CHECK-NEXT: [[VLD4_V:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld4.v1i64.p0(ptr [[A]], i32 4)8310// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4_V]], 08311// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4_V]], 18312// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4_V]], 28313// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4_V]], 38314// CHECK-NEXT: store <1 x i64> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88315// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88316// CHECK-NEXT: store <1 x i64> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88317// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168318// CHECK-NEXT: store <1 x i64> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88319// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248320// CHECK-NEXT: store <1 x i64> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88321// CHECK-NEXT: ret void8322//8323uint64x1x4_t test_vld4_u64(uint64_t const * a) {8324 return vld4_u64(a);8325}8326 8327// CHECK-LABEL: define void @test_vld4_s8(8328// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X8X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8329// CHECK-NEXT: [[ENTRY:.*:]]8330// CHECK-NEXT: [[VLD4_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4.v8i8.p0(ptr [[A]], i32 1)8331// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 08332// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 18333// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 28334// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 38335// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88336// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88337// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88338// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168339// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88340// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248341// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88342// CHECK-NEXT: ret void8343//8344int8x8x4_t test_vld4_s8(int8_t const * a) {8345 return vld4_s8(a);8346}8347 8348// CHECK-LABEL: define void @test_vld4_s16(8349// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X4X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8350// CHECK-NEXT: [[ENTRY:.*:]]8351// CHECK-NEXT: [[VLD4_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4.v4i16.p0(ptr [[A]], i32 2)8352// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 08353// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 18354// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 28355// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 38356// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88357// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88358// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88359// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168360// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88361// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248362// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88363// CHECK-NEXT: ret void8364//8365int16x4x4_t test_vld4_s16(int16_t const * a) {8366 return vld4_s16(a);8367}8368 8369// CHECK-LABEL: define void @test_vld4_s32(8370// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X2X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8371// CHECK-NEXT: [[ENTRY:.*:]]8372// CHECK-NEXT: [[VLD4_V:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4.v2i32.p0(ptr [[A]], i32 4)8373// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_V]], 08374// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_V]], 18375// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_V]], 28376// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_V]], 38377// CHECK-NEXT: store <2 x i32> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88378// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88379// CHECK-NEXT: store <2 x i32> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88380// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168381// CHECK-NEXT: store <2 x i32> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88382// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248383// CHECK-NEXT: store <2 x i32> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88384// CHECK-NEXT: ret void8385//8386int32x2x4_t test_vld4_s32(int32_t const * a) {8387 return vld4_s32(a);8388}8389 8390// CHECK-LABEL: define void @test_vld4_s64(8391// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT64X1X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8392// CHECK-NEXT: [[ENTRY:.*:]]8393// CHECK-NEXT: [[VLD4_V:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld4.v1i64.p0(ptr [[A]], i32 4)8394// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4_V]], 08395// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4_V]], 18396// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4_V]], 28397// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4_V]], 38398// CHECK-NEXT: store <1 x i64> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88399// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88400// CHECK-NEXT: store <1 x i64> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88401// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168402// CHECK-NEXT: store <1 x i64> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88403// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248404// CHECK-NEXT: store <1 x i64> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88405// CHECK-NEXT: ret void8406//8407int64x1x4_t test_vld4_s64(int64_t const * a) {8408 return vld4_s64(a);8409}8410 8411// CHECK-LABEL: define void @test_vld4_f16(8412// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X4X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8413// CHECK-NEXT: [[ENTRY:.*:]]8414// CHECK-NEXT: [[VLD4_V:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4.v4f16.p0(ptr [[A]], i32 2)8415// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4_V]], 08416// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4_V]], 18417// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4_V]], 28418// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4_V]], 38419// CHECK-NEXT: store <4 x half> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88420// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88421// CHECK-NEXT: store <4 x half> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88422// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168423// CHECK-NEXT: store <4 x half> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88424// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248425// CHECK-NEXT: store <4 x half> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88426// CHECK-NEXT: ret void8427//8428float16x4x4_t test_vld4_f16(float16_t const * a) {8429 return vld4_f16(a);8430}8431 8432// CHECK-LABEL: define void @test_vld4_f32(8433// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X2X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8434// CHECK-NEXT: [[ENTRY:.*:]]8435// CHECK-NEXT: [[VLD4_V:%.*]] = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld4.v2f32.p0(ptr [[A]], i32 4)8436// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD4_V]], 08437// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD4_V]], 18438// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD4_V]], 28439// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD4_V]], 38440// CHECK-NEXT: store <2 x float> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88441// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88442// CHECK-NEXT: store <2 x float> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88443// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168444// CHECK-NEXT: store <2 x float> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88445// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248446// CHECK-NEXT: store <2 x float> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88447// CHECK-NEXT: ret void8448//8449float32x2x4_t test_vld4_f32(float32_t const * a) {8450 return vld4_f32(a);8451}8452 8453// CHECK-LABEL: define void @test_vld4_p8(8454// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X8X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8455// CHECK-NEXT: [[ENTRY:.*:]]8456// CHECK-NEXT: [[VLD4_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4.v8i8.p0(ptr [[A]], i32 1)8457// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 08458// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 18459// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 28460// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_V]], 38461// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88462// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88463// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88464// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168465// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88466// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248467// CHECK-NEXT: store <8 x i8> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88468// CHECK-NEXT: ret void8469//8470poly8x8x4_t test_vld4_p8(poly8_t const * a) {8471 return vld4_p8(a);8472}8473 8474// CHECK-LABEL: define void @test_vld4_p16(8475// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X4X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {8476// CHECK-NEXT: [[ENTRY:.*:]]8477// CHECK-NEXT: [[VLD4_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4.v4i16.p0(ptr [[A]], i32 2)8478// CHECK-NEXT: [[VLD4_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 08479// CHECK-NEXT: [[VLD4_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 18480// CHECK-NEXT: [[VLD4_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 28481// CHECK-NEXT: [[VLD4_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_V]], 38482// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88483// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88484// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88485// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168486// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88487// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248488// CHECK-NEXT: store <4 x i16> [[VLD4_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88489// CHECK-NEXT: ret void8490//8491poly16x4x4_t test_vld4_p16(poly16_t const * a) {8492 return vld4_p16(a);8493}8494 8495// CHECK-LABEL: define void @test_vld4q_lane_u16(8496// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X8X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [8 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8497// CHECK-NEXT: [[ENTRY:.*:]]8498// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 08499// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 08500// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 18501// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 18502// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 28503// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 08504// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 38505// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 18506// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 48507// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 08508// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 58509// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 18510// CHECK-NEXT: [[B_COERCE_FCA_6_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 68511// CHECK-NEXT: [[B_SROA_9_48_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_6_EXTRACT]], i32 08512// CHECK-NEXT: [[B_COERCE_FCA_7_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 78513// CHECK-NEXT: [[B_SROA_9_56_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_9_48_VEC_INSERT]], i64 [[B_COERCE_FCA_7_EXTRACT]], i32 18514// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>8515// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>8516// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>8517// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_SROA_9_56_VEC_INSERT]] to <16 x i8>8518// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>8519// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>8520// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>8521// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>8522// CHECK-NEXT: [[VLD4Q_LANE_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4lane.v8i16.p0(ptr [[A]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], <8 x i16> [[TMP6]], <8 x i16> [[TMP7]], i32 7, i32 2)8523// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 08524// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 18525// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 28526// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 38527// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168528// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168529// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168530// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328531// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168532// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488533// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168534// CHECK-NEXT: ret void8535//8536uint16x8x4_t test_vld4q_lane_u16(uint16_t const * a, uint16x8x4_t b) {8537 return vld4q_lane_u16(a, b, 7);8538}8539 8540// CHECK-LABEL: define void @test_vld4q_lane_u32(8541// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X4X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [8 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8542// CHECK-NEXT: [[ENTRY:.*:]]8543// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 08544// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 08545// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 18546// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 18547// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 28548// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 08549// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 38550// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 18551// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 48552// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 08553// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 58554// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 18555// CHECK-NEXT: [[B_COERCE_FCA_6_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 68556// CHECK-NEXT: [[B_SROA_9_48_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_6_EXTRACT]], i32 08557// CHECK-NEXT: [[B_COERCE_FCA_7_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 78558// CHECK-NEXT: [[B_SROA_9_56_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_9_48_VEC_INSERT]], i64 [[B_COERCE_FCA_7_EXTRACT]], i32 18559// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>8560// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>8561// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>8562// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_SROA_9_56_VEC_INSERT]] to <16 x i8>8563// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>8564// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>8565// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>8566// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x i32>8567// CHECK-NEXT: [[VLD4Q_LANE_V:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32.p0(ptr [[A]], <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], i32 3, i32 4)8568// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_LANE_V]], 08569// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_LANE_V]], 18570// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_LANE_V]], 28571// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_LANE_V]], 38572// CHECK-NEXT: store <4 x i32> [[VLD4Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168573// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168574// CHECK-NEXT: store <4 x i32> [[VLD4Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168575// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328576// CHECK-NEXT: store <4 x i32> [[VLD4Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168577// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488578// CHECK-NEXT: store <4 x i32> [[VLD4Q_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168579// CHECK-NEXT: ret void8580//8581uint32x4x4_t test_vld4q_lane_u32(uint32_t const * a, uint32x4x4_t b) {8582 return vld4q_lane_u32(a, b, 3);8583}8584 8585// CHECK-LABEL: define void @test_vld4q_lane_s16(8586// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X8X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [8 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8587// CHECK-NEXT: [[ENTRY:.*:]]8588// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 08589// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 08590// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 18591// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 18592// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 28593// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 08594// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 38595// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 18596// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 48597// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 08598// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 58599// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 18600// CHECK-NEXT: [[B_COERCE_FCA_6_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 68601// CHECK-NEXT: [[B_SROA_9_48_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_6_EXTRACT]], i32 08602// CHECK-NEXT: [[B_COERCE_FCA_7_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 78603// CHECK-NEXT: [[B_SROA_9_56_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_9_48_VEC_INSERT]], i64 [[B_COERCE_FCA_7_EXTRACT]], i32 18604// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>8605// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>8606// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>8607// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_SROA_9_56_VEC_INSERT]] to <16 x i8>8608// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>8609// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>8610// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>8611// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>8612// CHECK-NEXT: [[VLD4Q_LANE_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4lane.v8i16.p0(ptr [[A]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], <8 x i16> [[TMP6]], <8 x i16> [[TMP7]], i32 7, i32 2)8613// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 08614// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 18615// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 28616// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 38617// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168618// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168619// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168620// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328621// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168622// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488623// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168624// CHECK-NEXT: ret void8625//8626int16x8x4_t test_vld4q_lane_s16(int16_t const * a, int16x8x4_t b) {8627 return vld4q_lane_s16(a, b, 7);8628}8629 8630// CHECK-LABEL: define void @test_vld4q_lane_s32(8631// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X4X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [8 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8632// CHECK-NEXT: [[ENTRY:.*:]]8633// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 08634// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 08635// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 18636// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 18637// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 28638// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 08639// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 38640// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 18641// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 48642// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 08643// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 58644// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 18645// CHECK-NEXT: [[B_COERCE_FCA_6_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 68646// CHECK-NEXT: [[B_SROA_9_48_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_6_EXTRACT]], i32 08647// CHECK-NEXT: [[B_COERCE_FCA_7_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 78648// CHECK-NEXT: [[B_SROA_9_56_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_9_48_VEC_INSERT]], i64 [[B_COERCE_FCA_7_EXTRACT]], i32 18649// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>8650// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>8651// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>8652// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_SROA_9_56_VEC_INSERT]] to <16 x i8>8653// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>8654// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>8655// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>8656// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x i32>8657// CHECK-NEXT: [[VLD4Q_LANE_V:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32.p0(ptr [[A]], <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], i32 3, i32 4)8658// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_LANE_V]], 08659// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_LANE_V]], 18660// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_LANE_V]], 28661// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD4Q_LANE_V]], 38662// CHECK-NEXT: store <4 x i32> [[VLD4Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168663// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168664// CHECK-NEXT: store <4 x i32> [[VLD4Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168665// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328666// CHECK-NEXT: store <4 x i32> [[VLD4Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168667// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488668// CHECK-NEXT: store <4 x i32> [[VLD4Q_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168669// CHECK-NEXT: ret void8670//8671int32x4x4_t test_vld4q_lane_s32(int32_t const * a, int32x4x4_t b) {8672 return vld4q_lane_s32(a, b, 3);8673}8674 8675// CHECK-LABEL: define void @test_vld4q_lane_f16(8676// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X8X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [8 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8677// CHECK-NEXT: [[ENTRY:.*:]]8678// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 08679// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 08680// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 18681// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 18682// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 28683// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 08684// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 38685// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 18686// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 48687// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 08688// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 58689// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 18690// CHECK-NEXT: [[B_COERCE_FCA_6_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 68691// CHECK-NEXT: [[B_SROA_9_48_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_6_EXTRACT]], i32 08692// CHECK-NEXT: [[B_COERCE_FCA_7_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 78693// CHECK-NEXT: [[B_SROA_9_56_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_9_48_VEC_INSERT]], i64 [[B_COERCE_FCA_7_EXTRACT]], i32 18694// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>8695// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>8696// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>8697// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_SROA_9_56_VEC_INSERT]] to <16 x i8>8698// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>8699// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>8700// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>8701// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x half>8702// CHECK-NEXT: [[VLD4Q_LANE_V:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0(ptr [[A]], <8 x half> [[TMP4]], <8 x half> [[TMP5]], <8 x half> [[TMP6]], <8 x half> [[TMP7]], i32 7, i32 2)8703// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4Q_LANE_V]], 08704// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4Q_LANE_V]], 18705// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4Q_LANE_V]], 28706// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4Q_LANE_V]], 38707// CHECK-NEXT: store <8 x half> [[VLD4Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168708// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168709// CHECK-NEXT: store <8 x half> [[VLD4Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168710// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328711// CHECK-NEXT: store <8 x half> [[VLD4Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168712// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488713// CHECK-NEXT: store <8 x half> [[VLD4Q_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168714// CHECK-NEXT: ret void8715//8716float16x8x4_t test_vld4q_lane_f16(float16_t const * a, float16x8x4_t b) {8717 return vld4q_lane_f16(a, b, 7);8718}8719 8720// CHECK-LABEL: define void @test_vld4q_lane_f32(8721// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X4X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [8 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8722// CHECK-NEXT: [[ENTRY:.*:]]8723// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 08724// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 08725// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 18726// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 18727// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 28728// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 08729// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 38730// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 18731// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 48732// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 08733// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 58734// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 18735// CHECK-NEXT: [[B_COERCE_FCA_6_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 68736// CHECK-NEXT: [[B_SROA_9_48_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_6_EXTRACT]], i32 08737// CHECK-NEXT: [[B_COERCE_FCA_7_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 78738// CHECK-NEXT: [[B_SROA_9_56_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_9_48_VEC_INSERT]], i64 [[B_COERCE_FCA_7_EXTRACT]], i32 18739// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>8740// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>8741// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>8742// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_SROA_9_56_VEC_INSERT]] to <16 x i8>8743// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>8744// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>8745// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>8746// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>8747// CHECK-NEXT: [[VLD4Q_LANE_V:%.*]] = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4lane.v4f32.p0(ptr [[A]], <4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x float> [[TMP6]], <4 x float> [[TMP7]], i32 3, i32 4)8748// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD4Q_LANE_V]], 08749// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD4Q_LANE_V]], 18750// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD4Q_LANE_V]], 28751// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD4Q_LANE_V]], 38752// CHECK-NEXT: store <4 x float> [[VLD4Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168753// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168754// CHECK-NEXT: store <4 x float> [[VLD4Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168755// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328756// CHECK-NEXT: store <4 x float> [[VLD4Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168757// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488758// CHECK-NEXT: store <4 x float> [[VLD4Q_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168759// CHECK-NEXT: ret void8760//8761float32x4x4_t test_vld4q_lane_f32(float32_t const * a, float32x4x4_t b) {8762 return vld4q_lane_f32(a, b, 3);8763}8764 8765// CHECK-LABEL: define void @test_vld4q_lane_p16(8766// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X8X4_T:%.*]]) align 16 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [8 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8767// CHECK-NEXT: [[ENTRY:.*:]]8768// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 08769// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_0_EXTRACT]], i32 08770// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 18771// CHECK-NEXT: [[B_SROA_0_8_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_0_0_VEC_INSERT]], i64 [[B_COERCE_FCA_1_EXTRACT]], i32 18772// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 28773// CHECK-NEXT: [[B_SROA_3_16_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_2_EXTRACT]], i32 08774// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 38775// CHECK-NEXT: [[B_SROA_3_24_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_3_16_VEC_INSERT]], i64 [[B_COERCE_FCA_3_EXTRACT]], i32 18776// CHECK-NEXT: [[B_COERCE_FCA_4_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 48777// CHECK-NEXT: [[B_SROA_6_32_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_4_EXTRACT]], i32 08778// CHECK-NEXT: [[B_COERCE_FCA_5_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 58779// CHECK-NEXT: [[B_SROA_6_40_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_6_32_VEC_INSERT]], i64 [[B_COERCE_FCA_5_EXTRACT]], i32 18780// CHECK-NEXT: [[B_COERCE_FCA_6_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 68781// CHECK-NEXT: [[B_SROA_9_48_VEC_INSERT:%.*]] = insertelement <2 x i64> undef, i64 [[B_COERCE_FCA_6_EXTRACT]], i32 08782// CHECK-NEXT: [[B_COERCE_FCA_7_EXTRACT:%.*]] = extractvalue [8 x i64] [[B_COERCE]], 78783// CHECK-NEXT: [[B_SROA_9_56_VEC_INSERT:%.*]] = insertelement <2 x i64> [[B_SROA_9_48_VEC_INSERT]], i64 [[B_COERCE_FCA_7_EXTRACT]], i32 18784// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_SROA_0_8_VEC_INSERT]] to <16 x i8>8785// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_SROA_3_24_VEC_INSERT]] to <16 x i8>8786// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_SROA_6_40_VEC_INSERT]] to <16 x i8>8787// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_SROA_9_56_VEC_INSERT]] to <16 x i8>8788// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>8789// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>8790// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>8791// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>8792// CHECK-NEXT: [[VLD4Q_LANE_V:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4lane.v8i16.p0(ptr [[A]], <8 x i16> [[TMP4]], <8 x i16> [[TMP5]], <8 x i16> [[TMP6]], <8 x i16> [[TMP7]], i32 7, i32 2)8793// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 08794// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 18795// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 28796// CHECK-NEXT: [[VLD4Q_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4Q_LANE_V]], 38797// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 168798// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168799// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 168800// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 328801// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 168802// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 488803// CHECK-NEXT: store <8 x i16> [[VLD4Q_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 168804// CHECK-NEXT: ret void8805//8806poly16x8x4_t test_vld4q_lane_p16(poly16_t const * a, poly16x8x4_t b) {8807 return vld4q_lane_p16(a, b, 7);8808}8809 8810// CHECK-LABEL: define void @test_vld4_lane_u8(8811// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT8X8X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8812// CHECK-NEXT: [[ENTRY:.*:]]8813// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 08814// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>8815// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 18816// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>8817// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 28818// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>8819// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 38820// CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>8821// CHECK-NEXT: [[VLD4_LANE_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4lane.v8i8.p0(ptr [[A]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]], <8 x i8> [[TMP3]], i32 7, i32 1)8822// CHECK-NEXT: [[VLD4_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 08823// CHECK-NEXT: [[VLD4_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 18824// CHECK-NEXT: [[VLD4_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 28825// CHECK-NEXT: [[VLD4_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 38826// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88827// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88828// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88829// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168830// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88831// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248832// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88833// CHECK-NEXT: ret void8834//8835uint8x8x4_t test_vld4_lane_u8(uint8_t const * a, uint8x8x4_t b) {8836 return vld4_lane_u8(a, b, 7);8837}8838 8839// CHECK-LABEL: define void @test_vld4_lane_u16(8840// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT16X4X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8841// CHECK-NEXT: [[ENTRY:.*:]]8842// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 08843// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>8844// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 18845// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>8846// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 28847// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <4 x i16>8848// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 38849// CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_COERCE_FCA_3_EXTRACT]] to <4 x i16>8850// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>8851// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>8852// CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>8853// CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP3]] to <8 x i8>8854// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>8855// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16>8856// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>8857// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x i16>8858// CHECK-NEXT: [[VLD4_LANE_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4lane.v4i16.p0(ptr [[A]], <4 x i16> [[TMP8]], <4 x i16> [[TMP9]], <4 x i16> [[TMP10]], <4 x i16> [[TMP11]], i32 3, i32 2)8859// CHECK-NEXT: [[VLD4_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 08860// CHECK-NEXT: [[VLD4_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 18861// CHECK-NEXT: [[VLD4_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 28862// CHECK-NEXT: [[VLD4_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 38863// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88864// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88865// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88866// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168867// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88868// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248869// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88870// CHECK-NEXT: ret void8871//8872uint16x4x4_t test_vld4_lane_u16(uint16_t const * a, uint16x4x4_t b) {8873 return vld4_lane_u16(a, b, 3);8874}8875 8876// CHECK-LABEL: define void @test_vld4_lane_u32(8877// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_UINT32X2X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8878// CHECK-NEXT: [[ENTRY:.*:]]8879// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 08880// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>8881// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 18882// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>8883// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 28884// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <2 x i32>8885// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 38886// CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_COERCE_FCA_3_EXTRACT]] to <2 x i32>8887// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>8888// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>8889// CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>8890// CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP3]] to <8 x i8>8891// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x i32>8892// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x i32>8893// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <2 x i32>8894// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <2 x i32>8895// CHECK-NEXT: [[VLD4_LANE_V:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4lane.v2i32.p0(ptr [[A]], <2 x i32> [[TMP8]], <2 x i32> [[TMP9]], <2 x i32> [[TMP10]], <2 x i32> [[TMP11]], i32 1, i32 4)8896// CHECK-NEXT: [[VLD4_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_LANE_V]], 08897// CHECK-NEXT: [[VLD4_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_LANE_V]], 18898// CHECK-NEXT: [[VLD4_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_LANE_V]], 28899// CHECK-NEXT: [[VLD4_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_LANE_V]], 38900// CHECK-NEXT: store <2 x i32> [[VLD4_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88901// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88902// CHECK-NEXT: store <2 x i32> [[VLD4_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88903// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168904// CHECK-NEXT: store <2 x i32> [[VLD4_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88905// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248906// CHECK-NEXT: store <2 x i32> [[VLD4_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88907// CHECK-NEXT: ret void8908//8909uint32x2x4_t test_vld4_lane_u32(uint32_t const * a, uint32x2x4_t b) {8910 return vld4_lane_u32(a, b, 1);8911}8912 8913// CHECK-LABEL: define void @test_vld4_lane_s8(8914// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT8X8X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8915// CHECK-NEXT: [[ENTRY:.*:]]8916// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 08917// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>8918// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 18919// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>8920// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 28921// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>8922// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 38923// CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>8924// CHECK-NEXT: [[VLD4_LANE_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4lane.v8i8.p0(ptr [[A]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]], <8 x i8> [[TMP3]], i32 7, i32 1)8925// CHECK-NEXT: [[VLD4_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 08926// CHECK-NEXT: [[VLD4_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 18927// CHECK-NEXT: [[VLD4_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 28928// CHECK-NEXT: [[VLD4_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 38929// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88930// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88931// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88932// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168933// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88934// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248935// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88936// CHECK-NEXT: ret void8937//8938int8x8x4_t test_vld4_lane_s8(int8_t const * a, int8x8x4_t b) {8939 return vld4_lane_s8(a, b, 7);8940}8941 8942// CHECK-LABEL: define void @test_vld4_lane_s16(8943// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT16X4X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8944// CHECK-NEXT: [[ENTRY:.*:]]8945// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 08946// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>8947// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 18948// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>8949// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 28950// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <4 x i16>8951// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 38952// CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_COERCE_FCA_3_EXTRACT]] to <4 x i16>8953// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>8954// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>8955// CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>8956// CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP3]] to <8 x i8>8957// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>8958// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16>8959// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>8960// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x i16>8961// CHECK-NEXT: [[VLD4_LANE_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4lane.v4i16.p0(ptr [[A]], <4 x i16> [[TMP8]], <4 x i16> [[TMP9]], <4 x i16> [[TMP10]], <4 x i16> [[TMP11]], i32 3, i32 2)8962// CHECK-NEXT: [[VLD4_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 08963// CHECK-NEXT: [[VLD4_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 18964// CHECK-NEXT: [[VLD4_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 28965// CHECK-NEXT: [[VLD4_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 38966// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 88967// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 88968// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 88969// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 168970// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 88971// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 248972// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 88973// CHECK-NEXT: ret void8974//8975int16x4x4_t test_vld4_lane_s16(int16_t const * a, int16x4x4_t b) {8976 return vld4_lane_s16(a, b, 3);8977}8978 8979// CHECK-LABEL: define void @test_vld4_lane_s32(8980// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_INT32X2X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {8981// CHECK-NEXT: [[ENTRY:.*:]]8982// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 08983// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <2 x i32>8984// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 18985// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <2 x i32>8986// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 28987// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <2 x i32>8988// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 38989// CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_COERCE_FCA_3_EXTRACT]] to <2 x i32>8990// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>8991// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>8992// CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP2]] to <8 x i8>8993// CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP3]] to <8 x i8>8994// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x i32>8995// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x i32>8996// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <2 x i32>8997// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <2 x i32>8998// CHECK-NEXT: [[VLD4_LANE_V:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4lane.v2i32.p0(ptr [[A]], <2 x i32> [[TMP8]], <2 x i32> [[TMP9]], <2 x i32> [[TMP10]], <2 x i32> [[TMP11]], i32 1, i32 4)8999// CHECK-NEXT: [[VLD4_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_LANE_V]], 09000// CHECK-NEXT: [[VLD4_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_LANE_V]], 19001// CHECK-NEXT: [[VLD4_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_LANE_V]], 29002// CHECK-NEXT: [[VLD4_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD4_LANE_V]], 39003// CHECK-NEXT: store <2 x i32> [[VLD4_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 89004// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 89005// CHECK-NEXT: store <2 x i32> [[VLD4_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 89006// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 169007// CHECK-NEXT: store <2 x i32> [[VLD4_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 89008// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 249009// CHECK-NEXT: store <2 x i32> [[VLD4_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 89010// CHECK-NEXT: ret void9011//9012int32x2x4_t test_vld4_lane_s32(int32_t const * a, int32x2x4_t b) {9013 return vld4_lane_s32(a, b, 1);9014}9015 9016// CHECK-LABEL: define void @test_vld4_lane_f16(9017// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT16X4X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {9018// CHECK-NEXT: [[ENTRY:.*:]]9019// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 09020// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x half>9021// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 19022// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x half>9023// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 29024// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <4 x half>9025// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 39026// CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_COERCE_FCA_3_EXTRACT]] to <4 x half>9027// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x half> [[TMP0]] to <8 x i8>9028// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x half> [[TMP1]] to <8 x i8>9029// CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x half> [[TMP2]] to <8 x i8>9030// CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x half> [[TMP3]] to <8 x i8>9031// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>9032// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half>9033// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>9034// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x half>9035// CHECK-NEXT: [[VLD4_LANE_V:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4lane.v4f16.p0(ptr [[A]], <4 x half> [[TMP8]], <4 x half> [[TMP9]], <4 x half> [[TMP10]], <4 x half> [[TMP11]], i32 3, i32 2)9036// CHECK-NEXT: [[VLD4_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4_LANE_V]], 09037// CHECK-NEXT: [[VLD4_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4_LANE_V]], 19038// CHECK-NEXT: [[VLD4_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4_LANE_V]], 29039// CHECK-NEXT: [[VLD4_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4_LANE_V]], 39040// CHECK-NEXT: store <4 x half> [[VLD4_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 89041// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 89042// CHECK-NEXT: store <4 x half> [[VLD4_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 89043// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 169044// CHECK-NEXT: store <4 x half> [[VLD4_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 89045// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 249046// CHECK-NEXT: store <4 x half> [[VLD4_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 89047// CHECK-NEXT: ret void9048//9049float16x4x4_t test_vld4_lane_f16(float16_t const * a, float16x4x4_t b) {9050 return vld4_lane_f16(a, b, 3);9051}9052 9053// CHECK-LABEL: define void @test_vld4_lane_f32(9054// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_FLOAT32X2X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {9055// CHECK-NEXT: [[ENTRY:.*:]]9056// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 09057// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <2 x float>9058// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 19059// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <2 x float>9060// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 29061// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <2 x float>9062// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 39063// CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_COERCE_FCA_3_EXTRACT]] to <2 x float>9064// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x float> [[TMP0]] to <8 x i8>9065// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x float> [[TMP1]] to <8 x i8>9066// CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x float> [[TMP2]] to <8 x i8>9067// CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x float> [[TMP3]] to <8 x i8>9068// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x float>9069// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <2 x float>9070// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <2 x float>9071// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <2 x float>9072// CHECK-NEXT: [[VLD4_LANE_V:%.*]] = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld4lane.v2f32.p0(ptr [[A]], <2 x float> [[TMP8]], <2 x float> [[TMP9]], <2 x float> [[TMP10]], <2 x float> [[TMP11]], i32 1, i32 4)9073// CHECK-NEXT: [[VLD4_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD4_LANE_V]], 09074// CHECK-NEXT: [[VLD4_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD4_LANE_V]], 19075// CHECK-NEXT: [[VLD4_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD4_LANE_V]], 29076// CHECK-NEXT: [[VLD4_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD4_LANE_V]], 39077// CHECK-NEXT: store <2 x float> [[VLD4_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 89078// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 89079// CHECK-NEXT: store <2 x float> [[VLD4_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 89080// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 169081// CHECK-NEXT: store <2 x float> [[VLD4_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 89082// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 249083// CHECK-NEXT: store <2 x float> [[VLD4_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 89084// CHECK-NEXT: ret void9085//9086float32x2x4_t test_vld4_lane_f32(float32_t const * a, float32x2x4_t b) {9087 return vld4_lane_f32(a, b, 1);9088}9089 9090// CHECK-LABEL: define void @test_vld4_lane_p8(9091// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY8X8X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {9092// CHECK-NEXT: [[ENTRY:.*:]]9093// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 09094// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>9095// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 19096// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>9097// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 29098// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>9099// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 39100// CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>9101// CHECK-NEXT: [[VLD4_LANE_V:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4lane.v8i8.p0(ptr [[A]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]], <8 x i8> [[TMP3]], i32 7, i32 1)9102// CHECK-NEXT: [[VLD4_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 09103// CHECK-NEXT: [[VLD4_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 19104// CHECK-NEXT: [[VLD4_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 29105// CHECK-NEXT: [[VLD4_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD4_LANE_V]], 39106// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 89107// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 89108// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 89109// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 169110// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 89111// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 249112// CHECK-NEXT: store <8 x i8> [[VLD4_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 89113// CHECK-NEXT: ret void9114//9115poly8x8x4_t test_vld4_lane_p8(poly8_t const * a, poly8x8x4_t b) {9116 return vld4_lane_p8(a, b, 7);9117}9118 9119// CHECK-LABEL: define void @test_vld4_lane_p16(9120// CHECK-SAME: ptr dead_on_unwind noalias writable sret([[STRUCT_POLY16X4X4_T:%.*]]) align 8 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]], [4 x i64] [[B_COERCE:%.*]]) #[[ATTR0]] {9121// CHECK-NEXT: [[ENTRY:.*:]]9122// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 09123// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[B_COERCE_FCA_0_EXTRACT]] to <4 x i16>9124// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 19125// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE_FCA_1_EXTRACT]] to <4 x i16>9126// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 29127// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE_FCA_2_EXTRACT]] to <4 x i16>9128// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x i64] [[B_COERCE]], 39129// CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[B_COERCE_FCA_3_EXTRACT]] to <4 x i16>9130// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>9131// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>9132// CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP2]] to <8 x i8>9133// CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP3]] to <8 x i8>9134// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>9135// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16>9136// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>9137// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x i16>9138// CHECK-NEXT: [[VLD4_LANE_V:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4lane.v4i16.p0(ptr [[A]], <4 x i16> [[TMP8]], <4 x i16> [[TMP9]], <4 x i16> [[TMP10]], <4 x i16> [[TMP11]], i32 3, i32 2)9139// CHECK-NEXT: [[VLD4_LANE_V_FCA_0_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 09140// CHECK-NEXT: [[VLD4_LANE_V_FCA_1_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 19141// CHECK-NEXT: [[VLD4_LANE_V_FCA_2_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 29142// CHECK-NEXT: [[VLD4_LANE_V_FCA_3_EXTRACT:%.*]] = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE_V]], 39143// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_0_EXTRACT]], ptr [[AGG_RESULT]], align 89144// CHECK-NEXT: [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 89145// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_1_EXTRACT]], ptr [[__RET_SROA_2_0_AGG_RESULT_SROA_IDX]], align 89146// CHECK-NEXT: [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 169147// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_2_EXTRACT]], ptr [[__RET_SROA_3_0_AGG_RESULT_SROA_IDX]], align 89148// CHECK-NEXT: [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[AGG_RESULT]], i32 249149// CHECK-NEXT: store <4 x i16> [[VLD4_LANE_V_FCA_3_EXTRACT]], ptr [[__RET_SROA_4_0_AGG_RESULT_SROA_IDX]], align 89150// CHECK-NEXT: ret void9151//9152poly16x4x4_t test_vld4_lane_p16(poly16_t const * a, poly16x4x4_t b) {9153 return vld4_lane_p16(a, b, 3);9154}9155 9156// CHECK-LABEL: define <8 x i8> @test_vmax_s8(9157// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {9158// CHECK-NEXT: [[ENTRY:.*:]]9159// CHECK-NEXT: [[VMAX_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])9160// CHECK-NEXT: ret <8 x i8> [[VMAX_V_I]]9161//9162int8x8_t test_vmax_s8(int8x8_t a, int8x8_t b) {9163 return vmax_s8(a, b);9164}9165 9166// CHECK-LABEL: define <4 x i16> @test_vmax_s16(9167// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {9168// CHECK-NEXT: [[ENTRY:.*:]]9169// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>9170// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>9171// CHECK-NEXT: [[VMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9172// CHECK-NEXT: [[VMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>9173// CHECK-NEXT: [[VMAX_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> [[VMAX_V_I]], <4 x i16> [[VMAX_V1_I]])9174// CHECK-NEXT: [[VMAX_V3_I:%.*]] = bitcast <4 x i16> [[VMAX_V2_I]] to <8 x i8>9175// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VMAX_V3_I]] to <4 x i16>9176// CHECK-NEXT: ret <4 x i16> [[TMP2]]9177//9178int16x4_t test_vmax_s16(int16x4_t a, int16x4_t b) {9179 return vmax_s16(a, b);9180}9181 9182// CHECK-LABEL: define <2 x i32> @test_vmax_s32(9183// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {9184// CHECK-NEXT: [[ENTRY:.*:]]9185// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>9186// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>9187// CHECK-NEXT: [[VMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9188// CHECK-NEXT: [[VMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>9189// CHECK-NEXT: [[VMAX_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> [[VMAX_V_I]], <2 x i32> [[VMAX_V1_I]])9190// CHECK-NEXT: [[VMAX_V3_I:%.*]] = bitcast <2 x i32> [[VMAX_V2_I]] to <8 x i8>9191// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VMAX_V3_I]] to <2 x i32>9192// CHECK-NEXT: ret <2 x i32> [[TMP2]]9193//9194int32x2_t test_vmax_s32(int32x2_t a, int32x2_t b) {9195 return vmax_s32(a, b);9196}9197 9198// CHECK-LABEL: define <8 x i8> @test_vmax_u8(9199// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {9200// CHECK-NEXT: [[ENTRY:.*:]]9201// CHECK-NEXT: [[VMAX_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])9202// CHECK-NEXT: ret <8 x i8> [[VMAX_V_I]]9203//9204uint8x8_t test_vmax_u8(uint8x8_t a, uint8x8_t b) {9205 return vmax_u8(a, b);9206}9207 9208// CHECK-LABEL: define <4 x i16> @test_vmax_u16(9209// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {9210// CHECK-NEXT: [[ENTRY:.*:]]9211// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>9212// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>9213// CHECK-NEXT: [[VMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9214// CHECK-NEXT: [[VMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>9215// CHECK-NEXT: [[VMAX_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> [[VMAX_V_I]], <4 x i16> [[VMAX_V1_I]])9216// CHECK-NEXT: [[VMAX_V3_I:%.*]] = bitcast <4 x i16> [[VMAX_V2_I]] to <8 x i8>9217// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VMAX_V3_I]] to <4 x i16>9218// CHECK-NEXT: ret <4 x i16> [[TMP2]]9219//9220uint16x4_t test_vmax_u16(uint16x4_t a, uint16x4_t b) {9221 return vmax_u16(a, b);9222}9223 9224// CHECK-LABEL: define <2 x i32> @test_vmax_u32(9225// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {9226// CHECK-NEXT: [[ENTRY:.*:]]9227// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>9228// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>9229// CHECK-NEXT: [[VMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9230// CHECK-NEXT: [[VMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>9231// CHECK-NEXT: [[VMAX_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> [[VMAX_V_I]], <2 x i32> [[VMAX_V1_I]])9232// CHECK-NEXT: [[VMAX_V3_I:%.*]] = bitcast <2 x i32> [[VMAX_V2_I]] to <8 x i8>9233// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VMAX_V3_I]] to <2 x i32>9234// CHECK-NEXT: ret <2 x i32> [[TMP2]]9235//9236uint32x2_t test_vmax_u32(uint32x2_t a, uint32x2_t b) {9237 return vmax_u32(a, b);9238}9239 9240// CHECK-LABEL: define <2 x float> @test_vmax_f32(9241// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {9242// CHECK-NEXT: [[ENTRY:.*:]]9243// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>9244// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>9245// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>9246// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>9247// CHECK-NEXT: [[VMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>9248// CHECK-NEXT: [[VMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>9249// CHECK-NEXT: [[VMAX_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> [[VMAX_V_I]], <2 x float> [[VMAX_V1_I]])9250// CHECK-NEXT: [[VMAX_V3_I:%.*]] = bitcast <2 x float> [[VMAX_V2_I]] to <8 x i8>9251// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VMAX_V3_I]] to <2 x i32>9252// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>9253// CHECK-NEXT: ret <2 x float> [[TMP5]]9254//9255float32x2_t test_vmax_f32(float32x2_t a, float32x2_t b) {9256 return vmax_f32(a, b);9257}9258 9259// CHECK-LABEL: define <16 x i8> @test_vmaxq_s8(9260// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {9261// CHECK-NEXT: [[ENTRY:.*:]]9262// CHECK-NEXT: [[VMAXQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])9263// CHECK-NEXT: ret <16 x i8> [[VMAXQ_V_I]]9264//9265int8x16_t test_vmaxq_s8(int8x16_t a, int8x16_t b) {9266 return vmaxq_s8(a, b);9267}9268 9269// CHECK-LABEL: define <8 x i16> @test_vmaxq_s16(9270// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {9271// CHECK-NEXT: [[ENTRY:.*:]]9272// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>9273// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>9274// CHECK-NEXT: [[VMAXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>9275// CHECK-NEXT: [[VMAXQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>9276// CHECK-NEXT: [[VMAXQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> [[VMAXQ_V_I]], <8 x i16> [[VMAXQ_V1_I]])9277// CHECK-NEXT: [[VMAXQ_V3_I:%.*]] = bitcast <8 x i16> [[VMAXQ_V2_I]] to <16 x i8>9278// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VMAXQ_V3_I]] to <8 x i16>9279// CHECK-NEXT: ret <8 x i16> [[TMP2]]9280//9281int16x8_t test_vmaxq_s16(int16x8_t a, int16x8_t b) {9282 return vmaxq_s16(a, b);9283}9284 9285// CHECK-LABEL: define <4 x i32> @test_vmaxq_s32(9286// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {9287// CHECK-NEXT: [[ENTRY:.*:]]9288// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>9289// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>9290// CHECK-NEXT: [[VMAXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>9291// CHECK-NEXT: [[VMAXQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>9292// CHECK-NEXT: [[VMAXQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> [[VMAXQ_V_I]], <4 x i32> [[VMAXQ_V1_I]])9293// CHECK-NEXT: [[VMAXQ_V3_I:%.*]] = bitcast <4 x i32> [[VMAXQ_V2_I]] to <16 x i8>9294// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VMAXQ_V3_I]] to <4 x i32>9295// CHECK-NEXT: ret <4 x i32> [[TMP2]]9296//9297int32x4_t test_vmaxq_s32(int32x4_t a, int32x4_t b) {9298 return vmaxq_s32(a, b);9299}9300 9301// CHECK-LABEL: define <16 x i8> @test_vmaxq_u8(9302// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {9303// CHECK-NEXT: [[ENTRY:.*:]]9304// CHECK-NEXT: [[VMAXQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])9305// CHECK-NEXT: ret <16 x i8> [[VMAXQ_V_I]]9306//9307uint8x16_t test_vmaxq_u8(uint8x16_t a, uint8x16_t b) {9308 return vmaxq_u8(a, b);9309}9310 9311// CHECK-LABEL: define <8 x i16> @test_vmaxq_u16(9312// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {9313// CHECK-NEXT: [[ENTRY:.*:]]9314// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>9315// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>9316// CHECK-NEXT: [[VMAXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>9317// CHECK-NEXT: [[VMAXQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>9318// CHECK-NEXT: [[VMAXQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> [[VMAXQ_V_I]], <8 x i16> [[VMAXQ_V1_I]])9319// CHECK-NEXT: [[VMAXQ_V3_I:%.*]] = bitcast <8 x i16> [[VMAXQ_V2_I]] to <16 x i8>9320// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VMAXQ_V3_I]] to <8 x i16>9321// CHECK-NEXT: ret <8 x i16> [[TMP2]]9322//9323uint16x8_t test_vmaxq_u16(uint16x8_t a, uint16x8_t b) {9324 return vmaxq_u16(a, b);9325}9326 9327// CHECK-LABEL: define <4 x i32> @test_vmaxq_u32(9328// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {9329// CHECK-NEXT: [[ENTRY:.*:]]9330// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>9331// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>9332// CHECK-NEXT: [[VMAXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>9333// CHECK-NEXT: [[VMAXQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>9334// CHECK-NEXT: [[VMAXQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> [[VMAXQ_V_I]], <4 x i32> [[VMAXQ_V1_I]])9335// CHECK-NEXT: [[VMAXQ_V3_I:%.*]] = bitcast <4 x i32> [[VMAXQ_V2_I]] to <16 x i8>9336// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VMAXQ_V3_I]] to <4 x i32>9337// CHECK-NEXT: ret <4 x i32> [[TMP2]]9338//9339uint32x4_t test_vmaxq_u32(uint32x4_t a, uint32x4_t b) {9340 return vmaxq_u32(a, b);9341}9342 9343// CHECK-LABEL: define <4 x float> @test_vmaxq_f32(9344// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {9345// CHECK-NEXT: [[ENTRY:.*:]]9346// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>9347// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>9348// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>9349// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>9350// CHECK-NEXT: [[VMAXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>9351// CHECK-NEXT: [[VMAXQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>9352// CHECK-NEXT: [[VMAXQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> [[VMAXQ_V_I]], <4 x float> [[VMAXQ_V1_I]])9353// CHECK-NEXT: [[VMAXQ_V3_I:%.*]] = bitcast <4 x float> [[VMAXQ_V2_I]] to <16 x i8>9354// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[VMAXQ_V3_I]] to <4 x i32>9355// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>9356// CHECK-NEXT: ret <4 x float> [[TMP5]]9357//9358float32x4_t test_vmaxq_f32(float32x4_t a, float32x4_t b) {9359 return vmaxq_f32(a, b);9360}9361 9362// CHECK-LABEL: define <8 x i8> @test_vmin_s8(9363// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {9364// CHECK-NEXT: [[ENTRY:.*:]]9365// CHECK-NEXT: [[VMIN_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])9366// CHECK-NEXT: ret <8 x i8> [[VMIN_V_I]]9367//9368int8x8_t test_vmin_s8(int8x8_t a, int8x8_t b) {9369 return vmin_s8(a, b);9370}9371 9372// CHECK-LABEL: define <4 x i16> @test_vmin_s16(9373// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {9374// CHECK-NEXT: [[ENTRY:.*:]]9375// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>9376// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>9377// CHECK-NEXT: [[VMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9378// CHECK-NEXT: [[VMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>9379// CHECK-NEXT: [[VMIN_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> [[VMIN_V_I]], <4 x i16> [[VMIN_V1_I]])9380// CHECK-NEXT: [[VMIN_V3_I:%.*]] = bitcast <4 x i16> [[VMIN_V2_I]] to <8 x i8>9381// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VMIN_V3_I]] to <4 x i16>9382// CHECK-NEXT: ret <4 x i16> [[TMP2]]9383//9384int16x4_t test_vmin_s16(int16x4_t a, int16x4_t b) {9385 return vmin_s16(a, b);9386}9387 9388// CHECK-LABEL: define <2 x i32> @test_vmin_s32(9389// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {9390// CHECK-NEXT: [[ENTRY:.*:]]9391// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>9392// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>9393// CHECK-NEXT: [[VMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9394// CHECK-NEXT: [[VMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>9395// CHECK-NEXT: [[VMIN_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> [[VMIN_V_I]], <2 x i32> [[VMIN_V1_I]])9396// CHECK-NEXT: [[VMIN_V3_I:%.*]] = bitcast <2 x i32> [[VMIN_V2_I]] to <8 x i8>9397// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VMIN_V3_I]] to <2 x i32>9398// CHECK-NEXT: ret <2 x i32> [[TMP2]]9399//9400int32x2_t test_vmin_s32(int32x2_t a, int32x2_t b) {9401 return vmin_s32(a, b);9402}9403 9404// CHECK-LABEL: define <8 x i8> @test_vmin_u8(9405// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {9406// CHECK-NEXT: [[ENTRY:.*:]]9407// CHECK-NEXT: [[VMIN_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])9408// CHECK-NEXT: ret <8 x i8> [[VMIN_V_I]]9409//9410uint8x8_t test_vmin_u8(uint8x8_t a, uint8x8_t b) {9411 return vmin_u8(a, b);9412}9413 9414// CHECK-LABEL: define <4 x i16> @test_vmin_u16(9415// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {9416// CHECK-NEXT: [[ENTRY:.*:]]9417// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>9418// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>9419// CHECK-NEXT: [[VMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9420// CHECK-NEXT: [[VMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>9421// CHECK-NEXT: [[VMIN_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> [[VMIN_V_I]], <4 x i16> [[VMIN_V1_I]])9422// CHECK-NEXT: [[VMIN_V3_I:%.*]] = bitcast <4 x i16> [[VMIN_V2_I]] to <8 x i8>9423// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VMIN_V3_I]] to <4 x i16>9424// CHECK-NEXT: ret <4 x i16> [[TMP2]]9425//9426uint16x4_t test_vmin_u16(uint16x4_t a, uint16x4_t b) {9427 return vmin_u16(a, b);9428}9429 9430// CHECK-LABEL: define <2 x i32> @test_vmin_u32(9431// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {9432// CHECK-NEXT: [[ENTRY:.*:]]9433// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>9434// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>9435// CHECK-NEXT: [[VMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9436// CHECK-NEXT: [[VMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>9437// CHECK-NEXT: [[VMIN_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> [[VMIN_V_I]], <2 x i32> [[VMIN_V1_I]])9438// CHECK-NEXT: [[VMIN_V3_I:%.*]] = bitcast <2 x i32> [[VMIN_V2_I]] to <8 x i8>9439// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VMIN_V3_I]] to <2 x i32>9440// CHECK-NEXT: ret <2 x i32> [[TMP2]]9441//9442uint32x2_t test_vmin_u32(uint32x2_t a, uint32x2_t b) {9443 return vmin_u32(a, b);9444}9445 9446// CHECK-LABEL: define <2 x float> @test_vmin_f32(9447// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {9448// CHECK-NEXT: [[ENTRY:.*:]]9449// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>9450// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>9451// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>9452// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>9453// CHECK-NEXT: [[VMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>9454// CHECK-NEXT: [[VMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>9455// CHECK-NEXT: [[VMIN_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> [[VMIN_V_I]], <2 x float> [[VMIN_V1_I]])9456// CHECK-NEXT: [[VMIN_V3_I:%.*]] = bitcast <2 x float> [[VMIN_V2_I]] to <8 x i8>9457// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VMIN_V3_I]] to <2 x i32>9458// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>9459// CHECK-NEXT: ret <2 x float> [[TMP5]]9460//9461float32x2_t test_vmin_f32(float32x2_t a, float32x2_t b) {9462 return vmin_f32(a, b);9463}9464 9465// CHECK-LABEL: define <16 x i8> @test_vminq_s8(9466// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {9467// CHECK-NEXT: [[ENTRY:.*:]]9468// CHECK-NEXT: [[VMINQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])9469// CHECK-NEXT: ret <16 x i8> [[VMINQ_V_I]]9470//9471int8x16_t test_vminq_s8(int8x16_t a, int8x16_t b) {9472 return vminq_s8(a, b);9473}9474 9475// CHECK-LABEL: define <8 x i16> @test_vminq_s16(9476// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {9477// CHECK-NEXT: [[ENTRY:.*:]]9478// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>9479// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>9480// CHECK-NEXT: [[VMINQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>9481// CHECK-NEXT: [[VMINQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>9482// CHECK-NEXT: [[VMINQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> [[VMINQ_V_I]], <8 x i16> [[VMINQ_V1_I]])9483// CHECK-NEXT: [[VMINQ_V3_I:%.*]] = bitcast <8 x i16> [[VMINQ_V2_I]] to <16 x i8>9484// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VMINQ_V3_I]] to <8 x i16>9485// CHECK-NEXT: ret <8 x i16> [[TMP2]]9486//9487int16x8_t test_vminq_s16(int16x8_t a, int16x8_t b) {9488 return vminq_s16(a, b);9489}9490 9491// CHECK-LABEL: define <4 x i32> @test_vminq_s32(9492// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {9493// CHECK-NEXT: [[ENTRY:.*:]]9494// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>9495// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>9496// CHECK-NEXT: [[VMINQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>9497// CHECK-NEXT: [[VMINQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>9498// CHECK-NEXT: [[VMINQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> [[VMINQ_V_I]], <4 x i32> [[VMINQ_V1_I]])9499// CHECK-NEXT: [[VMINQ_V3_I:%.*]] = bitcast <4 x i32> [[VMINQ_V2_I]] to <16 x i8>9500// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VMINQ_V3_I]] to <4 x i32>9501// CHECK-NEXT: ret <4 x i32> [[TMP2]]9502//9503int32x4_t test_vminq_s32(int32x4_t a, int32x4_t b) {9504 return vminq_s32(a, b);9505}9506 9507// CHECK-LABEL: define <16 x i8> @test_vminq_u8(9508// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {9509// CHECK-NEXT: [[ENTRY:.*:]]9510// CHECK-NEXT: [[VMINQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])9511// CHECK-NEXT: ret <16 x i8> [[VMINQ_V_I]]9512//9513uint8x16_t test_vminq_u8(uint8x16_t a, uint8x16_t b) {9514 return vminq_u8(a, b);9515}9516 9517// CHECK-LABEL: define <8 x i16> @test_vminq_u16(9518// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {9519// CHECK-NEXT: [[ENTRY:.*:]]9520// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>9521// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>9522// CHECK-NEXT: [[VMINQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>9523// CHECK-NEXT: [[VMINQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>9524// CHECK-NEXT: [[VMINQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> [[VMINQ_V_I]], <8 x i16> [[VMINQ_V1_I]])9525// CHECK-NEXT: [[VMINQ_V3_I:%.*]] = bitcast <8 x i16> [[VMINQ_V2_I]] to <16 x i8>9526// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VMINQ_V3_I]] to <8 x i16>9527// CHECK-NEXT: ret <8 x i16> [[TMP2]]9528//9529uint16x8_t test_vminq_u16(uint16x8_t a, uint16x8_t b) {9530 return vminq_u16(a, b);9531}9532 9533// CHECK-LABEL: define <4 x i32> @test_vminq_u32(9534// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {9535// CHECK-NEXT: [[ENTRY:.*:]]9536// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>9537// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>9538// CHECK-NEXT: [[VMINQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>9539// CHECK-NEXT: [[VMINQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>9540// CHECK-NEXT: [[VMINQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> [[VMINQ_V_I]], <4 x i32> [[VMINQ_V1_I]])9541// CHECK-NEXT: [[VMINQ_V3_I:%.*]] = bitcast <4 x i32> [[VMINQ_V2_I]] to <16 x i8>9542// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VMINQ_V3_I]] to <4 x i32>9543// CHECK-NEXT: ret <4 x i32> [[TMP2]]9544//9545uint32x4_t test_vminq_u32(uint32x4_t a, uint32x4_t b) {9546 return vminq_u32(a, b);9547}9548 9549// CHECK-LABEL: define <4 x float> @test_vminq_f32(9550// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {9551// CHECK-NEXT: [[ENTRY:.*:]]9552// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>9553// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>9554// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>9555// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>9556// CHECK-NEXT: [[VMINQ_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>9557// CHECK-NEXT: [[VMINQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>9558// CHECK-NEXT: [[VMINQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> [[VMINQ_V_I]], <4 x float> [[VMINQ_V1_I]])9559// CHECK-NEXT: [[VMINQ_V3_I:%.*]] = bitcast <4 x float> [[VMINQ_V2_I]] to <16 x i8>9560// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[VMINQ_V3_I]] to <4 x i32>9561// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>9562// CHECK-NEXT: ret <4 x float> [[TMP5]]9563//9564float32x4_t test_vminq_f32(float32x4_t a, float32x4_t b) {9565 return vminq_f32(a, b);9566}9567 9568// CHECK-LABEL: define <8 x i8> @test_vmla_s8(9569// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {9570// CHECK-NEXT: [[ENTRY:.*:]]9571// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i8> [[B]], [[C]]9572// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[MUL_I]]9573// CHECK-NEXT: ret <8 x i8> [[ADD_I]]9574//9575int8x8_t test_vmla_s8(int8x8_t a, int8x8_t b, int8x8_t c) {9576 return vmla_s8(a, b, c);9577}9578 9579// CHECK-LABEL: define <4 x i16> @test_vmla_s16(9580// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {9581// CHECK-NEXT: [[ENTRY:.*:]]9582// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[B]], [[C]]9583// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[MUL_I]]9584// CHECK-NEXT: ret <4 x i16> [[ADD_I]]9585//9586int16x4_t test_vmla_s16(int16x4_t a, int16x4_t b, int16x4_t c) {9587 return vmla_s16(a, b, c);9588}9589 9590// CHECK-LABEL: define <2 x i32> @test_vmla_s32(9591// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {9592// CHECK-NEXT: [[ENTRY:.*:]]9593// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[B]], [[C]]9594// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[MUL_I]]9595// CHECK-NEXT: ret <2 x i32> [[ADD_I]]9596//9597int32x2_t test_vmla_s32(int32x2_t a, int32x2_t b, int32x2_t c) {9598 return vmla_s32(a, b, c);9599}9600 9601// CHECK-LABEL: define <2 x float> @test_vmla_f32(9602// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[C:%.*]]) #[[ATTR0]] {9603// CHECK-NEXT: [[ENTRY:.*:]]9604// CHECK-NEXT: [[MUL_I:%.*]] = fmul <2 x float> [[B]], [[C]]9605// CHECK-NEXT: [[ADD_I:%.*]] = fadd <2 x float> [[A]], [[MUL_I]]9606// CHECK-NEXT: ret <2 x float> [[ADD_I]]9607//9608float32x2_t test_vmla_f32(float32x2_t a, float32x2_t b, float32x2_t c) {9609 return vmla_f32(a, b, c);9610}9611 9612// CHECK-LABEL: define <8 x i8> @test_vmla_u8(9613// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {9614// CHECK-NEXT: [[ENTRY:.*:]]9615// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i8> [[B]], [[C]]9616// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[MUL_I]]9617// CHECK-NEXT: ret <8 x i8> [[ADD_I]]9618//9619uint8x8_t test_vmla_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c) {9620 return vmla_u8(a, b, c);9621}9622 9623// CHECK-LABEL: define <4 x i16> @test_vmla_u16(9624// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {9625// CHECK-NEXT: [[ENTRY:.*:]]9626// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[B]], [[C]]9627// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[MUL_I]]9628// CHECK-NEXT: ret <4 x i16> [[ADD_I]]9629//9630uint16x4_t test_vmla_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c) {9631 return vmla_u16(a, b, c);9632}9633 9634// CHECK-LABEL: define <2 x i32> @test_vmla_u32(9635// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {9636// CHECK-NEXT: [[ENTRY:.*:]]9637// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[B]], [[C]]9638// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[MUL_I]]9639// CHECK-NEXT: ret <2 x i32> [[ADD_I]]9640//9641uint32x2_t test_vmla_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c) {9642 return vmla_u32(a, b, c);9643}9644 9645// CHECK-LABEL: define <16 x i8> @test_vmlaq_s8(9646// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]], <16 x i8> noundef [[C:%.*]]) #[[ATTR0]] {9647// CHECK-NEXT: [[ENTRY:.*:]]9648// CHECK-NEXT: [[MUL_I:%.*]] = mul <16 x i8> [[B]], [[C]]9649// CHECK-NEXT: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[MUL_I]]9650// CHECK-NEXT: ret <16 x i8> [[ADD_I]]9651//9652int8x16_t test_vmlaq_s8(int8x16_t a, int8x16_t b, int8x16_t c) {9653 return vmlaq_s8(a, b, c);9654}9655 9656// CHECK-LABEL: define <8 x i16> @test_vmlaq_s16(9657// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <8 x i16> noundef [[C:%.*]]) #[[ATTR0]] {9658// CHECK-NEXT: [[ENTRY:.*:]]9659// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[B]], [[C]]9660// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[MUL_I]]9661// CHECK-NEXT: ret <8 x i16> [[ADD_I]]9662//9663int16x8_t test_vmlaq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {9664 return vmlaq_s16(a, b, c);9665}9666 9667// CHECK-LABEL: define <4 x i32> @test_vmlaq_s32(9668// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <4 x i32> noundef [[C:%.*]]) #[[ATTR0]] {9669// CHECK-NEXT: [[ENTRY:.*:]]9670// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[B]], [[C]]9671// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[MUL_I]]9672// CHECK-NEXT: ret <4 x i32> [[ADD_I]]9673//9674int32x4_t test_vmlaq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {9675 return vmlaq_s32(a, b, c);9676}9677 9678// CHECK-LABEL: define <4 x float> @test_vmlaq_f32(9679// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]]) #[[ATTR0]] {9680// CHECK-NEXT: [[ENTRY:.*:]]9681// CHECK-NEXT: [[MUL_I:%.*]] = fmul <4 x float> [[B]], [[C]]9682// CHECK-NEXT: [[ADD_I:%.*]] = fadd <4 x float> [[A]], [[MUL_I]]9683// CHECK-NEXT: ret <4 x float> [[ADD_I]]9684//9685float32x4_t test_vmlaq_f32(float32x4_t a, float32x4_t b, float32x4_t c) {9686 return vmlaq_f32(a, b, c);9687}9688 9689// CHECK-LABEL: define <16 x i8> @test_vmlaq_u8(9690// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]], <16 x i8> noundef [[C:%.*]]) #[[ATTR0]] {9691// CHECK-NEXT: [[ENTRY:.*:]]9692// CHECK-NEXT: [[MUL_I:%.*]] = mul <16 x i8> [[B]], [[C]]9693// CHECK-NEXT: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[MUL_I]]9694// CHECK-NEXT: ret <16 x i8> [[ADD_I]]9695//9696uint8x16_t test_vmlaq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c) {9697 return vmlaq_u8(a, b, c);9698}9699 9700// CHECK-LABEL: define <8 x i16> @test_vmlaq_u16(9701// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <8 x i16> noundef [[C:%.*]]) #[[ATTR0]] {9702// CHECK-NEXT: [[ENTRY:.*:]]9703// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[B]], [[C]]9704// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[MUL_I]]9705// CHECK-NEXT: ret <8 x i16> [[ADD_I]]9706//9707uint16x8_t test_vmlaq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c) {9708 return vmlaq_u16(a, b, c);9709}9710 9711// CHECK-LABEL: define <4 x i32> @test_vmlaq_u32(9712// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <4 x i32> noundef [[C:%.*]]) #[[ATTR0]] {9713// CHECK-NEXT: [[ENTRY:.*:]]9714// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[B]], [[C]]9715// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[MUL_I]]9716// CHECK-NEXT: ret <4 x i32> [[ADD_I]]9717//9718uint32x4_t test_vmlaq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c) {9719 return vmlaq_u32(a, b, c);9720}9721 9722// CHECK-LABEL: define <8 x i16> @test_vmlal_s8(9723// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {9724// CHECK-NEXT: [[ENTRY:.*:]]9725// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> [[B]], <8 x i8> [[C]])9726// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[VMULL_I]]9727// CHECK-NEXT: ret <8 x i16> [[ADD_I]]9728//9729int16x8_t test_vmlal_s8(int16x8_t a, int8x8_t b, int8x8_t c) {9730 return vmlal_s8(a, b, c);9731}9732 9733// CHECK-LABEL: define <4 x i32> @test_vmlal_s16(9734// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {9735// CHECK-NEXT: [[ENTRY:.*:]]9736// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>9737// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>9738// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9739// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>9740// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])9741// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[VMULL2_I]]9742// CHECK-NEXT: ret <4 x i32> [[ADD_I]]9743//9744int32x4_t test_vmlal_s16(int32x4_t a, int16x4_t b, int16x4_t c) {9745 return vmlal_s16(a, b, c);9746}9747 9748// CHECK-LABEL: define <2 x i64> @test_vmlal_s32(9749// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {9750// CHECK-NEXT: [[ENTRY:.*:]]9751// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>9752// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>9753// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9754// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>9755// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])9756// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[VMULL2_I]]9757// CHECK-NEXT: ret <2 x i64> [[ADD_I]]9758//9759int64x2_t test_vmlal_s32(int64x2_t a, int32x2_t b, int32x2_t c) {9760 return vmlal_s32(a, b, c);9761}9762 9763// CHECK-LABEL: define <8 x i16> @test_vmlal_u8(9764// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {9765// CHECK-NEXT: [[ENTRY:.*:]]9766// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> [[B]], <8 x i8> [[C]])9767// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[VMULL_I]]9768// CHECK-NEXT: ret <8 x i16> [[ADD_I]]9769//9770uint16x8_t test_vmlal_u8(uint16x8_t a, uint8x8_t b, uint8x8_t c) {9771 return vmlal_u8(a, b, c);9772}9773 9774// CHECK-LABEL: define <4 x i32> @test_vmlal_u16(9775// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {9776// CHECK-NEXT: [[ENTRY:.*:]]9777// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>9778// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>9779// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9780// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>9781// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])9782// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[VMULL2_I]]9783// CHECK-NEXT: ret <4 x i32> [[ADD_I]]9784//9785uint32x4_t test_vmlal_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c) {9786 return vmlal_u16(a, b, c);9787}9788 9789// CHECK-LABEL: define <2 x i64> @test_vmlal_u32(9790// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {9791// CHECK-NEXT: [[ENTRY:.*:]]9792// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>9793// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>9794// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9795// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>9796// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])9797// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[VMULL2_I]]9798// CHECK-NEXT: ret <2 x i64> [[ADD_I]]9799//9800uint64x2_t test_vmlal_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c) {9801 return vmlal_u32(a, b, c);9802}9803 9804// CHECK-LABEL: define <4 x i32> @test_vmlal_lane_s16(9805// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {9806// CHECK-NEXT: [[ENTRY:.*:]]9807// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>9808// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9809// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>9810// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>9811// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>9812// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>9813// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>9814// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])9815// CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[A]], [[VMULL2_I]]9816// CHECK-NEXT: ret <4 x i32> [[ADD]]9817//9818int32x4_t test_vmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t c) {9819 return vmlal_lane_s16(a, b, c, 3);9820}9821 9822// CHECK-LABEL: define <2 x i64> @test_vmlal_lane_s32(9823// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {9824// CHECK-NEXT: [[ENTRY:.*:]]9825// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>9826// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9827// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>9828// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>9829// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>9830// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>9831// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>9832// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])9833// CHECK-NEXT: [[ADD:%.*]] = add <2 x i64> [[A]], [[VMULL2_I]]9834// CHECK-NEXT: ret <2 x i64> [[ADD]]9835//9836int64x2_t test_vmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t c) {9837 return vmlal_lane_s32(a, b, c, 1);9838}9839 9840// CHECK-LABEL: define <4 x i32> @test_vmlal_lane_u16(9841// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {9842// CHECK-NEXT: [[ENTRY:.*:]]9843// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>9844// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9845// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>9846// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>9847// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>9848// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>9849// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>9850// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])9851// CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[A]], [[VMULL2_I]]9852// CHECK-NEXT: ret <4 x i32> [[ADD]]9853//9854uint32x4_t test_vmlal_lane_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c) {9855 return vmlal_lane_u16(a, b, c, 3);9856}9857 9858// CHECK-LABEL: define <2 x i64> @test_vmlal_lane_u32(9859// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {9860// CHECK-NEXT: [[ENTRY:.*:]]9861// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>9862// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9863// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>9864// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>9865// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>9866// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>9867// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>9868// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])9869// CHECK-NEXT: [[ADD:%.*]] = add <2 x i64> [[A]], [[VMULL2_I]]9870// CHECK-NEXT: ret <2 x i64> [[ADD]]9871//9872uint64x2_t test_vmlal_lane_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c) {9873 return vmlal_lane_u32(a, b, c, 1);9874}9875 9876// CHECK-LABEL: define <4 x i32> @test_vmlal_n_s16(9877// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], i16 noundef signext [[C:%.*]]) #[[ATTR0]] {9878// CHECK-NEXT: [[ENTRY:.*:]]9879// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i32 09880// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[C]], i32 19881// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[C]], i32 29882// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[C]], i32 39883// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>9884// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>9885// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9886// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>9887// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])9888// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[VMULL2_I_I]]9889// CHECK-NEXT: ret <4 x i32> [[ADD_I]]9890//9891int32x4_t test_vmlal_n_s16(int32x4_t a, int16x4_t b, int16_t c) {9892 return vmlal_n_s16(a, b, c);9893}9894 9895// CHECK-LABEL: define <2 x i64> @test_vmlal_n_s32(9896// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {9897// CHECK-NEXT: [[ENTRY:.*:]]9898// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[C]], i32 09899// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[C]], i32 19900// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>9901// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>9902// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9903// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>9904// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])9905// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[VMULL2_I_I]]9906// CHECK-NEXT: ret <2 x i64> [[ADD_I]]9907//9908int64x2_t test_vmlal_n_s32(int64x2_t a, int32x2_t b, int32_t c) {9909 return vmlal_n_s32(a, b, c);9910}9911 9912// CHECK-LABEL: define <4 x i32> @test_vmlal_n_u16(9913// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], i16 noundef zeroext [[C:%.*]]) #[[ATTR0]] {9914// CHECK-NEXT: [[ENTRY:.*:]]9915// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i32 09916// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[C]], i32 19917// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[C]], i32 29918// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[C]], i32 39919// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>9920// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>9921// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9922// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>9923// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])9924// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[VMULL2_I_I]]9925// CHECK-NEXT: ret <4 x i32> [[ADD_I]]9926//9927uint32x4_t test_vmlal_n_u16(uint32x4_t a, uint16x4_t b, uint16_t c) {9928 return vmlal_n_u16(a, b, c);9929}9930 9931// CHECK-LABEL: define <2 x i64> @test_vmlal_n_u32(9932// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {9933// CHECK-NEXT: [[ENTRY:.*:]]9934// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[C]], i32 09935// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[C]], i32 19936// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>9937// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>9938// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9939// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>9940// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])9941// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[VMULL2_I_I]]9942// CHECK-NEXT: ret <2 x i64> [[ADD_I]]9943//9944uint64x2_t test_vmlal_n_u32(uint64x2_t a, uint32x2_t b, uint32_t c) {9945 return vmlal_n_u32(a, b, c);9946}9947 9948// CHECK-LABEL: define <4 x i16> @test_vmla_lane_s16(9949// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {9950// CHECK-NEXT: [[ENTRY:.*:]]9951// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>9952// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9953// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>9954// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i16> [[B]], [[LANE]]9955// CHECK-NEXT: [[ADD:%.*]] = add <4 x i16> [[A]], [[MUL]]9956// CHECK-NEXT: ret <4 x i16> [[ADD]]9957//9958int16x4_t test_vmla_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) {9959 return vmla_lane_s16(a, b, c, 3);9960}9961 9962// CHECK-LABEL: define <2 x i32> @test_vmla_lane_s32(9963// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {9964// CHECK-NEXT: [[ENTRY:.*:]]9965// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>9966// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9967// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>9968// CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[B]], [[LANE]]9969// CHECK-NEXT: [[ADD:%.*]] = add <2 x i32> [[A]], [[MUL]]9970// CHECK-NEXT: ret <2 x i32> [[ADD]]9971//9972int32x2_t test_vmla_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) {9973 return vmla_lane_s32(a, b, c, 1);9974}9975 9976// CHECK-LABEL: define <4 x i16> @test_vmla_lane_u16(9977// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {9978// CHECK-NEXT: [[ENTRY:.*:]]9979// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>9980// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>9981// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>9982// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i16> [[B]], [[LANE]]9983// CHECK-NEXT: [[ADD:%.*]] = add <4 x i16> [[A]], [[MUL]]9984// CHECK-NEXT: ret <4 x i16> [[ADD]]9985//9986uint16x4_t test_vmla_lane_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c) {9987 return vmla_lane_u16(a, b, c, 3);9988}9989 9990// CHECK-LABEL: define <2 x i32> @test_vmla_lane_u32(9991// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {9992// CHECK-NEXT: [[ENTRY:.*:]]9993// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>9994// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>9995// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>9996// CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[B]], [[LANE]]9997// CHECK-NEXT: [[ADD:%.*]] = add <2 x i32> [[A]], [[MUL]]9998// CHECK-NEXT: ret <2 x i32> [[ADD]]9999//10000uint32x2_t test_vmla_lane_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c) {10001 return vmla_lane_u32(a, b, c, 1);10002}10003 10004// CHECK-LABEL: define <2 x float> @test_vmla_lane_f32(10005// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[C:%.*]]) #[[ATTR0]] {10006// CHECK-NEXT: [[ENTRY:.*:]]10007// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[C]] to <2 x i32>10008// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>10009// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>10010// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <2 x i32> <i32 1, i32 1>10011// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[B]], [[LANE]]10012// CHECK-NEXT: [[ADD:%.*]] = fadd <2 x float> [[A]], [[MUL]]10013// CHECK-NEXT: ret <2 x float> [[ADD]]10014//10015float32x2_t test_vmla_lane_f32(float32x2_t a, float32x2_t b, float32x2_t c) {10016 return vmla_lane_f32(a, b, c, 1);10017}10018 10019// CHECK-LABEL: define <8 x i16> @test_vmlaq_lane_s16(10020// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10021// CHECK-NEXT: [[ENTRY:.*:]]10022// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>10023// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10024// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>10025// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i16> [[B]], [[LANE]]10026// CHECK-NEXT: [[ADD:%.*]] = add <8 x i16> [[A]], [[MUL]]10027// CHECK-NEXT: ret <8 x i16> [[ADD]]10028//10029int16x8_t test_vmlaq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t c) {10030 return vmlaq_lane_s16(a, b, c, 3);10031}10032 10033// CHECK-LABEL: define <4 x i32> @test_vmlaq_lane_s32(10034// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10035// CHECK-NEXT: [[ENTRY:.*:]]10036// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>10037// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10038// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>10039// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[B]], [[LANE]]10040// CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[A]], [[MUL]]10041// CHECK-NEXT: ret <4 x i32> [[ADD]]10042//10043int32x4_t test_vmlaq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t c) {10044 return vmlaq_lane_s32(a, b, c, 1);10045}10046 10047// CHECK-LABEL: define <8 x i16> @test_vmlaq_lane_u16(10048// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10049// CHECK-NEXT: [[ENTRY:.*:]]10050// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>10051// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10052// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>10053// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i16> [[B]], [[LANE]]10054// CHECK-NEXT: [[ADD:%.*]] = add <8 x i16> [[A]], [[MUL]]10055// CHECK-NEXT: ret <8 x i16> [[ADD]]10056//10057uint16x8_t test_vmlaq_lane_u16(uint16x8_t a, uint16x8_t b, uint16x4_t c) {10058 return vmlaq_lane_u16(a, b, c, 3);10059}10060 10061// CHECK-LABEL: define <4 x i32> @test_vmlaq_lane_u32(10062// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10063// CHECK-NEXT: [[ENTRY:.*:]]10064// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>10065// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10066// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>10067// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[B]], [[LANE]]10068// CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[A]], [[MUL]]10069// CHECK-NEXT: ret <4 x i32> [[ADD]]10070//10071uint32x4_t test_vmlaq_lane_u32(uint32x4_t a, uint32x4_t b, uint32x2_t c) {10072 return vmlaq_lane_u32(a, b, c, 1);10073}10074 10075// CHECK-LABEL: define <4 x float> @test_vmlaq_lane_f32(10076// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <2 x float> noundef [[C:%.*]]) #[[ATTR0]] {10077// CHECK-NEXT: [[ENTRY:.*:]]10078// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[C]] to <2 x i32>10079// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>10080// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>10081// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>10082// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[B]], [[LANE]]10083// CHECK-NEXT: [[ADD:%.*]] = fadd <4 x float> [[A]], [[MUL]]10084// CHECK-NEXT: ret <4 x float> [[ADD]]10085//10086float32x4_t test_vmlaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t c) {10087 return vmlaq_lane_f32(a, b, c, 1);10088}10089 10090// CHECK-LABEL: define <4 x i16> @test_vmla_n_s16(10091// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], i16 noundef signext [[C:%.*]]) #[[ATTR0]] {10092// CHECK-NEXT: [[ENTRY:.*:]]10093// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i32 010094// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[C]], i32 110095// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[C]], i32 210096// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[C]], i32 310097// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[B]], [[VECINIT3_I]]10098// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[MUL_I]]10099// CHECK-NEXT: ret <4 x i16> [[ADD_I]]10100//10101int16x4_t test_vmla_n_s16(int16x4_t a, int16x4_t b, int16_t c) {10102 return vmla_n_s16(a, b, c);10103}10104 10105// CHECK-LABEL: define <2 x i32> @test_vmla_n_s32(10106// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {10107// CHECK-NEXT: [[ENTRY:.*:]]10108// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[C]], i32 010109// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[C]], i32 110110// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[B]], [[VECINIT1_I]]10111// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[MUL_I]]10112// CHECK-NEXT: ret <2 x i32> [[ADD_I]]10113//10114int32x2_t test_vmla_n_s32(int32x2_t a, int32x2_t b, int32_t c) {10115 return vmla_n_s32(a, b, c);10116}10117 10118// CHECK-LABEL: define <4 x i16> @test_vmla_n_u16(10119// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], i16 noundef zeroext [[C:%.*]]) #[[ATTR0]] {10120// CHECK-NEXT: [[ENTRY:.*:]]10121// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i32 010122// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[C]], i32 110123// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[C]], i32 210124// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[C]], i32 310125// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[B]], [[VECINIT3_I]]10126// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[MUL_I]]10127// CHECK-NEXT: ret <4 x i16> [[ADD_I]]10128//10129uint16x4_t test_vmla_n_u16(uint16x4_t a, uint16x4_t b, uint16_t c) {10130 return vmla_n_u16(a, b, c);10131}10132 10133// CHECK-LABEL: define <2 x i32> @test_vmla_n_u32(10134// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {10135// CHECK-NEXT: [[ENTRY:.*:]]10136// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[C]], i32 010137// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[C]], i32 110138// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[B]], [[VECINIT1_I]]10139// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[MUL_I]]10140// CHECK-NEXT: ret <2 x i32> [[ADD_I]]10141//10142uint32x2_t test_vmla_n_u32(uint32x2_t a, uint32x2_t b, uint32_t c) {10143 return vmla_n_u32(a, b, c);10144}10145 10146// CHECK-LABEL: define <2 x float> @test_vmla_n_f32(10147// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], float noundef [[C:%.*]]) #[[ATTR0]] {10148// CHECK-NEXT: [[ENTRY:.*:]]10149// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x float> poison, float [[C]], i32 010150// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float [[C]], i32 110151// CHECK-NEXT: [[MUL_I:%.*]] = fmul <2 x float> [[B]], [[VECINIT1_I]]10152// CHECK-NEXT: [[ADD_I:%.*]] = fadd <2 x float> [[A]], [[MUL_I]]10153// CHECK-NEXT: ret <2 x float> [[ADD_I]]10154//10155float32x2_t test_vmla_n_f32(float32x2_t a, float32x2_t b, float32_t c) {10156 return vmla_n_f32(a, b, c);10157}10158 10159// CHECK-LABEL: define <8 x i16> @test_vmlaq_n_s16(10160// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], i16 noundef signext [[C:%.*]]) #[[ATTR0]] {10161// CHECK-NEXT: [[ENTRY:.*:]]10162// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[C]], i32 010163// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[C]], i32 110164// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[C]], i32 210165// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[C]], i32 310166// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[C]], i32 410167// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[C]], i32 510168// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[C]], i32 610169// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[C]], i32 710170// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[B]], [[VECINIT7_I]]10171// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[MUL_I]]10172// CHECK-NEXT: ret <8 x i16> [[ADD_I]]10173//10174int16x8_t test_vmlaq_n_s16(int16x8_t a, int16x8_t b, int16_t c) {10175 return vmlaq_n_s16(a, b, c);10176}10177 10178// CHECK-LABEL: define <4 x i32> @test_vmlaq_n_s32(10179// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {10180// CHECK-NEXT: [[ENTRY:.*:]]10181// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[C]], i32 010182// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[C]], i32 110183// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[C]], i32 210184// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[C]], i32 310185// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[B]], [[VECINIT3_I]]10186// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[MUL_I]]10187// CHECK-NEXT: ret <4 x i32> [[ADD_I]]10188//10189int32x4_t test_vmlaq_n_s32(int32x4_t a, int32x4_t b, int32_t c) {10190 return vmlaq_n_s32(a, b, c);10191}10192 10193// CHECK-LABEL: define <8 x i16> @test_vmlaq_n_u16(10194// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], i16 noundef zeroext [[C:%.*]]) #[[ATTR0]] {10195// CHECK-NEXT: [[ENTRY:.*:]]10196// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[C]], i32 010197// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[C]], i32 110198// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[C]], i32 210199// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[C]], i32 310200// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[C]], i32 410201// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[C]], i32 510202// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[C]], i32 610203// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[C]], i32 710204// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[B]], [[VECINIT7_I]]10205// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[MUL_I]]10206// CHECK-NEXT: ret <8 x i16> [[ADD_I]]10207//10208uint16x8_t test_vmlaq_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c) {10209 return vmlaq_n_u16(a, b, c);10210}10211 10212// CHECK-LABEL: define <4 x i32> @test_vmlaq_n_u32(10213// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {10214// CHECK-NEXT: [[ENTRY:.*:]]10215// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[C]], i32 010216// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[C]], i32 110217// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[C]], i32 210218// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[C]], i32 310219// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[B]], [[VECINIT3_I]]10220// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[MUL_I]]10221// CHECK-NEXT: ret <4 x i32> [[ADD_I]]10222//10223uint32x4_t test_vmlaq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c) {10224 return vmlaq_n_u32(a, b, c);10225}10226 10227// CHECK-LABEL: define <4 x float> @test_vmlaq_n_f32(10228// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], float noundef [[C:%.*]]) #[[ATTR0]] {10229// CHECK-NEXT: [[ENTRY:.*:]]10230// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[C]], i32 010231// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[C]], i32 110232// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[C]], i32 210233// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[C]], i32 310234// CHECK-NEXT: [[MUL_I:%.*]] = fmul <4 x float> [[B]], [[VECINIT3_I]]10235// CHECK-NEXT: [[ADD_I:%.*]] = fadd <4 x float> [[A]], [[MUL_I]]10236// CHECK-NEXT: ret <4 x float> [[ADD_I]]10237//10238float32x4_t test_vmlaq_n_f32(float32x4_t a, float32x4_t b, float32_t c) {10239 return vmlaq_n_f32(a, b, c);10240}10241 10242// CHECK-LABEL: define <8 x i8> @test_vmls_s8(10243// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {10244// CHECK-NEXT: [[ENTRY:.*:]]10245// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i8> [[B]], [[C]]10246// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[A]], [[MUL_I]]10247// CHECK-NEXT: ret <8 x i8> [[SUB_I]]10248//10249int8x8_t test_vmls_s8(int8x8_t a, int8x8_t b, int8x8_t c) {10250 return vmls_s8(a, b, c);10251}10252 10253// CHECK-LABEL: define <4 x i16> @test_vmls_s16(10254// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10255// CHECK-NEXT: [[ENTRY:.*:]]10256// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[B]], [[C]]10257// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[A]], [[MUL_I]]10258// CHECK-NEXT: ret <4 x i16> [[SUB_I]]10259//10260int16x4_t test_vmls_s16(int16x4_t a, int16x4_t b, int16x4_t c) {10261 return vmls_s16(a, b, c);10262}10263 10264// CHECK-LABEL: define <2 x i32> @test_vmls_s32(10265// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10266// CHECK-NEXT: [[ENTRY:.*:]]10267// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[B]], [[C]]10268// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[A]], [[MUL_I]]10269// CHECK-NEXT: ret <2 x i32> [[SUB_I]]10270//10271int32x2_t test_vmls_s32(int32x2_t a, int32x2_t b, int32x2_t c) {10272 return vmls_s32(a, b, c);10273}10274 10275// CHECK-LABEL: define <2 x float> @test_vmls_f32(10276// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[C:%.*]]) #[[ATTR0]] {10277// CHECK-NEXT: [[ENTRY:.*:]]10278// CHECK-NEXT: [[MUL_I:%.*]] = fmul <2 x float> [[B]], [[C]]10279// CHECK-NEXT: [[SUB_I:%.*]] = fsub <2 x float> [[A]], [[MUL_I]]10280// CHECK-NEXT: ret <2 x float> [[SUB_I]]10281//10282float32x2_t test_vmls_f32(float32x2_t a, float32x2_t b, float32x2_t c) {10283 return vmls_f32(a, b, c);10284}10285 10286// CHECK-LABEL: define <8 x i8> @test_vmls_u8(10287// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {10288// CHECK-NEXT: [[ENTRY:.*:]]10289// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i8> [[B]], [[C]]10290// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[A]], [[MUL_I]]10291// CHECK-NEXT: ret <8 x i8> [[SUB_I]]10292//10293uint8x8_t test_vmls_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c) {10294 return vmls_u8(a, b, c);10295}10296 10297// CHECK-LABEL: define <4 x i16> @test_vmls_u16(10298// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10299// CHECK-NEXT: [[ENTRY:.*:]]10300// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[B]], [[C]]10301// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[A]], [[MUL_I]]10302// CHECK-NEXT: ret <4 x i16> [[SUB_I]]10303//10304uint16x4_t test_vmls_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c) {10305 return vmls_u16(a, b, c);10306}10307 10308// CHECK-LABEL: define <2 x i32> @test_vmls_u32(10309// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10310// CHECK-NEXT: [[ENTRY:.*:]]10311// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[B]], [[C]]10312// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[A]], [[MUL_I]]10313// CHECK-NEXT: ret <2 x i32> [[SUB_I]]10314//10315uint32x2_t test_vmls_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c) {10316 return vmls_u32(a, b, c);10317}10318 10319// CHECK-LABEL: define <16 x i8> @test_vmlsq_s8(10320// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]], <16 x i8> noundef [[C:%.*]]) #[[ATTR0]] {10321// CHECK-NEXT: [[ENTRY:.*:]]10322// CHECK-NEXT: [[MUL_I:%.*]] = mul <16 x i8> [[B]], [[C]]10323// CHECK-NEXT: [[SUB_I:%.*]] = sub <16 x i8> [[A]], [[MUL_I]]10324// CHECK-NEXT: ret <16 x i8> [[SUB_I]]10325//10326int8x16_t test_vmlsq_s8(int8x16_t a, int8x16_t b, int8x16_t c) {10327 return vmlsq_s8(a, b, c);10328}10329 10330// CHECK-LABEL: define <8 x i16> @test_vmlsq_s16(10331// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <8 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10332// CHECK-NEXT: [[ENTRY:.*:]]10333// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[B]], [[C]]10334// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i16> [[A]], [[MUL_I]]10335// CHECK-NEXT: ret <8 x i16> [[SUB_I]]10336//10337int16x8_t test_vmlsq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {10338 return vmlsq_s16(a, b, c);10339}10340 10341// CHECK-LABEL: define <4 x i32> @test_vmlsq_s32(10342// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <4 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10343// CHECK-NEXT: [[ENTRY:.*:]]10344// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[B]], [[C]]10345// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> [[A]], [[MUL_I]]10346// CHECK-NEXT: ret <4 x i32> [[SUB_I]]10347//10348int32x4_t test_vmlsq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {10349 return vmlsq_s32(a, b, c);10350}10351 10352// CHECK-LABEL: define <4 x float> @test_vmlsq_f32(10353// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]]) #[[ATTR0]] {10354// CHECK-NEXT: [[ENTRY:.*:]]10355// CHECK-NEXT: [[MUL_I:%.*]] = fmul <4 x float> [[B]], [[C]]10356// CHECK-NEXT: [[SUB_I:%.*]] = fsub <4 x float> [[A]], [[MUL_I]]10357// CHECK-NEXT: ret <4 x float> [[SUB_I]]10358//10359float32x4_t test_vmlsq_f32(float32x4_t a, float32x4_t b, float32x4_t c) {10360 return vmlsq_f32(a, b, c);10361}10362 10363// CHECK-LABEL: define <16 x i8> @test_vmlsq_u8(10364// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]], <16 x i8> noundef [[C:%.*]]) #[[ATTR0]] {10365// CHECK-NEXT: [[ENTRY:.*:]]10366// CHECK-NEXT: [[MUL_I:%.*]] = mul <16 x i8> [[B]], [[C]]10367// CHECK-NEXT: [[SUB_I:%.*]] = sub <16 x i8> [[A]], [[MUL_I]]10368// CHECK-NEXT: ret <16 x i8> [[SUB_I]]10369//10370uint8x16_t test_vmlsq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c) {10371 return vmlsq_u8(a, b, c);10372}10373 10374// CHECK-LABEL: define <8 x i16> @test_vmlsq_u16(10375// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <8 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10376// CHECK-NEXT: [[ENTRY:.*:]]10377// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[B]], [[C]]10378// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i16> [[A]], [[MUL_I]]10379// CHECK-NEXT: ret <8 x i16> [[SUB_I]]10380//10381uint16x8_t test_vmlsq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c) {10382 return vmlsq_u16(a, b, c);10383}10384 10385// CHECK-LABEL: define <4 x i32> @test_vmlsq_u32(10386// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <4 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10387// CHECK-NEXT: [[ENTRY:.*:]]10388// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[B]], [[C]]10389// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> [[A]], [[MUL_I]]10390// CHECK-NEXT: ret <4 x i32> [[SUB_I]]10391//10392uint32x4_t test_vmlsq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c) {10393 return vmlsq_u32(a, b, c);10394}10395 10396// CHECK-LABEL: define <8 x i16> @test_vmlsl_s8(10397// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {10398// CHECK-NEXT: [[ENTRY:.*:]]10399// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> [[B]], <8 x i8> [[C]])10400// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i16> [[A]], [[VMULL_I]]10401// CHECK-NEXT: ret <8 x i16> [[SUB_I]]10402//10403int16x8_t test_vmlsl_s8(int16x8_t a, int8x8_t b, int8x8_t c) {10404 return vmlsl_s8(a, b, c);10405}10406 10407// CHECK-LABEL: define <4 x i32> @test_vmlsl_s16(10408// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10409// CHECK-NEXT: [[ENTRY:.*:]]10410// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>10411// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>10412// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10413// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>10414// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])10415// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> [[A]], [[VMULL2_I_I]]10416// CHECK-NEXT: ret <4 x i32> [[SUB_I]]10417//10418int32x4_t test_vmlsl_s16(int32x4_t a, int16x4_t b, int16x4_t c) {10419 return vmlsl_s16(a, b, c);10420}10421 10422// CHECK-LABEL: define <2 x i64> @test_vmlsl_s32(10423// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10424// CHECK-NEXT: [[ENTRY:.*:]]10425// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>10426// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>10427// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10428// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>10429// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])10430// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i64> [[A]], [[VMULL2_I_I]]10431// CHECK-NEXT: ret <2 x i64> [[SUB_I]]10432//10433int64x2_t test_vmlsl_s32(int64x2_t a, int32x2_t b, int32x2_t c) {10434 return vmlsl_s32(a, b, c);10435}10436 10437// CHECK-LABEL: define <8 x i16> @test_vmlsl_u8(10438// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] {10439// CHECK-NEXT: [[ENTRY:.*:]]10440// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> [[B]], <8 x i8> [[C]])10441// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i16> [[A]], [[VMULL_I]]10442// CHECK-NEXT: ret <8 x i16> [[SUB_I]]10443//10444uint16x8_t test_vmlsl_u8(uint16x8_t a, uint8x8_t b, uint8x8_t c) {10445 return vmlsl_u8(a, b, c);10446}10447 10448// CHECK-LABEL: define <4 x i32> @test_vmlsl_u16(10449// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10450// CHECK-NEXT: [[ENTRY:.*:]]10451// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>10452// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>10453// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10454// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>10455// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])10456// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> [[A]], [[VMULL2_I_I]]10457// CHECK-NEXT: ret <4 x i32> [[SUB_I]]10458//10459uint32x4_t test_vmlsl_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c) {10460 return vmlsl_u16(a, b, c);10461}10462 10463// CHECK-LABEL: define <2 x i64> @test_vmlsl_u32(10464// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10465// CHECK-NEXT: [[ENTRY:.*:]]10466// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>10467// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>10468// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10469// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>10470// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])10471// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i64> [[A]], [[VMULL2_I_I]]10472// CHECK-NEXT: ret <2 x i64> [[SUB_I]]10473//10474uint64x2_t test_vmlsl_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c) {10475 return vmlsl_u32(a, b, c);10476}10477 10478// CHECK-LABEL: define <4 x i32> @test_vmlsl_lane_s16(10479// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10480// CHECK-NEXT: [[ENTRY:.*:]]10481// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>10482// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10483// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>10484// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>10485// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>10486// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>10487// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>10488// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])10489// CHECK-NEXT: [[SUB:%.*]] = sub <4 x i32> [[A]], [[VMULL2_I]]10490// CHECK-NEXT: ret <4 x i32> [[SUB]]10491//10492int32x4_t test_vmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t c) {10493 return vmlsl_lane_s16(a, b, c, 3);10494}10495 10496// CHECK-LABEL: define <2 x i64> @test_vmlsl_lane_s32(10497// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10498// CHECK-NEXT: [[ENTRY:.*:]]10499// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>10500// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10501// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>10502// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>10503// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>10504// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>10505// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>10506// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])10507// CHECK-NEXT: [[SUB:%.*]] = sub <2 x i64> [[A]], [[VMULL2_I]]10508// CHECK-NEXT: ret <2 x i64> [[SUB]]10509//10510int64x2_t test_vmlsl_lane_s32(int64x2_t a, int32x2_t b, int32x2_t c) {10511 return vmlsl_lane_s32(a, b, c, 1);10512}10513 10514// CHECK-LABEL: define <4 x i32> @test_vmlsl_lane_u16(10515// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10516// CHECK-NEXT: [[ENTRY:.*:]]10517// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>10518// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10519// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>10520// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>10521// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>10522// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>10523// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>10524// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])10525// CHECK-NEXT: [[SUB:%.*]] = sub <4 x i32> [[A]], [[VMULL2_I]]10526// CHECK-NEXT: ret <4 x i32> [[SUB]]10527//10528uint32x4_t test_vmlsl_lane_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c) {10529 return vmlsl_lane_u16(a, b, c, 3);10530}10531 10532// CHECK-LABEL: define <2 x i64> @test_vmlsl_lane_u32(10533// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10534// CHECK-NEXT: [[ENTRY:.*:]]10535// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>10536// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10537// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>10538// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>10539// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>10540// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>10541// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>10542// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])10543// CHECK-NEXT: [[SUB:%.*]] = sub <2 x i64> [[A]], [[VMULL2_I]]10544// CHECK-NEXT: ret <2 x i64> [[SUB]]10545//10546uint64x2_t test_vmlsl_lane_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c) {10547 return vmlsl_lane_u32(a, b, c, 1);10548}10549 10550// CHECK-LABEL: define <4 x i32> @test_vmlsl_n_s16(10551// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], i16 noundef signext [[C:%.*]]) #[[ATTR0]] {10552// CHECK-NEXT: [[ENTRY:.*:]]10553// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i32 010554// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[C]], i32 110555// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[C]], i32 210556// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[C]], i32 310557// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>10558// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>10559// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10560// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>10561// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])10562// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> [[A]], [[VMULL2_I_I]]10563// CHECK-NEXT: ret <4 x i32> [[SUB_I]]10564//10565int32x4_t test_vmlsl_n_s16(int32x4_t a, int16x4_t b, int16_t c) {10566 return vmlsl_n_s16(a, b, c);10567}10568 10569// CHECK-LABEL: define <2 x i64> @test_vmlsl_n_s32(10570// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {10571// CHECK-NEXT: [[ENTRY:.*:]]10572// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[C]], i32 010573// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[C]], i32 110574// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>10575// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>10576// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10577// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>10578// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])10579// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i64> [[A]], [[VMULL2_I_I]]10580// CHECK-NEXT: ret <2 x i64> [[SUB_I]]10581//10582int64x2_t test_vmlsl_n_s32(int64x2_t a, int32x2_t b, int32_t c) {10583 return vmlsl_n_s32(a, b, c);10584}10585 10586// CHECK-LABEL: define <4 x i32> @test_vmlsl_n_u16(10587// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], i16 noundef zeroext [[C:%.*]]) #[[ATTR0]] {10588// CHECK-NEXT: [[ENTRY:.*:]]10589// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i32 010590// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[C]], i32 110591// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[C]], i32 210592// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[C]], i32 310593// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>10594// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>10595// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10596// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>10597// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])10598// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> [[A]], [[VMULL2_I_I]]10599// CHECK-NEXT: ret <4 x i32> [[SUB_I]]10600//10601uint32x4_t test_vmlsl_n_u16(uint32x4_t a, uint16x4_t b, uint16_t c) {10602 return vmlsl_n_u16(a, b, c);10603}10604 10605// CHECK-LABEL: define <2 x i64> @test_vmlsl_n_u32(10606// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {10607// CHECK-NEXT: [[ENTRY:.*:]]10608// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[C]], i32 010609// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[C]], i32 110610// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>10611// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>10612// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10613// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>10614// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])10615// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i64> [[A]], [[VMULL2_I_I]]10616// CHECK-NEXT: ret <2 x i64> [[SUB_I]]10617//10618uint64x2_t test_vmlsl_n_u32(uint64x2_t a, uint32x2_t b, uint32_t c) {10619 return vmlsl_n_u32(a, b, c);10620}10621 10622// CHECK-LABEL: define <4 x i16> @test_vmls_lane_s16(10623// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10624// CHECK-NEXT: [[ENTRY:.*:]]10625// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>10626// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10627// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>10628// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i16> [[B]], [[LANE]]10629// CHECK-NEXT: [[SUB:%.*]] = sub <4 x i16> [[A]], [[MUL]]10630// CHECK-NEXT: ret <4 x i16> [[SUB]]10631//10632int16x4_t test_vmls_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) {10633 return vmls_lane_s16(a, b, c, 3);10634}10635 10636// CHECK-LABEL: define <2 x i32> @test_vmls_lane_s32(10637// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10638// CHECK-NEXT: [[ENTRY:.*:]]10639// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>10640// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10641// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>10642// CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[B]], [[LANE]]10643// CHECK-NEXT: [[SUB:%.*]] = sub <2 x i32> [[A]], [[MUL]]10644// CHECK-NEXT: ret <2 x i32> [[SUB]]10645//10646int32x2_t test_vmls_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) {10647 return vmls_lane_s32(a, b, c, 1);10648}10649 10650// CHECK-LABEL: define <4 x i16> @test_vmls_lane_u16(10651// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10652// CHECK-NEXT: [[ENTRY:.*:]]10653// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>10654// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10655// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>10656// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i16> [[B]], [[LANE]]10657// CHECK-NEXT: [[SUB:%.*]] = sub <4 x i16> [[A]], [[MUL]]10658// CHECK-NEXT: ret <4 x i16> [[SUB]]10659//10660uint16x4_t test_vmls_lane_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c) {10661 return vmls_lane_u16(a, b, c, 3);10662}10663 10664// CHECK-LABEL: define <2 x i32> @test_vmls_lane_u32(10665// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10666// CHECK-NEXT: [[ENTRY:.*:]]10667// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>10668// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10669// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>10670// CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[B]], [[LANE]]10671// CHECK-NEXT: [[SUB:%.*]] = sub <2 x i32> [[A]], [[MUL]]10672// CHECK-NEXT: ret <2 x i32> [[SUB]]10673//10674uint32x2_t test_vmls_lane_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c) {10675 return vmls_lane_u32(a, b, c, 1);10676}10677 10678// CHECK-LABEL: define <2 x float> @test_vmls_lane_f32(10679// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], <2 x float> noundef [[C:%.*]]) #[[ATTR0]] {10680// CHECK-NEXT: [[ENTRY:.*:]]10681// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[C]] to <2 x i32>10682// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>10683// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>10684// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <2 x i32> <i32 1, i32 1>10685// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[B]], [[LANE]]10686// CHECK-NEXT: [[SUB:%.*]] = fsub <2 x float> [[A]], [[MUL]]10687// CHECK-NEXT: ret <2 x float> [[SUB]]10688//10689float32x2_t test_vmls_lane_f32(float32x2_t a, float32x2_t b, float32x2_t c) {10690 return vmls_lane_f32(a, b, c, 1);10691}10692 10693// CHECK-LABEL: define <8 x i16> @test_vmlsq_lane_s16(10694// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10695// CHECK-NEXT: [[ENTRY:.*:]]10696// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>10697// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10698// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>10699// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i16> [[B]], [[LANE]]10700// CHECK-NEXT: [[SUB:%.*]] = sub <8 x i16> [[A]], [[MUL]]10701// CHECK-NEXT: ret <8 x i16> [[SUB]]10702//10703int16x8_t test_vmlsq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t c) {10704 return vmlsq_lane_s16(a, b, c, 3);10705}10706 10707// CHECK-LABEL: define <4 x i32> @test_vmlsq_lane_s32(10708// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10709// CHECK-NEXT: [[ENTRY:.*:]]10710// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>10711// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10712// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>10713// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[B]], [[LANE]]10714// CHECK-NEXT: [[SUB:%.*]] = sub <4 x i32> [[A]], [[MUL]]10715// CHECK-NEXT: ret <4 x i32> [[SUB]]10716//10717int32x4_t test_vmlsq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t c) {10718 return vmlsq_lane_s32(a, b, c, 1);10719}10720 10721// CHECK-LABEL: define <8 x i16> @test_vmlsq_lane_u16(10722// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {10723// CHECK-NEXT: [[ENTRY:.*:]]10724// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>10725// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10726// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>10727// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i16> [[B]], [[LANE]]10728// CHECK-NEXT: [[SUB:%.*]] = sub <8 x i16> [[A]], [[MUL]]10729// CHECK-NEXT: ret <8 x i16> [[SUB]]10730//10731uint16x8_t test_vmlsq_lane_u16(uint16x8_t a, uint16x8_t b, uint16x4_t c) {10732 return vmlsq_lane_u16(a, b, c, 3);10733}10734 10735// CHECK-LABEL: define <4 x i32> @test_vmlsq_lane_u32(10736// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {10737// CHECK-NEXT: [[ENTRY:.*:]]10738// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>10739// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10740// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>10741// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[B]], [[LANE]]10742// CHECK-NEXT: [[SUB:%.*]] = sub <4 x i32> [[A]], [[MUL]]10743// CHECK-NEXT: ret <4 x i32> [[SUB]]10744//10745uint32x4_t test_vmlsq_lane_u32(uint32x4_t a, uint32x4_t b, uint32x2_t c) {10746 return vmlsq_lane_u32(a, b, c, 1);10747}10748 10749// CHECK-LABEL: define <4 x float> @test_vmlsq_lane_f32(10750// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], <2 x float> noundef [[C:%.*]]) #[[ATTR0]] {10751// CHECK-NEXT: [[ENTRY:.*:]]10752// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[C]] to <2 x i32>10753// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>10754// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>10755// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>10756// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[B]], [[LANE]]10757// CHECK-NEXT: [[SUB:%.*]] = fsub <4 x float> [[A]], [[MUL]]10758// CHECK-NEXT: ret <4 x float> [[SUB]]10759//10760float32x4_t test_vmlsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t c) {10761 return vmlsq_lane_f32(a, b, c, 1);10762}10763 10764// CHECK-LABEL: define <4 x i16> @test_vmls_n_s16(10765// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], i16 noundef signext [[C:%.*]]) #[[ATTR0]] {10766// CHECK-NEXT: [[ENTRY:.*:]]10767// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i32 010768// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[C]], i32 110769// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[C]], i32 210770// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[C]], i32 310771// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[B]], [[VECINIT3_I]]10772// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[A]], [[MUL_I]]10773// CHECK-NEXT: ret <4 x i16> [[SUB_I]]10774//10775int16x4_t test_vmls_n_s16(int16x4_t a, int16x4_t b, int16_t c) {10776 return vmls_n_s16(a, b, c);10777}10778 10779// CHECK-LABEL: define <2 x i32> @test_vmls_n_s32(10780// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {10781// CHECK-NEXT: [[ENTRY:.*:]]10782// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[C]], i32 010783// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[C]], i32 110784// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[B]], [[VECINIT1_I]]10785// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[A]], [[MUL_I]]10786// CHECK-NEXT: ret <2 x i32> [[SUB_I]]10787//10788int32x2_t test_vmls_n_s32(int32x2_t a, int32x2_t b, int32_t c) {10789 return vmls_n_s32(a, b, c);10790}10791 10792// CHECK-LABEL: define <4 x i16> @test_vmls_n_u16(10793// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], i16 noundef zeroext [[C:%.*]]) #[[ATTR0]] {10794// CHECK-NEXT: [[ENTRY:.*:]]10795// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i32 010796// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[C]], i32 110797// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[C]], i32 210798// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[C]], i32 310799// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[B]], [[VECINIT3_I]]10800// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[A]], [[MUL_I]]10801// CHECK-NEXT: ret <4 x i16> [[SUB_I]]10802//10803uint16x4_t test_vmls_n_u16(uint16x4_t a, uint16x4_t b, uint16_t c) {10804 return vmls_n_u16(a, b, c);10805}10806 10807// CHECK-LABEL: define <2 x i32> @test_vmls_n_u32(10808// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {10809// CHECK-NEXT: [[ENTRY:.*:]]10810// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[C]], i32 010811// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[C]], i32 110812// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[B]], [[VECINIT1_I]]10813// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[A]], [[MUL_I]]10814// CHECK-NEXT: ret <2 x i32> [[SUB_I]]10815//10816uint32x2_t test_vmls_n_u32(uint32x2_t a, uint32x2_t b, uint32_t c) {10817 return vmls_n_u32(a, b, c);10818}10819 10820// CHECK-LABEL: define <2 x float> @test_vmls_n_f32(10821// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]], float noundef [[C:%.*]]) #[[ATTR0]] {10822// CHECK-NEXT: [[ENTRY:.*:]]10823// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x float> poison, float [[C]], i32 010824// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float [[C]], i32 110825// CHECK-NEXT: [[MUL_I:%.*]] = fmul <2 x float> [[B]], [[VECINIT1_I]]10826// CHECK-NEXT: [[SUB_I:%.*]] = fsub <2 x float> [[A]], [[MUL_I]]10827// CHECK-NEXT: ret <2 x float> [[SUB_I]]10828//10829float32x2_t test_vmls_n_f32(float32x2_t a, float32x2_t b, float32_t c) {10830 return vmls_n_f32(a, b, c);10831}10832 10833// CHECK-LABEL: define <8 x i16> @test_vmlsq_n_s16(10834// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], i16 noundef signext [[C:%.*]]) #[[ATTR0]] {10835// CHECK-NEXT: [[ENTRY:.*:]]10836// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[C]], i32 010837// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[C]], i32 110838// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[C]], i32 210839// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[C]], i32 310840// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[C]], i32 410841// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[C]], i32 510842// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[C]], i32 610843// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[C]], i32 710844// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[B]], [[VECINIT7_I]]10845// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i16> [[A]], [[MUL_I]]10846// CHECK-NEXT: ret <8 x i16> [[SUB_I]]10847//10848int16x8_t test_vmlsq_n_s16(int16x8_t a, int16x8_t b, int16_t c) {10849 return vmlsq_n_s16(a, b, c);10850}10851 10852// CHECK-LABEL: define <4 x i32> @test_vmlsq_n_s32(10853// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {10854// CHECK-NEXT: [[ENTRY:.*:]]10855// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[C]], i32 010856// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[C]], i32 110857// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[C]], i32 210858// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[C]], i32 310859// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[B]], [[VECINIT3_I]]10860// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> [[A]], [[MUL_I]]10861// CHECK-NEXT: ret <4 x i32> [[SUB_I]]10862//10863int32x4_t test_vmlsq_n_s32(int32x4_t a, int32x4_t b, int32_t c) {10864 return vmlsq_n_s32(a, b, c);10865}10866 10867// CHECK-LABEL: define <8 x i16> @test_vmlsq_n_u16(10868// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]], i16 noundef zeroext [[C:%.*]]) #[[ATTR0]] {10869// CHECK-NEXT: [[ENTRY:.*:]]10870// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[C]], i32 010871// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[C]], i32 110872// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[C]], i32 210873// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[C]], i32 310874// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[C]], i32 410875// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[C]], i32 510876// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[C]], i32 610877// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[C]], i32 710878// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[B]], [[VECINIT7_I]]10879// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i16> [[A]], [[MUL_I]]10880// CHECK-NEXT: ret <8 x i16> [[SUB_I]]10881//10882uint16x8_t test_vmlsq_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c) {10883 return vmlsq_n_u16(a, b, c);10884}10885 10886// CHECK-LABEL: define <4 x i32> @test_vmlsq_n_u32(10887// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {10888// CHECK-NEXT: [[ENTRY:.*:]]10889// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[C]], i32 010890// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[C]], i32 110891// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[C]], i32 210892// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[C]], i32 310893// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[B]], [[VECINIT3_I]]10894// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> [[A]], [[MUL_I]]10895// CHECK-NEXT: ret <4 x i32> [[SUB_I]]10896//10897uint32x4_t test_vmlsq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c) {10898 return vmlsq_n_u32(a, b, c);10899}10900 10901// CHECK-LABEL: define <4 x float> @test_vmlsq_n_f32(10902// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]], float noundef [[C:%.*]]) #[[ATTR0]] {10903// CHECK-NEXT: [[ENTRY:.*:]]10904// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[C]], i32 010905// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[C]], i32 110906// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[C]], i32 210907// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[C]], i32 310908// CHECK-NEXT: [[MUL_I:%.*]] = fmul <4 x float> [[B]], [[VECINIT3_I]]10909// CHECK-NEXT: [[SUB_I:%.*]] = fsub <4 x float> [[A]], [[MUL_I]]10910// CHECK-NEXT: ret <4 x float> [[SUB_I]]10911//10912float32x4_t test_vmlsq_n_f32(float32x4_t a, float32x4_t b, float32_t c) {10913 return vmlsq_n_f32(a, b, c);10914}10915 10916// CHECK-LABEL: define <8 x i16> @test_vmovl_s8(10917// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {10918// CHECK-NEXT: [[ENTRY:.*:]]10919// CHECK-NEXT: [[VMOVL_I:%.*]] = sext <8 x i8> [[A]] to <8 x i16>10920// CHECK-NEXT: ret <8 x i16> [[VMOVL_I]]10921//10922int16x8_t test_vmovl_s8(int8x8_t a) {10923 return vmovl_s8(a);10924}10925 10926// CHECK-LABEL: define <4 x i32> @test_vmovl_s16(10927// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {10928// CHECK-NEXT: [[ENTRY:.*:]]10929// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>10930// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10931// CHECK-NEXT: [[VMOVL_I:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>10932// CHECK-NEXT: ret <4 x i32> [[VMOVL_I]]10933//10934int32x4_t test_vmovl_s16(int16x4_t a) {10935 return vmovl_s16(a);10936}10937 10938// CHECK-LABEL: define <2 x i64> @test_vmovl_s32(10939// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {10940// CHECK-NEXT: [[ENTRY:.*:]]10941// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>10942// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10943// CHECK-NEXT: [[VMOVL_I:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>10944// CHECK-NEXT: ret <2 x i64> [[VMOVL_I]]10945//10946int64x2_t test_vmovl_s32(int32x2_t a) {10947 return vmovl_s32(a);10948}10949 10950// CHECK-LABEL: define <8 x i16> @test_vmovl_u8(10951// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {10952// CHECK-NEXT: [[ENTRY:.*:]]10953// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <8 x i8> [[A]] to <8 x i16>10954// CHECK-NEXT: ret <8 x i16> [[VMOVL_I]]10955//10956uint16x8_t test_vmovl_u8(uint8x8_t a) {10957 return vmovl_u8(a);10958}10959 10960// CHECK-LABEL: define <4 x i32> @test_vmovl_u16(10961// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {10962// CHECK-NEXT: [[ENTRY:.*:]]10963// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>10964// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>10965// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>10966// CHECK-NEXT: ret <4 x i32> [[VMOVL_I]]10967//10968uint32x4_t test_vmovl_u16(uint16x4_t a) {10969 return vmovl_u16(a);10970}10971 10972// CHECK-LABEL: define <2 x i64> @test_vmovl_u32(10973// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {10974// CHECK-NEXT: [[ENTRY:.*:]]10975// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>10976// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>10977// CHECK-NEXT: [[VMOVL_I:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>10978// CHECK-NEXT: ret <2 x i64> [[VMOVL_I]]10979//10980uint64x2_t test_vmovl_u32(uint32x2_t a) {10981 return vmovl_u32(a);10982}10983 10984// CHECK-LABEL: define <8 x i8> @test_vmovn_s16(10985// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {10986// CHECK-NEXT: [[ENTRY:.*:]]10987// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>10988// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>10989// CHECK-NEXT: [[VMOVN_I:%.*]] = trunc <8 x i16> [[TMP1]] to <8 x i8>10990// CHECK-NEXT: ret <8 x i8> [[VMOVN_I]]10991//10992int8x8_t test_vmovn_s16(int16x8_t a) {10993 return vmovn_s16(a);10994}10995 10996// CHECK-LABEL: define <4 x i16> @test_vmovn_s32(10997// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {10998// CHECK-NEXT: [[ENTRY:.*:]]10999// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>11000// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>11001// CHECK-NEXT: [[VMOVN_I:%.*]] = trunc <4 x i32> [[TMP1]] to <4 x i16>11002// CHECK-NEXT: ret <4 x i16> [[VMOVN_I]]11003//11004int16x4_t test_vmovn_s32(int32x4_t a) {11005 return vmovn_s32(a);11006}11007 11008// CHECK-LABEL: define <2 x i32> @test_vmovn_s64(11009// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {11010// CHECK-NEXT: [[ENTRY:.*:]]11011// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>11012// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>11013// CHECK-NEXT: [[VMOVN_I:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32>11014// CHECK-NEXT: ret <2 x i32> [[VMOVN_I]]11015//11016int32x2_t test_vmovn_s64(int64x2_t a) {11017 return vmovn_s64(a);11018}11019 11020// CHECK-LABEL: define <8 x i8> @test_vmovn_u16(11021// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {11022// CHECK-NEXT: [[ENTRY:.*:]]11023// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>11024// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>11025// CHECK-NEXT: [[VMOVN_I:%.*]] = trunc <8 x i16> [[TMP1]] to <8 x i8>11026// CHECK-NEXT: ret <8 x i8> [[VMOVN_I]]11027//11028uint8x8_t test_vmovn_u16(uint16x8_t a) {11029 return vmovn_u16(a);11030}11031 11032// CHECK-LABEL: define <4 x i16> @test_vmovn_u32(11033// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {11034// CHECK-NEXT: [[ENTRY:.*:]]11035// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>11036// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>11037// CHECK-NEXT: [[VMOVN_I:%.*]] = trunc <4 x i32> [[TMP1]] to <4 x i16>11038// CHECK-NEXT: ret <4 x i16> [[VMOVN_I]]11039//11040uint16x4_t test_vmovn_u32(uint32x4_t a) {11041 return vmovn_u32(a);11042}11043 11044// CHECK-LABEL: define <2 x i32> @test_vmovn_u64(11045// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {11046// CHECK-NEXT: [[ENTRY:.*:]]11047// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>11048// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>11049// CHECK-NEXT: [[VMOVN_I:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32>11050// CHECK-NEXT: ret <2 x i32> [[VMOVN_I]]11051//11052uint32x2_t test_vmovn_u64(uint64x2_t a) {11053 return vmovn_u64(a);11054}11055 11056// CHECK-LABEL: define <8 x i8> @test_vmov_n_u8(11057// CHECK-SAME: i8 noundef zeroext [[A:%.*]]) #[[ATTR0]] {11058// CHECK-NEXT: [[ENTRY:.*:]]11059// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i32 011060// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i8> [[VECINIT_I]], i8 [[A]], i32 111061// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i8> [[VECINIT1_I]], i8 [[A]], i32 211062// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i8> [[VECINIT2_I]], i8 [[A]], i32 311063// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i8> [[VECINIT3_I]], i8 [[A]], i32 411064// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i8> [[VECINIT4_I]], i8 [[A]], i32 511065// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i8> [[VECINIT5_I]], i8 [[A]], i32 611066// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i8> [[VECINIT6_I]], i8 [[A]], i32 711067// CHECK-NEXT: ret <8 x i8> [[VECINIT7_I]]11068//11069uint8x8_t test_vmov_n_u8(uint8_t a) {11070 return vmov_n_u8(a);11071}11072 11073// CHECK-LABEL: define <4 x i16> @test_vmov_n_u16(11074// CHECK-SAME: i16 noundef zeroext [[A:%.*]]) #[[ATTR0]] {11075// CHECK-NEXT: [[ENTRY:.*:]]11076// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i32 011077// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[A]], i32 111078// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[A]], i32 211079// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[A]], i32 311080// CHECK-NEXT: ret <4 x i16> [[VECINIT3_I]]11081//11082uint16x4_t test_vmov_n_u16(uint16_t a) {11083 return vmov_n_u16(a);11084}11085 11086// CHECK-LABEL: define <2 x i32> @test_vmov_n_u32(11087// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {11088// CHECK-NEXT: [[ENTRY:.*:]]11089// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i32 011090// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[A]], i32 111091// CHECK-NEXT: ret <2 x i32> [[VECINIT1_I]]11092//11093uint32x2_t test_vmov_n_u32(uint32_t a) {11094 return vmov_n_u32(a);11095}11096 11097// CHECK-LABEL: define <8 x i8> @test_vmov_n_s8(11098// CHECK-SAME: i8 noundef signext [[A:%.*]]) #[[ATTR0]] {11099// CHECK-NEXT: [[ENTRY:.*:]]11100// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i32 011101// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i8> [[VECINIT_I]], i8 [[A]], i32 111102// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i8> [[VECINIT1_I]], i8 [[A]], i32 211103// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i8> [[VECINIT2_I]], i8 [[A]], i32 311104// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i8> [[VECINIT3_I]], i8 [[A]], i32 411105// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i8> [[VECINIT4_I]], i8 [[A]], i32 511106// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i8> [[VECINIT5_I]], i8 [[A]], i32 611107// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i8> [[VECINIT6_I]], i8 [[A]], i32 711108// CHECK-NEXT: ret <8 x i8> [[VECINIT7_I]]11109//11110int8x8_t test_vmov_n_s8(int8_t a) {11111 return vmov_n_s8(a);11112}11113 11114// CHECK-LABEL: define <4 x i16> @test_vmov_n_s16(11115// CHECK-SAME: i16 noundef signext [[A:%.*]]) #[[ATTR0]] {11116// CHECK-NEXT: [[ENTRY:.*:]]11117// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i32 011118// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[A]], i32 111119// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[A]], i32 211120// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[A]], i32 311121// CHECK-NEXT: ret <4 x i16> [[VECINIT3_I]]11122//11123int16x4_t test_vmov_n_s16(int16_t a) {11124 return vmov_n_s16(a);11125}11126 11127// CHECK-LABEL: define <2 x i32> @test_vmov_n_s32(11128// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {11129// CHECK-NEXT: [[ENTRY:.*:]]11130// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i32 011131// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[A]], i32 111132// CHECK-NEXT: ret <2 x i32> [[VECINIT1_I]]11133//11134int32x2_t test_vmov_n_s32(int32_t a) {11135 return vmov_n_s32(a);11136}11137 11138// CHECK-LABEL: define <8 x i8> @test_vmov_n_p8(11139// CHECK-SAME: i8 noundef signext [[A:%.*]]) #[[ATTR0]] {11140// CHECK-NEXT: [[ENTRY:.*:]]11141// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i32 011142// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i8> [[VECINIT_I]], i8 [[A]], i32 111143// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i8> [[VECINIT1_I]], i8 [[A]], i32 211144// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i8> [[VECINIT2_I]], i8 [[A]], i32 311145// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i8> [[VECINIT3_I]], i8 [[A]], i32 411146// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i8> [[VECINIT4_I]], i8 [[A]], i32 511147// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i8> [[VECINIT5_I]], i8 [[A]], i32 611148// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i8> [[VECINIT6_I]], i8 [[A]], i32 711149// CHECK-NEXT: ret <8 x i8> [[VECINIT7_I]]11150//11151poly8x8_t test_vmov_n_p8(poly8_t a) {11152 return vmov_n_p8(a);11153}11154 11155// CHECK-LABEL: define <4 x i16> @test_vmov_n_p16(11156// CHECK-SAME: i16 noundef signext [[A:%.*]]) #[[ATTR0]] {11157// CHECK-NEXT: [[ENTRY:.*:]]11158// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i32 011159// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[A]], i32 111160// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[A]], i32 211161// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[A]], i32 311162// CHECK-NEXT: ret <4 x i16> [[VECINIT3_I]]11163//11164poly16x4_t test_vmov_n_p16(poly16_t a) {11165 return vmov_n_p16(a);11166}11167 11168// CHECK-LABEL: define <4 x half> @test_vmov_n_f16(11169// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {11170// CHECK-NEXT: [[ENTRY:.*:]]11171// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A]], align 211172// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x half> poison, half [[TMP0]], i32 011173// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[TMP0]], i32 111174// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[TMP0]], i32 211175// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[TMP0]], i32 311176// CHECK-NEXT: ret <4 x half> [[VECINIT3]]11177//11178float16x4_t test_vmov_n_f16(float16_t *a) {11179 return vmov_n_f16(*a);11180}11181 11182// CHECK-LABEL: define <2 x float> @test_vmov_n_f32(11183// CHECK-SAME: float noundef [[A:%.*]]) #[[ATTR0]] {11184// CHECK-NEXT: [[ENTRY:.*:]]11185// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x float> poison, float [[A]], i32 011186// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float [[A]], i32 111187// CHECK-NEXT: ret <2 x float> [[VECINIT1_I]]11188//11189float32x2_t test_vmov_n_f32(float32_t a) {11190 return vmov_n_f32(a);11191}11192 11193// CHECK-LABEL: define <16 x i8> @test_vmovq_n_u8(11194// CHECK-SAME: i8 noundef zeroext [[A:%.*]]) #[[ATTR0]] {11195// CHECK-NEXT: [[ENTRY:.*:]]11196// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> poison, i8 [[A]], i32 011197// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <16 x i8> [[VECINIT_I]], i8 [[A]], i32 111198// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <16 x i8> [[VECINIT1_I]], i8 [[A]], i32 211199// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <16 x i8> [[VECINIT2_I]], i8 [[A]], i32 311200// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <16 x i8> [[VECINIT3_I]], i8 [[A]], i32 411201// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <16 x i8> [[VECINIT4_I]], i8 [[A]], i32 511202// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <16 x i8> [[VECINIT5_I]], i8 [[A]], i32 611203// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <16 x i8> [[VECINIT6_I]], i8 [[A]], i32 711204// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <16 x i8> [[VECINIT7_I]], i8 [[A]], i32 811205// CHECK-NEXT: [[VECINIT9_I:%.*]] = insertelement <16 x i8> [[VECINIT8_I]], i8 [[A]], i32 911206// CHECK-NEXT: [[VECINIT10_I:%.*]] = insertelement <16 x i8> [[VECINIT9_I]], i8 [[A]], i32 1011207// CHECK-NEXT: [[VECINIT11_I:%.*]] = insertelement <16 x i8> [[VECINIT10_I]], i8 [[A]], i32 1111208// CHECK-NEXT: [[VECINIT12_I:%.*]] = insertelement <16 x i8> [[VECINIT11_I]], i8 [[A]], i32 1211209// CHECK-NEXT: [[VECINIT13_I:%.*]] = insertelement <16 x i8> [[VECINIT12_I]], i8 [[A]], i32 1311210// CHECK-NEXT: [[VECINIT14_I:%.*]] = insertelement <16 x i8> [[VECINIT13_I]], i8 [[A]], i32 1411211// CHECK-NEXT: [[VECINIT15_I:%.*]] = insertelement <16 x i8> [[VECINIT14_I]], i8 [[A]], i32 1511212// CHECK-NEXT: ret <16 x i8> [[VECINIT15_I]]11213//11214uint8x16_t test_vmovq_n_u8(uint8_t a) {11215 return vmovq_n_u8(a);11216}11217 11218// CHECK-LABEL: define <8 x i16> @test_vmovq_n_u16(11219// CHECK-SAME: i16 noundef zeroext [[A:%.*]]) #[[ATTR0]] {11220// CHECK-NEXT: [[ENTRY:.*:]]11221// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[A]], i32 011222// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[A]], i32 111223// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[A]], i32 211224// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[A]], i32 311225// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[A]], i32 411226// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[A]], i32 511227// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[A]], i32 611228// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[A]], i32 711229// CHECK-NEXT: ret <8 x i16> [[VECINIT7_I]]11230//11231uint16x8_t test_vmovq_n_u16(uint16_t a) {11232 return vmovq_n_u16(a);11233}11234 11235// CHECK-LABEL: define <4 x i32> @test_vmovq_n_u32(11236// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {11237// CHECK-NEXT: [[ENTRY:.*:]]11238// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 011239// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[A]], i32 111240// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[A]], i32 211241// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[A]], i32 311242// CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]]11243//11244uint32x4_t test_vmovq_n_u32(uint32_t a) {11245 return vmovq_n_u32(a);11246}11247 11248// CHECK-LABEL: define <16 x i8> @test_vmovq_n_s8(11249// CHECK-SAME: i8 noundef signext [[A:%.*]]) #[[ATTR0]] {11250// CHECK-NEXT: [[ENTRY:.*:]]11251// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> poison, i8 [[A]], i32 011252// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <16 x i8> [[VECINIT_I]], i8 [[A]], i32 111253// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <16 x i8> [[VECINIT1_I]], i8 [[A]], i32 211254// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <16 x i8> [[VECINIT2_I]], i8 [[A]], i32 311255// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <16 x i8> [[VECINIT3_I]], i8 [[A]], i32 411256// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <16 x i8> [[VECINIT4_I]], i8 [[A]], i32 511257// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <16 x i8> [[VECINIT5_I]], i8 [[A]], i32 611258// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <16 x i8> [[VECINIT6_I]], i8 [[A]], i32 711259// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <16 x i8> [[VECINIT7_I]], i8 [[A]], i32 811260// CHECK-NEXT: [[VECINIT9_I:%.*]] = insertelement <16 x i8> [[VECINIT8_I]], i8 [[A]], i32 911261// CHECK-NEXT: [[VECINIT10_I:%.*]] = insertelement <16 x i8> [[VECINIT9_I]], i8 [[A]], i32 1011262// CHECK-NEXT: [[VECINIT11_I:%.*]] = insertelement <16 x i8> [[VECINIT10_I]], i8 [[A]], i32 1111263// CHECK-NEXT: [[VECINIT12_I:%.*]] = insertelement <16 x i8> [[VECINIT11_I]], i8 [[A]], i32 1211264// CHECK-NEXT: [[VECINIT13_I:%.*]] = insertelement <16 x i8> [[VECINIT12_I]], i8 [[A]], i32 1311265// CHECK-NEXT: [[VECINIT14_I:%.*]] = insertelement <16 x i8> [[VECINIT13_I]], i8 [[A]], i32 1411266// CHECK-NEXT: [[VECINIT15_I:%.*]] = insertelement <16 x i8> [[VECINIT14_I]], i8 [[A]], i32 1511267// CHECK-NEXT: ret <16 x i8> [[VECINIT15_I]]11268//11269int8x16_t test_vmovq_n_s8(int8_t a) {11270 return vmovq_n_s8(a);11271}11272 11273// CHECK-LABEL: define <8 x i16> @test_vmovq_n_s16(11274// CHECK-SAME: i16 noundef signext [[A:%.*]]) #[[ATTR0]] {11275// CHECK-NEXT: [[ENTRY:.*:]]11276// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[A]], i32 011277// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[A]], i32 111278// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[A]], i32 211279// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[A]], i32 311280// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[A]], i32 411281// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[A]], i32 511282// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[A]], i32 611283// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[A]], i32 711284// CHECK-NEXT: ret <8 x i16> [[VECINIT7_I]]11285//11286int16x8_t test_vmovq_n_s16(int16_t a) {11287 return vmovq_n_s16(a);11288}11289 11290// CHECK-LABEL: define <4 x i32> @test_vmovq_n_s32(11291// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {11292// CHECK-NEXT: [[ENTRY:.*:]]11293// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 011294// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[A]], i32 111295// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[A]], i32 211296// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[A]], i32 311297// CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]]11298//11299int32x4_t test_vmovq_n_s32(int32_t a) {11300 return vmovq_n_s32(a);11301}11302 11303// CHECK-LABEL: define <16 x i8> @test_vmovq_n_p8(11304// CHECK-SAME: i8 noundef signext [[A:%.*]]) #[[ATTR0]] {11305// CHECK-NEXT: [[ENTRY:.*:]]11306// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> poison, i8 [[A]], i32 011307// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <16 x i8> [[VECINIT_I]], i8 [[A]], i32 111308// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <16 x i8> [[VECINIT1_I]], i8 [[A]], i32 211309// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <16 x i8> [[VECINIT2_I]], i8 [[A]], i32 311310// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <16 x i8> [[VECINIT3_I]], i8 [[A]], i32 411311// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <16 x i8> [[VECINIT4_I]], i8 [[A]], i32 511312// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <16 x i8> [[VECINIT5_I]], i8 [[A]], i32 611313// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <16 x i8> [[VECINIT6_I]], i8 [[A]], i32 711314// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <16 x i8> [[VECINIT7_I]], i8 [[A]], i32 811315// CHECK-NEXT: [[VECINIT9_I:%.*]] = insertelement <16 x i8> [[VECINIT8_I]], i8 [[A]], i32 911316// CHECK-NEXT: [[VECINIT10_I:%.*]] = insertelement <16 x i8> [[VECINIT9_I]], i8 [[A]], i32 1011317// CHECK-NEXT: [[VECINIT11_I:%.*]] = insertelement <16 x i8> [[VECINIT10_I]], i8 [[A]], i32 1111318// CHECK-NEXT: [[VECINIT12_I:%.*]] = insertelement <16 x i8> [[VECINIT11_I]], i8 [[A]], i32 1211319// CHECK-NEXT: [[VECINIT13_I:%.*]] = insertelement <16 x i8> [[VECINIT12_I]], i8 [[A]], i32 1311320// CHECK-NEXT: [[VECINIT14_I:%.*]] = insertelement <16 x i8> [[VECINIT13_I]], i8 [[A]], i32 1411321// CHECK-NEXT: [[VECINIT15_I:%.*]] = insertelement <16 x i8> [[VECINIT14_I]], i8 [[A]], i32 1511322// CHECK-NEXT: ret <16 x i8> [[VECINIT15_I]]11323//11324poly8x16_t test_vmovq_n_p8(poly8_t a) {11325 return vmovq_n_p8(a);11326}11327 11328// CHECK-LABEL: define <8 x i16> @test_vmovq_n_p16(11329// CHECK-SAME: i16 noundef signext [[A:%.*]]) #[[ATTR0]] {11330// CHECK-NEXT: [[ENTRY:.*:]]11331// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[A]], i32 011332// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[A]], i32 111333// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[A]], i32 211334// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[A]], i32 311335// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[A]], i32 411336// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[A]], i32 511337// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[A]], i32 611338// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[A]], i32 711339// CHECK-NEXT: ret <8 x i16> [[VECINIT7_I]]11340//11341poly16x8_t test_vmovq_n_p16(poly16_t a) {11342 return vmovq_n_p16(a);11343}11344 11345// CHECK-LABEL: define <8 x half> @test_vmovq_n_f16(11346// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] {11347// CHECK-NEXT: [[ENTRY:.*:]]11348// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A]], align 211349// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <8 x half> poison, half [[TMP0]], i32 011350// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[TMP0]], i32 111351// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[TMP0]], i32 211352// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[TMP0]], i32 311353// CHECK-NEXT: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[TMP0]], i32 411354// CHECK-NEXT: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[TMP0]], i32 511355// CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[TMP0]], i32 611356// CHECK-NEXT: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[TMP0]], i32 711357// CHECK-NEXT: ret <8 x half> [[VECINIT7]]11358//11359float16x8_t test_vmovq_n_f16(float16_t *a) {11360 return vmovq_n_f16(*a);11361}11362 11363// CHECK-LABEL: define <4 x float> @test_vmovq_n_f32(11364// CHECK-SAME: float noundef [[A:%.*]]) #[[ATTR0]] {11365// CHECK-NEXT: [[ENTRY:.*:]]11366// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[A]], i32 011367// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[A]], i32 111368// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[A]], i32 211369// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[A]], i32 311370// CHECK-NEXT: ret <4 x float> [[VECINIT3_I]]11371//11372float32x4_t test_vmovq_n_f32(float32_t a) {11373 return vmovq_n_f32(a);11374}11375 11376// CHECK-LABEL: define <1 x i64> @test_vmov_n_s64(11377// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {11378// CHECK-NEXT: [[ENTRY:.*:]]11379// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <1 x i64> poison, i64 [[A]], i32 011380// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[VECINIT_I]], [[VECINIT_I]]11381// CHECK-NEXT: ret <1 x i64> [[ADD_I]]11382//11383int64x1_t test_vmov_n_s64(int64_t a) {11384 int64x1_t tmp = vmov_n_s64(a);11385 return vadd_s64(tmp, tmp);11386}11387 11388// CHECK-LABEL: define <1 x i64> @test_vmov_n_u64(11389// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {11390// CHECK-NEXT: [[ENTRY:.*:]]11391// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <1 x i64> poison, i64 [[A]], i32 011392// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[VECINIT_I]], [[VECINIT_I]]11393// CHECK-NEXT: ret <1 x i64> [[ADD_I]]11394//11395uint64x1_t test_vmov_n_u64(uint64_t a) {11396 uint64x1_t tmp = vmov_n_u64(a);11397 return vadd_u64(tmp, tmp);11398}11399 11400// CHECK-LABEL: define <2 x i64> @test_vmovq_n_s64(11401// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {11402// CHECK-NEXT: [[ENTRY:.*:]]11403// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 [[A]], i32 011404// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 [[A]], i32 111405// CHECK-NEXT: ret <2 x i64> [[VECINIT1_I]]11406//11407int64x2_t test_vmovq_n_s64(int64_t a) {11408 return vmovq_n_s64(a);11409}11410 11411// CHECK-LABEL: define <2 x i64> @test_vmovq_n_u64(11412// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] {11413// CHECK-NEXT: [[ENTRY:.*:]]11414// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 [[A]], i32 011415// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 [[A]], i32 111416// CHECK-NEXT: ret <2 x i64> [[VECINIT1_I]]11417//11418uint64x2_t test_vmovq_n_u64(uint64_t a) {11419 return vmovq_n_u64(a);11420}11421 11422// CHECK-LABEL: define <8 x i8> @test_vmul_s8(11423// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {11424// CHECK-NEXT: [[ENTRY:.*:]]11425// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i8> [[A]], [[B]]11426// CHECK-NEXT: ret <8 x i8> [[MUL_I]]11427//11428int8x8_t test_vmul_s8(int8x8_t a, int8x8_t b) {11429 return vmul_s8(a, b);11430}11431 11432// CHECK-LABEL: define <4 x i16> @test_vmul_s16(11433// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11434// CHECK-NEXT: [[ENTRY:.*:]]11435// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[A]], [[B]]11436// CHECK-NEXT: ret <4 x i16> [[MUL_I]]11437//11438int16x4_t test_vmul_s16(int16x4_t a, int16x4_t b) {11439 return vmul_s16(a, b);11440}11441 11442// CHECK-LABEL: define <2 x i32> @test_vmul_s32(11443// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11444// CHECK-NEXT: [[ENTRY:.*:]]11445// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[A]], [[B]]11446// CHECK-NEXT: ret <2 x i32> [[MUL_I]]11447//11448int32x2_t test_vmul_s32(int32x2_t a, int32x2_t b) {11449 return vmul_s32(a, b);11450}11451 11452// CHECK-LABEL: define <2 x float> @test_vmul_f32(11453// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {11454// CHECK-NEXT: [[ENTRY:.*:]]11455// CHECK-NEXT: [[MUL_I:%.*]] = fmul <2 x float> [[A]], [[B]]11456// CHECK-NEXT: ret <2 x float> [[MUL_I]]11457//11458float32x2_t test_vmul_f32(float32x2_t a, float32x2_t b) {11459 return vmul_f32(a, b);11460}11461 11462// CHECK-LABEL: define <8 x i8> @test_vmul_u8(11463// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {11464// CHECK-NEXT: [[ENTRY:.*:]]11465// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i8> [[A]], [[B]]11466// CHECK-NEXT: ret <8 x i8> [[MUL_I]]11467//11468uint8x8_t test_vmul_u8(uint8x8_t a, uint8x8_t b) {11469 return vmul_u8(a, b);11470}11471 11472// CHECK-LABEL: define <4 x i16> @test_vmul_u16(11473// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11474// CHECK-NEXT: [[ENTRY:.*:]]11475// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[A]], [[B]]11476// CHECK-NEXT: ret <4 x i16> [[MUL_I]]11477//11478uint16x4_t test_vmul_u16(uint16x4_t a, uint16x4_t b) {11479 return vmul_u16(a, b);11480}11481 11482// CHECK-LABEL: define <2 x i32> @test_vmul_u32(11483// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11484// CHECK-NEXT: [[ENTRY:.*:]]11485// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[A]], [[B]]11486// CHECK-NEXT: ret <2 x i32> [[MUL_I]]11487//11488uint32x2_t test_vmul_u32(uint32x2_t a, uint32x2_t b) {11489 return vmul_u32(a, b);11490}11491 11492// CHECK-LABEL: define <16 x i8> @test_vmulq_s8(11493// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {11494// CHECK-NEXT: [[ENTRY:.*:]]11495// CHECK-NEXT: [[MUL_I:%.*]] = mul <16 x i8> [[A]], [[B]]11496// CHECK-NEXT: ret <16 x i8> [[MUL_I]]11497//11498int8x16_t test_vmulq_s8(int8x16_t a, int8x16_t b) {11499 return vmulq_s8(a, b);11500}11501 11502// CHECK-LABEL: define <8 x i16> @test_vmulq_s16(11503// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11504// CHECK-NEXT: [[ENTRY:.*:]]11505// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[A]], [[B]]11506// CHECK-NEXT: ret <8 x i16> [[MUL_I]]11507//11508int16x8_t test_vmulq_s16(int16x8_t a, int16x8_t b) {11509 return vmulq_s16(a, b);11510}11511 11512// CHECK-LABEL: define <4 x i32> @test_vmulq_s32(11513// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11514// CHECK-NEXT: [[ENTRY:.*:]]11515// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[A]], [[B]]11516// CHECK-NEXT: ret <4 x i32> [[MUL_I]]11517//11518int32x4_t test_vmulq_s32(int32x4_t a, int32x4_t b) {11519 return vmulq_s32(a, b);11520}11521 11522// CHECK-LABEL: define <4 x float> @test_vmulq_f32(11523// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {11524// CHECK-NEXT: [[ENTRY:.*:]]11525// CHECK-NEXT: [[MUL_I:%.*]] = fmul <4 x float> [[A]], [[B]]11526// CHECK-NEXT: ret <4 x float> [[MUL_I]]11527//11528float32x4_t test_vmulq_f32(float32x4_t a, float32x4_t b) {11529 return vmulq_f32(a, b);11530}11531 11532// CHECK-LABEL: define <16 x i8> @test_vmulq_u8(11533// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {11534// CHECK-NEXT: [[ENTRY:.*:]]11535// CHECK-NEXT: [[MUL_I:%.*]] = mul <16 x i8> [[A]], [[B]]11536// CHECK-NEXT: ret <16 x i8> [[MUL_I]]11537//11538uint8x16_t test_vmulq_u8(uint8x16_t a, uint8x16_t b) {11539 return vmulq_u8(a, b);11540}11541 11542// CHECK-LABEL: define <8 x i16> @test_vmulq_u16(11543// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11544// CHECK-NEXT: [[ENTRY:.*:]]11545// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[A]], [[B]]11546// CHECK-NEXT: ret <8 x i16> [[MUL_I]]11547//11548uint16x8_t test_vmulq_u16(uint16x8_t a, uint16x8_t b) {11549 return vmulq_u16(a, b);11550}11551 11552// CHECK-LABEL: define <4 x i32> @test_vmulq_u32(11553// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11554// CHECK-NEXT: [[ENTRY:.*:]]11555// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[A]], [[B]]11556// CHECK-NEXT: ret <4 x i32> [[MUL_I]]11557//11558uint32x4_t test_vmulq_u32(uint32x4_t a, uint32x4_t b) {11559 return vmulq_u32(a, b);11560}11561 11562// CHECK-LABEL: define <8 x i16> @test_vmull_s8(11563// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {11564// CHECK-NEXT: [[ENTRY:.*:]]11565// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> [[A]], <8 x i8> [[B]])11566// CHECK-NEXT: ret <8 x i16> [[VMULL_I]]11567//11568int16x8_t test_vmull_s8(int8x8_t a, int8x8_t b) {11569 return vmull_s8(a, b);11570}11571 11572// CHECK-LABEL: define <4 x i32> @test_vmull_s16(11573// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11574// CHECK-NEXT: [[ENTRY:.*:]]11575// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>11576// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>11577// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>11578// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>11579// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])11580// CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]11581//11582int32x4_t test_vmull_s16(int16x4_t a, int16x4_t b) {11583 return vmull_s16(a, b);11584}11585 11586// CHECK-LABEL: define <2 x i64> @test_vmull_s32(11587// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11588// CHECK-NEXT: [[ENTRY:.*:]]11589// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>11590// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>11591// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>11592// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>11593// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])11594// CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]11595//11596int64x2_t test_vmull_s32(int32x2_t a, int32x2_t b) {11597 return vmull_s32(a, b);11598}11599 11600// CHECK-LABEL: define <8 x i16> @test_vmull_u8(11601// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {11602// CHECK-NEXT: [[ENTRY:.*:]]11603// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> [[A]], <8 x i8> [[B]])11604// CHECK-NEXT: ret <8 x i16> [[VMULL_I]]11605//11606uint16x8_t test_vmull_u8(uint8x8_t a, uint8x8_t b) {11607 return vmull_u8(a, b);11608}11609 11610// CHECK-LABEL: define <4 x i32> @test_vmull_u16(11611// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11612// CHECK-NEXT: [[ENTRY:.*:]]11613// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>11614// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>11615// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>11616// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>11617// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])11618// CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]11619//11620uint32x4_t test_vmull_u16(uint16x4_t a, uint16x4_t b) {11621 return vmull_u16(a, b);11622}11623 11624// CHECK-LABEL: define <2 x i64> @test_vmull_u32(11625// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11626// CHECK-NEXT: [[ENTRY:.*:]]11627// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>11628// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>11629// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>11630// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>11631// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])11632// CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]11633//11634uint64x2_t test_vmull_u32(uint32x2_t a, uint32x2_t b) {11635 return vmull_u32(a, b);11636}11637 11638// CHECK-LABEL: define <8 x i16> @test_vmull_p8(11639// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {11640// CHECK-NEXT: [[ENTRY:.*:]]11641// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> [[A]], <8 x i8> [[B]])11642// CHECK-NEXT: ret <8 x i16> [[VMULL_I]]11643//11644poly16x8_t test_vmull_p8(poly8x8_t a, poly8x8_t b) {11645 return vmull_p8(a, b);11646}11647 11648// CHECK-LABEL: define <4 x i32> @test_vmull_lane_s16(11649// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11650// CHECK-NEXT: [[ENTRY:.*:]]11651// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>11652// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>11653// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>11654// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>11655// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>11656// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>11657// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>11658// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])11659// CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]11660//11661int32x4_t test_vmull_lane_s16(int16x4_t a, int16x4_t b) {11662 return vmull_lane_s16(a, b, 3);11663}11664 11665// CHECK-LABEL: define <2 x i64> @test_vmull_lane_s32(11666// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11667// CHECK-NEXT: [[ENTRY:.*:]]11668// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>11669// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>11670// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>11671// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>11672// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>11673// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>11674// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>11675// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])11676// CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]11677//11678int64x2_t test_vmull_lane_s32(int32x2_t a, int32x2_t b) {11679 return vmull_lane_s32(a, b, 1);11680}11681 11682// CHECK-LABEL: define <4 x i32> @test_vmull_lane_u16(11683// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11684// CHECK-NEXT: [[ENTRY:.*:]]11685// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>11686// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>11687// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>11688// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>11689// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>11690// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>11691// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>11692// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]])11693// CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]11694//11695uint32x4_t test_vmull_lane_u16(uint16x4_t a, uint16x4_t b) {11696 return vmull_lane_u16(a, b, 3);11697}11698 11699// CHECK-LABEL: define <2 x i64> @test_vmull_lane_u32(11700// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11701// CHECK-NEXT: [[ENTRY:.*:]]11702// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>11703// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>11704// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>11705// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>11706// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>11707// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>11708// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>11709// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]])11710// CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]11711//11712uint64x2_t test_vmull_lane_u32(uint32x2_t a, uint32x2_t b) {11713 return vmull_lane_u32(a, b, 1);11714}11715 11716// CHECK-LABEL: define <4 x i32> @test_vmull_n_s16(11717// CHECK-SAME: <4 x i16> noundef [[A:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {11718// CHECK-NEXT: [[ENTRY:.*:]]11719// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i32 011720// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[B]], i32 111721// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[B]], i32 211722// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[B]], i32 311723// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>11724// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>11725// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>11726// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>11727// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])11728// CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]]11729//11730int32x4_t test_vmull_n_s16(int16x4_t a, int16_t b) {11731 return vmull_n_s16(a, b);11732}11733 11734// CHECK-LABEL: define <2 x i64> @test_vmull_n_s32(11735// CHECK-SAME: <2 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {11736// CHECK-NEXT: [[ENTRY:.*:]]11737// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i32 011738// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[B]], i32 111739// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>11740// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>11741// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>11742// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>11743// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])11744// CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]]11745//11746int64x2_t test_vmull_n_s32(int32x2_t a, int32_t b) {11747 return vmull_n_s32(a, b);11748}11749 11750// CHECK-LABEL: define <4 x i32> @test_vmull_n_u16(11751// CHECK-SAME: <4 x i16> noundef [[A:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {11752// CHECK-NEXT: [[ENTRY:.*:]]11753// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i32 011754// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[B]], i32 111755// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[B]], i32 211756// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[B]], i32 311757// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>11758// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>11759// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>11760// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>11761// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]])11762// CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]]11763//11764uint32x4_t test_vmull_n_u16(uint16x4_t a, uint16_t b) {11765 return vmull_n_u16(a, b);11766}11767 11768// CHECK-LABEL: define <2 x i64> @test_vmull_n_u32(11769// CHECK-SAME: <2 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {11770// CHECK-NEXT: [[ENTRY:.*:]]11771// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i32 011772// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[B]], i32 111773// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>11774// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>11775// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>11776// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>11777// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]])11778// CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]]11779//11780uint64x2_t test_vmull_n_u32(uint32x2_t a, uint32_t b) {11781 return vmull_n_u32(a, b);11782}11783 11784// CHECK-LABEL: define <8 x i8> @test_vmul_p8(11785// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {11786// CHECK-NEXT: [[ENTRY:.*:]]11787// CHECK-NEXT: [[VMUL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])11788// CHECK-NEXT: ret <8 x i8> [[VMUL_V_I]]11789//11790poly8x8_t test_vmul_p8(poly8x8_t a, poly8x8_t b) {11791 return vmul_p8(a, b);11792}11793 11794// CHECK-LABEL: define <16 x i8> @test_vmulq_p8(11795// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {11796// CHECK-NEXT: [[ENTRY:.*:]]11797// CHECK-NEXT: [[VMULQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])11798// CHECK-NEXT: ret <16 x i8> [[VMULQ_V_I]]11799//11800poly8x16_t test_vmulq_p8(poly8x16_t a, poly8x16_t b) {11801 return vmulq_p8(a, b);11802}11803 11804// CHECK-LABEL: define <4 x i16> @test_vmul_lane_s16(11805// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11806// CHECK-NEXT: [[ENTRY:.*:]]11807// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>11808// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>11809// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>11810// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i16> [[A]], [[LANE]]11811// CHECK-NEXT: ret <4 x i16> [[MUL]]11812//11813int16x4_t test_vmul_lane_s16(int16x4_t a, int16x4_t b) {11814 return vmul_lane_s16(a, b, 3);11815}11816 11817// CHECK-LABEL: define <2 x i32> @test_vmul_lane_s32(11818// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11819// CHECK-NEXT: [[ENTRY:.*:]]11820// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>11821// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>11822// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>11823// CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[A]], [[LANE]]11824// CHECK-NEXT: ret <2 x i32> [[MUL]]11825//11826int32x2_t test_vmul_lane_s32(int32x2_t a, int32x2_t b) {11827 return vmul_lane_s32(a, b, 1);11828}11829 11830// CHECK-LABEL: define <2 x float> @test_vmul_lane_f32(11831// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {11832// CHECK-NEXT: [[ENTRY:.*:]]11833// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>11834// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>11835// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>11836// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <2 x i32> <i32 1, i32 1>11837// CHECK-NEXT: [[MUL:%.*]] = fmul <2 x float> [[A]], [[LANE]]11838// CHECK-NEXT: ret <2 x float> [[MUL]]11839//11840float32x2_t test_vmul_lane_f32(float32x2_t a, float32x2_t b) {11841 return vmul_lane_f32(a, b, 1);11842}11843 11844// CHECK-LABEL: define <4 x i16> @test_vmul_lane_u16(11845// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11846// CHECK-NEXT: [[ENTRY:.*:]]11847// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>11848// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>11849// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>11850// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i16> [[A]], [[LANE]]11851// CHECK-NEXT: ret <4 x i16> [[MUL]]11852//11853uint16x4_t test_vmul_lane_u16(uint16x4_t a, uint16x4_t b) {11854 return vmul_lane_u16(a, b, 3);11855}11856 11857// CHECK-LABEL: define <2 x i32> @test_vmul_lane_u32(11858// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11859// CHECK-NEXT: [[ENTRY:.*:]]11860// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>11861// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>11862// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>11863// CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[A]], [[LANE]]11864// CHECK-NEXT: ret <2 x i32> [[MUL]]11865//11866uint32x2_t test_vmul_lane_u32(uint32x2_t a, uint32x2_t b) {11867 return vmul_lane_u32(a, b, 1);11868}11869 11870// CHECK-LABEL: define <8 x i16> @test_vmulq_lane_s16(11871// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11872// CHECK-NEXT: [[ENTRY:.*:]]11873// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>11874// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>11875// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>11876// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i16> [[A]], [[LANE]]11877// CHECK-NEXT: ret <8 x i16> [[MUL]]11878//11879int16x8_t test_vmulq_lane_s16(int16x8_t a, int16x4_t b) {11880 return vmulq_lane_s16(a, b, 3);11881}11882 11883// CHECK-LABEL: define <4 x i32> @test_vmulq_lane_s32(11884// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11885// CHECK-NEXT: [[ENTRY:.*:]]11886// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>11887// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>11888// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>11889// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[A]], [[LANE]]11890// CHECK-NEXT: ret <4 x i32> [[MUL]]11891//11892int32x4_t test_vmulq_lane_s32(int32x4_t a, int32x2_t b) {11893 return vmulq_lane_s32(a, b, 1);11894}11895 11896// CHECK-LABEL: define <4 x float> @test_vmulq_lane_f32(11897// CHECK-SAME: <4 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {11898// CHECK-NEXT: [[ENTRY:.*:]]11899// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>11900// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>11901// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>11902// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP2]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>11903// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x float> [[A]], [[LANE]]11904// CHECK-NEXT: ret <4 x float> [[MUL]]11905//11906float32x4_t test_vmulq_lane_f32(float32x4_t a, float32x2_t b) {11907 return vmulq_lane_f32(a, b, 1);11908}11909 11910// CHECK-LABEL: define <8 x i16> @test_vmulq_lane_u16(11911// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {11912// CHECK-NEXT: [[ENTRY:.*:]]11913// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>11914// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>11915// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>11916// CHECK-NEXT: [[MUL:%.*]] = mul <8 x i16> [[A]], [[LANE]]11917// CHECK-NEXT: ret <8 x i16> [[MUL]]11918//11919uint16x8_t test_vmulq_lane_u16(uint16x8_t a, uint16x4_t b) {11920 return vmulq_lane_u16(a, b, 3);11921}11922 11923// CHECK-LABEL: define <4 x i32> @test_vmulq_lane_u32(11924// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {11925// CHECK-NEXT: [[ENTRY:.*:]]11926// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>11927// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>11928// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>11929// CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[A]], [[LANE]]11930// CHECK-NEXT: ret <4 x i32> [[MUL]]11931//11932uint32x4_t test_vmulq_lane_u32(uint32x4_t a, uint32x2_t b) {11933 return vmulq_lane_u32(a, b, 1);11934}11935 11936// CHECK-LABEL: define <4 x i16> @test_vmul_n_s16(11937// CHECK-SAME: <4 x i16> noundef [[A:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {11938// CHECK-NEXT: [[ENTRY:.*:]]11939// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i32 011940// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[B]], i32 111941// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[B]], i32 211942// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[B]], i32 311943// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[A]], [[VECINIT3_I]]11944// CHECK-NEXT: ret <4 x i16> [[MUL_I]]11945//11946int16x4_t test_vmul_n_s16(int16x4_t a, int16_t b) {11947 return vmul_n_s16(a, b);11948}11949 11950// CHECK-LABEL: define <2 x i32> @test_vmul_n_s32(11951// CHECK-SAME: <2 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {11952// CHECK-NEXT: [[ENTRY:.*:]]11953// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i32 011954// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[B]], i32 111955// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[A]], [[VECINIT1_I]]11956// CHECK-NEXT: ret <2 x i32> [[MUL_I]]11957//11958int32x2_t test_vmul_n_s32(int32x2_t a, int32_t b) {11959 return vmul_n_s32(a, b);11960}11961 11962// CHECK-LABEL: define <2 x float> @test_vmul_n_f32(11963// CHECK-SAME: <2 x float> noundef [[A:%.*]], float noundef [[B:%.*]]) #[[ATTR0]] {11964// CHECK-NEXT: [[ENTRY:.*:]]11965// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x float> poison, float [[B]], i32 011966// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float [[B]], i32 111967// CHECK-NEXT: [[MUL_I:%.*]] = fmul <2 x float> [[A]], [[VECINIT1_I]]11968// CHECK-NEXT: ret <2 x float> [[MUL_I]]11969//11970float32x2_t test_vmul_n_f32(float32x2_t a, float32_t b) {11971 return vmul_n_f32(a, b);11972}11973 11974// CHECK-LABEL: define <4 x i16> @test_vmul_n_u16(11975// CHECK-SAME: <4 x i16> noundef [[A:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {11976// CHECK-NEXT: [[ENTRY:.*:]]11977// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i32 011978// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[B]], i32 111979// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[B]], i32 211980// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[B]], i32 311981// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i16> [[A]], [[VECINIT3_I]]11982// CHECK-NEXT: ret <4 x i16> [[MUL_I]]11983//11984uint16x4_t test_vmul_n_u16(uint16x4_t a, uint16_t b) {11985 return vmul_n_u16(a, b);11986}11987 11988// CHECK-LABEL: define <2 x i32> @test_vmul_n_u32(11989// CHECK-SAME: <2 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {11990// CHECK-NEXT: [[ENTRY:.*:]]11991// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i32 011992// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[B]], i32 111993// CHECK-NEXT: [[MUL_I:%.*]] = mul <2 x i32> [[A]], [[VECINIT1_I]]11994// CHECK-NEXT: ret <2 x i32> [[MUL_I]]11995//11996uint32x2_t test_vmul_n_u32(uint32x2_t a, uint32_t b) {11997 return vmul_n_u32(a, b);11998}11999 12000// CHECK-LABEL: define <8 x i16> @test_vmulq_n_s16(12001// CHECK-SAME: <8 x i16> noundef [[A:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {12002// CHECK-NEXT: [[ENTRY:.*:]]12003// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[B]], i32 012004// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[B]], i32 112005// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[B]], i32 212006// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[B]], i32 312007// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[B]], i32 412008// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[B]], i32 512009// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[B]], i32 612010// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[B]], i32 712011// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[A]], [[VECINIT7_I]]12012// CHECK-NEXT: ret <8 x i16> [[MUL_I]]12013//12014int16x8_t test_vmulq_n_s16(int16x8_t a, int16_t b) {12015 return vmulq_n_s16(a, b);12016}12017 12018// CHECK-LABEL: define <4 x i32> @test_vmulq_n_s32(12019// CHECK-SAME: <4 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {12020// CHECK-NEXT: [[ENTRY:.*:]]12021// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[B]], i32 012022// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[B]], i32 112023// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[B]], i32 212024// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[B]], i32 312025// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[A]], [[VECINIT3_I]]12026// CHECK-NEXT: ret <4 x i32> [[MUL_I]]12027//12028int32x4_t test_vmulq_n_s32(int32x4_t a, int32_t b) {12029 return vmulq_n_s32(a, b);12030}12031 12032// CHECK-LABEL: define <4 x float> @test_vmulq_n_f32(12033// CHECK-SAME: <4 x float> noundef [[A:%.*]], float noundef [[B:%.*]]) #[[ATTR0]] {12034// CHECK-NEXT: [[ENTRY:.*:]]12035// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[B]], i32 012036// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[B]], i32 112037// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[B]], i32 212038// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[B]], i32 312039// CHECK-NEXT: [[MUL_I:%.*]] = fmul <4 x float> [[A]], [[VECINIT3_I]]12040// CHECK-NEXT: ret <4 x float> [[MUL_I]]12041//12042float32x4_t test_vmulq_n_f32(float32x4_t a, float32_t b) {12043 return vmulq_n_f32(a, b);12044}12045 12046// CHECK-LABEL: define <8 x i16> @test_vmulq_n_u16(12047// CHECK-SAME: <8 x i16> noundef [[A:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {12048// CHECK-NEXT: [[ENTRY:.*:]]12049// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[B]], i32 012050// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[B]], i32 112051// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[B]], i32 212052// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[B]], i32 312053// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[B]], i32 412054// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[B]], i32 512055// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[B]], i32 612056// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[B]], i32 712057// CHECK-NEXT: [[MUL_I:%.*]] = mul <8 x i16> [[A]], [[VECINIT7_I]]12058// CHECK-NEXT: ret <8 x i16> [[MUL_I]]12059//12060uint16x8_t test_vmulq_n_u16(uint16x8_t a, uint16_t b) {12061 return vmulq_n_u16(a, b);12062}12063 12064// CHECK-LABEL: define <4 x i32> @test_vmulq_n_u32(12065// CHECK-SAME: <4 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {12066// CHECK-NEXT: [[ENTRY:.*:]]12067// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[B]], i32 012068// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[B]], i32 112069// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[B]], i32 212070// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[B]], i32 312071// CHECK-NEXT: [[MUL_I:%.*]] = mul <4 x i32> [[A]], [[VECINIT3_I]]12072// CHECK-NEXT: ret <4 x i32> [[MUL_I]]12073//12074uint32x4_t test_vmulq_n_u32(uint32x4_t a, uint32_t b) {12075 return vmulq_n_u32(a, b);12076}12077 12078// CHECK-LABEL: define <8 x i8> @test_vmvn_s8(12079// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12080// CHECK-NEXT: [[ENTRY:.*:]]12081// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[A]], splat (i8 -1)12082// CHECK-NEXT: ret <8 x i8> [[NOT_I]]12083//12084int8x8_t test_vmvn_s8(int8x8_t a) {12085 return vmvn_s8(a);12086}12087 12088// CHECK-LABEL: define <4 x i16> @test_vmvn_s16(12089// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {12090// CHECK-NEXT: [[ENTRY:.*:]]12091// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[A]], splat (i16 -1)12092// CHECK-NEXT: ret <4 x i16> [[NOT_I]]12093//12094int16x4_t test_vmvn_s16(int16x4_t a) {12095 return vmvn_s16(a);12096}12097 12098// CHECK-LABEL: define <2 x i32> @test_vmvn_s32(12099// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {12100// CHECK-NEXT: [[ENTRY:.*:]]12101// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[A]], splat (i32 -1)12102// CHECK-NEXT: ret <2 x i32> [[NOT_I]]12103//12104int32x2_t test_vmvn_s32(int32x2_t a) {12105 return vmvn_s32(a);12106}12107 12108// CHECK-LABEL: define <8 x i8> @test_vmvn_u8(12109// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12110// CHECK-NEXT: [[ENTRY:.*:]]12111// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[A]], splat (i8 -1)12112// CHECK-NEXT: ret <8 x i8> [[NOT_I]]12113//12114uint8x8_t test_vmvn_u8(uint8x8_t a) {12115 return vmvn_u8(a);12116}12117 12118// CHECK-LABEL: define <4 x i16> @test_vmvn_u16(12119// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {12120// CHECK-NEXT: [[ENTRY:.*:]]12121// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[A]], splat (i16 -1)12122// CHECK-NEXT: ret <4 x i16> [[NOT_I]]12123//12124uint16x4_t test_vmvn_u16(uint16x4_t a) {12125 return vmvn_u16(a);12126}12127 12128// CHECK-LABEL: define <2 x i32> @test_vmvn_u32(12129// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {12130// CHECK-NEXT: [[ENTRY:.*:]]12131// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[A]], splat (i32 -1)12132// CHECK-NEXT: ret <2 x i32> [[NOT_I]]12133//12134uint32x2_t test_vmvn_u32(uint32x2_t a) {12135 return vmvn_u32(a);12136}12137 12138// CHECK-LABEL: define <8 x i8> @test_vmvn_p8(12139// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12140// CHECK-NEXT: [[ENTRY:.*:]]12141// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[A]], splat (i8 -1)12142// CHECK-NEXT: ret <8 x i8> [[NOT_I]]12143//12144poly8x8_t test_vmvn_p8(poly8x8_t a) {12145 return vmvn_p8(a);12146}12147 12148// CHECK-LABEL: define <16 x i8> @test_vmvnq_s8(12149// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12150// CHECK-NEXT: [[ENTRY:.*:]]12151// CHECK-NEXT: [[NOT_I:%.*]] = xor <16 x i8> [[A]], splat (i8 -1)12152// CHECK-NEXT: ret <16 x i8> [[NOT_I]]12153//12154int8x16_t test_vmvnq_s8(int8x16_t a) {12155 return vmvnq_s8(a);12156}12157 12158// CHECK-LABEL: define <8 x i16> @test_vmvnq_s16(12159// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {12160// CHECK-NEXT: [[ENTRY:.*:]]12161// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i16> [[A]], splat (i16 -1)12162// CHECK-NEXT: ret <8 x i16> [[NOT_I]]12163//12164int16x8_t test_vmvnq_s16(int16x8_t a) {12165 return vmvnq_s16(a);12166}12167 12168// CHECK-LABEL: define <4 x i32> @test_vmvnq_s32(12169// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {12170// CHECK-NEXT: [[ENTRY:.*:]]12171// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i32> [[A]], splat (i32 -1)12172// CHECK-NEXT: ret <4 x i32> [[NOT_I]]12173//12174int32x4_t test_vmvnq_s32(int32x4_t a) {12175 return vmvnq_s32(a);12176}12177 12178// CHECK-LABEL: define <16 x i8> @test_vmvnq_u8(12179// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12180// CHECK-NEXT: [[ENTRY:.*:]]12181// CHECK-NEXT: [[NOT_I:%.*]] = xor <16 x i8> [[A]], splat (i8 -1)12182// CHECK-NEXT: ret <16 x i8> [[NOT_I]]12183//12184uint8x16_t test_vmvnq_u8(uint8x16_t a) {12185 return vmvnq_u8(a);12186}12187 12188// CHECK-LABEL: define <8 x i16> @test_vmvnq_u16(12189// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {12190// CHECK-NEXT: [[ENTRY:.*:]]12191// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i16> [[A]], splat (i16 -1)12192// CHECK-NEXT: ret <8 x i16> [[NOT_I]]12193//12194uint16x8_t test_vmvnq_u16(uint16x8_t a) {12195 return vmvnq_u16(a);12196}12197 12198// CHECK-LABEL: define <4 x i32> @test_vmvnq_u32(12199// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {12200// CHECK-NEXT: [[ENTRY:.*:]]12201// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i32> [[A]], splat (i32 -1)12202// CHECK-NEXT: ret <4 x i32> [[NOT_I]]12203//12204uint32x4_t test_vmvnq_u32(uint32x4_t a) {12205 return vmvnq_u32(a);12206}12207 12208// CHECK-LABEL: define <16 x i8> @test_vmvnq_p8(12209// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12210// CHECK-NEXT: [[ENTRY:.*:]]12211// CHECK-NEXT: [[NOT_I:%.*]] = xor <16 x i8> [[A]], splat (i8 -1)12212// CHECK-NEXT: ret <16 x i8> [[NOT_I]]12213//12214poly8x16_t test_vmvnq_p8(poly8x16_t a) {12215 return vmvnq_p8(a);12216}12217 12218// CHECK-LABEL: define <8 x i8> @test_vneg_s8(12219// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12220// CHECK-NEXT: [[ENTRY:.*:]]12221// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i8> zeroinitializer, [[A]]12222// CHECK-NEXT: ret <8 x i8> [[SUB_I]]12223//12224int8x8_t test_vneg_s8(int8x8_t a) {12225 return vneg_s8(a);12226}12227 12228// CHECK-LABEL: define <4 x i16> @test_vneg_s16(12229// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {12230// CHECK-NEXT: [[ENTRY:.*:]]12231// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> zeroinitializer, [[A]]12232// CHECK-NEXT: ret <4 x i16> [[SUB_I]]12233//12234int16x4_t test_vneg_s16(int16x4_t a) {12235 return vneg_s16(a);12236}12237 12238// CHECK-LABEL: define <2 x i32> @test_vneg_s32(12239// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {12240// CHECK-NEXT: [[ENTRY:.*:]]12241// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> zeroinitializer, [[A]]12242// CHECK-NEXT: ret <2 x i32> [[SUB_I]]12243//12244int32x2_t test_vneg_s32(int32x2_t a) {12245 return vneg_s32(a);12246}12247 12248// CHECK-LABEL: define <2 x float> @test_vneg_f32(12249// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {12250// CHECK-NEXT: [[ENTRY:.*:]]12251// CHECK-NEXT: [[FNEG_I:%.*]] = fneg <2 x float> [[A]]12252// CHECK-NEXT: ret <2 x float> [[FNEG_I]]12253//12254float32x2_t test_vneg_f32(float32x2_t a) {12255 return vneg_f32(a);12256}12257 12258// CHECK-LABEL: define <16 x i8> @test_vnegq_s8(12259// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12260// CHECK-NEXT: [[ENTRY:.*:]]12261// CHECK-NEXT: [[SUB_I:%.*]] = sub <16 x i8> zeroinitializer, [[A]]12262// CHECK-NEXT: ret <16 x i8> [[SUB_I]]12263//12264int8x16_t test_vnegq_s8(int8x16_t a) {12265 return vnegq_s8(a);12266}12267 12268// CHECK-LABEL: define <8 x i16> @test_vnegq_s16(12269// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {12270// CHECK-NEXT: [[ENTRY:.*:]]12271// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i16> zeroinitializer, [[A]]12272// CHECK-NEXT: ret <8 x i16> [[SUB_I]]12273//12274int16x8_t test_vnegq_s16(int16x8_t a) {12275 return vnegq_s16(a);12276}12277 12278// CHECK-LABEL: define <4 x i32> @test_vnegq_s32(12279// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {12280// CHECK-NEXT: [[ENTRY:.*:]]12281// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> zeroinitializer, [[A]]12282// CHECK-NEXT: ret <4 x i32> [[SUB_I]]12283//12284int32x4_t test_vnegq_s32(int32x4_t a) {12285 return vnegq_s32(a);12286}12287 12288// CHECK-LABEL: define <4 x float> @test_vnegq_f32(12289// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {12290// CHECK-NEXT: [[ENTRY:.*:]]12291// CHECK-NEXT: [[FNEG_I:%.*]] = fneg <4 x float> [[A]]12292// CHECK-NEXT: ret <4 x float> [[FNEG_I]]12293//12294float32x4_t test_vnegq_f32(float32x4_t a) {12295 return vnegq_f32(a);12296}12297 12298// CHECK-LABEL: define <8 x i8> @test_vorn_s8(12299// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12300// CHECK-NEXT: [[ENTRY:.*:]]12301// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[B]], splat (i8 -1)12302// CHECK-NEXT: [[OR_I:%.*]] = or <8 x i8> [[A]], [[NOT_I]]12303// CHECK-NEXT: ret <8 x i8> [[OR_I]]12304//12305int8x8_t test_vorn_s8(int8x8_t a, int8x8_t b) {12306 return vorn_s8(a, b);12307}12308 12309// CHECK-LABEL: define <4 x i16> @test_vorn_s16(12310// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12311// CHECK-NEXT: [[ENTRY:.*:]]12312// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[B]], splat (i16 -1)12313// CHECK-NEXT: [[OR_I:%.*]] = or <4 x i16> [[A]], [[NOT_I]]12314// CHECK-NEXT: ret <4 x i16> [[OR_I]]12315//12316int16x4_t test_vorn_s16(int16x4_t a, int16x4_t b) {12317 return vorn_s16(a, b);12318}12319 12320// CHECK-LABEL: define <2 x i32> @test_vorn_s32(12321// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12322// CHECK-NEXT: [[ENTRY:.*:]]12323// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[B]], splat (i32 -1)12324// CHECK-NEXT: [[OR_I:%.*]] = or <2 x i32> [[A]], [[NOT_I]]12325// CHECK-NEXT: ret <2 x i32> [[OR_I]]12326//12327int32x2_t test_vorn_s32(int32x2_t a, int32x2_t b) {12328 return vorn_s32(a, b);12329}12330 12331// CHECK-LABEL: define <1 x i64> @test_vorn_s64(12332// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {12333// CHECK-NEXT: [[ENTRY:.*:]]12334// CHECK-NEXT: [[NOT_I:%.*]] = xor <1 x i64> [[B]], splat (i64 -1)12335// CHECK-NEXT: [[OR_I:%.*]] = or <1 x i64> [[A]], [[NOT_I]]12336// CHECK-NEXT: ret <1 x i64> [[OR_I]]12337//12338int64x1_t test_vorn_s64(int64x1_t a, int64x1_t b) {12339 return vorn_s64(a, b);12340}12341 12342// CHECK-LABEL: define <8 x i8> @test_vorn_u8(12343// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12344// CHECK-NEXT: [[ENTRY:.*:]]12345// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[B]], splat (i8 -1)12346// CHECK-NEXT: [[OR_I:%.*]] = or <8 x i8> [[A]], [[NOT_I]]12347// CHECK-NEXT: ret <8 x i8> [[OR_I]]12348//12349uint8x8_t test_vorn_u8(uint8x8_t a, uint8x8_t b) {12350 return vorn_u8(a, b);12351}12352 12353// CHECK-LABEL: define <4 x i16> @test_vorn_u16(12354// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12355// CHECK-NEXT: [[ENTRY:.*:]]12356// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[B]], splat (i16 -1)12357// CHECK-NEXT: [[OR_I:%.*]] = or <4 x i16> [[A]], [[NOT_I]]12358// CHECK-NEXT: ret <4 x i16> [[OR_I]]12359//12360uint16x4_t test_vorn_u16(uint16x4_t a, uint16x4_t b) {12361 return vorn_u16(a, b);12362}12363 12364// CHECK-LABEL: define <2 x i32> @test_vorn_u32(12365// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12366// CHECK-NEXT: [[ENTRY:.*:]]12367// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[B]], splat (i32 -1)12368// CHECK-NEXT: [[OR_I:%.*]] = or <2 x i32> [[A]], [[NOT_I]]12369// CHECK-NEXT: ret <2 x i32> [[OR_I]]12370//12371uint32x2_t test_vorn_u32(uint32x2_t a, uint32x2_t b) {12372 return vorn_u32(a, b);12373}12374 12375// CHECK-LABEL: define <1 x i64> @test_vorn_u64(12376// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {12377// CHECK-NEXT: [[ENTRY:.*:]]12378// CHECK-NEXT: [[NOT_I:%.*]] = xor <1 x i64> [[B]], splat (i64 -1)12379// CHECK-NEXT: [[OR_I:%.*]] = or <1 x i64> [[A]], [[NOT_I]]12380// CHECK-NEXT: ret <1 x i64> [[OR_I]]12381//12382uint64x1_t test_vorn_u64(uint64x1_t a, uint64x1_t b) {12383 return vorn_u64(a, b);12384}12385 12386// CHECK-LABEL: define <16 x i8> @test_vornq_s8(12387// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12388// CHECK-NEXT: [[ENTRY:.*:]]12389// CHECK-NEXT: [[NOT_I:%.*]] = xor <16 x i8> [[B]], splat (i8 -1)12390// CHECK-NEXT: [[OR_I:%.*]] = or <16 x i8> [[A]], [[NOT_I]]12391// CHECK-NEXT: ret <16 x i8> [[OR_I]]12392//12393int8x16_t test_vornq_s8(int8x16_t a, int8x16_t b) {12394 return vornq_s8(a, b);12395}12396 12397// CHECK-LABEL: define <8 x i16> @test_vornq_s16(12398// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12399// CHECK-NEXT: [[ENTRY:.*:]]12400// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i16> [[B]], splat (i16 -1)12401// CHECK-NEXT: [[OR_I:%.*]] = or <8 x i16> [[A]], [[NOT_I]]12402// CHECK-NEXT: ret <8 x i16> [[OR_I]]12403//12404int16x8_t test_vornq_s16(int16x8_t a, int16x8_t b) {12405 return vornq_s16(a, b);12406}12407 12408// CHECK-LABEL: define <4 x i32> @test_vornq_s32(12409// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12410// CHECK-NEXT: [[ENTRY:.*:]]12411// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i32> [[B]], splat (i32 -1)12412// CHECK-NEXT: [[OR_I:%.*]] = or <4 x i32> [[A]], [[NOT_I]]12413// CHECK-NEXT: ret <4 x i32> [[OR_I]]12414//12415int32x4_t test_vornq_s32(int32x4_t a, int32x4_t b) {12416 return vornq_s32(a, b);12417}12418 12419// CHECK-LABEL: define <2 x i64> @test_vornq_s64(12420// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {12421// CHECK-NEXT: [[ENTRY:.*:]]12422// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i64> [[B]], splat (i64 -1)12423// CHECK-NEXT: [[OR_I:%.*]] = or <2 x i64> [[A]], [[NOT_I]]12424// CHECK-NEXT: ret <2 x i64> [[OR_I]]12425//12426int64x2_t test_vornq_s64(int64x2_t a, int64x2_t b) {12427 return vornq_s64(a, b);12428}12429 12430// CHECK-LABEL: define <16 x i8> @test_vornq_u8(12431// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12432// CHECK-NEXT: [[ENTRY:.*:]]12433// CHECK-NEXT: [[NOT_I:%.*]] = xor <16 x i8> [[B]], splat (i8 -1)12434// CHECK-NEXT: [[OR_I:%.*]] = or <16 x i8> [[A]], [[NOT_I]]12435// CHECK-NEXT: ret <16 x i8> [[OR_I]]12436//12437uint8x16_t test_vornq_u8(uint8x16_t a, uint8x16_t b) {12438 return vornq_u8(a, b);12439}12440 12441// CHECK-LABEL: define <8 x i16> @test_vornq_u16(12442// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12443// CHECK-NEXT: [[ENTRY:.*:]]12444// CHECK-NEXT: [[NOT_I:%.*]] = xor <8 x i16> [[B]], splat (i16 -1)12445// CHECK-NEXT: [[OR_I:%.*]] = or <8 x i16> [[A]], [[NOT_I]]12446// CHECK-NEXT: ret <8 x i16> [[OR_I]]12447//12448uint16x8_t test_vornq_u16(uint16x8_t a, uint16x8_t b) {12449 return vornq_u16(a, b);12450}12451 12452// CHECK-LABEL: define <4 x i32> @test_vornq_u32(12453// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12454// CHECK-NEXT: [[ENTRY:.*:]]12455// CHECK-NEXT: [[NOT_I:%.*]] = xor <4 x i32> [[B]], splat (i32 -1)12456// CHECK-NEXT: [[OR_I:%.*]] = or <4 x i32> [[A]], [[NOT_I]]12457// CHECK-NEXT: ret <4 x i32> [[OR_I]]12458//12459uint32x4_t test_vornq_u32(uint32x4_t a, uint32x4_t b) {12460 return vornq_u32(a, b);12461}12462 12463// CHECK-LABEL: define <2 x i64> @test_vornq_u64(12464// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {12465// CHECK-NEXT: [[ENTRY:.*:]]12466// CHECK-NEXT: [[NOT_I:%.*]] = xor <2 x i64> [[B]], splat (i64 -1)12467// CHECK-NEXT: [[OR_I:%.*]] = or <2 x i64> [[A]], [[NOT_I]]12468// CHECK-NEXT: ret <2 x i64> [[OR_I]]12469//12470uint64x2_t test_vornq_u64(uint64x2_t a, uint64x2_t b) {12471 return vornq_u64(a, b);12472}12473 12474// CHECK-LABEL: define <8 x i8> @test_vorr_s8(12475// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12476// CHECK-NEXT: [[ENTRY:.*:]]12477// CHECK-NEXT: [[OR_I:%.*]] = or <8 x i8> [[A]], [[B]]12478// CHECK-NEXT: ret <8 x i8> [[OR_I]]12479//12480int8x8_t test_vorr_s8(int8x8_t a, int8x8_t b) {12481 return vorr_s8(a, b);12482}12483 12484// CHECK-LABEL: define <4 x i16> @test_vorr_s16(12485// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12486// CHECK-NEXT: [[ENTRY:.*:]]12487// CHECK-NEXT: [[OR_I:%.*]] = or <4 x i16> [[A]], [[B]]12488// CHECK-NEXT: ret <4 x i16> [[OR_I]]12489//12490int16x4_t test_vorr_s16(int16x4_t a, int16x4_t b) {12491 return vorr_s16(a, b);12492}12493 12494// CHECK-LABEL: define <2 x i32> @test_vorr_s32(12495// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12496// CHECK-NEXT: [[ENTRY:.*:]]12497// CHECK-NEXT: [[OR_I:%.*]] = or <2 x i32> [[A]], [[B]]12498// CHECK-NEXT: ret <2 x i32> [[OR_I]]12499//12500int32x2_t test_vorr_s32(int32x2_t a, int32x2_t b) {12501 return vorr_s32(a, b);12502}12503 12504// CHECK-LABEL: define <1 x i64> @test_vorr_s64(12505// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {12506// CHECK-NEXT: [[ENTRY:.*:]]12507// CHECK-NEXT: [[OR_I:%.*]] = or <1 x i64> [[A]], [[B]]12508// CHECK-NEXT: ret <1 x i64> [[OR_I]]12509//12510int64x1_t test_vorr_s64(int64x1_t a, int64x1_t b) {12511 return vorr_s64(a, b);12512}12513 12514// CHECK-LABEL: define <8 x i8> @test_vorr_u8(12515// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12516// CHECK-NEXT: [[ENTRY:.*:]]12517// CHECK-NEXT: [[OR_I:%.*]] = or <8 x i8> [[A]], [[B]]12518// CHECK-NEXT: ret <8 x i8> [[OR_I]]12519//12520uint8x8_t test_vorr_u8(uint8x8_t a, uint8x8_t b) {12521 return vorr_u8(a, b);12522}12523 12524// CHECK-LABEL: define <4 x i16> @test_vorr_u16(12525// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12526// CHECK-NEXT: [[ENTRY:.*:]]12527// CHECK-NEXT: [[OR_I:%.*]] = or <4 x i16> [[A]], [[B]]12528// CHECK-NEXT: ret <4 x i16> [[OR_I]]12529//12530uint16x4_t test_vorr_u16(uint16x4_t a, uint16x4_t b) {12531 return vorr_u16(a, b);12532}12533 12534// CHECK-LABEL: define <2 x i32> @test_vorr_u32(12535// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12536// CHECK-NEXT: [[ENTRY:.*:]]12537// CHECK-NEXT: [[OR_I:%.*]] = or <2 x i32> [[A]], [[B]]12538// CHECK-NEXT: ret <2 x i32> [[OR_I]]12539//12540uint32x2_t test_vorr_u32(uint32x2_t a, uint32x2_t b) {12541 return vorr_u32(a, b);12542}12543 12544// CHECK-LABEL: define <1 x i64> @test_vorr_u64(12545// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {12546// CHECK-NEXT: [[ENTRY:.*:]]12547// CHECK-NEXT: [[OR_I:%.*]] = or <1 x i64> [[A]], [[B]]12548// CHECK-NEXT: ret <1 x i64> [[OR_I]]12549//12550uint64x1_t test_vorr_u64(uint64x1_t a, uint64x1_t b) {12551 return vorr_u64(a, b);12552}12553 12554// CHECK-LABEL: define <16 x i8> @test_vorrq_s8(12555// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12556// CHECK-NEXT: [[ENTRY:.*:]]12557// CHECK-NEXT: [[OR_I:%.*]] = or <16 x i8> [[A]], [[B]]12558// CHECK-NEXT: ret <16 x i8> [[OR_I]]12559//12560int8x16_t test_vorrq_s8(int8x16_t a, int8x16_t b) {12561 return vorrq_s8(a, b);12562}12563 12564// CHECK-LABEL: define <8 x i16> @test_vorrq_s16(12565// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12566// CHECK-NEXT: [[ENTRY:.*:]]12567// CHECK-NEXT: [[OR_I:%.*]] = or <8 x i16> [[A]], [[B]]12568// CHECK-NEXT: ret <8 x i16> [[OR_I]]12569//12570int16x8_t test_vorrq_s16(int16x8_t a, int16x8_t b) {12571 return vorrq_s16(a, b);12572}12573 12574// CHECK-LABEL: define <4 x i32> @test_vorrq_s32(12575// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12576// CHECK-NEXT: [[ENTRY:.*:]]12577// CHECK-NEXT: [[OR_I:%.*]] = or <4 x i32> [[A]], [[B]]12578// CHECK-NEXT: ret <4 x i32> [[OR_I]]12579//12580int32x4_t test_vorrq_s32(int32x4_t a, int32x4_t b) {12581 return vorrq_s32(a, b);12582}12583 12584// CHECK-LABEL: define <2 x i64> @test_vorrq_s64(12585// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {12586// CHECK-NEXT: [[ENTRY:.*:]]12587// CHECK-NEXT: [[OR_I:%.*]] = or <2 x i64> [[A]], [[B]]12588// CHECK-NEXT: ret <2 x i64> [[OR_I]]12589//12590int64x2_t test_vorrq_s64(int64x2_t a, int64x2_t b) {12591 return vorrq_s64(a, b);12592}12593 12594// CHECK-LABEL: define <16 x i8> @test_vorrq_u8(12595// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12596// CHECK-NEXT: [[ENTRY:.*:]]12597// CHECK-NEXT: [[OR_I:%.*]] = or <16 x i8> [[A]], [[B]]12598// CHECK-NEXT: ret <16 x i8> [[OR_I]]12599//12600uint8x16_t test_vorrq_u8(uint8x16_t a, uint8x16_t b) {12601 return vorrq_u8(a, b);12602}12603 12604// CHECK-LABEL: define <8 x i16> @test_vorrq_u16(12605// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12606// CHECK-NEXT: [[ENTRY:.*:]]12607// CHECK-NEXT: [[OR_I:%.*]] = or <8 x i16> [[A]], [[B]]12608// CHECK-NEXT: ret <8 x i16> [[OR_I]]12609//12610uint16x8_t test_vorrq_u16(uint16x8_t a, uint16x8_t b) {12611 return vorrq_u16(a, b);12612}12613 12614// CHECK-LABEL: define <4 x i32> @test_vorrq_u32(12615// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12616// CHECK-NEXT: [[ENTRY:.*:]]12617// CHECK-NEXT: [[OR_I:%.*]] = or <4 x i32> [[A]], [[B]]12618// CHECK-NEXT: ret <4 x i32> [[OR_I]]12619//12620uint32x4_t test_vorrq_u32(uint32x4_t a, uint32x4_t b) {12621 return vorrq_u32(a, b);12622}12623 12624// CHECK-LABEL: define <2 x i64> @test_vorrq_u64(12625// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {12626// CHECK-NEXT: [[ENTRY:.*:]]12627// CHECK-NEXT: [[OR_I:%.*]] = or <2 x i64> [[A]], [[B]]12628// CHECK-NEXT: ret <2 x i64> [[OR_I]]12629//12630uint64x2_t test_vorrq_u64(uint64x2_t a, uint64x2_t b) {12631 return vorrq_u64(a, b);12632}12633 12634// CHECK-LABEL: define <4 x i16> @test_vpadal_s8(12635// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12636// CHECK-NEXT: [[ENTRY:.*:]]12637// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>12638// CHECK-NEXT: [[VPADAL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>12639// CHECK-NEXT: [[VPADAL_V1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> [[VPADAL_V_I]], <8 x i8> [[B]])12640// CHECK-NEXT: ret <4 x i16> [[VPADAL_V1_I]]12641//12642int16x4_t test_vpadal_s8(int16x4_t a, int8x8_t b) {12643 return vpadal_s8(a, b);12644}12645 12646// CHECK-LABEL: define <2 x i32> @test_vpadal_s16(12647// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12648// CHECK-NEXT: [[ENTRY:.*:]]12649// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>12650// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>12651// CHECK-NEXT: [[VPADAL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>12652// CHECK-NEXT: [[VPADAL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>12653// CHECK-NEXT: [[VPADAL_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> [[VPADAL_V_I]], <4 x i16> [[VPADAL_V1_I]])12654// CHECK-NEXT: ret <2 x i32> [[VPADAL_V2_I]]12655//12656int32x2_t test_vpadal_s16(int32x2_t a, int16x4_t b) {12657 return vpadal_s16(a, b);12658}12659 12660// CHECK-LABEL: define <1 x i64> @test_vpadal_s32(12661// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12662// CHECK-NEXT: [[ENTRY:.*:]]12663// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>12664// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>12665// CHECK-NEXT: [[VPADAL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>12666// CHECK-NEXT: [[VPADAL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>12667// CHECK-NEXT: [[VPADAL_V2_I:%.*]] = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> [[VPADAL_V_I]], <2 x i32> [[VPADAL_V1_I]])12668// CHECK-NEXT: ret <1 x i64> [[VPADAL_V2_I]]12669//12670int64x1_t test_vpadal_s32(int64x1_t a, int32x2_t b) {12671 return vpadal_s32(a, b);12672}12673 12674// CHECK-LABEL: define <4 x i16> @test_vpadal_u8(12675// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12676// CHECK-NEXT: [[ENTRY:.*:]]12677// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>12678// CHECK-NEXT: [[VPADAL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>12679// CHECK-NEXT: [[VPADAL_V1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> [[VPADAL_V_I]], <8 x i8> [[B]])12680// CHECK-NEXT: ret <4 x i16> [[VPADAL_V1_I]]12681//12682uint16x4_t test_vpadal_u8(uint16x4_t a, uint8x8_t b) {12683 return vpadal_u8(a, b);12684}12685 12686// CHECK-LABEL: define <2 x i32> @test_vpadal_u16(12687// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12688// CHECK-NEXT: [[ENTRY:.*:]]12689// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>12690// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>12691// CHECK-NEXT: [[VPADAL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>12692// CHECK-NEXT: [[VPADAL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>12693// CHECK-NEXT: [[VPADAL_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> [[VPADAL_V_I]], <4 x i16> [[VPADAL_V1_I]])12694// CHECK-NEXT: ret <2 x i32> [[VPADAL_V2_I]]12695//12696uint32x2_t test_vpadal_u16(uint32x2_t a, uint16x4_t b) {12697 return vpadal_u16(a, b);12698}12699 12700// CHECK-LABEL: define <1 x i64> @test_vpadal_u32(12701// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12702// CHECK-NEXT: [[ENTRY:.*:]]12703// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>12704// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>12705// CHECK-NEXT: [[VPADAL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>12706// CHECK-NEXT: [[VPADAL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>12707// CHECK-NEXT: [[VPADAL_V2_I:%.*]] = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> [[VPADAL_V_I]], <2 x i32> [[VPADAL_V1_I]])12708// CHECK-NEXT: ret <1 x i64> [[VPADAL_V2_I]]12709//12710uint64x1_t test_vpadal_u32(uint64x1_t a, uint32x2_t b) {12711 return vpadal_u32(a, b);12712}12713 12714// CHECK-LABEL: define <8 x i16> @test_vpadalq_s8(12715// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12716// CHECK-NEXT: [[ENTRY:.*:]]12717// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>12718// CHECK-NEXT: [[VPADALQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>12719// CHECK-NEXT: [[VPADALQ_V1_I:%.*]] = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> [[VPADALQ_V_I]], <16 x i8> [[B]])12720// CHECK-NEXT: ret <8 x i16> [[VPADALQ_V1_I]]12721//12722int16x8_t test_vpadalq_s8(int16x8_t a, int8x16_t b) {12723 return vpadalq_s8(a, b);12724}12725 12726// CHECK-LABEL: define <4 x i32> @test_vpadalq_s16(12727// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12728// CHECK-NEXT: [[ENTRY:.*:]]12729// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>12730// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>12731// CHECK-NEXT: [[VPADALQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>12732// CHECK-NEXT: [[VPADALQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>12733// CHECK-NEXT: [[VPADALQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> [[VPADALQ_V_I]], <8 x i16> [[VPADALQ_V1_I]])12734// CHECK-NEXT: ret <4 x i32> [[VPADALQ_V2_I]]12735//12736int32x4_t test_vpadalq_s16(int32x4_t a, int16x8_t b) {12737 return vpadalq_s16(a, b);12738}12739 12740// CHECK-LABEL: define <2 x i64> @test_vpadalq_s32(12741// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12742// CHECK-NEXT: [[ENTRY:.*:]]12743// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>12744// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>12745// CHECK-NEXT: [[VPADALQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>12746// CHECK-NEXT: [[VPADALQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>12747// CHECK-NEXT: [[VPADALQ_V2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> [[VPADALQ_V_I]], <4 x i32> [[VPADALQ_V1_I]])12748// CHECK-NEXT: ret <2 x i64> [[VPADALQ_V2_I]]12749//12750int64x2_t test_vpadalq_s32(int64x2_t a, int32x4_t b) {12751 return vpadalq_s32(a, b);12752}12753 12754// CHECK-LABEL: define <8 x i16> @test_vpadalq_u8(12755// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12756// CHECK-NEXT: [[ENTRY:.*:]]12757// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>12758// CHECK-NEXT: [[VPADALQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>12759// CHECK-NEXT: [[VPADALQ_V1_I:%.*]] = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> [[VPADALQ_V_I]], <16 x i8> [[B]])12760// CHECK-NEXT: ret <8 x i16> [[VPADALQ_V1_I]]12761//12762uint16x8_t test_vpadalq_u8(uint16x8_t a, uint8x16_t b) {12763 return vpadalq_u8(a, b);12764}12765 12766// CHECK-LABEL: define <4 x i32> @test_vpadalq_u16(12767// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12768// CHECK-NEXT: [[ENTRY:.*:]]12769// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>12770// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>12771// CHECK-NEXT: [[VPADALQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>12772// CHECK-NEXT: [[VPADALQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>12773// CHECK-NEXT: [[VPADALQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> [[VPADALQ_V_I]], <8 x i16> [[VPADALQ_V1_I]])12774// CHECK-NEXT: ret <4 x i32> [[VPADALQ_V2_I]]12775//12776uint32x4_t test_vpadalq_u16(uint32x4_t a, uint16x8_t b) {12777 return vpadalq_u16(a, b);12778}12779 12780// CHECK-LABEL: define <2 x i64> @test_vpadalq_u32(12781// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12782// CHECK-NEXT: [[ENTRY:.*:]]12783// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>12784// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>12785// CHECK-NEXT: [[VPADALQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>12786// CHECK-NEXT: [[VPADALQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>12787// CHECK-NEXT: [[VPADALQ_V2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> [[VPADALQ_V_I]], <4 x i32> [[VPADALQ_V1_I]])12788// CHECK-NEXT: ret <2 x i64> [[VPADALQ_V2_I]]12789//12790uint64x2_t test_vpadalq_u32(uint64x2_t a, uint32x4_t b) {12791 return vpadalq_u32(a, b);12792}12793 12794// CHECK-LABEL: define <8 x i8> @test_vpadd_s8(12795// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12796// CHECK-NEXT: [[ENTRY:.*:]]12797// CHECK-NEXT: [[VPADD_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])12798// CHECK-NEXT: ret <8 x i8> [[VPADD_V_I]]12799//12800int8x8_t test_vpadd_s8(int8x8_t a, int8x8_t b) {12801 return vpadd_s8(a, b);12802}12803 12804// CHECK-LABEL: define <4 x i16> @test_vpadd_s16(12805// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12806// CHECK-NEXT: [[ENTRY:.*:]]12807// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>12808// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>12809// CHECK-NEXT: [[VPADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>12810// CHECK-NEXT: [[VPADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>12811// CHECK-NEXT: [[VPADD_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> [[VPADD_V_I]], <4 x i16> [[VPADD_V1_I]])12812// CHECK-NEXT: [[VPADD_V3_I:%.*]] = bitcast <4 x i16> [[VPADD_V2_I]] to <8 x i8>12813// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPADD_V3_I]] to <4 x i16>12814// CHECK-NEXT: ret <4 x i16> [[TMP2]]12815//12816int16x4_t test_vpadd_s16(int16x4_t a, int16x4_t b) {12817 return vpadd_s16(a, b);12818}12819 12820// CHECK-LABEL: define <2 x i32> @test_vpadd_s32(12821// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12822// CHECK-NEXT: [[ENTRY:.*:]]12823// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>12824// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>12825// CHECK-NEXT: [[VPADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>12826// CHECK-NEXT: [[VPADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>12827// CHECK-NEXT: [[VPADD_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> [[VPADD_V_I]], <2 x i32> [[VPADD_V1_I]])12828// CHECK-NEXT: [[VPADD_V3_I:%.*]] = bitcast <2 x i32> [[VPADD_V2_I]] to <8 x i8>12829// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPADD_V3_I]] to <2 x i32>12830// CHECK-NEXT: ret <2 x i32> [[TMP2]]12831//12832int32x2_t test_vpadd_s32(int32x2_t a, int32x2_t b) {12833 return vpadd_s32(a, b);12834}12835 12836// CHECK-LABEL: define <8 x i8> @test_vpadd_u8(12837// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {12838// CHECK-NEXT: [[ENTRY:.*:]]12839// CHECK-NEXT: [[VPADD_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])12840// CHECK-NEXT: ret <8 x i8> [[VPADD_V_I]]12841//12842uint8x8_t test_vpadd_u8(uint8x8_t a, uint8x8_t b) {12843 return vpadd_u8(a, b);12844}12845 12846// CHECK-LABEL: define <4 x i16> @test_vpadd_u16(12847// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {12848// CHECK-NEXT: [[ENTRY:.*:]]12849// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>12850// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>12851// CHECK-NEXT: [[VPADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>12852// CHECK-NEXT: [[VPADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>12853// CHECK-NEXT: [[VPADD_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> [[VPADD_V_I]], <4 x i16> [[VPADD_V1_I]])12854// CHECK-NEXT: [[VPADD_V3_I:%.*]] = bitcast <4 x i16> [[VPADD_V2_I]] to <8 x i8>12855// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPADD_V3_I]] to <4 x i16>12856// CHECK-NEXT: ret <4 x i16> [[TMP2]]12857//12858uint16x4_t test_vpadd_u16(uint16x4_t a, uint16x4_t b) {12859 return vpadd_u16(a, b);12860}12861 12862// CHECK-LABEL: define <2 x i32> @test_vpadd_u32(12863// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {12864// CHECK-NEXT: [[ENTRY:.*:]]12865// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>12866// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>12867// CHECK-NEXT: [[VPADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>12868// CHECK-NEXT: [[VPADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>12869// CHECK-NEXT: [[VPADD_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> [[VPADD_V_I]], <2 x i32> [[VPADD_V1_I]])12870// CHECK-NEXT: [[VPADD_V3_I:%.*]] = bitcast <2 x i32> [[VPADD_V2_I]] to <8 x i8>12871// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPADD_V3_I]] to <2 x i32>12872// CHECK-NEXT: ret <2 x i32> [[TMP2]]12873//12874uint32x2_t test_vpadd_u32(uint32x2_t a, uint32x2_t b) {12875 return vpadd_u32(a, b);12876}12877 12878// CHECK-LABEL: define <2 x float> @test_vpadd_f32(12879// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {12880// CHECK-NEXT: [[ENTRY:.*:]]12881// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>12882// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>12883// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>12884// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>12885// CHECK-NEXT: [[VPADD_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>12886// CHECK-NEXT: [[VPADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>12887// CHECK-NEXT: [[VPADD_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> [[VPADD_V_I]], <2 x float> [[VPADD_V1_I]])12888// CHECK-NEXT: [[VPADD_V3_I:%.*]] = bitcast <2 x float> [[VPADD_V2_I]] to <8 x i8>12889// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VPADD_V3_I]] to <2 x i32>12890// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>12891// CHECK-NEXT: ret <2 x float> [[TMP5]]12892//12893float32x2_t test_vpadd_f32(float32x2_t a, float32x2_t b) {12894 return vpadd_f32(a, b);12895}12896 12897// CHECK-LABEL: define <4 x i16> @test_vpaddl_s8(12898// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12899// CHECK-NEXT: [[ENTRY:.*:]]12900// CHECK-NEXT: [[VPADDL_I:%.*]] = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> [[A]])12901// CHECK-NEXT: ret <4 x i16> [[VPADDL_I]]12902//12903int16x4_t test_vpaddl_s8(int8x8_t a) {12904 return vpaddl_s8(a);12905}12906 12907// CHECK-LABEL: define <2 x i32> @test_vpaddl_s16(12908// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {12909// CHECK-NEXT: [[ENTRY:.*:]]12910// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>12911// CHECK-NEXT: [[VPADDL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>12912// CHECK-NEXT: [[VPADDL1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> [[VPADDL_I]])12913// CHECK-NEXT: ret <2 x i32> [[VPADDL1_I]]12914//12915int32x2_t test_vpaddl_s16(int16x4_t a) {12916 return vpaddl_s16(a);12917}12918 12919// CHECK-LABEL: define <1 x i64> @test_vpaddl_s32(12920// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {12921// CHECK-NEXT: [[ENTRY:.*:]]12922// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>12923// CHECK-NEXT: [[VPADDL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>12924// CHECK-NEXT: [[VPADDL1_I:%.*]] = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> [[VPADDL_I]])12925// CHECK-NEXT: ret <1 x i64> [[VPADDL1_I]]12926//12927int64x1_t test_vpaddl_s32(int32x2_t a) {12928 return vpaddl_s32(a);12929}12930 12931// CHECK-LABEL: define <4 x i16> @test_vpaddl_u8(12932// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12933// CHECK-NEXT: [[ENTRY:.*:]]12934// CHECK-NEXT: [[VPADDL_I:%.*]] = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> [[A]])12935// CHECK-NEXT: ret <4 x i16> [[VPADDL_I]]12936//12937uint16x4_t test_vpaddl_u8(uint8x8_t a) {12938 return vpaddl_u8(a);12939}12940 12941// CHECK-LABEL: define <2 x i32> @test_vpaddl_u16(12942// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {12943// CHECK-NEXT: [[ENTRY:.*:]]12944// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>12945// CHECK-NEXT: [[VPADDL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>12946// CHECK-NEXT: [[VPADDL1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> [[VPADDL_I]])12947// CHECK-NEXT: ret <2 x i32> [[VPADDL1_I]]12948//12949uint32x2_t test_vpaddl_u16(uint16x4_t a) {12950 return vpaddl_u16(a);12951}12952 12953// CHECK-LABEL: define <1 x i64> @test_vpaddl_u32(12954// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {12955// CHECK-NEXT: [[ENTRY:.*:]]12956// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>12957// CHECK-NEXT: [[VPADDL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>12958// CHECK-NEXT: [[VPADDL1_I:%.*]] = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> [[VPADDL_I]])12959// CHECK-NEXT: ret <1 x i64> [[VPADDL1_I]]12960//12961uint64x1_t test_vpaddl_u32(uint32x2_t a) {12962 return vpaddl_u32(a);12963}12964 12965// CHECK-LABEL: define <8 x i16> @test_vpaddlq_s8(12966// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {12967// CHECK-NEXT: [[ENTRY:.*:]]12968// CHECK-NEXT: [[VPADDL_I:%.*]] = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> [[A]])12969// CHECK-NEXT: ret <8 x i16> [[VPADDL_I]]12970//12971int16x8_t test_vpaddlq_s8(int8x16_t a) {12972 return vpaddlq_s8(a);12973}12974 12975// CHECK-LABEL: define <4 x i32> @test_vpaddlq_s16(12976// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {12977// CHECK-NEXT: [[ENTRY:.*:]]12978// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>12979// CHECK-NEXT: [[VPADDL_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>12980// CHECK-NEXT: [[VPADDL1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> [[VPADDL_I]])12981// CHECK-NEXT: ret <4 x i32> [[VPADDL1_I]]12982//12983int32x4_t test_vpaddlq_s16(int16x8_t a) {12984 return vpaddlq_s16(a);12985}12986 12987// CHECK-LABEL: define <2 x i64> @test_vpaddlq_s32(12988// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {12989// CHECK-NEXT: [[ENTRY:.*:]]12990// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>12991// CHECK-NEXT: [[VPADDL_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>12992// CHECK-NEXT: [[VPADDL1_I:%.*]] = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> [[VPADDL_I]])12993// CHECK-NEXT: ret <2 x i64> [[VPADDL1_I]]12994//12995int64x2_t test_vpaddlq_s32(int32x4_t a) {12996 return vpaddlq_s32(a);12997}12998 12999// CHECK-LABEL: define <8 x i16> @test_vpaddlq_u8(13000// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {13001// CHECK-NEXT: [[ENTRY:.*:]]13002// CHECK-NEXT: [[VPADDL_I:%.*]] = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> [[A]])13003// CHECK-NEXT: ret <8 x i16> [[VPADDL_I]]13004//13005uint16x8_t test_vpaddlq_u8(uint8x16_t a) {13006 return vpaddlq_u8(a);13007}13008 13009// CHECK-LABEL: define <4 x i32> @test_vpaddlq_u16(13010// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {13011// CHECK-NEXT: [[ENTRY:.*:]]13012// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>13013// CHECK-NEXT: [[VPADDL_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>13014// CHECK-NEXT: [[VPADDL1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> [[VPADDL_I]])13015// CHECK-NEXT: ret <4 x i32> [[VPADDL1_I]]13016//13017uint32x4_t test_vpaddlq_u16(uint16x8_t a) {13018 return vpaddlq_u16(a);13019}13020 13021// CHECK-LABEL: define <2 x i64> @test_vpaddlq_u32(13022// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {13023// CHECK-NEXT: [[ENTRY:.*:]]13024// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13025// CHECK-NEXT: [[VPADDL_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>13026// CHECK-NEXT: [[VPADDL1_I:%.*]] = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> [[VPADDL_I]])13027// CHECK-NEXT: ret <2 x i64> [[VPADDL1_I]]13028//13029uint64x2_t test_vpaddlq_u32(uint32x4_t a) {13030 return vpaddlq_u32(a);13031}13032 13033// CHECK-LABEL: define <8 x i8> @test_vpmax_s8(13034// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {13035// CHECK-NEXT: [[ENTRY:.*:]]13036// CHECK-NEXT: [[VPMAX_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])13037// CHECK-NEXT: ret <8 x i8> [[VPMAX_V_I]]13038//13039int8x8_t test_vpmax_s8(int8x8_t a, int8x8_t b) {13040 return vpmax_s8(a, b);13041}13042 13043// CHECK-LABEL: define <4 x i16> @test_vpmax_s16(13044// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13045// CHECK-NEXT: [[ENTRY:.*:]]13046// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>13047// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13048// CHECK-NEXT: [[VPMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13049// CHECK-NEXT: [[VPMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13050// CHECK-NEXT: [[VPMAX_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> [[VPMAX_V_I]], <4 x i16> [[VPMAX_V1_I]])13051// CHECK-NEXT: [[VPMAX_V3_I:%.*]] = bitcast <4 x i16> [[VPMAX_V2_I]] to <8 x i8>13052// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPMAX_V3_I]] to <4 x i16>13053// CHECK-NEXT: ret <4 x i16> [[TMP2]]13054//13055int16x4_t test_vpmax_s16(int16x4_t a, int16x4_t b) {13056 return vpmax_s16(a, b);13057}13058 13059// CHECK-LABEL: define <2 x i32> @test_vpmax_s32(13060// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13061// CHECK-NEXT: [[ENTRY:.*:]]13062// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>13063// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13064// CHECK-NEXT: [[VPMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13065// CHECK-NEXT: [[VPMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13066// CHECK-NEXT: [[VPMAX_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> [[VPMAX_V_I]], <2 x i32> [[VPMAX_V1_I]])13067// CHECK-NEXT: [[VPMAX_V3_I:%.*]] = bitcast <2 x i32> [[VPMAX_V2_I]] to <8 x i8>13068// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPMAX_V3_I]] to <2 x i32>13069// CHECK-NEXT: ret <2 x i32> [[TMP2]]13070//13071int32x2_t test_vpmax_s32(int32x2_t a, int32x2_t b) {13072 return vpmax_s32(a, b);13073}13074 13075// CHECK-LABEL: define <8 x i8> @test_vpmax_u8(13076// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {13077// CHECK-NEXT: [[ENTRY:.*:]]13078// CHECK-NEXT: [[VPMAX_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])13079// CHECK-NEXT: ret <8 x i8> [[VPMAX_V_I]]13080//13081uint8x8_t test_vpmax_u8(uint8x8_t a, uint8x8_t b) {13082 return vpmax_u8(a, b);13083}13084 13085// CHECK-LABEL: define <4 x i16> @test_vpmax_u16(13086// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13087// CHECK-NEXT: [[ENTRY:.*:]]13088// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>13089// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13090// CHECK-NEXT: [[VPMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13091// CHECK-NEXT: [[VPMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13092// CHECK-NEXT: [[VPMAX_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> [[VPMAX_V_I]], <4 x i16> [[VPMAX_V1_I]])13093// CHECK-NEXT: [[VPMAX_V3_I:%.*]] = bitcast <4 x i16> [[VPMAX_V2_I]] to <8 x i8>13094// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPMAX_V3_I]] to <4 x i16>13095// CHECK-NEXT: ret <4 x i16> [[TMP2]]13096//13097uint16x4_t test_vpmax_u16(uint16x4_t a, uint16x4_t b) {13098 return vpmax_u16(a, b);13099}13100 13101// CHECK-LABEL: define <2 x i32> @test_vpmax_u32(13102// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13103// CHECK-NEXT: [[ENTRY:.*:]]13104// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>13105// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13106// CHECK-NEXT: [[VPMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13107// CHECK-NEXT: [[VPMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13108// CHECK-NEXT: [[VPMAX_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> [[VPMAX_V_I]], <2 x i32> [[VPMAX_V1_I]])13109// CHECK-NEXT: [[VPMAX_V3_I:%.*]] = bitcast <2 x i32> [[VPMAX_V2_I]] to <8 x i8>13110// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPMAX_V3_I]] to <2 x i32>13111// CHECK-NEXT: ret <2 x i32> [[TMP2]]13112//13113uint32x2_t test_vpmax_u32(uint32x2_t a, uint32x2_t b) {13114 return vpmax_u32(a, b);13115}13116 13117// CHECK-LABEL: define <2 x float> @test_vpmax_f32(13118// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {13119// CHECK-NEXT: [[ENTRY:.*:]]13120// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>13121// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>13122// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>13123// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>13124// CHECK-NEXT: [[VPMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>13125// CHECK-NEXT: [[VPMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>13126// CHECK-NEXT: [[VPMAX_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float> [[VPMAX_V_I]], <2 x float> [[VPMAX_V1_I]])13127// CHECK-NEXT: [[VPMAX_V3_I:%.*]] = bitcast <2 x float> [[VPMAX_V2_I]] to <8 x i8>13128// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VPMAX_V3_I]] to <2 x i32>13129// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>13130// CHECK-NEXT: ret <2 x float> [[TMP5]]13131//13132float32x2_t test_vpmax_f32(float32x2_t a, float32x2_t b) {13133 return vpmax_f32(a, b);13134}13135 13136// CHECK-LABEL: define <8 x i8> @test_vpmin_s8(13137// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {13138// CHECK-NEXT: [[ENTRY:.*:]]13139// CHECK-NEXT: [[VPMIN_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])13140// CHECK-NEXT: ret <8 x i8> [[VPMIN_V_I]]13141//13142int8x8_t test_vpmin_s8(int8x8_t a, int8x8_t b) {13143 return vpmin_s8(a, b);13144}13145 13146// CHECK-LABEL: define <4 x i16> @test_vpmin_s16(13147// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13148// CHECK-NEXT: [[ENTRY:.*:]]13149// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>13150// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13151// CHECK-NEXT: [[VPMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13152// CHECK-NEXT: [[VPMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13153// CHECK-NEXT: [[VPMIN_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> [[VPMIN_V_I]], <4 x i16> [[VPMIN_V1_I]])13154// CHECK-NEXT: [[VPMIN_V3_I:%.*]] = bitcast <4 x i16> [[VPMIN_V2_I]] to <8 x i8>13155// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPMIN_V3_I]] to <4 x i16>13156// CHECK-NEXT: ret <4 x i16> [[TMP2]]13157//13158int16x4_t test_vpmin_s16(int16x4_t a, int16x4_t b) {13159 return vpmin_s16(a, b);13160}13161 13162// CHECK-LABEL: define <2 x i32> @test_vpmin_s32(13163// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13164// CHECK-NEXT: [[ENTRY:.*:]]13165// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>13166// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13167// CHECK-NEXT: [[VPMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13168// CHECK-NEXT: [[VPMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13169// CHECK-NEXT: [[VPMIN_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> [[VPMIN_V_I]], <2 x i32> [[VPMIN_V1_I]])13170// CHECK-NEXT: [[VPMIN_V3_I:%.*]] = bitcast <2 x i32> [[VPMIN_V2_I]] to <8 x i8>13171// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPMIN_V3_I]] to <2 x i32>13172// CHECK-NEXT: ret <2 x i32> [[TMP2]]13173//13174int32x2_t test_vpmin_s32(int32x2_t a, int32x2_t b) {13175 return vpmin_s32(a, b);13176}13177 13178// CHECK-LABEL: define <8 x i8> @test_vpmin_u8(13179// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {13180// CHECK-NEXT: [[ENTRY:.*:]]13181// CHECK-NEXT: [[VPMIN_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])13182// CHECK-NEXT: ret <8 x i8> [[VPMIN_V_I]]13183//13184uint8x8_t test_vpmin_u8(uint8x8_t a, uint8x8_t b) {13185 return vpmin_u8(a, b);13186}13187 13188// CHECK-LABEL: define <4 x i16> @test_vpmin_u16(13189// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13190// CHECK-NEXT: [[ENTRY:.*:]]13191// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>13192// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13193// CHECK-NEXT: [[VPMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13194// CHECK-NEXT: [[VPMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13195// CHECK-NEXT: [[VPMIN_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> [[VPMIN_V_I]], <4 x i16> [[VPMIN_V1_I]])13196// CHECK-NEXT: [[VPMIN_V3_I:%.*]] = bitcast <4 x i16> [[VPMIN_V2_I]] to <8 x i8>13197// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPMIN_V3_I]] to <4 x i16>13198// CHECK-NEXT: ret <4 x i16> [[TMP2]]13199//13200uint16x4_t test_vpmin_u16(uint16x4_t a, uint16x4_t b) {13201 return vpmin_u16(a, b);13202}13203 13204// CHECK-LABEL: define <2 x i32> @test_vpmin_u32(13205// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13206// CHECK-NEXT: [[ENTRY:.*:]]13207// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>13208// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13209// CHECK-NEXT: [[VPMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13210// CHECK-NEXT: [[VPMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13211// CHECK-NEXT: [[VPMIN_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> [[VPMIN_V_I]], <2 x i32> [[VPMIN_V1_I]])13212// CHECK-NEXT: [[VPMIN_V3_I:%.*]] = bitcast <2 x i32> [[VPMIN_V2_I]] to <8 x i8>13213// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VPMIN_V3_I]] to <2 x i32>13214// CHECK-NEXT: ret <2 x i32> [[TMP2]]13215//13216uint32x2_t test_vpmin_u32(uint32x2_t a, uint32x2_t b) {13217 return vpmin_u32(a, b);13218}13219 13220// CHECK-LABEL: define <2 x float> @test_vpmin_f32(13221// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {13222// CHECK-NEXT: [[ENTRY:.*:]]13223// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>13224// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>13225// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>13226// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>13227// CHECK-NEXT: [[VPMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>13228// CHECK-NEXT: [[VPMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>13229// CHECK-NEXT: [[VPMIN_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> [[VPMIN_V_I]], <2 x float> [[VPMIN_V1_I]])13230// CHECK-NEXT: [[VPMIN_V3_I:%.*]] = bitcast <2 x float> [[VPMIN_V2_I]] to <8 x i8>13231// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VPMIN_V3_I]] to <2 x i32>13232// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>13233// CHECK-NEXT: ret <2 x float> [[TMP5]]13234//13235float32x2_t test_vpmin_f32(float32x2_t a, float32x2_t b) {13236 return vpmin_f32(a, b);13237}13238 13239// CHECK-LABEL: define <8 x i8> @test_vqabs_s8(13240// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {13241// CHECK-NEXT: [[ENTRY:.*:]]13242// CHECK-NEXT: [[VQABS_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> [[A]])13243// CHECK-NEXT: ret <8 x i8> [[VQABS_V_I]]13244//13245int8x8_t test_vqabs_s8(int8x8_t a) {13246 return vqabs_s8(a);13247}13248 13249// CHECK-LABEL: define <4 x i16> @test_vqabs_s16(13250// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {13251// CHECK-NEXT: [[ENTRY:.*:]]13252// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>13253// CHECK-NEXT: [[VQABS_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13254// CHECK-NEXT: [[VQABS_V1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> [[VQABS_V_I]])13255// CHECK-NEXT: [[VQABS_V2_I:%.*]] = bitcast <4 x i16> [[VQABS_V1_I]] to <8 x i8>13256// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VQABS_V2_I]] to <4 x i16>13257// CHECK-NEXT: ret <4 x i16> [[TMP1]]13258//13259int16x4_t test_vqabs_s16(int16x4_t a) {13260 return vqabs_s16(a);13261}13262 13263// CHECK-LABEL: define <2 x i32> @test_vqabs_s32(13264// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {13265// CHECK-NEXT: [[ENTRY:.*:]]13266// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>13267// CHECK-NEXT: [[VQABS_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13268// CHECK-NEXT: [[VQABS_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> [[VQABS_V_I]])13269// CHECK-NEXT: [[VQABS_V2_I:%.*]] = bitcast <2 x i32> [[VQABS_V1_I]] to <8 x i8>13270// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VQABS_V2_I]] to <2 x i32>13271// CHECK-NEXT: ret <2 x i32> [[TMP1]]13272//13273int32x2_t test_vqabs_s32(int32x2_t a) {13274 return vqabs_s32(a);13275}13276 13277// CHECK-LABEL: define <16 x i8> @test_vqabsq_s8(13278// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {13279// CHECK-NEXT: [[ENTRY:.*:]]13280// CHECK-NEXT: [[VQABSQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> [[A]])13281// CHECK-NEXT: ret <16 x i8> [[VQABSQ_V_I]]13282//13283int8x16_t test_vqabsq_s8(int8x16_t a) {13284 return vqabsq_s8(a);13285}13286 13287// CHECK-LABEL: define <8 x i16> @test_vqabsq_s16(13288// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {13289// CHECK-NEXT: [[ENTRY:.*:]]13290// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>13291// CHECK-NEXT: [[VQABSQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>13292// CHECK-NEXT: [[VQABSQ_V1_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> [[VQABSQ_V_I]])13293// CHECK-NEXT: [[VQABSQ_V2_I:%.*]] = bitcast <8 x i16> [[VQABSQ_V1_I]] to <16 x i8>13294// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VQABSQ_V2_I]] to <8 x i16>13295// CHECK-NEXT: ret <8 x i16> [[TMP1]]13296//13297int16x8_t test_vqabsq_s16(int16x8_t a) {13298 return vqabsq_s16(a);13299}13300 13301// CHECK-LABEL: define <4 x i32> @test_vqabsq_s32(13302// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {13303// CHECK-NEXT: [[ENTRY:.*:]]13304// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13305// CHECK-NEXT: [[VQABSQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>13306// CHECK-NEXT: [[VQABSQ_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> [[VQABSQ_V_I]])13307// CHECK-NEXT: [[VQABSQ_V2_I:%.*]] = bitcast <4 x i32> [[VQABSQ_V1_I]] to <16 x i8>13308// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VQABSQ_V2_I]] to <4 x i32>13309// CHECK-NEXT: ret <4 x i32> [[TMP1]]13310//13311int32x4_t test_vqabsq_s32(int32x4_t a) {13312 return vqabsq_s32(a);13313}13314 13315// CHECK-LABEL: define <8 x i8> @test_vqadd_s8(13316// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {13317// CHECK-NEXT: [[ENTRY:.*:]]13318// CHECK-NEXT: [[VQADD_V_I:%.*]] = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])13319// CHECK-NEXT: ret <8 x i8> [[VQADD_V_I]]13320//13321int8x8_t test_vqadd_s8(int8x8_t a, int8x8_t b) {13322 return vqadd_s8(a, b);13323}13324 13325// CHECK-LABEL: define <4 x i16> @test_vqadd_s16(13326// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13327// CHECK-NEXT: [[ENTRY:.*:]]13328// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>13329// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13330// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13331// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13332// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[VQADD_V_I]], <4 x i16> [[VQADD_V1_I]])13333// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <4 x i16> [[VQADD_V2_I]] to <8 x i8>13334// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to <4 x i16>13335// CHECK-NEXT: ret <4 x i16> [[TMP2]]13336//13337int16x4_t test_vqadd_s16(int16x4_t a, int16x4_t b) {13338 return vqadd_s16(a, b);13339}13340 13341// CHECK-LABEL: define <2 x i32> @test_vqadd_s32(13342// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13343// CHECK-NEXT: [[ENTRY:.*:]]13344// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>13345// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13346// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13347// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13348// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[VQADD_V_I]], <2 x i32> [[VQADD_V1_I]])13349// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <2 x i32> [[VQADD_V2_I]] to <8 x i8>13350// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to <2 x i32>13351// CHECK-NEXT: ret <2 x i32> [[TMP2]]13352//13353int32x2_t test_vqadd_s32(int32x2_t a, int32x2_t b) {13354 return vqadd_s32(a, b);13355}13356 13357// CHECK-LABEL: define <1 x i64> @test_vqadd_s64(13358// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {13359// CHECK-NEXT: [[ENTRY:.*:]]13360// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>13361// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>13362// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>13363// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>13364// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <1 x i64> @llvm.sadd.sat.v1i64(<1 x i64> [[VQADD_V_I]], <1 x i64> [[VQADD_V1_I]])13365// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <1 x i64> [[VQADD_V2_I]] to <8 x i8>13366// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to i6413367// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 013368// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]13369//13370int64x1_t test_vqadd_s64(int64x1_t a, int64x1_t b) {13371 return vqadd_s64(a, b);13372}13373 13374// CHECK-LABEL: define <8 x i8> @test_vqadd_u8(13375// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {13376// CHECK-NEXT: [[ENTRY:.*:]]13377// CHECK-NEXT: [[VQADD_V_I:%.*]] = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])13378// CHECK-NEXT: ret <8 x i8> [[VQADD_V_I]]13379//13380uint8x8_t test_vqadd_u8(uint8x8_t a, uint8x8_t b) {13381 return vqadd_u8(a, b);13382}13383 13384// CHECK-LABEL: define <4 x i16> @test_vqadd_u16(13385// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13386// CHECK-NEXT: [[ENTRY:.*:]]13387// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>13388// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13389// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13390// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13391// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> [[VQADD_V_I]], <4 x i16> [[VQADD_V1_I]])13392// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <4 x i16> [[VQADD_V2_I]] to <8 x i8>13393// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to <4 x i16>13394// CHECK-NEXT: ret <4 x i16> [[TMP2]]13395//13396uint16x4_t test_vqadd_u16(uint16x4_t a, uint16x4_t b) {13397 return vqadd_u16(a, b);13398}13399 13400// CHECK-LABEL: define <2 x i32> @test_vqadd_u32(13401// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13402// CHECK-NEXT: [[ENTRY:.*:]]13403// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>13404// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13405// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13406// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13407// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[VQADD_V_I]], <2 x i32> [[VQADD_V1_I]])13408// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <2 x i32> [[VQADD_V2_I]] to <8 x i8>13409// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to <2 x i32>13410// CHECK-NEXT: ret <2 x i32> [[TMP2]]13411//13412uint32x2_t test_vqadd_u32(uint32x2_t a, uint32x2_t b) {13413 return vqadd_u32(a, b);13414}13415 13416// CHECK-LABEL: define <1 x i64> @test_vqadd_u64(13417// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {13418// CHECK-NEXT: [[ENTRY:.*:]]13419// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>13420// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>13421// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>13422// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>13423// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <1 x i64> @llvm.uadd.sat.v1i64(<1 x i64> [[VQADD_V_I]], <1 x i64> [[VQADD_V1_I]])13424// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <1 x i64> [[VQADD_V2_I]] to <8 x i8>13425// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to i6413426// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 013427// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]13428//13429uint64x1_t test_vqadd_u64(uint64x1_t a, uint64x1_t b) {13430 return vqadd_u64(a, b);13431}13432 13433// CHECK-LABEL: define <16 x i8> @test_vqaddq_s8(13434// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {13435// CHECK-NEXT: [[ENTRY:.*:]]13436// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])13437// CHECK-NEXT: ret <16 x i8> [[VQADDQ_V_I]]13438//13439int8x16_t test_vqaddq_s8(int8x16_t a, int8x16_t b) {13440 return vqaddq_s8(a, b);13441}13442 13443// CHECK-LABEL: define <8 x i16> @test_vqaddq_s16(13444// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13445// CHECK-NEXT: [[ENTRY:.*:]]13446// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>13447// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>13448// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>13449// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>13450// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> [[VQADDQ_V_I]], <8 x i16> [[VQADDQ_V1_I]])13451// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <8 x i16> [[VQADDQ_V2_I]] to <16 x i8>13452// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <8 x i16>13453// CHECK-NEXT: ret <8 x i16> [[TMP2]]13454//13455int16x8_t test_vqaddq_s16(int16x8_t a, int16x8_t b) {13456 return vqaddq_s16(a, b);13457}13458 13459// CHECK-LABEL: define <4 x i32> @test_vqaddq_s32(13460// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13461// CHECK-NEXT: [[ENTRY:.*:]]13462// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13463// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>13464// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>13465// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>13466// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[VQADDQ_V_I]], <4 x i32> [[VQADDQ_V1_I]])13467// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <4 x i32> [[VQADDQ_V2_I]] to <16 x i8>13468// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <4 x i32>13469// CHECK-NEXT: ret <4 x i32> [[TMP2]]13470//13471int32x4_t test_vqaddq_s32(int32x4_t a, int32x4_t b) {13472 return vqaddq_s32(a, b);13473}13474 13475// CHECK-LABEL: define <2 x i64> @test_vqaddq_s64(13476// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {13477// CHECK-NEXT: [[ENTRY:.*:]]13478// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>13479// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>13480// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>13481// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>13482// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> [[VQADDQ_V_I]], <2 x i64> [[VQADDQ_V1_I]])13483// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <2 x i64> [[VQADDQ_V2_I]] to <16 x i8>13484// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <2 x i64>13485// CHECK-NEXT: ret <2 x i64> [[TMP2]]13486//13487int64x2_t test_vqaddq_s64(int64x2_t a, int64x2_t b) {13488 return vqaddq_s64(a, b);13489}13490 13491// CHECK-LABEL: define <16 x i8> @test_vqaddq_u8(13492// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {13493// CHECK-NEXT: [[ENTRY:.*:]]13494// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])13495// CHECK-NEXT: ret <16 x i8> [[VQADDQ_V_I]]13496//13497uint8x16_t test_vqaddq_u8(uint8x16_t a, uint8x16_t b) {13498 return vqaddq_u8(a, b);13499}13500 13501// CHECK-LABEL: define <8 x i16> @test_vqaddq_u16(13502// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13503// CHECK-NEXT: [[ENTRY:.*:]]13504// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>13505// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>13506// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>13507// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>13508// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[VQADDQ_V_I]], <8 x i16> [[VQADDQ_V1_I]])13509// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <8 x i16> [[VQADDQ_V2_I]] to <16 x i8>13510// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <8 x i16>13511// CHECK-NEXT: ret <8 x i16> [[TMP2]]13512//13513uint16x8_t test_vqaddq_u16(uint16x8_t a, uint16x8_t b) {13514 return vqaddq_u16(a, b);13515}13516 13517// CHECK-LABEL: define <4 x i32> @test_vqaddq_u32(13518// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13519// CHECK-NEXT: [[ENTRY:.*:]]13520// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13521// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>13522// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>13523// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>13524// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> [[VQADDQ_V_I]], <4 x i32> [[VQADDQ_V1_I]])13525// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <4 x i32> [[VQADDQ_V2_I]] to <16 x i8>13526// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <4 x i32>13527// CHECK-NEXT: ret <4 x i32> [[TMP2]]13528//13529uint32x4_t test_vqaddq_u32(uint32x4_t a, uint32x4_t b) {13530 return vqaddq_u32(a, b);13531}13532 13533// CHECK-LABEL: define <2 x i64> @test_vqaddq_u64(13534// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {13535// CHECK-NEXT: [[ENTRY:.*:]]13536// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>13537// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>13538// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>13539// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>13540// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> [[VQADDQ_V_I]], <2 x i64> [[VQADDQ_V1_I]])13541// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <2 x i64> [[VQADDQ_V2_I]] to <16 x i8>13542// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <2 x i64>13543// CHECK-NEXT: ret <2 x i64> [[TMP2]]13544//13545uint64x2_t test_vqaddq_u64(uint64x2_t a, uint64x2_t b) {13546 return vqaddq_u64(a, b);13547}13548 13549// CHECK-LABEL: define <4 x i32> @test_vqdmlal_s16(13550// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {13551// CHECK-NEXT: [[ENTRY:.*:]]13552// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13553// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13554// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>13555// CHECK-NEXT: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13556// CHECK-NEXT: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>13557// CHECK-NEXT: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]])13558// CHECK-NEXT: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>13559// CHECK-NEXT: [[VQDMLAL_V3_I:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL2_I]])13560// CHECK-NEXT: ret <4 x i32> [[VQDMLAL_V3_I]]13561//13562int32x4_t test_vqdmlal_s16(int32x4_t a, int16x4_t b, int16x4_t c) {13563 return vqdmlal_s16(a, b, c);13564}13565 13566// CHECK-LABEL: define <2 x i64> @test_vqdmlal_s32(13567// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {13568// CHECK-NEXT: [[ENTRY:.*:]]13569// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>13570// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13571// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>13572// CHECK-NEXT: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13573// CHECK-NEXT: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>13574// CHECK-NEXT: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]])13575// CHECK-NEXT: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>13576// CHECK-NEXT: [[VQDMLAL_V3_I:%.*]] = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL2_I]])13577// CHECK-NEXT: ret <2 x i64> [[VQDMLAL_V3_I]]13578//13579int64x2_t test_vqdmlal_s32(int64x2_t a, int32x2_t b, int32x2_t c) {13580 return vqdmlal_s32(a, b, c);13581}13582 13583// CHECK-LABEL: define <4 x i32> @test_vqdmlal_lane_s16(13584// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {13585// CHECK-NEXT: [[ENTRY:.*:]]13586// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>13587// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13588// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>13589// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13590// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13591// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>13592// CHECK-NEXT: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>13593// CHECK-NEXT: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>13594// CHECK-NEXT: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]])13595// CHECK-NEXT: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>13596// CHECK-NEXT: [[VQDMLAL_V3_I:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32> [[VQDMLAL2_I]])13597// CHECK-NEXT: ret <4 x i32> [[VQDMLAL_V3_I]]13598//13599int32x4_t test_vqdmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t c) {13600 return vqdmlal_lane_s16(a, b, c, 3);13601}13602 13603// CHECK-LABEL: define <2 x i64> @test_vqdmlal_lane_s32(13604// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {13605// CHECK-NEXT: [[ENTRY:.*:]]13606// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>13607// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13608// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>13609// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>13610// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13611// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>13612// CHECK-NEXT: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>13613// CHECK-NEXT: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x i32>13614// CHECK-NEXT: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]])13615// CHECK-NEXT: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>13616// CHECK-NEXT: [[VQDMLAL_V3_I:%.*]] = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64> [[VQDMLAL2_I]])13617// CHECK-NEXT: ret <2 x i64> [[VQDMLAL_V3_I]]13618//13619int64x2_t test_vqdmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t c) {13620 return vqdmlal_lane_s32(a, b, c, 1);13621}13622 13623// CHECK-LABEL: define <4 x i32> @test_vqdmlal_n_s16(13624// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], i16 noundef signext [[C:%.*]]) #[[ATTR0]] {13625// CHECK-NEXT: [[ENTRY:.*:]]13626// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i32 013627// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[C]], i32 113628// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[C]], i32 213629// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[C]], i32 313630// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13631// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13632// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>13633// CHECK-NEXT: [[VQDMLAL_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13634// CHECK-NEXT: [[VQDMLAL1_I_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>13635// CHECK-NEXT: [[VQDMLAL2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> [[VQDMLAL_I_I]], <4 x i16> [[VQDMLAL1_I_I]])13636// CHECK-NEXT: [[VQDMLAL_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>13637// CHECK-NEXT: [[VQDMLAL_V3_I_I:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[VQDMLAL_V_I_I]], <4 x i32> [[VQDMLAL2_I_I]])13638// CHECK-NEXT: ret <4 x i32> [[VQDMLAL_V3_I_I]]13639//13640int32x4_t test_vqdmlal_n_s16(int32x4_t a, int16x4_t b, int16_t c) {13641 return vqdmlal_n_s16(a, b, c);13642}13643 13644// CHECK-LABEL: define <2 x i64> @test_vqdmlal_n_s32(13645// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {13646// CHECK-NEXT: [[ENTRY:.*:]]13647// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[C]], i32 013648// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[C]], i32 113649// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>13650// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13651// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>13652// CHECK-NEXT: [[VQDMLAL_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13653// CHECK-NEXT: [[VQDMLAL1_I_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>13654// CHECK-NEXT: [[VQDMLAL2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> [[VQDMLAL_I_I]], <2 x i32> [[VQDMLAL1_I_I]])13655// CHECK-NEXT: [[VQDMLAL_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>13656// CHECK-NEXT: [[VQDMLAL_V3_I_I:%.*]] = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> [[VQDMLAL_V_I_I]], <2 x i64> [[VQDMLAL2_I_I]])13657// CHECK-NEXT: ret <2 x i64> [[VQDMLAL_V3_I_I]]13658//13659int64x2_t test_vqdmlal_n_s32(int64x2_t a, int32x2_t b, int32_t c) {13660 return vqdmlal_n_s32(a, b, c);13661}13662 13663// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_s16(13664// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {13665// CHECK-NEXT: [[ENTRY:.*:]]13666// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13667// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13668// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>13669// CHECK-NEXT: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13670// CHECK-NEXT: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>13671// CHECK-NEXT: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]])13672// CHECK-NEXT: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>13673// CHECK-NEXT: [[VQDMLSL_V3_I:%.*]] = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL2_I]])13674// CHECK-NEXT: ret <4 x i32> [[VQDMLSL_V3_I]]13675//13676int32x4_t test_vqdmlsl_s16(int32x4_t a, int16x4_t b, int16x4_t c) {13677 return vqdmlsl_s16(a, b, c);13678}13679 13680// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_s32(13681// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {13682// CHECK-NEXT: [[ENTRY:.*:]]13683// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>13684// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13685// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>13686// CHECK-NEXT: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13687// CHECK-NEXT: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>13688// CHECK-NEXT: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]])13689// CHECK-NEXT: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>13690// CHECK-NEXT: [[VQDMLSL_V3_I:%.*]] = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL2_I]])13691// CHECK-NEXT: ret <2 x i64> [[VQDMLSL_V3_I]]13692//13693int64x2_t test_vqdmlsl_s32(int64x2_t a, int32x2_t b, int32x2_t c) {13694 return vqdmlsl_s32(a, b, c);13695}13696 13697// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_lane_s16(13698// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], <4 x i16> noundef [[C:%.*]]) #[[ATTR0]] {13699// CHECK-NEXT: [[ENTRY:.*:]]13700// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[C]] to <8 x i8>13701// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13702// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>13703// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13704// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13705// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>13706// CHECK-NEXT: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>13707// CHECK-NEXT: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>13708// CHECK-NEXT: [[VQDMLAL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16> [[VQDMLAL1_I]])13709// CHECK-NEXT: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>13710// CHECK-NEXT: [[VQDMLSL_V3_I:%.*]] = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32> [[VQDMLAL2_I]])13711// CHECK-NEXT: ret <4 x i32> [[VQDMLSL_V3_I]]13712//13713int32x4_t test_vqdmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t c) {13714 return vqdmlsl_lane_s16(a, b, c, 3);13715}13716 13717// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_lane_s32(13718// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], <2 x i32> noundef [[C:%.*]]) #[[ATTR0]] {13719// CHECK-NEXT: [[ENTRY:.*:]]13720// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[C]] to <8 x i8>13721// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13722// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>13723// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>13724// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13725// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>13726// CHECK-NEXT: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>13727// CHECK-NEXT: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP4]] to <2 x i32>13728// CHECK-NEXT: [[VQDMLAL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32> [[VQDMLAL1_I]])13729// CHECK-NEXT: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>13730// CHECK-NEXT: [[VQDMLSL_V3_I:%.*]] = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64> [[VQDMLAL2_I]])13731// CHECK-NEXT: ret <2 x i64> [[VQDMLSL_V3_I]]13732//13733int64x2_t test_vqdmlsl_lane_s32(int64x2_t a, int32x2_t b, int32x2_t c) {13734 return vqdmlsl_lane_s32(a, b, c, 1);13735}13736 13737// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_n_s16(13738// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]], i16 noundef signext [[C:%.*]]) #[[ATTR0]] {13739// CHECK-NEXT: [[ENTRY:.*:]]13740// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[C]], i32 013741// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[C]], i32 113742// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[C]], i32 213743// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[C]], i32 313744// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13745// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13746// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>13747// CHECK-NEXT: [[VQDMLAL_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13748// CHECK-NEXT: [[VQDMLAL1_I_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>13749// CHECK-NEXT: [[VQDMLAL2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> [[VQDMLAL_I_I]], <4 x i16> [[VQDMLAL1_I_I]])13750// CHECK-NEXT: [[VQDMLSL_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>13751// CHECK-NEXT: [[VQDMLSL_V3_I_I:%.*]] = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> [[VQDMLSL_V_I_I]], <4 x i32> [[VQDMLAL2_I_I]])13752// CHECK-NEXT: ret <4 x i32> [[VQDMLSL_V3_I_I]]13753//13754int32x4_t test_vqdmlsl_n_s16(int32x4_t a, int16x4_t b, int16_t c) {13755 return vqdmlsl_n_s16(a, b, c);13756}13757 13758// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_n_s32(13759// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] {13760// CHECK-NEXT: [[ENTRY:.*:]]13761// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[C]], i32 013762// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[C]], i32 113763// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>13764// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13765// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>13766// CHECK-NEXT: [[VQDMLAL_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13767// CHECK-NEXT: [[VQDMLAL1_I_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>13768// CHECK-NEXT: [[VQDMLAL2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> [[VQDMLAL_I_I]], <2 x i32> [[VQDMLAL1_I_I]])13769// CHECK-NEXT: [[VQDMLSL_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>13770// CHECK-NEXT: [[VQDMLSL_V3_I_I:%.*]] = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> [[VQDMLSL_V_I_I]], <2 x i64> [[VQDMLAL2_I_I]])13771// CHECK-NEXT: ret <2 x i64> [[VQDMLSL_V3_I_I]]13772//13773int64x2_t test_vqdmlsl_n_s32(int64x2_t a, int32x2_t b, int32_t c) {13774 return vqdmlsl_n_s32(a, b, c);13775}13776 13777// CHECK-LABEL: define <4 x i16> @test_vqdmulh_s16(13778// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13779// CHECK-NEXT: [[ENTRY:.*:]]13780// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>13781// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13782// CHECK-NEXT: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13783// CHECK-NEXT: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13784// CHECK-NEXT: [[VQDMULH_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> [[VQDMULH_V_I]], <4 x i16> [[VQDMULH_V1_I]])13785// CHECK-NEXT: [[VQDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQDMULH_V2_I]] to <8 x i8>13786// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <4 x i16>13787// CHECK-NEXT: ret <4 x i16> [[TMP2]]13788//13789int16x4_t test_vqdmulh_s16(int16x4_t a, int16x4_t b) {13790 return vqdmulh_s16(a, b);13791}13792 13793// CHECK-LABEL: define <2 x i32> @test_vqdmulh_s32(13794// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13795// CHECK-NEXT: [[ENTRY:.*:]]13796// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>13797// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13798// CHECK-NEXT: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13799// CHECK-NEXT: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13800// CHECK-NEXT: [[VQDMULH_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> [[VQDMULH_V_I]], <2 x i32> [[VQDMULH_V1_I]])13801// CHECK-NEXT: [[VQDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQDMULH_V2_I]] to <8 x i8>13802// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <2 x i32>13803// CHECK-NEXT: ret <2 x i32> [[TMP2]]13804//13805int32x2_t test_vqdmulh_s32(int32x2_t a, int32x2_t b) {13806 return vqdmulh_s32(a, b);13807}13808 13809// CHECK-LABEL: define <8 x i16> @test_vqdmulhq_s16(13810// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13811// CHECK-NEXT: [[ENTRY:.*:]]13812// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>13813// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>13814// CHECK-NEXT: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>13815// CHECK-NEXT: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>13816// CHECK-NEXT: [[VQDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> [[VQDMULHQ_V_I]], <8 x i16> [[VQDMULHQ_V1_I]])13817// CHECK-NEXT: [[VQDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQDMULHQ_V2_I]] to <16 x i8>13818// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <8 x i16>13819// CHECK-NEXT: ret <8 x i16> [[TMP2]]13820//13821int16x8_t test_vqdmulhq_s16(int16x8_t a, int16x8_t b) {13822 return vqdmulhq_s16(a, b);13823}13824 13825// CHECK-LABEL: define <4 x i32> @test_vqdmulhq_s32(13826// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13827// CHECK-NEXT: [[ENTRY:.*:]]13828// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13829// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>13830// CHECK-NEXT: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>13831// CHECK-NEXT: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>13832// CHECK-NEXT: [[VQDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> [[VQDMULHQ_V_I]], <4 x i32> [[VQDMULHQ_V1_I]])13833// CHECK-NEXT: [[VQDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULHQ_V2_I]] to <16 x i8>13834// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <4 x i32>13835// CHECK-NEXT: ret <4 x i32> [[TMP2]]13836//13837int32x4_t test_vqdmulhq_s32(int32x4_t a, int32x4_t b) {13838 return vqdmulhq_s32(a, b);13839}13840 13841// CHECK-LABEL: define <4 x i16> @test_vqdmulh_lane_s16(13842// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13843// CHECK-NEXT: [[ENTRY:.*:]]13844// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13845// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13846// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>13847// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>13848// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>13849// CHECK-NEXT: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>13850// CHECK-NEXT: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>13851// CHECK-NEXT: [[VQDMULH_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> [[VQDMULH_V_I]], <4 x i16> [[VQDMULH_V1_I]])13852// CHECK-NEXT: [[VQDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQDMULH_V2_I]] to <8 x i8>13853// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <4 x i16>13854// CHECK-NEXT: ret <4 x i16> [[TMP4]]13855//13856int16x4_t test_vqdmulh_lane_s16(int16x4_t a, int16x4_t b) {13857 return vqdmulh_lane_s16(a, b, 3);13858}13859 13860// CHECK-LABEL: define <2 x i32> @test_vqdmulh_lane_s32(13861// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13862// CHECK-NEXT: [[ENTRY:.*:]]13863// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13864// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13865// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>13866// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>13867// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>13868// CHECK-NEXT: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>13869// CHECK-NEXT: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>13870// CHECK-NEXT: [[VQDMULH_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> [[VQDMULH_V_I]], <2 x i32> [[VQDMULH_V1_I]])13871// CHECK-NEXT: [[VQDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQDMULH_V2_I]] to <8 x i8>13872// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I]] to <2 x i32>13873// CHECK-NEXT: ret <2 x i32> [[TMP4]]13874//13875int32x2_t test_vqdmulh_lane_s32(int32x2_t a, int32x2_t b) {13876 return vqdmulh_lane_s32(a, b, 1);13877}13878 13879// CHECK-LABEL: define <8 x i16> @test_vqdmulhq_lane_s16(13880// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {13881// CHECK-NEXT: [[ENTRY:.*:]]13882// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>13883// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13884// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>13885// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>13886// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[LANE]] to <16 x i8>13887// CHECK-NEXT: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>13888// CHECK-NEXT: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>13889// CHECK-NEXT: [[VQDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> [[VQDMULHQ_V_I]], <8 x i16> [[VQDMULHQ_V1_I]])13890// CHECK-NEXT: [[VQDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQDMULHQ_V2_I]] to <16 x i8>13891// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <8 x i16>13892// CHECK-NEXT: ret <8 x i16> [[TMP4]]13893//13894int16x8_t test_vqdmulhq_lane_s16(int16x8_t a, int16x4_t b) {13895 return vqdmulhq_lane_s16(a, b, 3);13896}13897 13898// CHECK-LABEL: define <4 x i32> @test_vqdmulhq_lane_s32(13899// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {13900// CHECK-NEXT: [[ENTRY:.*:]]13901// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>13902// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13903// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>13904// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13905// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[LANE]] to <16 x i8>13906// CHECK-NEXT: [[VQDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>13907// CHECK-NEXT: [[VQDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x i32>13908// CHECK-NEXT: [[VQDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> [[VQDMULHQ_V_I]], <4 x i32> [[VQDMULHQ_V1_I]])13909// CHECK-NEXT: [[VQDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULHQ_V2_I]] to <16 x i8>13910// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I]] to <4 x i32>13911// CHECK-NEXT: ret <4 x i32> [[TMP4]]13912//13913int32x4_t test_vqdmulhq_lane_s32(int32x4_t a, int32x2_t b) {13914 return vqdmulhq_lane_s32(a, b, 1);13915}13916 13917// CHECK-LABEL: define <4 x i16> @test_vqdmulh_n_s16(13918// CHECK-SAME: <4 x i16> noundef [[A:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {13919// CHECK-NEXT: [[ENTRY:.*:]]13920// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i32 013921// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[B]], i32 113922// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[B]], i32 213923// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[B]], i32 313924// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>13925// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>13926// CHECK-NEXT: [[VQDMULH_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>13927// CHECK-NEXT: [[VQDMULH_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>13928// CHECK-NEXT: [[VQDMULH_V2_I_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> [[VQDMULH_V_I_I]], <4 x i16> [[VQDMULH_V1_I_I]])13929// CHECK-NEXT: [[VQDMULH_V3_I_I:%.*]] = bitcast <4 x i16> [[VQDMULH_V2_I_I]] to <8 x i8>13930// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I_I]] to <4 x i16>13931// CHECK-NEXT: ret <4 x i16> [[TMP2]]13932//13933int16x4_t test_vqdmulh_n_s16(int16x4_t a, int16_t b) {13934 return vqdmulh_n_s16(a, b);13935}13936 13937// CHECK-LABEL: define <2 x i32> @test_vqdmulh_n_s32(13938// CHECK-SAME: <2 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {13939// CHECK-NEXT: [[ENTRY:.*:]]13940// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i32 013941// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[B]], i32 113942// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>13943// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>13944// CHECK-NEXT: [[VQDMULH_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>13945// CHECK-NEXT: [[VQDMULH_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>13946// CHECK-NEXT: [[VQDMULH_V2_I_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> [[VQDMULH_V_I_I]], <2 x i32> [[VQDMULH_V1_I_I]])13947// CHECK-NEXT: [[VQDMULH_V3_I_I:%.*]] = bitcast <2 x i32> [[VQDMULH_V2_I_I]] to <8 x i8>13948// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQDMULH_V3_I_I]] to <2 x i32>13949// CHECK-NEXT: ret <2 x i32> [[TMP2]]13950//13951int32x2_t test_vqdmulh_n_s32(int32x2_t a, int32_t b) {13952 return vqdmulh_n_s32(a, b);13953}13954 13955// CHECK-LABEL: define <8 x i16> @test_vqdmulhq_n_s16(13956// CHECK-SAME: <8 x i16> noundef [[A:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {13957// CHECK-NEXT: [[ENTRY:.*:]]13958// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[B]], i32 013959// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[B]], i32 113960// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[B]], i32 213961// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[B]], i32 313962// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[B]], i32 413963// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[B]], i32 513964// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[B]], i32 613965// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[B]], i32 713966// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>13967// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <16 x i8>13968// CHECK-NEXT: [[VQDMULHQ_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>13969// CHECK-NEXT: [[VQDMULHQ_V1_I_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>13970// CHECK-NEXT: [[VQDMULHQ_V2_I_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> [[VQDMULHQ_V_I_I]], <8 x i16> [[VQDMULHQ_V1_I_I]])13971// CHECK-NEXT: [[VQDMULHQ_V3_I_I:%.*]] = bitcast <8 x i16> [[VQDMULHQ_V2_I_I]] to <16 x i8>13972// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I_I]] to <8 x i16>13973// CHECK-NEXT: ret <8 x i16> [[TMP2]]13974//13975int16x8_t test_vqdmulhq_n_s16(int16x8_t a, int16_t b) {13976 return vqdmulhq_n_s16(a, b);13977}13978 13979// CHECK-LABEL: define <4 x i32> @test_vqdmulhq_n_s32(13980// CHECK-SAME: <4 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {13981// CHECK-NEXT: [[ENTRY:.*:]]13982// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[B]], i32 013983// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[B]], i32 113984// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[B]], i32 213985// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[B]], i32 313986// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>13987// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[VECINIT3_I]] to <16 x i8>13988// CHECK-NEXT: [[VQDMULHQ_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>13989// CHECK-NEXT: [[VQDMULHQ_V1_I_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>13990// CHECK-NEXT: [[VQDMULHQ_V2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> [[VQDMULHQ_V_I_I]], <4 x i32> [[VQDMULHQ_V1_I_I]])13991// CHECK-NEXT: [[VQDMULHQ_V3_I_I:%.*]] = bitcast <4 x i32> [[VQDMULHQ_V2_I_I]] to <16 x i8>13992// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULHQ_V3_I_I]] to <4 x i32>13993// CHECK-NEXT: ret <4 x i32> [[TMP2]]13994//13995int32x4_t test_vqdmulhq_n_s32(int32x4_t a, int32_t b) {13996 return vqdmulhq_n_s32(a, b);13997}13998 13999// CHECK-LABEL: define <4 x i32> @test_vqdmull_s16(14000// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14001// CHECK-NEXT: [[ENTRY:.*:]]14002// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14003// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>14004// CHECK-NEXT: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14005// CHECK-NEXT: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>14006// CHECK-NEXT: [[VQDMULL_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V1_I]])14007// CHECK-NEXT: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to <16 x i8>14008// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32>14009// CHECK-NEXT: ret <4 x i32> [[TMP2]]14010//14011int32x4_t test_vqdmull_s16(int16x4_t a, int16x4_t b) {14012 return vqdmull_s16(a, b);14013}14014 14015// CHECK-LABEL: define <2 x i64> @test_vqdmull_s32(14016// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14017// CHECK-NEXT: [[ENTRY:.*:]]14018// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14019// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>14020// CHECK-NEXT: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14021// CHECK-NEXT: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>14022// CHECK-NEXT: [[VQDMULL_V2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V1_I]])14023// CHECK-NEXT: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to <16 x i8>14024// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64>14025// CHECK-NEXT: ret <2 x i64> [[TMP2]]14026//14027int64x2_t test_vqdmull_s32(int32x2_t a, int32x2_t b) {14028 return vqdmull_s32(a, b);14029}14030 14031// CHECK-LABEL: define <4 x i32> @test_vqdmull_lane_s16(14032// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14033// CHECK-NEXT: [[ENTRY:.*:]]14034// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>14035// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14036// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>14037// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14038// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>14039// CHECK-NEXT: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>14040// CHECK-NEXT: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>14041// CHECK-NEXT: [[VQDMULL_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16> [[VQDMULL_V1_I]])14042// CHECK-NEXT: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to <16 x i8>14043// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32>14044// CHECK-NEXT: ret <4 x i32> [[TMP4]]14045//14046int32x4_t test_vqdmull_lane_s16(int16x4_t a, int16x4_t b) {14047 return vqdmull_lane_s16(a, b, 3);14048}14049 14050// CHECK-LABEL: define <2 x i64> @test_vqdmull_lane_s32(14051// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14052// CHECK-NEXT: [[ENTRY:.*:]]14053// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>14054// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14055// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>14056// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14057// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>14058// CHECK-NEXT: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>14059// CHECK-NEXT: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>14060// CHECK-NEXT: [[VQDMULL_V2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32> [[VQDMULL_V1_I]])14061// CHECK-NEXT: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to <16 x i8>14062// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64>14063// CHECK-NEXT: ret <2 x i64> [[TMP4]]14064//14065int64x2_t test_vqdmull_lane_s32(int32x2_t a, int32x2_t b) {14066 return vqdmull_lane_s32(a, b, 1);14067}14068 14069// CHECK-LABEL: define <4 x i32> @test_vqdmull_n_s16(14070// CHECK-SAME: <4 x i16> noundef [[A:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {14071// CHECK-NEXT: [[ENTRY:.*:]]14072// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i32 014073// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[B]], i32 114074// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[B]], i32 214075// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[B]], i32 314076// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14077// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>14078// CHECK-NEXT: [[VQDMULL_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14079// CHECK-NEXT: [[VQDMULL_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>14080// CHECK-NEXT: [[VQDMULL_V2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> [[VQDMULL_V_I_I]], <4 x i16> [[VQDMULL_V1_I_I]])14081// CHECK-NEXT: [[VQDMULL_V3_I_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I_I]] to <16 x i8>14082// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I_I]] to <4 x i32>14083// CHECK-NEXT: ret <4 x i32> [[TMP2]]14084//14085int32x4_t test_vqdmull_n_s16(int16x4_t a, int16_t b) {14086 return vqdmull_n_s16(a, b);14087}14088 14089// CHECK-LABEL: define <2 x i64> @test_vqdmull_n_s32(14090// CHECK-SAME: <2 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {14091// CHECK-NEXT: [[ENTRY:.*:]]14092// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i32 014093// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[B]], i32 114094// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14095// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>14096// CHECK-NEXT: [[VQDMULL_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14097// CHECK-NEXT: [[VQDMULL_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>14098// CHECK-NEXT: [[VQDMULL_V2_I_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> [[VQDMULL_V_I_I]], <2 x i32> [[VQDMULL_V1_I_I]])14099// CHECK-NEXT: [[VQDMULL_V3_I_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I_I]] to <16 x i8>14100// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I_I]] to <2 x i64>14101// CHECK-NEXT: ret <2 x i64> [[TMP2]]14102//14103int64x2_t test_vqdmull_n_s32(int32x2_t a, int32_t b) {14104 return vqdmull_n_s32(a, b);14105}14106 14107// CHECK-LABEL: define <8 x i8> @test_vqmovn_s16(14108// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {14109// CHECK-NEXT: [[ENTRY:.*:]]14110// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14111// CHECK-NEXT: [[VQMOVN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14112// CHECK-NEXT: [[VQMOVN_V1_I:%.*]] = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> [[VQMOVN_V_I]])14113// CHECK-NEXT: ret <8 x i8> [[VQMOVN_V1_I]]14114//14115int8x8_t test_vqmovn_s16(int16x8_t a) {14116 return vqmovn_s16(a);14117}14118 14119// CHECK-LABEL: define <4 x i16> @test_vqmovn_s32(14120// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {14121// CHECK-NEXT: [[ENTRY:.*:]]14122// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14123// CHECK-NEXT: [[VQMOVN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14124// CHECK-NEXT: [[VQMOVN_V1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> [[VQMOVN_V_I]])14125// CHECK-NEXT: [[VQMOVN_V2_I:%.*]] = bitcast <4 x i16> [[VQMOVN_V1_I]] to <8 x i8>14126// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VQMOVN_V2_I]] to <4 x i16>14127// CHECK-NEXT: ret <4 x i16> [[TMP1]]14128//14129int16x4_t test_vqmovn_s32(int32x4_t a) {14130 return vqmovn_s32(a);14131}14132 14133// CHECK-LABEL: define <2 x i32> @test_vqmovn_s64(14134// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {14135// CHECK-NEXT: [[ENTRY:.*:]]14136// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>14137// CHECK-NEXT: [[VQMOVN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>14138// CHECK-NEXT: [[VQMOVN_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> [[VQMOVN_V_I]])14139// CHECK-NEXT: [[VQMOVN_V2_I:%.*]] = bitcast <2 x i32> [[VQMOVN_V1_I]] to <8 x i8>14140// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VQMOVN_V2_I]] to <2 x i32>14141// CHECK-NEXT: ret <2 x i32> [[TMP1]]14142//14143int32x2_t test_vqmovn_s64(int64x2_t a) {14144 return vqmovn_s64(a);14145}14146 14147// CHECK-LABEL: define <8 x i8> @test_vqmovn_u16(14148// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {14149// CHECK-NEXT: [[ENTRY:.*:]]14150// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14151// CHECK-NEXT: [[VQMOVN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14152// CHECK-NEXT: [[VQMOVN_V1_I:%.*]] = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> [[VQMOVN_V_I]])14153// CHECK-NEXT: ret <8 x i8> [[VQMOVN_V1_I]]14154//14155uint8x8_t test_vqmovn_u16(uint16x8_t a) {14156 return vqmovn_u16(a);14157}14158 14159// CHECK-LABEL: define <4 x i16> @test_vqmovn_u32(14160// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {14161// CHECK-NEXT: [[ENTRY:.*:]]14162// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14163// CHECK-NEXT: [[VQMOVN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14164// CHECK-NEXT: [[VQMOVN_V1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> [[VQMOVN_V_I]])14165// CHECK-NEXT: [[VQMOVN_V2_I:%.*]] = bitcast <4 x i16> [[VQMOVN_V1_I]] to <8 x i8>14166// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VQMOVN_V2_I]] to <4 x i16>14167// CHECK-NEXT: ret <4 x i16> [[TMP1]]14168//14169uint16x4_t test_vqmovn_u32(uint32x4_t a) {14170 return vqmovn_u32(a);14171}14172 14173// CHECK-LABEL: define <2 x i32> @test_vqmovn_u64(14174// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {14175// CHECK-NEXT: [[ENTRY:.*:]]14176// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>14177// CHECK-NEXT: [[VQMOVN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>14178// CHECK-NEXT: [[VQMOVN_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> [[VQMOVN_V_I]])14179// CHECK-NEXT: [[VQMOVN_V2_I:%.*]] = bitcast <2 x i32> [[VQMOVN_V1_I]] to <8 x i8>14180// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VQMOVN_V2_I]] to <2 x i32>14181// CHECK-NEXT: ret <2 x i32> [[TMP1]]14182//14183uint32x2_t test_vqmovn_u64(uint64x2_t a) {14184 return vqmovn_u64(a);14185}14186 14187// CHECK-LABEL: define <8 x i8> @test_vqmovun_s16(14188// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {14189// CHECK-NEXT: [[ENTRY:.*:]]14190// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14191// CHECK-NEXT: [[VQMOVUN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14192// CHECK-NEXT: [[VQMOVUN_V1_I:%.*]] = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> [[VQMOVUN_V_I]])14193// CHECK-NEXT: ret <8 x i8> [[VQMOVUN_V1_I]]14194//14195uint8x8_t test_vqmovun_s16(int16x8_t a) {14196 return vqmovun_s16(a);14197}14198 14199// CHECK-LABEL: define <4 x i16> @test_vqmovun_s32(14200// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {14201// CHECK-NEXT: [[ENTRY:.*:]]14202// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14203// CHECK-NEXT: [[VQMOVUN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14204// CHECK-NEXT: [[VQMOVUN_V1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> [[VQMOVUN_V_I]])14205// CHECK-NEXT: [[VQMOVUN_V2_I:%.*]] = bitcast <4 x i16> [[VQMOVUN_V1_I]] to <8 x i8>14206// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VQMOVUN_V2_I]] to <4 x i16>14207// CHECK-NEXT: ret <4 x i16> [[TMP1]]14208//14209uint16x4_t test_vqmovun_s32(int32x4_t a) {14210 return vqmovun_s32(a);14211}14212 14213// CHECK-LABEL: define <2 x i32> @test_vqmovun_s64(14214// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {14215// CHECK-NEXT: [[ENTRY:.*:]]14216// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>14217// CHECK-NEXT: [[VQMOVUN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>14218// CHECK-NEXT: [[VQMOVUN_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> [[VQMOVUN_V_I]])14219// CHECK-NEXT: [[VQMOVUN_V2_I:%.*]] = bitcast <2 x i32> [[VQMOVUN_V1_I]] to <8 x i8>14220// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VQMOVUN_V2_I]] to <2 x i32>14221// CHECK-NEXT: ret <2 x i32> [[TMP1]]14222//14223uint32x2_t test_vqmovun_s64(int64x2_t a) {14224 return vqmovun_s64(a);14225}14226 14227// CHECK-LABEL: define <8 x i8> @test_vqneg_s8(14228// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {14229// CHECK-NEXT: [[ENTRY:.*:]]14230// CHECK-NEXT: [[VQNEG_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> [[A]])14231// CHECK-NEXT: ret <8 x i8> [[VQNEG_V_I]]14232//14233int8x8_t test_vqneg_s8(int8x8_t a) {14234 return vqneg_s8(a);14235}14236 14237// CHECK-LABEL: define <4 x i16> @test_vqneg_s16(14238// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {14239// CHECK-NEXT: [[ENTRY:.*:]]14240// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14241// CHECK-NEXT: [[VQNEG_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14242// CHECK-NEXT: [[VQNEG_V1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> [[VQNEG_V_I]])14243// CHECK-NEXT: [[VQNEG_V2_I:%.*]] = bitcast <4 x i16> [[VQNEG_V1_I]] to <8 x i8>14244// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VQNEG_V2_I]] to <4 x i16>14245// CHECK-NEXT: ret <4 x i16> [[TMP1]]14246//14247int16x4_t test_vqneg_s16(int16x4_t a) {14248 return vqneg_s16(a);14249}14250 14251// CHECK-LABEL: define <2 x i32> @test_vqneg_s32(14252// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {14253// CHECK-NEXT: [[ENTRY:.*:]]14254// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14255// CHECK-NEXT: [[VQNEG_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14256// CHECK-NEXT: [[VQNEG_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> [[VQNEG_V_I]])14257// CHECK-NEXT: [[VQNEG_V2_I:%.*]] = bitcast <2 x i32> [[VQNEG_V1_I]] to <8 x i8>14258// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VQNEG_V2_I]] to <2 x i32>14259// CHECK-NEXT: ret <2 x i32> [[TMP1]]14260//14261int32x2_t test_vqneg_s32(int32x2_t a) {14262 return vqneg_s32(a);14263}14264 14265// CHECK-LABEL: define <16 x i8> @test_vqnegq_s8(14266// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {14267// CHECK-NEXT: [[ENTRY:.*:]]14268// CHECK-NEXT: [[VQNEGQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> [[A]])14269// CHECK-NEXT: ret <16 x i8> [[VQNEGQ_V_I]]14270//14271int8x16_t test_vqnegq_s8(int8x16_t a) {14272 return vqnegq_s8(a);14273}14274 14275// CHECK-LABEL: define <8 x i16> @test_vqnegq_s16(14276// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {14277// CHECK-NEXT: [[ENTRY:.*:]]14278// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14279// CHECK-NEXT: [[VQNEGQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14280// CHECK-NEXT: [[VQNEGQ_V1_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> [[VQNEGQ_V_I]])14281// CHECK-NEXT: [[VQNEGQ_V2_I:%.*]] = bitcast <8 x i16> [[VQNEGQ_V1_I]] to <16 x i8>14282// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VQNEGQ_V2_I]] to <8 x i16>14283// CHECK-NEXT: ret <8 x i16> [[TMP1]]14284//14285int16x8_t test_vqnegq_s16(int16x8_t a) {14286 return vqnegq_s16(a);14287}14288 14289// CHECK-LABEL: define <4 x i32> @test_vqnegq_s32(14290// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {14291// CHECK-NEXT: [[ENTRY:.*:]]14292// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14293// CHECK-NEXT: [[VQNEGQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14294// CHECK-NEXT: [[VQNEGQ_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> [[VQNEGQ_V_I]])14295// CHECK-NEXT: [[VQNEGQ_V2_I:%.*]] = bitcast <4 x i32> [[VQNEGQ_V1_I]] to <16 x i8>14296// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VQNEGQ_V2_I]] to <4 x i32>14297// CHECK-NEXT: ret <4 x i32> [[TMP1]]14298//14299int32x4_t test_vqnegq_s32(int32x4_t a) {14300 return vqnegq_s32(a);14301}14302 14303// CHECK-LABEL: define <4 x i16> @test_vqrdmulh_s16(14304// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14305// CHECK-NEXT: [[ENTRY:.*:]]14306// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14307// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>14308// CHECK-NEXT: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14309// CHECK-NEXT: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>14310// CHECK-NEXT: [[VQRDMULH_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> [[VQRDMULH_V_I]], <4 x i16> [[VQRDMULH_V1_I]])14311// CHECK-NEXT: [[VQRDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQRDMULH_V2_I]] to <8 x i8>14312// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <4 x i16>14313// CHECK-NEXT: ret <4 x i16> [[TMP2]]14314//14315int16x4_t test_vqrdmulh_s16(int16x4_t a, int16x4_t b) {14316 return vqrdmulh_s16(a, b);14317}14318 14319// CHECK-LABEL: define <2 x i32> @test_vqrdmulh_s32(14320// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14321// CHECK-NEXT: [[ENTRY:.*:]]14322// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14323// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>14324// CHECK-NEXT: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14325// CHECK-NEXT: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>14326// CHECK-NEXT: [[VQRDMULH_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> [[VQRDMULH_V_I]], <2 x i32> [[VQRDMULH_V1_I]])14327// CHECK-NEXT: [[VQRDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQRDMULH_V2_I]] to <8 x i8>14328// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <2 x i32>14329// CHECK-NEXT: ret <2 x i32> [[TMP2]]14330//14331int32x2_t test_vqrdmulh_s32(int32x2_t a, int32x2_t b) {14332 return vqrdmulh_s32(a, b);14333}14334 14335// CHECK-LABEL: define <8 x i16> @test_vqrdmulhq_s16(14336// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14337// CHECK-NEXT: [[ENTRY:.*:]]14338// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14339// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>14340// CHECK-NEXT: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14341// CHECK-NEXT: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>14342// CHECK-NEXT: [[VQRDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> [[VQRDMULHQ_V_I]], <8 x i16> [[VQRDMULHQ_V1_I]])14343// CHECK-NEXT: [[VQRDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQRDMULHQ_V2_I]] to <16 x i8>14344// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <8 x i16>14345// CHECK-NEXT: ret <8 x i16> [[TMP2]]14346//14347int16x8_t test_vqrdmulhq_s16(int16x8_t a, int16x8_t b) {14348 return vqrdmulhq_s16(a, b);14349}14350 14351// CHECK-LABEL: define <4 x i32> @test_vqrdmulhq_s32(14352// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14353// CHECK-NEXT: [[ENTRY:.*:]]14354// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14355// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>14356// CHECK-NEXT: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14357// CHECK-NEXT: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>14358// CHECK-NEXT: [[VQRDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> [[VQRDMULHQ_V_I]], <4 x i32> [[VQRDMULHQ_V1_I]])14359// CHECK-NEXT: [[VQRDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQRDMULHQ_V2_I]] to <16 x i8>14360// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <4 x i32>14361// CHECK-NEXT: ret <4 x i32> [[TMP2]]14362//14363int32x4_t test_vqrdmulhq_s32(int32x4_t a, int32x4_t b) {14364 return vqrdmulhq_s32(a, b);14365}14366 14367// CHECK-LABEL: define <4 x i16> @test_vqrdmulh_lane_s16(14368// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14369// CHECK-NEXT: [[ENTRY:.*:]]14370// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>14371// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14372// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>14373// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14374// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>14375// CHECK-NEXT: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>14376// CHECK-NEXT: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>14377// CHECK-NEXT: [[VQRDMULH_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> [[VQRDMULH_V_I]], <4 x i16> [[VQRDMULH_V1_I]])14378// CHECK-NEXT: [[VQRDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQRDMULH_V2_I]] to <8 x i8>14379// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <4 x i16>14380// CHECK-NEXT: ret <4 x i16> [[TMP4]]14381//14382int16x4_t test_vqrdmulh_lane_s16(int16x4_t a, int16x4_t b) {14383 return vqrdmulh_lane_s16(a, b, 3);14384}14385 14386// CHECK-LABEL: define <2 x i32> @test_vqrdmulh_lane_s32(14387// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14388// CHECK-NEXT: [[ENTRY:.*:]]14389// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>14390// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14391// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 1, i32 1>14392// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14393// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>14394// CHECK-NEXT: [[VQRDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>14395// CHECK-NEXT: [[VQRDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>14396// CHECK-NEXT: [[VQRDMULH_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> [[VQRDMULH_V_I]], <2 x i32> [[VQRDMULH_V1_I]])14397// CHECK-NEXT: [[VQRDMULH_V3_I:%.*]] = bitcast <2 x i32> [[VQRDMULH_V2_I]] to <8 x i8>14398// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I]] to <2 x i32>14399// CHECK-NEXT: ret <2 x i32> [[TMP4]]14400//14401int32x2_t test_vqrdmulh_lane_s32(int32x2_t a, int32x2_t b) {14402 return vqrdmulh_lane_s32(a, b, 1);14403}14404 14405// CHECK-LABEL: define <8 x i16> @test_vqrdmulhq_lane_s16(14406// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14407// CHECK-NEXT: [[ENTRY:.*:]]14408// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>14409// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14410// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>14411// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14412// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[LANE]] to <16 x i8>14413// CHECK-NEXT: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>14414// CHECK-NEXT: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <8 x i16>14415// CHECK-NEXT: [[VQRDMULHQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> [[VQRDMULHQ_V_I]], <8 x i16> [[VQRDMULHQ_V1_I]])14416// CHECK-NEXT: [[VQRDMULHQ_V3_I:%.*]] = bitcast <8 x i16> [[VQRDMULHQ_V2_I]] to <16 x i8>14417// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <8 x i16>14418// CHECK-NEXT: ret <8 x i16> [[TMP4]]14419//14420int16x8_t test_vqrdmulhq_lane_s16(int16x8_t a, int16x4_t b) {14421 return vqrdmulhq_lane_s16(a, b, 3);14422}14423 14424// CHECK-LABEL: define <4 x i32> @test_vqrdmulhq_lane_s32(14425// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14426// CHECK-NEXT: [[ENTRY:.*:]]14427// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>14428// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14429// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>14430// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14431// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[LANE]] to <16 x i8>14432// CHECK-NEXT: [[VQRDMULHQ_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x i32>14433// CHECK-NEXT: [[VQRDMULHQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x i32>14434// CHECK-NEXT: [[VQRDMULHQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> [[VQRDMULHQ_V_I]], <4 x i32> [[VQRDMULHQ_V1_I]])14435// CHECK-NEXT: [[VQRDMULHQ_V3_I:%.*]] = bitcast <4 x i32> [[VQRDMULHQ_V2_I]] to <16 x i8>14436// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I]] to <4 x i32>14437// CHECK-NEXT: ret <4 x i32> [[TMP4]]14438//14439int32x4_t test_vqrdmulhq_lane_s32(int32x4_t a, int32x2_t b) {14440 return vqrdmulhq_lane_s32(a, b, 1);14441}14442 14443// CHECK-LABEL: define <4 x i16> @test_vqrdmulh_n_s16(14444// CHECK-SAME: <4 x i16> noundef [[A:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {14445// CHECK-NEXT: [[ENTRY:.*:]]14446// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i32 014447// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[B]], i32 114448// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[B]], i32 214449// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[B]], i32 314450// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14451// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to <8 x i8>14452// CHECK-NEXT: [[VQRDMULH_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14453// CHECK-NEXT: [[VQRDMULH_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>14454// CHECK-NEXT: [[VQRDMULH_V2_I_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> [[VQRDMULH_V_I_I]], <4 x i16> [[VQRDMULH_V1_I_I]])14455// CHECK-NEXT: [[VQRDMULH_V3_I_I:%.*]] = bitcast <4 x i16> [[VQRDMULH_V2_I_I]] to <8 x i8>14456// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I_I]] to <4 x i16>14457// CHECK-NEXT: ret <4 x i16> [[TMP2]]14458//14459int16x4_t test_vqrdmulh_n_s16(int16x4_t a, int16_t b) {14460 return vqrdmulh_n_s16(a, b);14461}14462 14463// CHECK-LABEL: define <2 x i32> @test_vqrdmulh_n_s32(14464// CHECK-SAME: <2 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {14465// CHECK-NEXT: [[ENTRY:.*:]]14466// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i32 014467// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[B]], i32 114468// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14469// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to <8 x i8>14470// CHECK-NEXT: [[VQRDMULH_V_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14471// CHECK-NEXT: [[VQRDMULH_V1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>14472// CHECK-NEXT: [[VQRDMULH_V2_I_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> [[VQRDMULH_V_I_I]], <2 x i32> [[VQRDMULH_V1_I_I]])14473// CHECK-NEXT: [[VQRDMULH_V3_I_I:%.*]] = bitcast <2 x i32> [[VQRDMULH_V2_I_I]] to <8 x i8>14474// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRDMULH_V3_I_I]] to <2 x i32>14475// CHECK-NEXT: ret <2 x i32> [[TMP2]]14476//14477int32x2_t test_vqrdmulh_n_s32(int32x2_t a, int32_t b) {14478 return vqrdmulh_n_s32(a, b);14479}14480 14481// CHECK-LABEL: define <8 x i16> @test_vqrdmulhq_n_s16(14482// CHECK-SAME: <8 x i16> noundef [[A:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {14483// CHECK-NEXT: [[ENTRY:.*:]]14484// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[B]], i32 014485// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[B]], i32 114486// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[B]], i32 214487// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[B]], i32 314488// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[B]], i32 414489// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[B]], i32 514490// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[B]], i32 614491// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[B]], i32 714492// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14493// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <16 x i8>14494// CHECK-NEXT: [[VQRDMULHQ_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14495// CHECK-NEXT: [[VQRDMULHQ_V1_I_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>14496// CHECK-NEXT: [[VQRDMULHQ_V2_I_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> [[VQRDMULHQ_V_I_I]], <8 x i16> [[VQRDMULHQ_V1_I_I]])14497// CHECK-NEXT: [[VQRDMULHQ_V3_I_I:%.*]] = bitcast <8 x i16> [[VQRDMULHQ_V2_I_I]] to <16 x i8>14498// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I_I]] to <8 x i16>14499// CHECK-NEXT: ret <8 x i16> [[TMP2]]14500//14501int16x8_t test_vqrdmulhq_n_s16(int16x8_t a, int16_t b) {14502 return vqrdmulhq_n_s16(a, b);14503}14504 14505// CHECK-LABEL: define <4 x i32> @test_vqrdmulhq_n_s32(14506// CHECK-SAME: <4 x i32> noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {14507// CHECK-NEXT: [[ENTRY:.*:]]14508// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[B]], i32 014509// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[B]], i32 114510// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[B]], i32 214511// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[B]], i32 314512// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14513// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[VECINIT3_I]] to <16 x i8>14514// CHECK-NEXT: [[VQRDMULHQ_V_I_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14515// CHECK-NEXT: [[VQRDMULHQ_V1_I_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>14516// CHECK-NEXT: [[VQRDMULHQ_V2_I_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> [[VQRDMULHQ_V_I_I]], <4 x i32> [[VQRDMULHQ_V1_I_I]])14517// CHECK-NEXT: [[VQRDMULHQ_V3_I_I:%.*]] = bitcast <4 x i32> [[VQRDMULHQ_V2_I_I]] to <16 x i8>14518// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRDMULHQ_V3_I_I]] to <4 x i32>14519// CHECK-NEXT: ret <4 x i32> [[TMP2]]14520//14521int32x4_t test_vqrdmulhq_n_s32(int32x4_t a, int32_t b) {14522 return vqrdmulhq_n_s32(a, b);14523}14524 14525// CHECK-LABEL: define <8 x i8> @test_vqrshl_s8(14526// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {14527// CHECK-NEXT: [[ENTRY:.*:]]14528// CHECK-NEXT: [[VQRSHL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])14529// CHECK-NEXT: ret <8 x i8> [[VQRSHL_V_I]]14530//14531int8x8_t test_vqrshl_s8(int8x8_t a, int8x8_t b) {14532 return vqrshl_s8(a, b);14533}14534 14535// CHECK-LABEL: define <4 x i16> @test_vqrshl_s16(14536// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14537// CHECK-NEXT: [[ENTRY:.*:]]14538// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14539// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>14540// CHECK-NEXT: [[VQRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14541// CHECK-NEXT: [[VQRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>14542// CHECK-NEXT: [[VQRSHL_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16> [[VQRSHL_V_I]], <4 x i16> [[VQRSHL_V1_I]])14543// CHECK-NEXT: [[VQRSHL_V3_I:%.*]] = bitcast <4 x i16> [[VQRSHL_V2_I]] to <8 x i8>14544// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRSHL_V3_I]] to <4 x i16>14545// CHECK-NEXT: ret <4 x i16> [[TMP2]]14546//14547int16x4_t test_vqrshl_s16(int16x4_t a, int16x4_t b) {14548 return vqrshl_s16(a, b);14549}14550 14551// CHECK-LABEL: define <2 x i32> @test_vqrshl_s32(14552// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14553// CHECK-NEXT: [[ENTRY:.*:]]14554// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14555// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>14556// CHECK-NEXT: [[VQRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14557// CHECK-NEXT: [[VQRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>14558// CHECK-NEXT: [[VQRSHL_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32> [[VQRSHL_V_I]], <2 x i32> [[VQRSHL_V1_I]])14559// CHECK-NEXT: [[VQRSHL_V3_I:%.*]] = bitcast <2 x i32> [[VQRSHL_V2_I]] to <8 x i8>14560// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRSHL_V3_I]] to <2 x i32>14561// CHECK-NEXT: ret <2 x i32> [[TMP2]]14562//14563int32x2_t test_vqrshl_s32(int32x2_t a, int32x2_t b) {14564 return vqrshl_s32(a, b);14565}14566 14567// CHECK-LABEL: define <1 x i64> @test_vqrshl_s64(14568// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {14569// CHECK-NEXT: [[ENTRY:.*:]]14570// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>14571// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>14572// CHECK-NEXT: [[VQRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>14573// CHECK-NEXT: [[VQRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>14574// CHECK-NEXT: [[VQRSHL_V2_I:%.*]] = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> [[VQRSHL_V_I]], <1 x i64> [[VQRSHL_V1_I]])14575// CHECK-NEXT: [[VQRSHL_V3_I:%.*]] = bitcast <1 x i64> [[VQRSHL_V2_I]] to <8 x i8>14576// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRSHL_V3_I]] to i6414577// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 014578// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]14579//14580int64x1_t test_vqrshl_s64(int64x1_t a, int64x1_t b) {14581 return vqrshl_s64(a, b);14582}14583 14584// CHECK-LABEL: define <8 x i8> @test_vqrshl_u8(14585// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {14586// CHECK-NEXT: [[ENTRY:.*:]]14587// CHECK-NEXT: [[VQRSHL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])14588// CHECK-NEXT: ret <8 x i8> [[VQRSHL_V_I]]14589//14590uint8x8_t test_vqrshl_u8(uint8x8_t a, int8x8_t b) {14591 return vqrshl_u8(a, b);14592}14593 14594// CHECK-LABEL: define <4 x i16> @test_vqrshl_u16(14595// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14596// CHECK-NEXT: [[ENTRY:.*:]]14597// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14598// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>14599// CHECK-NEXT: [[VQRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14600// CHECK-NEXT: [[VQRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>14601// CHECK-NEXT: [[VQRSHL_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16> [[VQRSHL_V_I]], <4 x i16> [[VQRSHL_V1_I]])14602// CHECK-NEXT: [[VQRSHL_V3_I:%.*]] = bitcast <4 x i16> [[VQRSHL_V2_I]] to <8 x i8>14603// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRSHL_V3_I]] to <4 x i16>14604// CHECK-NEXT: ret <4 x i16> [[TMP2]]14605//14606uint16x4_t test_vqrshl_u16(uint16x4_t a, int16x4_t b) {14607 return vqrshl_u16(a, b);14608}14609 14610// CHECK-LABEL: define <2 x i32> @test_vqrshl_u32(14611// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14612// CHECK-NEXT: [[ENTRY:.*:]]14613// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14614// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>14615// CHECK-NEXT: [[VQRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14616// CHECK-NEXT: [[VQRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>14617// CHECK-NEXT: [[VQRSHL_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32> [[VQRSHL_V_I]], <2 x i32> [[VQRSHL_V1_I]])14618// CHECK-NEXT: [[VQRSHL_V3_I:%.*]] = bitcast <2 x i32> [[VQRSHL_V2_I]] to <8 x i8>14619// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRSHL_V3_I]] to <2 x i32>14620// CHECK-NEXT: ret <2 x i32> [[TMP2]]14621//14622uint32x2_t test_vqrshl_u32(uint32x2_t a, int32x2_t b) {14623 return vqrshl_u32(a, b);14624}14625 14626// CHECK-LABEL: define <1 x i64> @test_vqrshl_u64(14627// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {14628// CHECK-NEXT: [[ENTRY:.*:]]14629// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>14630// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>14631// CHECK-NEXT: [[VQRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>14632// CHECK-NEXT: [[VQRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>14633// CHECK-NEXT: [[VQRSHL_V2_I:%.*]] = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> [[VQRSHL_V_I]], <1 x i64> [[VQRSHL_V1_I]])14634// CHECK-NEXT: [[VQRSHL_V3_I:%.*]] = bitcast <1 x i64> [[VQRSHL_V2_I]] to <8 x i8>14635// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQRSHL_V3_I]] to i6414636// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 014637// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]14638//14639uint64x1_t test_vqrshl_u64(uint64x1_t a, int64x1_t b) {14640 return vqrshl_u64(a, b);14641}14642 14643// CHECK-LABEL: define <16 x i8> @test_vqrshlq_s8(14644// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {14645// CHECK-NEXT: [[ENTRY:.*:]]14646// CHECK-NEXT: [[VQRSHLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])14647// CHECK-NEXT: ret <16 x i8> [[VQRSHLQ_V_I]]14648//14649int8x16_t test_vqrshlq_s8(int8x16_t a, int8x16_t b) {14650 return vqrshlq_s8(a, b);14651}14652 14653// CHECK-LABEL: define <8 x i16> @test_vqrshlq_s16(14654// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14655// CHECK-NEXT: [[ENTRY:.*:]]14656// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14657// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>14658// CHECK-NEXT: [[VQRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14659// CHECK-NEXT: [[VQRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>14660// CHECK-NEXT: [[VQRSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16> [[VQRSHLQ_V_I]], <8 x i16> [[VQRSHLQ_V1_I]])14661// CHECK-NEXT: [[VQRSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VQRSHLQ_V2_I]] to <16 x i8>14662// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRSHLQ_V3_I]] to <8 x i16>14663// CHECK-NEXT: ret <8 x i16> [[TMP2]]14664//14665int16x8_t test_vqrshlq_s16(int16x8_t a, int16x8_t b) {14666 return vqrshlq_s16(a, b);14667}14668 14669// CHECK-LABEL: define <4 x i32> @test_vqrshlq_s32(14670// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14671// CHECK-NEXT: [[ENTRY:.*:]]14672// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14673// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>14674// CHECK-NEXT: [[VQRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14675// CHECK-NEXT: [[VQRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>14676// CHECK-NEXT: [[VQRSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32> [[VQRSHLQ_V_I]], <4 x i32> [[VQRSHLQ_V1_I]])14677// CHECK-NEXT: [[VQRSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VQRSHLQ_V2_I]] to <16 x i8>14678// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRSHLQ_V3_I]] to <4 x i32>14679// CHECK-NEXT: ret <4 x i32> [[TMP2]]14680//14681int32x4_t test_vqrshlq_s32(int32x4_t a, int32x4_t b) {14682 return vqrshlq_s32(a, b);14683}14684 14685// CHECK-LABEL: define <2 x i64> @test_vqrshlq_s64(14686// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {14687// CHECK-NEXT: [[ENTRY:.*:]]14688// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>14689// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>14690// CHECK-NEXT: [[VQRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>14691// CHECK-NEXT: [[VQRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>14692// CHECK-NEXT: [[VQRSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64> [[VQRSHLQ_V_I]], <2 x i64> [[VQRSHLQ_V1_I]])14693// CHECK-NEXT: [[VQRSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VQRSHLQ_V2_I]] to <16 x i8>14694// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRSHLQ_V3_I]] to <2 x i64>14695// CHECK-NEXT: ret <2 x i64> [[TMP2]]14696//14697int64x2_t test_vqrshlq_s64(int64x2_t a, int64x2_t b) {14698 return vqrshlq_s64(a, b);14699}14700 14701// CHECK-LABEL: define <16 x i8> @test_vqrshlq_u8(14702// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {14703// CHECK-NEXT: [[ENTRY:.*:]]14704// CHECK-NEXT: [[VQRSHLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])14705// CHECK-NEXT: ret <16 x i8> [[VQRSHLQ_V_I]]14706//14707uint8x16_t test_vqrshlq_u8(uint8x16_t a, int8x16_t b) {14708 return vqrshlq_u8(a, b);14709}14710 14711// CHECK-LABEL: define <8 x i16> @test_vqrshlq_u16(14712// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14713// CHECK-NEXT: [[ENTRY:.*:]]14714// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14715// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>14716// CHECK-NEXT: [[VQRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14717// CHECK-NEXT: [[VQRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>14718// CHECK-NEXT: [[VQRSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16> [[VQRSHLQ_V_I]], <8 x i16> [[VQRSHLQ_V1_I]])14719// CHECK-NEXT: [[VQRSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VQRSHLQ_V2_I]] to <16 x i8>14720// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRSHLQ_V3_I]] to <8 x i16>14721// CHECK-NEXT: ret <8 x i16> [[TMP2]]14722//14723uint16x8_t test_vqrshlq_u16(uint16x8_t a, int16x8_t b) {14724 return vqrshlq_u16(a, b);14725}14726 14727// CHECK-LABEL: define <4 x i32> @test_vqrshlq_u32(14728// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14729// CHECK-NEXT: [[ENTRY:.*:]]14730// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14731// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>14732// CHECK-NEXT: [[VQRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14733// CHECK-NEXT: [[VQRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>14734// CHECK-NEXT: [[VQRSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32> [[VQRSHLQ_V_I]], <4 x i32> [[VQRSHLQ_V1_I]])14735// CHECK-NEXT: [[VQRSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VQRSHLQ_V2_I]] to <16 x i8>14736// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRSHLQ_V3_I]] to <4 x i32>14737// CHECK-NEXT: ret <4 x i32> [[TMP2]]14738//14739uint32x4_t test_vqrshlq_u32(uint32x4_t a, int32x4_t b) {14740 return vqrshlq_u32(a, b);14741}14742 14743// CHECK-LABEL: define <2 x i64> @test_vqrshlq_u64(14744// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {14745// CHECK-NEXT: [[ENTRY:.*:]]14746// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>14747// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>14748// CHECK-NEXT: [[VQRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>14749// CHECK-NEXT: [[VQRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>14750// CHECK-NEXT: [[VQRSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64> [[VQRSHLQ_V_I]], <2 x i64> [[VQRSHLQ_V1_I]])14751// CHECK-NEXT: [[VQRSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VQRSHLQ_V2_I]] to <16 x i8>14752// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQRSHLQ_V3_I]] to <2 x i64>14753// CHECK-NEXT: ret <2 x i64> [[TMP2]]14754//14755uint64x2_t test_vqrshlq_u64(uint64x2_t a, int64x2_t b) {14756 return vqrshlq_u64(a, b);14757}14758 14759// CHECK-LABEL: define <8 x i8> @test_vqrshrn_n_s16(14760// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {14761// CHECK-NEXT: [[ENTRY:.*:]]14762// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14763// CHECK-NEXT: [[VQRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14764// CHECK-NEXT: [[VQRSHRN_N1:%.*]] = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> [[VQRSHRN_N]], <8 x i16> splat (i16 -1))14765// CHECK-NEXT: ret <8 x i8> [[VQRSHRN_N1]]14766//14767int8x8_t test_vqrshrn_n_s16(int16x8_t a) {14768 return vqrshrn_n_s16(a, 1);14769}14770 14771// CHECK-LABEL: define <4 x i16> @test_vqrshrn_n_s32(14772// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {14773// CHECK-NEXT: [[ENTRY:.*:]]14774// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14775// CHECK-NEXT: [[VQRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14776// CHECK-NEXT: [[VQRSHRN_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> [[VQRSHRN_N]], <4 x i32> splat (i32 -1))14777// CHECK-NEXT: ret <4 x i16> [[VQRSHRN_N1]]14778//14779int16x4_t test_vqrshrn_n_s32(int32x4_t a) {14780 return vqrshrn_n_s32(a, 1);14781}14782 14783// CHECK-LABEL: define <2 x i32> @test_vqrshrn_n_s64(14784// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {14785// CHECK-NEXT: [[ENTRY:.*:]]14786// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>14787// CHECK-NEXT: [[VQRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>14788// CHECK-NEXT: [[VQRSHRN_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> [[VQRSHRN_N]], <2 x i64> splat (i64 -1))14789// CHECK-NEXT: ret <2 x i32> [[VQRSHRN_N1]]14790//14791int32x2_t test_vqrshrn_n_s64(int64x2_t a) {14792 return vqrshrn_n_s64(a, 1);14793}14794 14795// CHECK-LABEL: define <8 x i8> @test_vqrshrn_n_u16(14796// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {14797// CHECK-NEXT: [[ENTRY:.*:]]14798// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14799// CHECK-NEXT: [[VQRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14800// CHECK-NEXT: [[VQRSHRN_N1:%.*]] = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> [[VQRSHRN_N]], <8 x i16> splat (i16 -1))14801// CHECK-NEXT: ret <8 x i8> [[VQRSHRN_N1]]14802//14803uint8x8_t test_vqrshrn_n_u16(uint16x8_t a) {14804 return vqrshrn_n_u16(a, 1);14805}14806 14807// CHECK-LABEL: define <4 x i16> @test_vqrshrn_n_u32(14808// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {14809// CHECK-NEXT: [[ENTRY:.*:]]14810// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14811// CHECK-NEXT: [[VQRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14812// CHECK-NEXT: [[VQRSHRN_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> [[VQRSHRN_N]], <4 x i32> splat (i32 -1))14813// CHECK-NEXT: ret <4 x i16> [[VQRSHRN_N1]]14814//14815uint16x4_t test_vqrshrn_n_u32(uint32x4_t a) {14816 return vqrshrn_n_u32(a, 1);14817}14818 14819// CHECK-LABEL: define <2 x i32> @test_vqrshrn_n_u64(14820// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {14821// CHECK-NEXT: [[ENTRY:.*:]]14822// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>14823// CHECK-NEXT: [[VQRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>14824// CHECK-NEXT: [[VQRSHRN_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> [[VQRSHRN_N]], <2 x i64> splat (i64 -1))14825// CHECK-NEXT: ret <2 x i32> [[VQRSHRN_N1]]14826//14827uint32x2_t test_vqrshrn_n_u64(uint64x2_t a) {14828 return vqrshrn_n_u64(a, 1);14829}14830 14831// CHECK-LABEL: define <8 x i8> @test_vqrshrun_n_s16(14832// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {14833// CHECK-NEXT: [[ENTRY:.*:]]14834// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14835// CHECK-NEXT: [[VQRSHRUN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>14836// CHECK-NEXT: [[VQRSHRUN_N1:%.*]] = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> [[VQRSHRUN_N]], <8 x i16> splat (i16 -1))14837// CHECK-NEXT: ret <8 x i8> [[VQRSHRUN_N1]]14838//14839uint8x8_t test_vqrshrun_n_s16(int16x8_t a) {14840 return vqrshrun_n_s16(a, 1);14841}14842 14843// CHECK-LABEL: define <4 x i16> @test_vqrshrun_n_s32(14844// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {14845// CHECK-NEXT: [[ENTRY:.*:]]14846// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>14847// CHECK-NEXT: [[VQRSHRUN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>14848// CHECK-NEXT: [[VQRSHRUN_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> [[VQRSHRUN_N]], <4 x i32> splat (i32 -1))14849// CHECK-NEXT: ret <4 x i16> [[VQRSHRUN_N1]]14850//14851uint16x4_t test_vqrshrun_n_s32(int32x4_t a) {14852 return vqrshrun_n_s32(a, 1);14853}14854 14855// CHECK-LABEL: define <2 x i32> @test_vqrshrun_n_s64(14856// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {14857// CHECK-NEXT: [[ENTRY:.*:]]14858// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>14859// CHECK-NEXT: [[VQRSHRUN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>14860// CHECK-NEXT: [[VQRSHRUN_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> [[VQRSHRUN_N]], <2 x i64> splat (i64 -1))14861// CHECK-NEXT: ret <2 x i32> [[VQRSHRUN_N1]]14862//14863uint32x2_t test_vqrshrun_n_s64(int64x2_t a) {14864 return vqrshrun_n_s64(a, 1);14865}14866 14867// CHECK-LABEL: define <8 x i8> @test_vqshl_s8(14868// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {14869// CHECK-NEXT: [[ENTRY:.*:]]14870// CHECK-NEXT: [[VQSHL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])14871// CHECK-NEXT: ret <8 x i8> [[VQSHL_V_I]]14872//14873int8x8_t test_vqshl_s8(int8x8_t a, int8x8_t b) {14874 return vqshl_s8(a, b);14875}14876 14877// CHECK-LABEL: define <4 x i16> @test_vqshl_s16(14878// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14879// CHECK-NEXT: [[ENTRY:.*:]]14880// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14881// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>14882// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14883// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>14884// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> [[VQSHL_V_I]], <4 x i16> [[VQSHL_V1_I]])14885// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <4 x i16> [[VQSHL_V2_I]] to <8 x i8>14886// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <4 x i16>14887// CHECK-NEXT: ret <4 x i16> [[TMP2]]14888//14889int16x4_t test_vqshl_s16(int16x4_t a, int16x4_t b) {14890 return vqshl_s16(a, b);14891}14892 14893// CHECK-LABEL: define <2 x i32> @test_vqshl_s32(14894// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14895// CHECK-NEXT: [[ENTRY:.*:]]14896// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14897// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>14898// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14899// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>14900// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> [[VQSHL_V_I]], <2 x i32> [[VQSHL_V1_I]])14901// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <2 x i32> [[VQSHL_V2_I]] to <8 x i8>14902// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <2 x i32>14903// CHECK-NEXT: ret <2 x i32> [[TMP2]]14904//14905int32x2_t test_vqshl_s32(int32x2_t a, int32x2_t b) {14906 return vqshl_s32(a, b);14907}14908 14909// CHECK-LABEL: define <1 x i64> @test_vqshl_s64(14910// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {14911// CHECK-NEXT: [[ENTRY:.*:]]14912// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>14913// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>14914// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>14915// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>14916// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> [[VQSHL_V_I]], <1 x i64> [[VQSHL_V1_I]])14917// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <1 x i64> [[VQSHL_V2_I]] to <8 x i8>14918// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to i6414919// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 014920// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]14921//14922int64x1_t test_vqshl_s64(int64x1_t a, int64x1_t b) {14923 return vqshl_s64(a, b);14924}14925 14926// CHECK-LABEL: define <8 x i8> @test_vqshl_u8(14927// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {14928// CHECK-NEXT: [[ENTRY:.*:]]14929// CHECK-NEXT: [[VQSHL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])14930// CHECK-NEXT: ret <8 x i8> [[VQSHL_V_I]]14931//14932uint8x8_t test_vqshl_u8(uint8x8_t a, int8x8_t b) {14933 return vqshl_u8(a, b);14934}14935 14936// CHECK-LABEL: define <4 x i16> @test_vqshl_u16(14937// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14938// CHECK-NEXT: [[ENTRY:.*:]]14939// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>14940// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>14941// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>14942// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>14943// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> [[VQSHL_V_I]], <4 x i16> [[VQSHL_V1_I]])14944// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <4 x i16> [[VQSHL_V2_I]] to <8 x i8>14945// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <4 x i16>14946// CHECK-NEXT: ret <4 x i16> [[TMP2]]14947//14948uint16x4_t test_vqshl_u16(uint16x4_t a, int16x4_t b) {14949 return vqshl_u16(a, b);14950}14951 14952// CHECK-LABEL: define <2 x i32> @test_vqshl_u32(14953// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {14954// CHECK-NEXT: [[ENTRY:.*:]]14955// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>14956// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>14957// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>14958// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>14959// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> [[VQSHL_V_I]], <2 x i32> [[VQSHL_V1_I]])14960// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <2 x i32> [[VQSHL_V2_I]] to <8 x i8>14961// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <2 x i32>14962// CHECK-NEXT: ret <2 x i32> [[TMP2]]14963//14964uint32x2_t test_vqshl_u32(uint32x2_t a, int32x2_t b) {14965 return vqshl_u32(a, b);14966}14967 14968// CHECK-LABEL: define <1 x i64> @test_vqshl_u64(14969// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {14970// CHECK-NEXT: [[ENTRY:.*:]]14971// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>14972// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>14973// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>14974// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>14975// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> [[VQSHL_V_I]], <1 x i64> [[VQSHL_V1_I]])14976// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <1 x i64> [[VQSHL_V2_I]] to <8 x i8>14977// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to i6414978// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 014979// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]14980//14981uint64x1_t test_vqshl_u64(uint64x1_t a, int64x1_t b) {14982 return vqshl_u64(a, b);14983}14984 14985// CHECK-LABEL: define <16 x i8> @test_vqshlq_s8(14986// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {14987// CHECK-NEXT: [[ENTRY:.*:]]14988// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])14989// CHECK-NEXT: ret <16 x i8> [[VQSHLQ_V_I]]14990//14991int8x16_t test_vqshlq_s8(int8x16_t a, int8x16_t b) {14992 return vqshlq_s8(a, b);14993}14994 14995// CHECK-LABEL: define <8 x i16> @test_vqshlq_s16(14996// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {14997// CHECK-NEXT: [[ENTRY:.*:]]14998// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>14999// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>15000// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15001// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>15002// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> [[VQSHLQ_V_I]], <8 x i16> [[VQSHLQ_V1_I]])15003// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSHLQ_V2_I]] to <16 x i8>15004// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <8 x i16>15005// CHECK-NEXT: ret <8 x i16> [[TMP2]]15006//15007int16x8_t test_vqshlq_s16(int16x8_t a, int16x8_t b) {15008 return vqshlq_s16(a, b);15009}15010 15011// CHECK-LABEL: define <4 x i32> @test_vqshlq_s32(15012// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {15013// CHECK-NEXT: [[ENTRY:.*:]]15014// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15015// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>15016// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15017// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>15018// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> [[VQSHLQ_V_I]], <4 x i32> [[VQSHLQ_V1_I]])15019// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSHLQ_V2_I]] to <16 x i8>15020// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <4 x i32>15021// CHECK-NEXT: ret <4 x i32> [[TMP2]]15022//15023int32x4_t test_vqshlq_s32(int32x4_t a, int32x4_t b) {15024 return vqshlq_s32(a, b);15025}15026 15027// CHECK-LABEL: define <2 x i64> @test_vqshlq_s64(15028// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {15029// CHECK-NEXT: [[ENTRY:.*:]]15030// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15031// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>15032// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15033// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>15034// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> [[VQSHLQ_V_I]], <2 x i64> [[VQSHLQ_V1_I]])15035// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSHLQ_V2_I]] to <16 x i8>15036// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <2 x i64>15037// CHECK-NEXT: ret <2 x i64> [[TMP2]]15038//15039int64x2_t test_vqshlq_s64(int64x2_t a, int64x2_t b) {15040 return vqshlq_s64(a, b);15041}15042 15043// CHECK-LABEL: define <16 x i8> @test_vqshlq_u8(15044// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {15045// CHECK-NEXT: [[ENTRY:.*:]]15046// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])15047// CHECK-NEXT: ret <16 x i8> [[VQSHLQ_V_I]]15048//15049uint8x16_t test_vqshlq_u8(uint8x16_t a, int8x16_t b) {15050 return vqshlq_u8(a, b);15051}15052 15053// CHECK-LABEL: define <8 x i16> @test_vqshlq_u16(15054// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {15055// CHECK-NEXT: [[ENTRY:.*:]]15056// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15057// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>15058// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15059// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>15060// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> [[VQSHLQ_V_I]], <8 x i16> [[VQSHLQ_V1_I]])15061// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSHLQ_V2_I]] to <16 x i8>15062// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <8 x i16>15063// CHECK-NEXT: ret <8 x i16> [[TMP2]]15064//15065uint16x8_t test_vqshlq_u16(uint16x8_t a, int16x8_t b) {15066 return vqshlq_u16(a, b);15067}15068 15069// CHECK-LABEL: define <4 x i32> @test_vqshlq_u32(15070// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {15071// CHECK-NEXT: [[ENTRY:.*:]]15072// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15073// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>15074// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15075// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>15076// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> [[VQSHLQ_V_I]], <4 x i32> [[VQSHLQ_V1_I]])15077// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSHLQ_V2_I]] to <16 x i8>15078// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <4 x i32>15079// CHECK-NEXT: ret <4 x i32> [[TMP2]]15080//15081uint32x4_t test_vqshlq_u32(uint32x4_t a, int32x4_t b) {15082 return vqshlq_u32(a, b);15083}15084 15085// CHECK-LABEL: define <2 x i64> @test_vqshlq_u64(15086// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {15087// CHECK-NEXT: [[ENTRY:.*:]]15088// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15089// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>15090// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15091// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>15092// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> [[VQSHLQ_V_I]], <2 x i64> [[VQSHLQ_V1_I]])15093// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSHLQ_V2_I]] to <16 x i8>15094// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <2 x i64>15095// CHECK-NEXT: ret <2 x i64> [[TMP2]]15096//15097uint64x2_t test_vqshlq_u64(uint64x2_t a, int64x2_t b) {15098 return vqshlq_u64(a, b);15099}15100 15101// CHECK-LABEL: define <8 x i8> @test_vqshlu_n_s8(15102// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {15103// CHECK-NEXT: [[ENTRY:.*:]]15104// CHECK-NEXT: [[VQSHLU_N:%.*]] = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 1))15105// CHECK-NEXT: ret <8 x i8> [[VQSHLU_N]]15106//15107uint8x8_t test_vqshlu_n_s8(int8x8_t a) {15108 return vqshlu_n_s8(a, 1);15109}15110 15111// CHECK-LABEL: define <4 x i16> @test_vqshlu_n_s16(15112// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15113// CHECK-NEXT: [[ENTRY:.*:]]15114// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>15115// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>15116// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> [[VQSHLU_N]], <4 x i16> splat (i16 1))15117// CHECK-NEXT: ret <4 x i16> [[VQSHLU_N1]]15118//15119uint16x4_t test_vqshlu_n_s16(int16x4_t a) {15120 return vqshlu_n_s16(a, 1);15121}15122 15123// CHECK-LABEL: define <2 x i32> @test_vqshlu_n_s32(15124// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15125// CHECK-NEXT: [[ENTRY:.*:]]15126// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>15127// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>15128// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> [[VQSHLU_N]], <2 x i32> splat (i32 1))15129// CHECK-NEXT: ret <2 x i32> [[VQSHLU_N1]]15130//15131uint32x2_t test_vqshlu_n_s32(int32x2_t a) {15132 return vqshlu_n_s32(a, 1);15133}15134 15135// CHECK-LABEL: define <1 x i64> @test_vqshlu_n_s64(15136// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15137// CHECK-NEXT: [[ENTRY:.*:]]15138// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>15139// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>15140// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> [[VQSHLU_N]], <1 x i64> splat (i64 1))15141// CHECK-NEXT: ret <1 x i64> [[VQSHLU_N1]]15142//15143uint64x1_t test_vqshlu_n_s64(int64x1_t a) {15144 return vqshlu_n_s64(a, 1);15145}15146 15147// CHECK-LABEL: define <16 x i8> @test_vqshluq_n_s8(15148// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {15149// CHECK-NEXT: [[ENTRY:.*:]]15150// CHECK-NEXT: [[VQSHLU_N:%.*]] = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 1))15151// CHECK-NEXT: ret <16 x i8> [[VQSHLU_N]]15152//15153uint8x16_t test_vqshluq_n_s8(int8x16_t a) {15154 return vqshluq_n_s8(a, 1);15155}15156 15157// CHECK-LABEL: define <8 x i16> @test_vqshluq_n_s16(15158// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15159// CHECK-NEXT: [[ENTRY:.*:]]15160// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15161// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15162// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> [[VQSHLU_N]], <8 x i16> splat (i16 1))15163// CHECK-NEXT: ret <8 x i16> [[VQSHLU_N1]]15164//15165uint16x8_t test_vqshluq_n_s16(int16x8_t a) {15166 return vqshluq_n_s16(a, 1);15167}15168 15169// CHECK-LABEL: define <4 x i32> @test_vqshluq_n_s32(15170// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15171// CHECK-NEXT: [[ENTRY:.*:]]15172// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15173// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15174// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> [[VQSHLU_N]], <4 x i32> splat (i32 1))15175// CHECK-NEXT: ret <4 x i32> [[VQSHLU_N1]]15176//15177uint32x4_t test_vqshluq_n_s32(int32x4_t a) {15178 return vqshluq_n_s32(a, 1);15179}15180 15181// CHECK-LABEL: define <2 x i64> @test_vqshluq_n_s64(15182// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15183// CHECK-NEXT: [[ENTRY:.*:]]15184// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15185// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15186// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> [[VQSHLU_N]], <2 x i64> splat (i64 1))15187// CHECK-NEXT: ret <2 x i64> [[VQSHLU_N1]]15188//15189uint64x2_t test_vqshluq_n_s64(int64x2_t a) {15190 return vqshluq_n_s64(a, 1);15191}15192 15193// CHECK-LABEL: define <8 x i8> @test_vqshl_n_s8(15194// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {15195// CHECK-NEXT: [[ENTRY:.*:]]15196// CHECK-NEXT: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 1))15197// CHECK-NEXT: ret <8 x i8> [[VQSHL_N]]15198//15199int8x8_t test_vqshl_n_s8(int8x8_t a) {15200 return vqshl_n_s8(a, 1);15201}15202 15203// CHECK-LABEL: define <4 x i16> @test_vqshl_n_s16(15204// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15205// CHECK-NEXT: [[ENTRY:.*:]]15206// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>15207// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>15208// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> splat (i16 1))15209// CHECK-NEXT: ret <4 x i16> [[VQSHL_N1]]15210//15211int16x4_t test_vqshl_n_s16(int16x4_t a) {15212 return vqshl_n_s16(a, 1);15213}15214 15215// CHECK-LABEL: define <2 x i32> @test_vqshl_n_s32(15216// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15217// CHECK-NEXT: [[ENTRY:.*:]]15218// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>15219// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>15220// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> splat (i32 1))15221// CHECK-NEXT: ret <2 x i32> [[VQSHL_N1]]15222//15223int32x2_t test_vqshl_n_s32(int32x2_t a) {15224 return vqshl_n_s32(a, 1);15225}15226 15227// CHECK-LABEL: define <1 x i64> @test_vqshl_n_s64(15228// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15229// CHECK-NEXT: [[ENTRY:.*:]]15230// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>15231// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>15232// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> splat (i64 1))15233// CHECK-NEXT: ret <1 x i64> [[VQSHL_N1]]15234//15235int64x1_t test_vqshl_n_s64(int64x1_t a) {15236 return vqshl_n_s64(a, 1);15237}15238 15239// CHECK-LABEL: define <8 x i8> @test_vqshl_n_u8(15240// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {15241// CHECK-NEXT: [[ENTRY:.*:]]15242// CHECK-NEXT: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 1))15243// CHECK-NEXT: ret <8 x i8> [[VQSHL_N]]15244//15245uint8x8_t test_vqshl_n_u8(uint8x8_t a) {15246 return vqshl_n_u8(a, 1);15247}15248 15249// CHECK-LABEL: define <4 x i16> @test_vqshl_n_u16(15250// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15251// CHECK-NEXT: [[ENTRY:.*:]]15252// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>15253// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>15254// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> splat (i16 1))15255// CHECK-NEXT: ret <4 x i16> [[VQSHL_N1]]15256//15257uint16x4_t test_vqshl_n_u16(uint16x4_t a) {15258 return vqshl_n_u16(a, 1);15259}15260 15261// CHECK-LABEL: define <2 x i32> @test_vqshl_n_u32(15262// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15263// CHECK-NEXT: [[ENTRY:.*:]]15264// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>15265// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>15266// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> splat (i32 1))15267// CHECK-NEXT: ret <2 x i32> [[VQSHL_N1]]15268//15269uint32x2_t test_vqshl_n_u32(uint32x2_t a) {15270 return vqshl_n_u32(a, 1);15271}15272 15273// CHECK-LABEL: define <1 x i64> @test_vqshl_n_u64(15274// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15275// CHECK-NEXT: [[ENTRY:.*:]]15276// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>15277// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>15278// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> splat (i64 1))15279// CHECK-NEXT: ret <1 x i64> [[VQSHL_N1]]15280//15281uint64x1_t test_vqshl_n_u64(uint64x1_t a) {15282 return vqshl_n_u64(a, 1);15283}15284 15285// CHECK-LABEL: define <16 x i8> @test_vqshlq_n_s8(15286// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {15287// CHECK-NEXT: [[ENTRY:.*:]]15288// CHECK-NEXT: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 1))15289// CHECK-NEXT: ret <16 x i8> [[VQSHL_N]]15290//15291int8x16_t test_vqshlq_n_s8(int8x16_t a) {15292 return vqshlq_n_s8(a, 1);15293}15294 15295// CHECK-LABEL: define <8 x i16> @test_vqshlq_n_s16(15296// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15297// CHECK-NEXT: [[ENTRY:.*:]]15298// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15299// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15300// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> splat (i16 1))15301// CHECK-NEXT: ret <8 x i16> [[VQSHL_N1]]15302//15303int16x8_t test_vqshlq_n_s16(int16x8_t a) {15304 return vqshlq_n_s16(a, 1);15305}15306 15307// CHECK-LABEL: define <4 x i32> @test_vqshlq_n_s32(15308// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15309// CHECK-NEXT: [[ENTRY:.*:]]15310// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15311// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15312// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> splat (i32 1))15313// CHECK-NEXT: ret <4 x i32> [[VQSHL_N1]]15314//15315int32x4_t test_vqshlq_n_s32(int32x4_t a) {15316 return vqshlq_n_s32(a, 1);15317}15318 15319// CHECK-LABEL: define <2 x i64> @test_vqshlq_n_s64(15320// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15321// CHECK-NEXT: [[ENTRY:.*:]]15322// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15323// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15324// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> splat (i64 1))15325// CHECK-NEXT: ret <2 x i64> [[VQSHL_N1]]15326//15327int64x2_t test_vqshlq_n_s64(int64x2_t a) {15328 return vqshlq_n_s64(a, 1);15329}15330 15331// CHECK-LABEL: define <16 x i8> @test_vqshlq_n_u8(15332// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {15333// CHECK-NEXT: [[ENTRY:.*:]]15334// CHECK-NEXT: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 1))15335// CHECK-NEXT: ret <16 x i8> [[VQSHL_N]]15336//15337uint8x16_t test_vqshlq_n_u8(uint8x16_t a) {15338 return vqshlq_n_u8(a, 1);15339}15340 15341// CHECK-LABEL: define <8 x i16> @test_vqshlq_n_u16(15342// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15343// CHECK-NEXT: [[ENTRY:.*:]]15344// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15345// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15346// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> splat (i16 1))15347// CHECK-NEXT: ret <8 x i16> [[VQSHL_N1]]15348//15349uint16x8_t test_vqshlq_n_u16(uint16x8_t a) {15350 return vqshlq_n_u16(a, 1);15351}15352 15353// CHECK-LABEL: define <4 x i32> @test_vqshlq_n_u32(15354// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15355// CHECK-NEXT: [[ENTRY:.*:]]15356// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15357// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15358// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> splat (i32 1))15359// CHECK-NEXT: ret <4 x i32> [[VQSHL_N1]]15360//15361uint32x4_t test_vqshlq_n_u32(uint32x4_t a) {15362 return vqshlq_n_u32(a, 1);15363}15364 15365// CHECK-LABEL: define <2 x i64> @test_vqshlq_n_u64(15366// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15367// CHECK-NEXT: [[ENTRY:.*:]]15368// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15369// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15370// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> splat (i64 1))15371// CHECK-NEXT: ret <2 x i64> [[VQSHL_N1]]15372//15373uint64x2_t test_vqshlq_n_u64(uint64x2_t a) {15374 return vqshlq_n_u64(a, 1);15375}15376 15377// CHECK-LABEL: define <8 x i8> @test_vqshrn_n_s16(15378// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15379// CHECK-NEXT: [[ENTRY:.*:]]15380// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15381// CHECK-NEXT: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15382// CHECK-NEXT: [[VQSHRN_N1:%.*]] = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> [[VQSHRN_N]], <8 x i16> splat (i16 -1))15383// CHECK-NEXT: ret <8 x i8> [[VQSHRN_N1]]15384//15385int8x8_t test_vqshrn_n_s16(int16x8_t a) {15386 return vqshrn_n_s16(a, 1);15387}15388 15389// CHECK-LABEL: define <4 x i16> @test_vqshrn_n_s32(15390// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15391// CHECK-NEXT: [[ENTRY:.*:]]15392// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15393// CHECK-NEXT: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15394// CHECK-NEXT: [[VQSHRN_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> [[VQSHRN_N]], <4 x i32> splat (i32 -1))15395// CHECK-NEXT: ret <4 x i16> [[VQSHRN_N1]]15396//15397int16x4_t test_vqshrn_n_s32(int32x4_t a) {15398 return vqshrn_n_s32(a, 1);15399}15400 15401// CHECK-LABEL: define <2 x i32> @test_vqshrn_n_s64(15402// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15403// CHECK-NEXT: [[ENTRY:.*:]]15404// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15405// CHECK-NEXT: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15406// CHECK-NEXT: [[VQSHRN_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> [[VQSHRN_N]], <2 x i64> splat (i64 -1))15407// CHECK-NEXT: ret <2 x i32> [[VQSHRN_N1]]15408//15409int32x2_t test_vqshrn_n_s64(int64x2_t a) {15410 return vqshrn_n_s64(a, 1);15411}15412 15413// CHECK-LABEL: define <8 x i8> @test_vqshrn_n_u16(15414// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15415// CHECK-NEXT: [[ENTRY:.*:]]15416// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15417// CHECK-NEXT: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15418// CHECK-NEXT: [[VQSHRN_N1:%.*]] = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> [[VQSHRN_N]], <8 x i16> splat (i16 -1))15419// CHECK-NEXT: ret <8 x i8> [[VQSHRN_N1]]15420//15421uint8x8_t test_vqshrn_n_u16(uint16x8_t a) {15422 return vqshrn_n_u16(a, 1);15423}15424 15425// CHECK-LABEL: define <4 x i16> @test_vqshrn_n_u32(15426// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15427// CHECK-NEXT: [[ENTRY:.*:]]15428// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15429// CHECK-NEXT: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15430// CHECK-NEXT: [[VQSHRN_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> [[VQSHRN_N]], <4 x i32> splat (i32 -1))15431// CHECK-NEXT: ret <4 x i16> [[VQSHRN_N1]]15432//15433uint16x4_t test_vqshrn_n_u32(uint32x4_t a) {15434 return vqshrn_n_u32(a, 1);15435}15436 15437// CHECK-LABEL: define <2 x i32> @test_vqshrn_n_u64(15438// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15439// CHECK-NEXT: [[ENTRY:.*:]]15440// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15441// CHECK-NEXT: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15442// CHECK-NEXT: [[VQSHRN_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> [[VQSHRN_N]], <2 x i64> splat (i64 -1))15443// CHECK-NEXT: ret <2 x i32> [[VQSHRN_N1]]15444//15445uint32x2_t test_vqshrn_n_u64(uint64x2_t a) {15446 return vqshrn_n_u64(a, 1);15447}15448 15449// CHECK-LABEL: define <8 x i8> @test_vqshrun_n_s16(15450// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15451// CHECK-NEXT: [[ENTRY:.*:]]15452// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15453// CHECK-NEXT: [[VQSHRUN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15454// CHECK-NEXT: [[VQSHRUN_N1:%.*]] = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> [[VQSHRUN_N]], <8 x i16> splat (i16 -1))15455// CHECK-NEXT: ret <8 x i8> [[VQSHRUN_N1]]15456//15457uint8x8_t test_vqshrun_n_s16(int16x8_t a) {15458 return vqshrun_n_s16(a, 1);15459}15460 15461// CHECK-LABEL: define <4 x i16> @test_vqshrun_n_s32(15462// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15463// CHECK-NEXT: [[ENTRY:.*:]]15464// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15465// CHECK-NEXT: [[VQSHRUN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15466// CHECK-NEXT: [[VQSHRUN_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> [[VQSHRUN_N]], <4 x i32> splat (i32 -1))15467// CHECK-NEXT: ret <4 x i16> [[VQSHRUN_N1]]15468//15469uint16x4_t test_vqshrun_n_s32(int32x4_t a) {15470 return vqshrun_n_s32(a, 1);15471}15472 15473// CHECK-LABEL: define <2 x i32> @test_vqshrun_n_s64(15474// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15475// CHECK-NEXT: [[ENTRY:.*:]]15476// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15477// CHECK-NEXT: [[VQSHRUN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15478// CHECK-NEXT: [[VQSHRUN_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> [[VQSHRUN_N]], <2 x i64> splat (i64 -1))15479// CHECK-NEXT: ret <2 x i32> [[VQSHRUN_N1]]15480//15481uint32x2_t test_vqshrun_n_s64(int64x2_t a) {15482 return vqshrun_n_s64(a, 1);15483}15484 15485// CHECK-LABEL: define <8 x i8> @test_vqsub_s8(15486// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {15487// CHECK-NEXT: [[ENTRY:.*:]]15488// CHECK-NEXT: [[VQSUB_V_I:%.*]] = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])15489// CHECK-NEXT: ret <8 x i8> [[VQSUB_V_I]]15490//15491int8x8_t test_vqsub_s8(int8x8_t a, int8x8_t b) {15492 return vqsub_s8(a, b);15493}15494 15495// CHECK-LABEL: define <4 x i16> @test_vqsub_s16(15496// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {15497// CHECK-NEXT: [[ENTRY:.*:]]15498// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>15499// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>15500// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>15501// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>15502// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> [[VQSUB_V_I]], <4 x i16> [[VQSUB_V1_I]])15503// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <4 x i16> [[VQSUB_V2_I]] to <8 x i8>15504// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <4 x i16>15505// CHECK-NEXT: ret <4 x i16> [[TMP2]]15506//15507int16x4_t test_vqsub_s16(int16x4_t a, int16x4_t b) {15508 return vqsub_s16(a, b);15509}15510 15511// CHECK-LABEL: define <2 x i32> @test_vqsub_s32(15512// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {15513// CHECK-NEXT: [[ENTRY:.*:]]15514// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>15515// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>15516// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>15517// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>15518// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> [[VQSUB_V_I]], <2 x i32> [[VQSUB_V1_I]])15519// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <2 x i32> [[VQSUB_V2_I]] to <8 x i8>15520// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <2 x i32>15521// CHECK-NEXT: ret <2 x i32> [[TMP2]]15522//15523int32x2_t test_vqsub_s32(int32x2_t a, int32x2_t b) {15524 return vqsub_s32(a, b);15525}15526 15527// CHECK-LABEL: define <1 x i64> @test_vqsub_s64(15528// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {15529// CHECK-NEXT: [[ENTRY:.*:]]15530// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>15531// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>15532// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>15533// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>15534// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <1 x i64> @llvm.ssub.sat.v1i64(<1 x i64> [[VQSUB_V_I]], <1 x i64> [[VQSUB_V1_I]])15535// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <1 x i64> [[VQSUB_V2_I]] to <8 x i8>15536// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to i6415537// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 015538// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]15539//15540int64x1_t test_vqsub_s64(int64x1_t a, int64x1_t b) {15541 return vqsub_s64(a, b);15542}15543 15544// CHECK-LABEL: define <8 x i8> @test_vqsub_u8(15545// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {15546// CHECK-NEXT: [[ENTRY:.*:]]15547// CHECK-NEXT: [[VQSUB_V_I:%.*]] = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])15548// CHECK-NEXT: ret <8 x i8> [[VQSUB_V_I]]15549//15550uint8x8_t test_vqsub_u8(uint8x8_t a, uint8x8_t b) {15551 return vqsub_u8(a, b);15552}15553 15554// CHECK-LABEL: define <4 x i16> @test_vqsub_u16(15555// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {15556// CHECK-NEXT: [[ENTRY:.*:]]15557// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>15558// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>15559// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>15560// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>15561// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> [[VQSUB_V_I]], <4 x i16> [[VQSUB_V1_I]])15562// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <4 x i16> [[VQSUB_V2_I]] to <8 x i8>15563// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <4 x i16>15564// CHECK-NEXT: ret <4 x i16> [[TMP2]]15565//15566uint16x4_t test_vqsub_u16(uint16x4_t a, uint16x4_t b) {15567 return vqsub_u16(a, b);15568}15569 15570// CHECK-LABEL: define <2 x i32> @test_vqsub_u32(15571// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {15572// CHECK-NEXT: [[ENTRY:.*:]]15573// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>15574// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>15575// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>15576// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>15577// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> [[VQSUB_V_I]], <2 x i32> [[VQSUB_V1_I]])15578// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <2 x i32> [[VQSUB_V2_I]] to <8 x i8>15579// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to <2 x i32>15580// CHECK-NEXT: ret <2 x i32> [[TMP2]]15581//15582uint32x2_t test_vqsub_u32(uint32x2_t a, uint32x2_t b) {15583 return vqsub_u32(a, b);15584}15585 15586// CHECK-LABEL: define <1 x i64> @test_vqsub_u64(15587// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {15588// CHECK-NEXT: [[ENTRY:.*:]]15589// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>15590// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>15591// CHECK-NEXT: [[VQSUB_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>15592// CHECK-NEXT: [[VQSUB_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>15593// CHECK-NEXT: [[VQSUB_V2_I:%.*]] = call <1 x i64> @llvm.usub.sat.v1i64(<1 x i64> [[VQSUB_V_I]], <1 x i64> [[VQSUB_V1_I]])15594// CHECK-NEXT: [[VQSUB_V3_I:%.*]] = bitcast <1 x i64> [[VQSUB_V2_I]] to <8 x i8>15595// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSUB_V3_I]] to i6415596// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 015597// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]15598//15599uint64x1_t test_vqsub_u64(uint64x1_t a, uint64x1_t b) {15600 return vqsub_u64(a, b);15601}15602 15603// CHECK-LABEL: define <16 x i8> @test_vqsubq_s8(15604// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {15605// CHECK-NEXT: [[ENTRY:.*:]]15606// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])15607// CHECK-NEXT: ret <16 x i8> [[VQSUBQ_V_I]]15608//15609int8x16_t test_vqsubq_s8(int8x16_t a, int8x16_t b) {15610 return vqsubq_s8(a, b);15611}15612 15613// CHECK-LABEL: define <8 x i16> @test_vqsubq_s16(15614// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {15615// CHECK-NEXT: [[ENTRY:.*:]]15616// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15617// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>15618// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15619// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>15620// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> [[VQSUBQ_V_I]], <8 x i16> [[VQSUBQ_V1_I]])15621// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSUBQ_V2_I]] to <16 x i8>15622// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <8 x i16>15623// CHECK-NEXT: ret <8 x i16> [[TMP2]]15624//15625int16x8_t test_vqsubq_s16(int16x8_t a, int16x8_t b) {15626 return vqsubq_s16(a, b);15627}15628 15629// CHECK-LABEL: define <4 x i32> @test_vqsubq_s32(15630// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {15631// CHECK-NEXT: [[ENTRY:.*:]]15632// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15633// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>15634// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15635// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>15636// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> [[VQSUBQ_V_I]], <4 x i32> [[VQSUBQ_V1_I]])15637// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSUBQ_V2_I]] to <16 x i8>15638// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <4 x i32>15639// CHECK-NEXT: ret <4 x i32> [[TMP2]]15640//15641int32x4_t test_vqsubq_s32(int32x4_t a, int32x4_t b) {15642 return vqsubq_s32(a, b);15643}15644 15645// CHECK-LABEL: define <2 x i64> @test_vqsubq_s64(15646// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {15647// CHECK-NEXT: [[ENTRY:.*:]]15648// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15649// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>15650// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15651// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>15652// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> [[VQSUBQ_V_I]], <2 x i64> [[VQSUBQ_V1_I]])15653// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSUBQ_V2_I]] to <16 x i8>15654// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <2 x i64>15655// CHECK-NEXT: ret <2 x i64> [[TMP2]]15656//15657int64x2_t test_vqsubq_s64(int64x2_t a, int64x2_t b) {15658 return vqsubq_s64(a, b);15659}15660 15661// CHECK-LABEL: define <16 x i8> @test_vqsubq_u8(15662// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {15663// CHECK-NEXT: [[ENTRY:.*:]]15664// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])15665// CHECK-NEXT: ret <16 x i8> [[VQSUBQ_V_I]]15666//15667uint8x16_t test_vqsubq_u8(uint8x16_t a, uint8x16_t b) {15668 return vqsubq_u8(a, b);15669}15670 15671// CHECK-LABEL: define <8 x i16> @test_vqsubq_u16(15672// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {15673// CHECK-NEXT: [[ENTRY:.*:]]15674// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15675// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>15676// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15677// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>15678// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> [[VQSUBQ_V_I]], <8 x i16> [[VQSUBQ_V1_I]])15679// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSUBQ_V2_I]] to <16 x i8>15680// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <8 x i16>15681// CHECK-NEXT: ret <8 x i16> [[TMP2]]15682//15683uint16x8_t test_vqsubq_u16(uint16x8_t a, uint16x8_t b) {15684 return vqsubq_u16(a, b);15685}15686 15687// CHECK-LABEL: define <4 x i32> @test_vqsubq_u32(15688// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {15689// CHECK-NEXT: [[ENTRY:.*:]]15690// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15691// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>15692// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15693// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>15694// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> [[VQSUBQ_V_I]], <4 x i32> [[VQSUBQ_V1_I]])15695// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSUBQ_V2_I]] to <16 x i8>15696// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <4 x i32>15697// CHECK-NEXT: ret <4 x i32> [[TMP2]]15698//15699uint32x4_t test_vqsubq_u32(uint32x4_t a, uint32x4_t b) {15700 return vqsubq_u32(a, b);15701}15702 15703// CHECK-LABEL: define <2 x i64> @test_vqsubq_u64(15704// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {15705// CHECK-NEXT: [[ENTRY:.*:]]15706// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15707// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>15708// CHECK-NEXT: [[VQSUBQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15709// CHECK-NEXT: [[VQSUBQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>15710// CHECK-NEXT: [[VQSUBQ_V2_I:%.*]] = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> [[VQSUBQ_V_I]], <2 x i64> [[VQSUBQ_V1_I]])15711// CHECK-NEXT: [[VQSUBQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSUBQ_V2_I]] to <16 x i8>15712// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSUBQ_V3_I]] to <2 x i64>15713// CHECK-NEXT: ret <2 x i64> [[TMP2]]15714//15715uint64x2_t test_vqsubq_u64(uint64x2_t a, uint64x2_t b) {15716 return vqsubq_u64(a, b);15717}15718 15719// CHECK-LABEL: define <8 x i8> @test_vraddhn_s16(15720// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {15721// CHECK-NEXT: [[ENTRY:.*:]]15722// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15723// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>15724// CHECK-NEXT: [[VRADDHN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15725// CHECK-NEXT: [[VRADDHN_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>15726// CHECK-NEXT: [[VRADDHN_V2_I:%.*]] = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> [[VRADDHN_V_I]], <8 x i16> [[VRADDHN_V1_I]])15727// CHECK-NEXT: ret <8 x i8> [[VRADDHN_V2_I]]15728//15729int8x8_t test_vraddhn_s16(int16x8_t a, int16x8_t b) {15730 return vraddhn_s16(a, b);15731}15732 15733// CHECK-LABEL: define <4 x i16> @test_vraddhn_s32(15734// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {15735// CHECK-NEXT: [[ENTRY:.*:]]15736// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15737// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>15738// CHECK-NEXT: [[VRADDHN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15739// CHECK-NEXT: [[VRADDHN_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>15740// CHECK-NEXT: [[VRADDHN_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> [[VRADDHN_V_I]], <4 x i32> [[VRADDHN_V1_I]])15741// CHECK-NEXT: [[VRADDHN_V3_I:%.*]] = bitcast <4 x i16> [[VRADDHN_V2_I]] to <8 x i8>15742// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRADDHN_V3_I]] to <4 x i16>15743// CHECK-NEXT: ret <4 x i16> [[TMP2]]15744//15745int16x4_t test_vraddhn_s32(int32x4_t a, int32x4_t b) {15746 return vraddhn_s32(a, b);15747}15748 15749// CHECK-LABEL: define <2 x i32> @test_vraddhn_s64(15750// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {15751// CHECK-NEXT: [[ENTRY:.*:]]15752// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15753// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>15754// CHECK-NEXT: [[VRADDHN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15755// CHECK-NEXT: [[VRADDHN_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>15756// CHECK-NEXT: [[VRADDHN_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> [[VRADDHN_V_I]], <2 x i64> [[VRADDHN_V1_I]])15757// CHECK-NEXT: [[VRADDHN_V3_I:%.*]] = bitcast <2 x i32> [[VRADDHN_V2_I]] to <8 x i8>15758// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRADDHN_V3_I]] to <2 x i32>15759// CHECK-NEXT: ret <2 x i32> [[TMP2]]15760//15761int32x2_t test_vraddhn_s64(int64x2_t a, int64x2_t b) {15762 return vraddhn_s64(a, b);15763}15764 15765// CHECK-LABEL: define <8 x i8> @test_vraddhn_u16(15766// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {15767// CHECK-NEXT: [[ENTRY:.*:]]15768// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>15769// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>15770// CHECK-NEXT: [[VRADDHN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>15771// CHECK-NEXT: [[VRADDHN_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>15772// CHECK-NEXT: [[VRADDHN_V2_I:%.*]] = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> [[VRADDHN_V_I]], <8 x i16> [[VRADDHN_V1_I]])15773// CHECK-NEXT: ret <8 x i8> [[VRADDHN_V2_I]]15774//15775uint8x8_t test_vraddhn_u16(uint16x8_t a, uint16x8_t b) {15776 return vraddhn_u16(a, b);15777}15778 15779// CHECK-LABEL: define <4 x i16> @test_vraddhn_u32(15780// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {15781// CHECK-NEXT: [[ENTRY:.*:]]15782// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15783// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>15784// CHECK-NEXT: [[VRADDHN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15785// CHECK-NEXT: [[VRADDHN_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>15786// CHECK-NEXT: [[VRADDHN_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> [[VRADDHN_V_I]], <4 x i32> [[VRADDHN_V1_I]])15787// CHECK-NEXT: [[VRADDHN_V3_I:%.*]] = bitcast <4 x i16> [[VRADDHN_V2_I]] to <8 x i8>15788// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRADDHN_V3_I]] to <4 x i16>15789// CHECK-NEXT: ret <4 x i16> [[TMP2]]15790//15791uint16x4_t test_vraddhn_u32(uint32x4_t a, uint32x4_t b) {15792 return vraddhn_u32(a, b);15793}15794 15795// CHECK-LABEL: define <2 x i32> @test_vraddhn_u64(15796// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {15797// CHECK-NEXT: [[ENTRY:.*:]]15798// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>15799// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>15800// CHECK-NEXT: [[VRADDHN_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>15801// CHECK-NEXT: [[VRADDHN_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>15802// CHECK-NEXT: [[VRADDHN_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> [[VRADDHN_V_I]], <2 x i64> [[VRADDHN_V1_I]])15803// CHECK-NEXT: [[VRADDHN_V3_I:%.*]] = bitcast <2 x i32> [[VRADDHN_V2_I]] to <8 x i8>15804// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRADDHN_V3_I]] to <2 x i32>15805// CHECK-NEXT: ret <2 x i32> [[TMP2]]15806//15807uint32x2_t test_vraddhn_u64(uint64x2_t a, uint64x2_t b) {15808 return vraddhn_u64(a, b);15809}15810 15811// CHECK-LABEL: define <2 x float> @test_vrecpe_f32(15812// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {15813// CHECK-NEXT: [[ENTRY:.*:]]15814// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>15815// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>15816// CHECK-NEXT: [[VRECPE_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>15817// CHECK-NEXT: [[VRECPE_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> [[VRECPE_V_I]])15818// CHECK-NEXT: ret <2 x float> [[VRECPE_V1_I]]15819//15820float32x2_t test_vrecpe_f32(float32x2_t a) {15821 return vrecpe_f32(a);15822}15823 15824// CHECK-LABEL: define <2 x i32> @test_vrecpe_u32(15825// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15826// CHECK-NEXT: [[ENTRY:.*:]]15827// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>15828// CHECK-NEXT: [[VRECPE_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>15829// CHECK-NEXT: [[VRECPE_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> [[VRECPE_V_I]])15830// CHECK-NEXT: ret <2 x i32> [[VRECPE_V1_I]]15831//15832uint32x2_t test_vrecpe_u32(uint32x2_t a) {15833 return vrecpe_u32(a);15834}15835 15836// CHECK-LABEL: define <4 x float> @test_vrecpeq_f32(15837// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {15838// CHECK-NEXT: [[ENTRY:.*:]]15839// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>15840// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>15841// CHECK-NEXT: [[VRECPEQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>15842// CHECK-NEXT: [[VRECPEQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> [[VRECPEQ_V_I]])15843// CHECK-NEXT: ret <4 x float> [[VRECPEQ_V1_I]]15844//15845float32x4_t test_vrecpeq_f32(float32x4_t a) {15846 return vrecpeq_f32(a);15847}15848 15849// CHECK-LABEL: define <4 x i32> @test_vrecpeq_u32(15850// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15851// CHECK-NEXT: [[ENTRY:.*:]]15852// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>15853// CHECK-NEXT: [[VRECPEQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>15854// CHECK-NEXT: [[VRECPEQ_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> [[VRECPEQ_V_I]])15855// CHECK-NEXT: ret <4 x i32> [[VRECPEQ_V1_I]]15856//15857uint32x4_t test_vrecpeq_u32(uint32x4_t a) {15858 return vrecpeq_u32(a);15859}15860 15861// CHECK-LABEL: define <2 x float> @test_vrecps_f32(15862// CHECK-SAME: <2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {15863// CHECK-NEXT: [[ENTRY:.*:]]15864// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>15865// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>15866// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>15867// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP1]] to <8 x i8>15868// CHECK-NEXT: [[VRECPS_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>15869// CHECK-NEXT: [[VRECPS_V1_I:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x float>15870// CHECK-NEXT: [[VRECPS_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> [[VRECPS_V_I]], <2 x float> [[VRECPS_V1_I]])15871// CHECK-NEXT: [[VRECPS_V3_I:%.*]] = bitcast <2 x float> [[VRECPS_V2_I]] to <8 x i8>15872// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[VRECPS_V3_I]] to <2 x i32>15873// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>15874// CHECK-NEXT: ret <2 x float> [[TMP5]]15875//15876float32x2_t test_vrecps_f32(float32x2_t a, float32x2_t b) {15877 return vrecps_f32(a, b);15878}15879 15880// CHECK-LABEL: define <4 x float> @test_vrecpsq_f32(15881// CHECK-SAME: <4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {15882// CHECK-NEXT: [[ENTRY:.*:]]15883// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>15884// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>15885// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>15886// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <16 x i8>15887// CHECK-NEXT: [[VRECPSQ_V_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>15888// CHECK-NEXT: [[VRECPSQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP3]] to <4 x float>15889// CHECK-NEXT: [[VRECPSQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> [[VRECPSQ_V_I]], <4 x float> [[VRECPSQ_V1_I]])15890// CHECK-NEXT: [[VRECPSQ_V3_I:%.*]] = bitcast <4 x float> [[VRECPSQ_V2_I]] to <16 x i8>15891// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[VRECPSQ_V3_I]] to <4 x i32>15892// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>15893// CHECK-NEXT: ret <4 x float> [[TMP5]]15894//15895float32x4_t test_vrecpsq_f32(float32x4_t a, float32x4_t b) {15896 return vrecpsq_f32(a, b);15897}15898 15899// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_s16(15900// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15901// CHECK-NEXT: [[ENTRY:.*:]]15902// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>15903// CHECK-NEXT: ret <8 x i8> [[TMP0]]15904//15905int8x8_t test_vreinterpret_s8_s16(int16x4_t a) {15906 return vreinterpret_s8_s16(a);15907}15908 15909// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_s32(15910// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15911// CHECK-NEXT: [[ENTRY:.*:]]15912// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>15913// CHECK-NEXT: ret <8 x i8> [[TMP0]]15914//15915int8x8_t test_vreinterpret_s8_s32(int32x2_t a) {15916 return vreinterpret_s8_s32(a);15917}15918 15919// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_s64(15920// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15921// CHECK-NEXT: [[ENTRY:.*:]]15922// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>15923// CHECK-NEXT: ret <8 x i8> [[TMP0]]15924//15925int8x8_t test_vreinterpret_s8_s64(int64x1_t a) {15926 return vreinterpret_s8_s64(a);15927}15928 15929// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_u8(15930// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {15931// CHECK-NEXT: [[ENTRY:.*:]]15932// CHECK-NEXT: ret <8 x i8> [[A]]15933//15934int8x8_t test_vreinterpret_s8_u8(uint8x8_t a) {15935 return vreinterpret_s8_u8(a);15936}15937 15938// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_u16(15939// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {15940// CHECK-NEXT: [[ENTRY:.*:]]15941// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>15942// CHECK-NEXT: ret <8 x i8> [[TMP0]]15943//15944int8x8_t test_vreinterpret_s8_u16(uint16x4_t a) {15945 return vreinterpret_s8_u16(a);15946}15947 15948// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_u32(15949// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {15950// CHECK-NEXT: [[ENTRY:.*:]]15951// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>15952// CHECK-NEXT: ret <8 x i8> [[TMP0]]15953//15954int8x8_t test_vreinterpret_s8_u32(uint32x2_t a) {15955 return vreinterpret_s8_u32(a);15956}15957 15958// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_u64(15959// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {15960// CHECK-NEXT: [[ENTRY:.*:]]15961// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>15962// CHECK-NEXT: ret <8 x i8> [[TMP0]]15963//15964int8x8_t test_vreinterpret_s8_u64(uint64x1_t a) {15965 return vreinterpret_s8_u64(a);15966}15967 15968// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_f16(15969// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {15970// CHECK-NEXT: [[ENTRY:.*:]]15971// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>15972// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>15973// CHECK-NEXT: ret <8 x i8> [[TMP1]]15974//15975int8x8_t test_vreinterpret_s8_f16(float16x4_t a) {15976 return vreinterpret_s8_f16(a);15977}15978 15979// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_f32(15980// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {15981// CHECK-NEXT: [[ENTRY:.*:]]15982// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>15983// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>15984// CHECK-NEXT: ret <8 x i8> [[TMP1]]15985//15986int8x8_t test_vreinterpret_s8_f32(float32x2_t a) {15987 return vreinterpret_s8_f32(a);15988}15989 15990// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_p8(15991// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {15992// CHECK-NEXT: [[ENTRY:.*:]]15993// CHECK-NEXT: ret <8 x i8> [[A]]15994//15995int8x8_t test_vreinterpret_s8_p8(poly8x8_t a) {15996 return vreinterpret_s8_p8(a);15997}15998 15999// CHECK-LABEL: define <8 x i8> @test_vreinterpret_s8_p16(16000// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16001// CHECK-NEXT: [[ENTRY:.*:]]16002// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>16003// CHECK-NEXT: ret <8 x i8> [[TMP0]]16004//16005int8x8_t test_vreinterpret_s8_p16(poly16x4_t a) {16006 return vreinterpret_s8_p16(a);16007}16008 16009// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_s8(16010// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16011// CHECK-NEXT: [[ENTRY:.*:]]16012// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>16013// CHECK-NEXT: ret <4 x i16> [[TMP0]]16014//16015int16x4_t test_vreinterpret_s16_s8(int8x8_t a) {16016 return vreinterpret_s16_s8(a);16017}16018 16019// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_s32(16020// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16021// CHECK-NEXT: [[ENTRY:.*:]]16022// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <4 x i16>16023// CHECK-NEXT: ret <4 x i16> [[TMP0]]16024//16025int16x4_t test_vreinterpret_s16_s32(int32x2_t a) {16026 return vreinterpret_s16_s32(a);16027}16028 16029// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_s64(16030// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16031// CHECK-NEXT: [[ENTRY:.*:]]16032// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>16033// CHECK-NEXT: ret <4 x i16> [[TMP0]]16034//16035int16x4_t test_vreinterpret_s16_s64(int64x1_t a) {16036 return vreinterpret_s16_s64(a);16037}16038 16039// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_u8(16040// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16041// CHECK-NEXT: [[ENTRY:.*:]]16042// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>16043// CHECK-NEXT: ret <4 x i16> [[TMP0]]16044//16045int16x4_t test_vreinterpret_s16_u8(uint8x8_t a) {16046 return vreinterpret_s16_u8(a);16047}16048 16049// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_u16(16050// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16051// CHECK-NEXT: [[ENTRY:.*:]]16052// CHECK-NEXT: ret <4 x i16> [[A]]16053//16054int16x4_t test_vreinterpret_s16_u16(uint16x4_t a) {16055 return vreinterpret_s16_u16(a);16056}16057 16058// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_u32(16059// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16060// CHECK-NEXT: [[ENTRY:.*:]]16061// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <4 x i16>16062// CHECK-NEXT: ret <4 x i16> [[TMP0]]16063//16064int16x4_t test_vreinterpret_s16_u32(uint32x2_t a) {16065 return vreinterpret_s16_u32(a);16066}16067 16068// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_u64(16069// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16070// CHECK-NEXT: [[ENTRY:.*:]]16071// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>16072// CHECK-NEXT: ret <4 x i16> [[TMP0]]16073//16074int16x4_t test_vreinterpret_s16_u64(uint64x1_t a) {16075 return vreinterpret_s16_u64(a);16076}16077 16078// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_f16(16079// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {16080// CHECK-NEXT: [[ENTRY:.*:]]16081// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>16082// CHECK-NEXT: ret <4 x i16> [[TMP0]]16083//16084int16x4_t test_vreinterpret_s16_f16(float16x4_t a) {16085 return vreinterpret_s16_f16(a);16086}16087 16088// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_f32(16089// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {16090// CHECK-NEXT: [[ENTRY:.*:]]16091// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>16092// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <4 x i16>16093// CHECK-NEXT: ret <4 x i16> [[TMP1]]16094//16095int16x4_t test_vreinterpret_s16_f32(float32x2_t a) {16096 return vreinterpret_s16_f32(a);16097}16098 16099// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_p8(16100// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16101// CHECK-NEXT: [[ENTRY:.*:]]16102// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>16103// CHECK-NEXT: ret <4 x i16> [[TMP0]]16104//16105int16x4_t test_vreinterpret_s16_p8(poly8x8_t a) {16106 return vreinterpret_s16_p8(a);16107}16108 16109// CHECK-LABEL: define <4 x i16> @test_vreinterpret_s16_p16(16110// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16111// CHECK-NEXT: [[ENTRY:.*:]]16112// CHECK-NEXT: ret <4 x i16> [[A]]16113//16114int16x4_t test_vreinterpret_s16_p16(poly16x4_t a) {16115 return vreinterpret_s16_p16(a);16116}16117 16118// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_s8(16119// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16120// CHECK-NEXT: [[ENTRY:.*:]]16121// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <2 x i32>16122// CHECK-NEXT: ret <2 x i32> [[TMP0]]16123//16124int32x2_t test_vreinterpret_s32_s8(int8x8_t a) {16125 return vreinterpret_s32_s8(a);16126}16127 16128// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_s16(16129// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16130// CHECK-NEXT: [[ENTRY:.*:]]16131// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <2 x i32>16132// CHECK-NEXT: ret <2 x i32> [[TMP0]]16133//16134int32x2_t test_vreinterpret_s32_s16(int16x4_t a) {16135 return vreinterpret_s32_s16(a);16136}16137 16138// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_s64(16139// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16140// CHECK-NEXT: [[ENTRY:.*:]]16141// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>16142// CHECK-NEXT: ret <2 x i32> [[TMP0]]16143//16144int32x2_t test_vreinterpret_s32_s64(int64x1_t a) {16145 return vreinterpret_s32_s64(a);16146}16147 16148// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_u8(16149// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16150// CHECK-NEXT: [[ENTRY:.*:]]16151// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <2 x i32>16152// CHECK-NEXT: ret <2 x i32> [[TMP0]]16153//16154int32x2_t test_vreinterpret_s32_u8(uint8x8_t a) {16155 return vreinterpret_s32_u8(a);16156}16157 16158// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_u16(16159// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16160// CHECK-NEXT: [[ENTRY:.*:]]16161// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <2 x i32>16162// CHECK-NEXT: ret <2 x i32> [[TMP0]]16163//16164int32x2_t test_vreinterpret_s32_u16(uint16x4_t a) {16165 return vreinterpret_s32_u16(a);16166}16167 16168// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_u32(16169// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16170// CHECK-NEXT: [[ENTRY:.*:]]16171// CHECK-NEXT: ret <2 x i32> [[A]]16172//16173int32x2_t test_vreinterpret_s32_u32(uint32x2_t a) {16174 return vreinterpret_s32_u32(a);16175}16176 16177// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_u64(16178// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16179// CHECK-NEXT: [[ENTRY:.*:]]16180// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>16181// CHECK-NEXT: ret <2 x i32> [[TMP0]]16182//16183int32x2_t test_vreinterpret_s32_u64(uint64x1_t a) {16184 return vreinterpret_s32_u64(a);16185}16186 16187// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_f16(16188// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {16189// CHECK-NEXT: [[ENTRY:.*:]]16190// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <2 x i32>16191// CHECK-NEXT: ret <2 x i32> [[TMP0]]16192//16193int32x2_t test_vreinterpret_s32_f16(float16x4_t a) {16194 return vreinterpret_s32_f16(a);16195}16196 16197// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_f32(16198// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {16199// CHECK-NEXT: [[ENTRY:.*:]]16200// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>16201// CHECK-NEXT: ret <2 x i32> [[TMP0]]16202//16203int32x2_t test_vreinterpret_s32_f32(float32x2_t a) {16204 return vreinterpret_s32_f32(a);16205}16206 16207// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_p8(16208// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16209// CHECK-NEXT: [[ENTRY:.*:]]16210// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <2 x i32>16211// CHECK-NEXT: ret <2 x i32> [[TMP0]]16212//16213int32x2_t test_vreinterpret_s32_p8(poly8x8_t a) {16214 return vreinterpret_s32_p8(a);16215}16216 16217// CHECK-LABEL: define <2 x i32> @test_vreinterpret_s32_p16(16218// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16219// CHECK-NEXT: [[ENTRY:.*:]]16220// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <2 x i32>16221// CHECK-NEXT: ret <2 x i32> [[TMP0]]16222//16223int32x2_t test_vreinterpret_s32_p16(poly16x4_t a) {16224 return vreinterpret_s32_p16(a);16225}16226 16227// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_s8(16228// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16229// CHECK-NEXT: [[ENTRY:.*:]]16230// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to i6416231// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016232// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16233//16234int64x1_t test_vreinterpret_s64_s8(int8x8_t a) {16235 return vreinterpret_s64_s8(a);16236}16237 16238// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_s16(16239// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16240// CHECK-NEXT: [[ENTRY:.*:]]16241// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to i6416242// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016243// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16244//16245int64x1_t test_vreinterpret_s64_s16(int16x4_t a) {16246 return vreinterpret_s64_s16(a);16247}16248 16249// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_s32(16250// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16251// CHECK-NEXT: [[ENTRY:.*:]]16252// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to i6416253// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016254// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16255//16256int64x1_t test_vreinterpret_s64_s32(int32x2_t a) {16257 return vreinterpret_s64_s32(a);16258}16259 16260// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_u8(16261// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16262// CHECK-NEXT: [[ENTRY:.*:]]16263// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to i6416264// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016265// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16266//16267int64x1_t test_vreinterpret_s64_u8(uint8x8_t a) {16268 return vreinterpret_s64_u8(a);16269}16270 16271// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_u16(16272// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16273// CHECK-NEXT: [[ENTRY:.*:]]16274// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to i6416275// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016276// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16277//16278int64x1_t test_vreinterpret_s64_u16(uint16x4_t a) {16279 return vreinterpret_s64_u16(a);16280}16281 16282// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_u32(16283// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16284// CHECK-NEXT: [[ENTRY:.*:]]16285// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to i6416286// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016287// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16288//16289int64x1_t test_vreinterpret_s64_u32(uint32x2_t a) {16290 return vreinterpret_s64_u32(a);16291}16292 16293// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_u64(16294// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16295// CHECK-NEXT: [[ENTRY:.*:]]16296// CHECK-NEXT: ret <1 x i64> [[A]]16297//16298int64x1_t test_vreinterpret_s64_u64(uint64x1_t a) {16299 return vreinterpret_s64_u64(a);16300}16301 16302// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_f16(16303// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {16304// CHECK-NEXT: [[ENTRY:.*:]]16305// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to i6416306// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016307// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16308//16309int64x1_t test_vreinterpret_s64_f16(float16x4_t a) {16310 return vreinterpret_s64_f16(a);16311}16312 16313// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_f32(16314// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {16315// CHECK-NEXT: [[ENTRY:.*:]]16316// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to i6416317// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016318// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16319//16320int64x1_t test_vreinterpret_s64_f32(float32x2_t a) {16321 return vreinterpret_s64_f32(a);16322}16323 16324// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_p8(16325// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16326// CHECK-NEXT: [[ENTRY:.*:]]16327// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to i6416328// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016329// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16330//16331int64x1_t test_vreinterpret_s64_p8(poly8x8_t a) {16332 return vreinterpret_s64_p8(a);16333}16334 16335// CHECK-LABEL: define <1 x i64> @test_vreinterpret_s64_p16(16336// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16337// CHECK-NEXT: [[ENTRY:.*:]]16338// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to i6416339// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016340// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16341//16342int64x1_t test_vreinterpret_s64_p16(poly16x4_t a) {16343 return vreinterpret_s64_p16(a);16344}16345 16346// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_s8(16347// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16348// CHECK-NEXT: [[ENTRY:.*:]]16349// CHECK-NEXT: ret <8 x i8> [[A]]16350//16351uint8x8_t test_vreinterpret_u8_s8(int8x8_t a) {16352 return vreinterpret_u8_s8(a);16353}16354 16355// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_s16(16356// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16357// CHECK-NEXT: [[ENTRY:.*:]]16358// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>16359// CHECK-NEXT: ret <8 x i8> [[TMP0]]16360//16361uint8x8_t test_vreinterpret_u8_s16(int16x4_t a) {16362 return vreinterpret_u8_s16(a);16363}16364 16365// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_s32(16366// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16367// CHECK-NEXT: [[ENTRY:.*:]]16368// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>16369// CHECK-NEXT: ret <8 x i8> [[TMP0]]16370//16371uint8x8_t test_vreinterpret_u8_s32(int32x2_t a) {16372 return vreinterpret_u8_s32(a);16373}16374 16375// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_s64(16376// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16377// CHECK-NEXT: [[ENTRY:.*:]]16378// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>16379// CHECK-NEXT: ret <8 x i8> [[TMP0]]16380//16381uint8x8_t test_vreinterpret_u8_s64(int64x1_t a) {16382 return vreinterpret_u8_s64(a);16383}16384 16385// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_u16(16386// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16387// CHECK-NEXT: [[ENTRY:.*:]]16388// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>16389// CHECK-NEXT: ret <8 x i8> [[TMP0]]16390//16391uint8x8_t test_vreinterpret_u8_u16(uint16x4_t a) {16392 return vreinterpret_u8_u16(a);16393}16394 16395// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_u32(16396// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16397// CHECK-NEXT: [[ENTRY:.*:]]16398// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>16399// CHECK-NEXT: ret <8 x i8> [[TMP0]]16400//16401uint8x8_t test_vreinterpret_u8_u32(uint32x2_t a) {16402 return vreinterpret_u8_u32(a);16403}16404 16405// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_u64(16406// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16407// CHECK-NEXT: [[ENTRY:.*:]]16408// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>16409// CHECK-NEXT: ret <8 x i8> [[TMP0]]16410//16411uint8x8_t test_vreinterpret_u8_u64(uint64x1_t a) {16412 return vreinterpret_u8_u64(a);16413}16414 16415// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_f16(16416// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {16417// CHECK-NEXT: [[ENTRY:.*:]]16418// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>16419// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>16420// CHECK-NEXT: ret <8 x i8> [[TMP1]]16421//16422uint8x8_t test_vreinterpret_u8_f16(float16x4_t a) {16423 return vreinterpret_u8_f16(a);16424}16425 16426// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_f32(16427// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {16428// CHECK-NEXT: [[ENTRY:.*:]]16429// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>16430// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>16431// CHECK-NEXT: ret <8 x i8> [[TMP1]]16432//16433uint8x8_t test_vreinterpret_u8_f32(float32x2_t a) {16434 return vreinterpret_u8_f32(a);16435}16436 16437// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_p8(16438// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16439// CHECK-NEXT: [[ENTRY:.*:]]16440// CHECK-NEXT: ret <8 x i8> [[A]]16441//16442uint8x8_t test_vreinterpret_u8_p8(poly8x8_t a) {16443 return vreinterpret_u8_p8(a);16444}16445 16446// CHECK-LABEL: define <8 x i8> @test_vreinterpret_u8_p16(16447// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16448// CHECK-NEXT: [[ENTRY:.*:]]16449// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>16450// CHECK-NEXT: ret <8 x i8> [[TMP0]]16451//16452uint8x8_t test_vreinterpret_u8_p16(poly16x4_t a) {16453 return vreinterpret_u8_p16(a);16454}16455 16456// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_s8(16457// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16458// CHECK-NEXT: [[ENTRY:.*:]]16459// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>16460// CHECK-NEXT: ret <4 x i16> [[TMP0]]16461//16462uint16x4_t test_vreinterpret_u16_s8(int8x8_t a) {16463 return vreinterpret_u16_s8(a);16464}16465 16466// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_s16(16467// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16468// CHECK-NEXT: [[ENTRY:.*:]]16469// CHECK-NEXT: ret <4 x i16> [[A]]16470//16471uint16x4_t test_vreinterpret_u16_s16(int16x4_t a) {16472 return vreinterpret_u16_s16(a);16473}16474 16475// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_s32(16476// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16477// CHECK-NEXT: [[ENTRY:.*:]]16478// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <4 x i16>16479// CHECK-NEXT: ret <4 x i16> [[TMP0]]16480//16481uint16x4_t test_vreinterpret_u16_s32(int32x2_t a) {16482 return vreinterpret_u16_s32(a);16483}16484 16485// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_s64(16486// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16487// CHECK-NEXT: [[ENTRY:.*:]]16488// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>16489// CHECK-NEXT: ret <4 x i16> [[TMP0]]16490//16491uint16x4_t test_vreinterpret_u16_s64(int64x1_t a) {16492 return vreinterpret_u16_s64(a);16493}16494 16495// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_u8(16496// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16497// CHECK-NEXT: [[ENTRY:.*:]]16498// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>16499// CHECK-NEXT: ret <4 x i16> [[TMP0]]16500//16501uint16x4_t test_vreinterpret_u16_u8(uint8x8_t a) {16502 return vreinterpret_u16_u8(a);16503}16504 16505// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_u32(16506// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16507// CHECK-NEXT: [[ENTRY:.*:]]16508// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <4 x i16>16509// CHECK-NEXT: ret <4 x i16> [[TMP0]]16510//16511uint16x4_t test_vreinterpret_u16_u32(uint32x2_t a) {16512 return vreinterpret_u16_u32(a);16513}16514 16515// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_u64(16516// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16517// CHECK-NEXT: [[ENTRY:.*:]]16518// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>16519// CHECK-NEXT: ret <4 x i16> [[TMP0]]16520//16521uint16x4_t test_vreinterpret_u16_u64(uint64x1_t a) {16522 return vreinterpret_u16_u64(a);16523}16524 16525// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_f16(16526// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {16527// CHECK-NEXT: [[ENTRY:.*:]]16528// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>16529// CHECK-NEXT: ret <4 x i16> [[TMP0]]16530//16531uint16x4_t test_vreinterpret_u16_f16(float16x4_t a) {16532 return vreinterpret_u16_f16(a);16533}16534 16535// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_f32(16536// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {16537// CHECK-NEXT: [[ENTRY:.*:]]16538// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>16539// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <4 x i16>16540// CHECK-NEXT: ret <4 x i16> [[TMP1]]16541//16542uint16x4_t test_vreinterpret_u16_f32(float32x2_t a) {16543 return vreinterpret_u16_f32(a);16544}16545 16546// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_p8(16547// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16548// CHECK-NEXT: [[ENTRY:.*:]]16549// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>16550// CHECK-NEXT: ret <4 x i16> [[TMP0]]16551//16552uint16x4_t test_vreinterpret_u16_p8(poly8x8_t a) {16553 return vreinterpret_u16_p8(a);16554}16555 16556// CHECK-LABEL: define <4 x i16> @test_vreinterpret_u16_p16(16557// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16558// CHECK-NEXT: [[ENTRY:.*:]]16559// CHECK-NEXT: ret <4 x i16> [[A]]16560//16561uint16x4_t test_vreinterpret_u16_p16(poly16x4_t a) {16562 return vreinterpret_u16_p16(a);16563}16564 16565// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_s8(16566// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16567// CHECK-NEXT: [[ENTRY:.*:]]16568// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <2 x i32>16569// CHECK-NEXT: ret <2 x i32> [[TMP0]]16570//16571uint32x2_t test_vreinterpret_u32_s8(int8x8_t a) {16572 return vreinterpret_u32_s8(a);16573}16574 16575// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_s16(16576// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16577// CHECK-NEXT: [[ENTRY:.*:]]16578// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <2 x i32>16579// CHECK-NEXT: ret <2 x i32> [[TMP0]]16580//16581uint32x2_t test_vreinterpret_u32_s16(int16x4_t a) {16582 return vreinterpret_u32_s16(a);16583}16584 16585// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_s32(16586// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16587// CHECK-NEXT: [[ENTRY:.*:]]16588// CHECK-NEXT: ret <2 x i32> [[A]]16589//16590uint32x2_t test_vreinterpret_u32_s32(int32x2_t a) {16591 return vreinterpret_u32_s32(a);16592}16593 16594// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_s64(16595// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16596// CHECK-NEXT: [[ENTRY:.*:]]16597// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>16598// CHECK-NEXT: ret <2 x i32> [[TMP0]]16599//16600uint32x2_t test_vreinterpret_u32_s64(int64x1_t a) {16601 return vreinterpret_u32_s64(a);16602}16603 16604// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_u8(16605// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16606// CHECK-NEXT: [[ENTRY:.*:]]16607// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <2 x i32>16608// CHECK-NEXT: ret <2 x i32> [[TMP0]]16609//16610uint32x2_t test_vreinterpret_u32_u8(uint8x8_t a) {16611 return vreinterpret_u32_u8(a);16612}16613 16614// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_u16(16615// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16616// CHECK-NEXT: [[ENTRY:.*:]]16617// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <2 x i32>16618// CHECK-NEXT: ret <2 x i32> [[TMP0]]16619//16620uint32x2_t test_vreinterpret_u32_u16(uint16x4_t a) {16621 return vreinterpret_u32_u16(a);16622}16623 16624// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_u64(16625// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16626// CHECK-NEXT: [[ENTRY:.*:]]16627// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x i32>16628// CHECK-NEXT: ret <2 x i32> [[TMP0]]16629//16630uint32x2_t test_vreinterpret_u32_u64(uint64x1_t a) {16631 return vreinterpret_u32_u64(a);16632}16633 16634// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_f16(16635// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {16636// CHECK-NEXT: [[ENTRY:.*:]]16637// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <2 x i32>16638// CHECK-NEXT: ret <2 x i32> [[TMP0]]16639//16640uint32x2_t test_vreinterpret_u32_f16(float16x4_t a) {16641 return vreinterpret_u32_f16(a);16642}16643 16644// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_f32(16645// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {16646// CHECK-NEXT: [[ENTRY:.*:]]16647// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>16648// CHECK-NEXT: ret <2 x i32> [[TMP0]]16649//16650uint32x2_t test_vreinterpret_u32_f32(float32x2_t a) {16651 return vreinterpret_u32_f32(a);16652}16653 16654// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_p8(16655// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16656// CHECK-NEXT: [[ENTRY:.*:]]16657// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <2 x i32>16658// CHECK-NEXT: ret <2 x i32> [[TMP0]]16659//16660uint32x2_t test_vreinterpret_u32_p8(poly8x8_t a) {16661 return vreinterpret_u32_p8(a);16662}16663 16664// CHECK-LABEL: define <2 x i32> @test_vreinterpret_u32_p16(16665// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16666// CHECK-NEXT: [[ENTRY:.*:]]16667// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <2 x i32>16668// CHECK-NEXT: ret <2 x i32> [[TMP0]]16669//16670uint32x2_t test_vreinterpret_u32_p16(poly16x4_t a) {16671 return vreinterpret_u32_p16(a);16672}16673 16674// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_s8(16675// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16676// CHECK-NEXT: [[ENTRY:.*:]]16677// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to i6416678// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016679// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16680//16681uint64x1_t test_vreinterpret_u64_s8(int8x8_t a) {16682 return vreinterpret_u64_s8(a);16683}16684 16685// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_s16(16686// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16687// CHECK-NEXT: [[ENTRY:.*:]]16688// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to i6416689// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016690// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16691//16692uint64x1_t test_vreinterpret_u64_s16(int16x4_t a) {16693 return vreinterpret_u64_s16(a);16694}16695 16696// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_s32(16697// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16698// CHECK-NEXT: [[ENTRY:.*:]]16699// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to i6416700// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016701// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16702//16703uint64x1_t test_vreinterpret_u64_s32(int32x2_t a) {16704 return vreinterpret_u64_s32(a);16705}16706 16707// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_s64(16708// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16709// CHECK-NEXT: [[ENTRY:.*:]]16710// CHECK-NEXT: ret <1 x i64> [[A]]16711//16712uint64x1_t test_vreinterpret_u64_s64(int64x1_t a) {16713 return vreinterpret_u64_s64(a);16714}16715 16716// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_u8(16717// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16718// CHECK-NEXT: [[ENTRY:.*:]]16719// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to i6416720// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016721// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16722//16723uint64x1_t test_vreinterpret_u64_u8(uint8x8_t a) {16724 return vreinterpret_u64_u8(a);16725}16726 16727// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_u16(16728// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16729// CHECK-NEXT: [[ENTRY:.*:]]16730// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to i6416731// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016732// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16733//16734uint64x1_t test_vreinterpret_u64_u16(uint16x4_t a) {16735 return vreinterpret_u64_u16(a);16736}16737 16738// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_u32(16739// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16740// CHECK-NEXT: [[ENTRY:.*:]]16741// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to i6416742// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016743// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16744//16745uint64x1_t test_vreinterpret_u64_u32(uint32x2_t a) {16746 return vreinterpret_u64_u32(a);16747}16748 16749// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_f16(16750// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {16751// CHECK-NEXT: [[ENTRY:.*:]]16752// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to i6416753// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016754// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16755//16756uint64x1_t test_vreinterpret_u64_f16(float16x4_t a) {16757 return vreinterpret_u64_f16(a);16758}16759 16760// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_f32(16761// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {16762// CHECK-NEXT: [[ENTRY:.*:]]16763// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to i6416764// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016765// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16766//16767uint64x1_t test_vreinterpret_u64_f32(float32x2_t a) {16768 return vreinterpret_u64_f32(a);16769}16770 16771// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_p8(16772// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16773// CHECK-NEXT: [[ENTRY:.*:]]16774// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to i6416775// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016776// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16777//16778uint64x1_t test_vreinterpret_u64_p8(poly8x8_t a) {16779 return vreinterpret_u64_p8(a);16780}16781 16782// CHECK-LABEL: define <1 x i64> @test_vreinterpret_u64_p16(16783// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16784// CHECK-NEXT: [[ENTRY:.*:]]16785// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to i6416786// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 016787// CHECK-NEXT: ret <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]]16788//16789uint64x1_t test_vreinterpret_u64_p16(poly16x4_t a) {16790 return vreinterpret_u64_p16(a);16791}16792 16793// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_s8(16794// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16795// CHECK-NEXT: [[ENTRY:.*:]]16796// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>16797// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <4 x half>16798// CHECK-NEXT: ret <4 x half> [[TMP1]]16799//16800float16x4_t test_vreinterpret_f16_s8(int8x8_t a) {16801 return vreinterpret_f16_s8(a);16802}16803 16804// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_s16(16805// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16806// CHECK-NEXT: [[ENTRY:.*:]]16807// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <4 x half>16808// CHECK-NEXT: ret <4 x half> [[TMP0]]16809//16810float16x4_t test_vreinterpret_f16_s16(int16x4_t a) {16811 return vreinterpret_f16_s16(a);16812}16813 16814// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_s32(16815// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16816// CHECK-NEXT: [[ENTRY:.*:]]16817// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <4 x half>16818// CHECK-NEXT: ret <4 x half> [[TMP0]]16819//16820float16x4_t test_vreinterpret_f16_s32(int32x2_t a) {16821 return vreinterpret_f16_s32(a);16822}16823 16824// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_s64(16825// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16826// CHECK-NEXT: [[ENTRY:.*:]]16827// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x half>16828// CHECK-NEXT: ret <4 x half> [[TMP0]]16829//16830float16x4_t test_vreinterpret_f16_s64(int64x1_t a) {16831 return vreinterpret_f16_s64(a);16832}16833 16834// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_u8(16835// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16836// CHECK-NEXT: [[ENTRY:.*:]]16837// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>16838// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <4 x half>16839// CHECK-NEXT: ret <4 x half> [[TMP1]]16840//16841float16x4_t test_vreinterpret_f16_u8(uint8x8_t a) {16842 return vreinterpret_f16_u8(a);16843}16844 16845// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_u16(16846// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16847// CHECK-NEXT: [[ENTRY:.*:]]16848// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <4 x half>16849// CHECK-NEXT: ret <4 x half> [[TMP0]]16850//16851float16x4_t test_vreinterpret_f16_u16(uint16x4_t a) {16852 return vreinterpret_f16_u16(a);16853}16854 16855// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_u32(16856// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16857// CHECK-NEXT: [[ENTRY:.*:]]16858// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <4 x half>16859// CHECK-NEXT: ret <4 x half> [[TMP0]]16860//16861float16x4_t test_vreinterpret_f16_u32(uint32x2_t a) {16862 return vreinterpret_f16_u32(a);16863}16864 16865// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_u64(16866// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16867// CHECK-NEXT: [[ENTRY:.*:]]16868// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x half>16869// CHECK-NEXT: ret <4 x half> [[TMP0]]16870//16871float16x4_t test_vreinterpret_f16_u64(uint64x1_t a) {16872 return vreinterpret_f16_u64(a);16873}16874 16875// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_f32(16876// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {16877// CHECK-NEXT: [[ENTRY:.*:]]16878// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>16879// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <4 x half>16880// CHECK-NEXT: ret <4 x half> [[TMP1]]16881//16882float16x4_t test_vreinterpret_f16_f32(float32x2_t a) {16883 return vreinterpret_f16_f32(a);16884}16885 16886// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_p8(16887// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16888// CHECK-NEXT: [[ENTRY:.*:]]16889// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>16890// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <4 x half>16891// CHECK-NEXT: ret <4 x half> [[TMP1]]16892//16893float16x4_t test_vreinterpret_f16_p8(poly8x8_t a) {16894 return vreinterpret_f16_p8(a);16895}16896 16897// CHECK-LABEL: define <4 x half> @test_vreinterpret_f16_p16(16898// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16899// CHECK-NEXT: [[ENTRY:.*:]]16900// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <4 x half>16901// CHECK-NEXT: ret <4 x half> [[TMP0]]16902//16903float16x4_t test_vreinterpret_f16_p16(poly16x4_t a) {16904 return vreinterpret_f16_p16(a);16905}16906 16907// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_s8(16908// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16909// CHECK-NEXT: [[ENTRY:.*:]]16910// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <2 x i32>16911// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <2 x float>16912// CHECK-NEXT: ret <2 x float> [[TMP1]]16913//16914float32x2_t test_vreinterpret_f32_s8(int8x8_t a) {16915 return vreinterpret_f32_s8(a);16916}16917 16918// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_s16(16919// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16920// CHECK-NEXT: [[ENTRY:.*:]]16921// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <2 x i32>16922// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <2 x float>16923// CHECK-NEXT: ret <2 x float> [[TMP1]]16924//16925float32x2_t test_vreinterpret_f32_s16(int16x4_t a) {16926 return vreinterpret_f32_s16(a);16927}16928 16929// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_s32(16930// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16931// CHECK-NEXT: [[ENTRY:.*:]]16932// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <2 x float>16933// CHECK-NEXT: ret <2 x float> [[TMP0]]16934//16935float32x2_t test_vreinterpret_f32_s32(int32x2_t a) {16936 return vreinterpret_f32_s32(a);16937}16938 16939// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_s64(16940// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16941// CHECK-NEXT: [[ENTRY:.*:]]16942// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x float>16943// CHECK-NEXT: ret <2 x float> [[TMP0]]16944//16945float32x2_t test_vreinterpret_f32_s64(int64x1_t a) {16946 return vreinterpret_f32_s64(a);16947}16948 16949// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_u8(16950// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {16951// CHECK-NEXT: [[ENTRY:.*:]]16952// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <2 x i32>16953// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <2 x float>16954// CHECK-NEXT: ret <2 x float> [[TMP1]]16955//16956float32x2_t test_vreinterpret_f32_u8(uint8x8_t a) {16957 return vreinterpret_f32_u8(a);16958}16959 16960// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_u16(16961// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {16962// CHECK-NEXT: [[ENTRY:.*:]]16963// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <2 x i32>16964// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <2 x float>16965// CHECK-NEXT: ret <2 x float> [[TMP1]]16966//16967float32x2_t test_vreinterpret_f32_u16(uint16x4_t a) {16968 return vreinterpret_f32_u16(a);16969}16970 16971// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_u32(16972// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {16973// CHECK-NEXT: [[ENTRY:.*:]]16974// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <2 x float>16975// CHECK-NEXT: ret <2 x float> [[TMP0]]16976//16977float32x2_t test_vreinterpret_f32_u32(uint32x2_t a) {16978 return vreinterpret_f32_u32(a);16979}16980 16981// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_u64(16982// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {16983// CHECK-NEXT: [[ENTRY:.*:]]16984// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <2 x float>16985// CHECK-NEXT: ret <2 x float> [[TMP0]]16986//16987float32x2_t test_vreinterpret_f32_u64(uint64x1_t a) {16988 return vreinterpret_f32_u64(a);16989}16990 16991// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_f16(16992// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {16993// CHECK-NEXT: [[ENTRY:.*:]]16994// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <2 x i32>16995// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <2 x float>16996// CHECK-NEXT: ret <2 x float> [[TMP1]]16997//16998float32x2_t test_vreinterpret_f32_f16(float16x4_t a) {16999 return vreinterpret_f32_f16(a);17000}17001 17002// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_p8(17003// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17004// CHECK-NEXT: [[ENTRY:.*:]]17005// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <2 x i32>17006// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <2 x float>17007// CHECK-NEXT: ret <2 x float> [[TMP1]]17008//17009float32x2_t test_vreinterpret_f32_p8(poly8x8_t a) {17010 return vreinterpret_f32_p8(a);17011}17012 17013// CHECK-LABEL: define <2 x float> @test_vreinterpret_f32_p16(17014// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17015// CHECK-NEXT: [[ENTRY:.*:]]17016// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <2 x i32>17017// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <2 x float>17018// CHECK-NEXT: ret <2 x float> [[TMP1]]17019//17020float32x2_t test_vreinterpret_f32_p16(poly16x4_t a) {17021 return vreinterpret_f32_p16(a);17022}17023 17024// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_s8(17025// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17026// CHECK-NEXT: [[ENTRY:.*:]]17027// CHECK-NEXT: ret <8 x i8> [[A]]17028//17029poly8x8_t test_vreinterpret_p8_s8(int8x8_t a) {17030 return vreinterpret_p8_s8(a);17031}17032 17033// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_s16(17034// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17035// CHECK-NEXT: [[ENTRY:.*:]]17036// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>17037// CHECK-NEXT: ret <8 x i8> [[TMP0]]17038//17039poly8x8_t test_vreinterpret_p8_s16(int16x4_t a) {17040 return vreinterpret_p8_s16(a);17041}17042 17043// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_s32(17044// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17045// CHECK-NEXT: [[ENTRY:.*:]]17046// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>17047// CHECK-NEXT: ret <8 x i8> [[TMP0]]17048//17049poly8x8_t test_vreinterpret_p8_s32(int32x2_t a) {17050 return vreinterpret_p8_s32(a);17051}17052 17053// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_s64(17054// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17055// CHECK-NEXT: [[ENTRY:.*:]]17056// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>17057// CHECK-NEXT: ret <8 x i8> [[TMP0]]17058//17059poly8x8_t test_vreinterpret_p8_s64(int64x1_t a) {17060 return vreinterpret_p8_s64(a);17061}17062 17063// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_u8(17064// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17065// CHECK-NEXT: [[ENTRY:.*:]]17066// CHECK-NEXT: ret <8 x i8> [[A]]17067//17068poly8x8_t test_vreinterpret_p8_u8(uint8x8_t a) {17069 return vreinterpret_p8_u8(a);17070}17071 17072// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_u16(17073// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17074// CHECK-NEXT: [[ENTRY:.*:]]17075// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>17076// CHECK-NEXT: ret <8 x i8> [[TMP0]]17077//17078poly8x8_t test_vreinterpret_p8_u16(uint16x4_t a) {17079 return vreinterpret_p8_u16(a);17080}17081 17082// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_u32(17083// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17084// CHECK-NEXT: [[ENTRY:.*:]]17085// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>17086// CHECK-NEXT: ret <8 x i8> [[TMP0]]17087//17088poly8x8_t test_vreinterpret_p8_u32(uint32x2_t a) {17089 return vreinterpret_p8_u32(a);17090}17091 17092// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_u64(17093// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17094// CHECK-NEXT: [[ENTRY:.*:]]17095// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>17096// CHECK-NEXT: ret <8 x i8> [[TMP0]]17097//17098poly8x8_t test_vreinterpret_p8_u64(uint64x1_t a) {17099 return vreinterpret_p8_u64(a);17100}17101 17102// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_f16(17103// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {17104// CHECK-NEXT: [[ENTRY:.*:]]17105// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>17106// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>17107// CHECK-NEXT: ret <8 x i8> [[TMP1]]17108//17109poly8x8_t test_vreinterpret_p8_f16(float16x4_t a) {17110 return vreinterpret_p8_f16(a);17111}17112 17113// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_f32(17114// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {17115// CHECK-NEXT: [[ENTRY:.*:]]17116// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>17117// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>17118// CHECK-NEXT: ret <8 x i8> [[TMP1]]17119//17120poly8x8_t test_vreinterpret_p8_f32(float32x2_t a) {17121 return vreinterpret_p8_f32(a);17122}17123 17124// CHECK-LABEL: define <8 x i8> @test_vreinterpret_p8_p16(17125// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17126// CHECK-NEXT: [[ENTRY:.*:]]17127// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>17128// CHECK-NEXT: ret <8 x i8> [[TMP0]]17129//17130poly8x8_t test_vreinterpret_p8_p16(poly16x4_t a) {17131 return vreinterpret_p8_p16(a);17132}17133 17134// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_s8(17135// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17136// CHECK-NEXT: [[ENTRY:.*:]]17137// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>17138// CHECK-NEXT: ret <4 x i16> [[TMP0]]17139//17140poly16x4_t test_vreinterpret_p16_s8(int8x8_t a) {17141 return vreinterpret_p16_s8(a);17142}17143 17144// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_s16(17145// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17146// CHECK-NEXT: [[ENTRY:.*:]]17147// CHECK-NEXT: ret <4 x i16> [[A]]17148//17149poly16x4_t test_vreinterpret_p16_s16(int16x4_t a) {17150 return vreinterpret_p16_s16(a);17151}17152 17153// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_s32(17154// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17155// CHECK-NEXT: [[ENTRY:.*:]]17156// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <4 x i16>17157// CHECK-NEXT: ret <4 x i16> [[TMP0]]17158//17159poly16x4_t test_vreinterpret_p16_s32(int32x2_t a) {17160 return vreinterpret_p16_s32(a);17161}17162 17163// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_s64(17164// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17165// CHECK-NEXT: [[ENTRY:.*:]]17166// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>17167// CHECK-NEXT: ret <4 x i16> [[TMP0]]17168//17169poly16x4_t test_vreinterpret_p16_s64(int64x1_t a) {17170 return vreinterpret_p16_s64(a);17171}17172 17173// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_u8(17174// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17175// CHECK-NEXT: [[ENTRY:.*:]]17176// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>17177// CHECK-NEXT: ret <4 x i16> [[TMP0]]17178//17179poly16x4_t test_vreinterpret_p16_u8(uint8x8_t a) {17180 return vreinterpret_p16_u8(a);17181}17182 17183// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_u16(17184// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17185// CHECK-NEXT: [[ENTRY:.*:]]17186// CHECK-NEXT: ret <4 x i16> [[A]]17187//17188poly16x4_t test_vreinterpret_p16_u16(uint16x4_t a) {17189 return vreinterpret_p16_u16(a);17190}17191 17192// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_u32(17193// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17194// CHECK-NEXT: [[ENTRY:.*:]]17195// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <4 x i16>17196// CHECK-NEXT: ret <4 x i16> [[TMP0]]17197//17198poly16x4_t test_vreinterpret_p16_u32(uint32x2_t a) {17199 return vreinterpret_p16_u32(a);17200}17201 17202// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_u64(17203// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17204// CHECK-NEXT: [[ENTRY:.*:]]17205// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <4 x i16>17206// CHECK-NEXT: ret <4 x i16> [[TMP0]]17207//17208poly16x4_t test_vreinterpret_p16_u64(uint64x1_t a) {17209 return vreinterpret_p16_u64(a);17210}17211 17212// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_f16(17213// CHECK-SAME: <4 x half> noundef [[A:%.*]]) #[[ATTR0]] {17214// CHECK-NEXT: [[ENTRY:.*:]]17215// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>17216// CHECK-NEXT: ret <4 x i16> [[TMP0]]17217//17218poly16x4_t test_vreinterpret_p16_f16(float16x4_t a) {17219 return vreinterpret_p16_f16(a);17220}17221 17222// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_f32(17223// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {17224// CHECK-NEXT: [[ENTRY:.*:]]17225// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>17226// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <4 x i16>17227// CHECK-NEXT: ret <4 x i16> [[TMP1]]17228//17229poly16x4_t test_vreinterpret_p16_f32(float32x2_t a) {17230 return vreinterpret_p16_f32(a);17231}17232 17233// CHECK-LABEL: define <4 x i16> @test_vreinterpret_p16_p8(17234// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17235// CHECK-NEXT: [[ENTRY:.*:]]17236// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[A]] to <4 x i16>17237// CHECK-NEXT: ret <4 x i16> [[TMP0]]17238//17239poly16x4_t test_vreinterpret_p16_p8(poly8x8_t a) {17240 return vreinterpret_p16_p8(a);17241}17242 17243// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_s16(17244// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17245// CHECK-NEXT: [[ENTRY:.*:]]17246// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>17247// CHECK-NEXT: ret <16 x i8> [[TMP0]]17248//17249int8x16_t test_vreinterpretq_s8_s16(int16x8_t a) {17250 return vreinterpretq_s8_s16(a);17251}17252 17253// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_s32(17254// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17255// CHECK-NEXT: [[ENTRY:.*:]]17256// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>17257// CHECK-NEXT: ret <16 x i8> [[TMP0]]17258//17259int8x16_t test_vreinterpretq_s8_s32(int32x4_t a) {17260 return vreinterpretq_s8_s32(a);17261}17262 17263// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_s64(17264// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17265// CHECK-NEXT: [[ENTRY:.*:]]17266// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>17267// CHECK-NEXT: ret <16 x i8> [[TMP0]]17268//17269int8x16_t test_vreinterpretq_s8_s64(int64x2_t a) {17270 return vreinterpretq_s8_s64(a);17271}17272 17273// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_u8(17274// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17275// CHECK-NEXT: [[ENTRY:.*:]]17276// CHECK-NEXT: ret <16 x i8> [[A]]17277//17278int8x16_t test_vreinterpretq_s8_u8(uint8x16_t a) {17279 return vreinterpretq_s8_u8(a);17280}17281 17282// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_u16(17283// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17284// CHECK-NEXT: [[ENTRY:.*:]]17285// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>17286// CHECK-NEXT: ret <16 x i8> [[TMP0]]17287//17288int8x16_t test_vreinterpretq_s8_u16(uint16x8_t a) {17289 return vreinterpretq_s8_u16(a);17290}17291 17292// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_u32(17293// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17294// CHECK-NEXT: [[ENTRY:.*:]]17295// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>17296// CHECK-NEXT: ret <16 x i8> [[TMP0]]17297//17298int8x16_t test_vreinterpretq_s8_u32(uint32x4_t a) {17299 return vreinterpretq_s8_u32(a);17300}17301 17302// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_u64(17303// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17304// CHECK-NEXT: [[ENTRY:.*:]]17305// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>17306// CHECK-NEXT: ret <16 x i8> [[TMP0]]17307//17308int8x16_t test_vreinterpretq_s8_u64(uint64x2_t a) {17309 return vreinterpretq_s8_u64(a);17310}17311 17312// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_f16(17313// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {17314// CHECK-NEXT: [[ENTRY:.*:]]17315// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>17316// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>17317// CHECK-NEXT: ret <16 x i8> [[TMP1]]17318//17319int8x16_t test_vreinterpretq_s8_f16(float16x8_t a) {17320 return vreinterpretq_s8_f16(a);17321}17322 17323// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_f32(17324// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {17325// CHECK-NEXT: [[ENTRY:.*:]]17326// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>17327// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>17328// CHECK-NEXT: ret <16 x i8> [[TMP1]]17329//17330int8x16_t test_vreinterpretq_s8_f32(float32x4_t a) {17331 return vreinterpretq_s8_f32(a);17332}17333 17334// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_p8(17335// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17336// CHECK-NEXT: [[ENTRY:.*:]]17337// CHECK-NEXT: ret <16 x i8> [[A]]17338//17339int8x16_t test_vreinterpretq_s8_p8(poly8x16_t a) {17340 return vreinterpretq_s8_p8(a);17341}17342 17343// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_s8_p16(17344// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17345// CHECK-NEXT: [[ENTRY:.*:]]17346// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>17347// CHECK-NEXT: ret <16 x i8> [[TMP0]]17348//17349int8x16_t test_vreinterpretq_s8_p16(poly16x8_t a) {17350 return vreinterpretq_s8_p16(a);17351}17352 17353// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_s8(17354// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17355// CHECK-NEXT: [[ENTRY:.*:]]17356// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>17357// CHECK-NEXT: ret <8 x i16> [[TMP0]]17358//17359int16x8_t test_vreinterpretq_s16_s8(int8x16_t a) {17360 return vreinterpretq_s16_s8(a);17361}17362 17363// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_s32(17364// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17365// CHECK-NEXT: [[ENTRY:.*:]]17366// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <8 x i16>17367// CHECK-NEXT: ret <8 x i16> [[TMP0]]17368//17369int16x8_t test_vreinterpretq_s16_s32(int32x4_t a) {17370 return vreinterpretq_s16_s32(a);17371}17372 17373// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_s64(17374// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17375// CHECK-NEXT: [[ENTRY:.*:]]17376// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <8 x i16>17377// CHECK-NEXT: ret <8 x i16> [[TMP0]]17378//17379int16x8_t test_vreinterpretq_s16_s64(int64x2_t a) {17380 return vreinterpretq_s16_s64(a);17381}17382 17383// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_u8(17384// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17385// CHECK-NEXT: [[ENTRY:.*:]]17386// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>17387// CHECK-NEXT: ret <8 x i16> [[TMP0]]17388//17389int16x8_t test_vreinterpretq_s16_u8(uint8x16_t a) {17390 return vreinterpretq_s16_u8(a);17391}17392 17393// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_u16(17394// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17395// CHECK-NEXT: [[ENTRY:.*:]]17396// CHECK-NEXT: ret <8 x i16> [[A]]17397//17398int16x8_t test_vreinterpretq_s16_u16(uint16x8_t a) {17399 return vreinterpretq_s16_u16(a);17400}17401 17402// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_u32(17403// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17404// CHECK-NEXT: [[ENTRY:.*:]]17405// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <8 x i16>17406// CHECK-NEXT: ret <8 x i16> [[TMP0]]17407//17408int16x8_t test_vreinterpretq_s16_u32(uint32x4_t a) {17409 return vreinterpretq_s16_u32(a);17410}17411 17412// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_u64(17413// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17414// CHECK-NEXT: [[ENTRY:.*:]]17415// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <8 x i16>17416// CHECK-NEXT: ret <8 x i16> [[TMP0]]17417//17418int16x8_t test_vreinterpretq_s16_u64(uint64x2_t a) {17419 return vreinterpretq_s16_u64(a);17420}17421 17422// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_f16(17423// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {17424// CHECK-NEXT: [[ENTRY:.*:]]17425// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>17426// CHECK-NEXT: ret <8 x i16> [[TMP0]]17427//17428int16x8_t test_vreinterpretq_s16_f16(float16x8_t a) {17429 return vreinterpretq_s16_f16(a);17430}17431 17432// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_f32(17433// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {17434// CHECK-NEXT: [[ENTRY:.*:]]17435// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>17436// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <8 x i16>17437// CHECK-NEXT: ret <8 x i16> [[TMP1]]17438//17439int16x8_t test_vreinterpretq_s16_f32(float32x4_t a) {17440 return vreinterpretq_s16_f32(a);17441}17442 17443// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_p8(17444// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17445// CHECK-NEXT: [[ENTRY:.*:]]17446// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>17447// CHECK-NEXT: ret <8 x i16> [[TMP0]]17448//17449int16x8_t test_vreinterpretq_s16_p8(poly8x16_t a) {17450 return vreinterpretq_s16_p8(a);17451}17452 17453// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_s16_p16(17454// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17455// CHECK-NEXT: [[ENTRY:.*:]]17456// CHECK-NEXT: ret <8 x i16> [[A]]17457//17458int16x8_t test_vreinterpretq_s16_p16(poly16x8_t a) {17459 return vreinterpretq_s16_p16(a);17460}17461 17462// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_s8(17463// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17464// CHECK-NEXT: [[ENTRY:.*:]]17465// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <4 x i32>17466// CHECK-NEXT: ret <4 x i32> [[TMP0]]17467//17468int32x4_t test_vreinterpretq_s32_s8(int8x16_t a) {17469 return vreinterpretq_s32_s8(a);17470}17471 17472// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_s16(17473// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17474// CHECK-NEXT: [[ENTRY:.*:]]17475// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <4 x i32>17476// CHECK-NEXT: ret <4 x i32> [[TMP0]]17477//17478int32x4_t test_vreinterpretq_s32_s16(int16x8_t a) {17479 return vreinterpretq_s32_s16(a);17480}17481 17482// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_s64(17483// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17484// CHECK-NEXT: [[ENTRY:.*:]]17485// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <4 x i32>17486// CHECK-NEXT: ret <4 x i32> [[TMP0]]17487//17488int32x4_t test_vreinterpretq_s32_s64(int64x2_t a) {17489 return vreinterpretq_s32_s64(a);17490}17491 17492// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_u8(17493// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17494// CHECK-NEXT: [[ENTRY:.*:]]17495// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <4 x i32>17496// CHECK-NEXT: ret <4 x i32> [[TMP0]]17497//17498int32x4_t test_vreinterpretq_s32_u8(uint8x16_t a) {17499 return vreinterpretq_s32_u8(a);17500}17501 17502// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_u16(17503// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17504// CHECK-NEXT: [[ENTRY:.*:]]17505// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <4 x i32>17506// CHECK-NEXT: ret <4 x i32> [[TMP0]]17507//17508int32x4_t test_vreinterpretq_s32_u16(uint16x8_t a) {17509 return vreinterpretq_s32_u16(a);17510}17511 17512// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_u32(17513// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17514// CHECK-NEXT: [[ENTRY:.*:]]17515// CHECK-NEXT: ret <4 x i32> [[A]]17516//17517int32x4_t test_vreinterpretq_s32_u32(uint32x4_t a) {17518 return vreinterpretq_s32_u32(a);17519}17520 17521// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_u64(17522// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17523// CHECK-NEXT: [[ENTRY:.*:]]17524// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <4 x i32>17525// CHECK-NEXT: ret <4 x i32> [[TMP0]]17526//17527int32x4_t test_vreinterpretq_s32_u64(uint64x2_t a) {17528 return vreinterpretq_s32_u64(a);17529}17530 17531// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_f16(17532// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {17533// CHECK-NEXT: [[ENTRY:.*:]]17534// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <4 x i32>17535// CHECK-NEXT: ret <4 x i32> [[TMP0]]17536//17537int32x4_t test_vreinterpretq_s32_f16(float16x8_t a) {17538 return vreinterpretq_s32_f16(a);17539}17540 17541// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_f32(17542// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {17543// CHECK-NEXT: [[ENTRY:.*:]]17544// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>17545// CHECK-NEXT: ret <4 x i32> [[TMP0]]17546//17547int32x4_t test_vreinterpretq_s32_f32(float32x4_t a) {17548 return vreinterpretq_s32_f32(a);17549}17550 17551// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_p8(17552// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17553// CHECK-NEXT: [[ENTRY:.*:]]17554// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <4 x i32>17555// CHECK-NEXT: ret <4 x i32> [[TMP0]]17556//17557int32x4_t test_vreinterpretq_s32_p8(poly8x16_t a) {17558 return vreinterpretq_s32_p8(a);17559}17560 17561// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_s32_p16(17562// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17563// CHECK-NEXT: [[ENTRY:.*:]]17564// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <4 x i32>17565// CHECK-NEXT: ret <4 x i32> [[TMP0]]17566//17567int32x4_t test_vreinterpretq_s32_p16(poly16x8_t a) {17568 return vreinterpretq_s32_p16(a);17569}17570 17571// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_s8(17572// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17573// CHECK-NEXT: [[ENTRY:.*:]]17574// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <2 x i64>17575// CHECK-NEXT: ret <2 x i64> [[TMP0]]17576//17577int64x2_t test_vreinterpretq_s64_s8(int8x16_t a) {17578 return vreinterpretq_s64_s8(a);17579}17580 17581// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_s16(17582// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17583// CHECK-NEXT: [[ENTRY:.*:]]17584// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <2 x i64>17585// CHECK-NEXT: ret <2 x i64> [[TMP0]]17586//17587int64x2_t test_vreinterpretq_s64_s16(int16x8_t a) {17588 return vreinterpretq_s64_s16(a);17589}17590 17591// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_s32(17592// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17593// CHECK-NEXT: [[ENTRY:.*:]]17594// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <2 x i64>17595// CHECK-NEXT: ret <2 x i64> [[TMP0]]17596//17597int64x2_t test_vreinterpretq_s64_s32(int32x4_t a) {17598 return vreinterpretq_s64_s32(a);17599}17600 17601// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_u8(17602// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17603// CHECK-NEXT: [[ENTRY:.*:]]17604// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <2 x i64>17605// CHECK-NEXT: ret <2 x i64> [[TMP0]]17606//17607int64x2_t test_vreinterpretq_s64_u8(uint8x16_t a) {17608 return vreinterpretq_s64_u8(a);17609}17610 17611// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_u16(17612// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17613// CHECK-NEXT: [[ENTRY:.*:]]17614// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <2 x i64>17615// CHECK-NEXT: ret <2 x i64> [[TMP0]]17616//17617int64x2_t test_vreinterpretq_s64_u16(uint16x8_t a) {17618 return vreinterpretq_s64_u16(a);17619}17620 17621// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_u32(17622// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17623// CHECK-NEXT: [[ENTRY:.*:]]17624// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <2 x i64>17625// CHECK-NEXT: ret <2 x i64> [[TMP0]]17626//17627int64x2_t test_vreinterpretq_s64_u32(uint32x4_t a) {17628 return vreinterpretq_s64_u32(a);17629}17630 17631// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_u64(17632// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17633// CHECK-NEXT: [[ENTRY:.*:]]17634// CHECK-NEXT: ret <2 x i64> [[A]]17635//17636int64x2_t test_vreinterpretq_s64_u64(uint64x2_t a) {17637 return vreinterpretq_s64_u64(a);17638}17639 17640// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_f16(17641// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {17642// CHECK-NEXT: [[ENTRY:.*:]]17643// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <2 x i64>17644// CHECK-NEXT: ret <2 x i64> [[TMP0]]17645//17646int64x2_t test_vreinterpretq_s64_f16(float16x8_t a) {17647 return vreinterpretq_s64_f16(a);17648}17649 17650// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_f32(17651// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {17652// CHECK-NEXT: [[ENTRY:.*:]]17653// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <2 x i64>17654// CHECK-NEXT: ret <2 x i64> [[TMP0]]17655//17656int64x2_t test_vreinterpretq_s64_f32(float32x4_t a) {17657 return vreinterpretq_s64_f32(a);17658}17659 17660// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_p8(17661// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17662// CHECK-NEXT: [[ENTRY:.*:]]17663// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <2 x i64>17664// CHECK-NEXT: ret <2 x i64> [[TMP0]]17665//17666int64x2_t test_vreinterpretq_s64_p8(poly8x16_t a) {17667 return vreinterpretq_s64_p8(a);17668}17669 17670// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_s64_p16(17671// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17672// CHECK-NEXT: [[ENTRY:.*:]]17673// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <2 x i64>17674// CHECK-NEXT: ret <2 x i64> [[TMP0]]17675//17676int64x2_t test_vreinterpretq_s64_p16(poly16x8_t a) {17677 return vreinterpretq_s64_p16(a);17678}17679 17680// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_s8(17681// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17682// CHECK-NEXT: [[ENTRY:.*:]]17683// CHECK-NEXT: ret <16 x i8> [[A]]17684//17685uint8x16_t test_vreinterpretq_u8_s8(int8x16_t a) {17686 return vreinterpretq_u8_s8(a);17687}17688 17689// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_s16(17690// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17691// CHECK-NEXT: [[ENTRY:.*:]]17692// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>17693// CHECK-NEXT: ret <16 x i8> [[TMP0]]17694//17695uint8x16_t test_vreinterpretq_u8_s16(int16x8_t a) {17696 return vreinterpretq_u8_s16(a);17697}17698 17699// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_s32(17700// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17701// CHECK-NEXT: [[ENTRY:.*:]]17702// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>17703// CHECK-NEXT: ret <16 x i8> [[TMP0]]17704//17705uint8x16_t test_vreinterpretq_u8_s32(int32x4_t a) {17706 return vreinterpretq_u8_s32(a);17707}17708 17709// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_s64(17710// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17711// CHECK-NEXT: [[ENTRY:.*:]]17712// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>17713// CHECK-NEXT: ret <16 x i8> [[TMP0]]17714//17715uint8x16_t test_vreinterpretq_u8_s64(int64x2_t a) {17716 return vreinterpretq_u8_s64(a);17717}17718 17719// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_u16(17720// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17721// CHECK-NEXT: [[ENTRY:.*:]]17722// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>17723// CHECK-NEXT: ret <16 x i8> [[TMP0]]17724//17725uint8x16_t test_vreinterpretq_u8_u16(uint16x8_t a) {17726 return vreinterpretq_u8_u16(a);17727}17728 17729// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_u32(17730// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17731// CHECK-NEXT: [[ENTRY:.*:]]17732// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>17733// CHECK-NEXT: ret <16 x i8> [[TMP0]]17734//17735uint8x16_t test_vreinterpretq_u8_u32(uint32x4_t a) {17736 return vreinterpretq_u8_u32(a);17737}17738 17739// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_u64(17740// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17741// CHECK-NEXT: [[ENTRY:.*:]]17742// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>17743// CHECK-NEXT: ret <16 x i8> [[TMP0]]17744//17745uint8x16_t test_vreinterpretq_u8_u64(uint64x2_t a) {17746 return vreinterpretq_u8_u64(a);17747}17748 17749// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_f16(17750// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {17751// CHECK-NEXT: [[ENTRY:.*:]]17752// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>17753// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>17754// CHECK-NEXT: ret <16 x i8> [[TMP1]]17755//17756uint8x16_t test_vreinterpretq_u8_f16(float16x8_t a) {17757 return vreinterpretq_u8_f16(a);17758}17759 17760// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_f32(17761// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {17762// CHECK-NEXT: [[ENTRY:.*:]]17763// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>17764// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>17765// CHECK-NEXT: ret <16 x i8> [[TMP1]]17766//17767uint8x16_t test_vreinterpretq_u8_f32(float32x4_t a) {17768 return vreinterpretq_u8_f32(a);17769}17770 17771// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_p8(17772// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17773// CHECK-NEXT: [[ENTRY:.*:]]17774// CHECK-NEXT: ret <16 x i8> [[A]]17775//17776uint8x16_t test_vreinterpretq_u8_p8(poly8x16_t a) {17777 return vreinterpretq_u8_p8(a);17778}17779 17780// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_u8_p16(17781// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17782// CHECK-NEXT: [[ENTRY:.*:]]17783// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>17784// CHECK-NEXT: ret <16 x i8> [[TMP0]]17785//17786uint8x16_t test_vreinterpretq_u8_p16(poly16x8_t a) {17787 return vreinterpretq_u8_p16(a);17788}17789 17790// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_s8(17791// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17792// CHECK-NEXT: [[ENTRY:.*:]]17793// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>17794// CHECK-NEXT: ret <8 x i16> [[TMP0]]17795//17796uint16x8_t test_vreinterpretq_u16_s8(int8x16_t a) {17797 return vreinterpretq_u16_s8(a);17798}17799 17800// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_s16(17801// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17802// CHECK-NEXT: [[ENTRY:.*:]]17803// CHECK-NEXT: ret <8 x i16> [[A]]17804//17805uint16x8_t test_vreinterpretq_u16_s16(int16x8_t a) {17806 return vreinterpretq_u16_s16(a);17807}17808 17809// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_s32(17810// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17811// CHECK-NEXT: [[ENTRY:.*:]]17812// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <8 x i16>17813// CHECK-NEXT: ret <8 x i16> [[TMP0]]17814//17815uint16x8_t test_vreinterpretq_u16_s32(int32x4_t a) {17816 return vreinterpretq_u16_s32(a);17817}17818 17819// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_s64(17820// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17821// CHECK-NEXT: [[ENTRY:.*:]]17822// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <8 x i16>17823// CHECK-NEXT: ret <8 x i16> [[TMP0]]17824//17825uint16x8_t test_vreinterpretq_u16_s64(int64x2_t a) {17826 return vreinterpretq_u16_s64(a);17827}17828 17829// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_u8(17830// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17831// CHECK-NEXT: [[ENTRY:.*:]]17832// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>17833// CHECK-NEXT: ret <8 x i16> [[TMP0]]17834//17835uint16x8_t test_vreinterpretq_u16_u8(uint8x16_t a) {17836 return vreinterpretq_u16_u8(a);17837}17838 17839// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_u32(17840// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17841// CHECK-NEXT: [[ENTRY:.*:]]17842// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <8 x i16>17843// CHECK-NEXT: ret <8 x i16> [[TMP0]]17844//17845uint16x8_t test_vreinterpretq_u16_u32(uint32x4_t a) {17846 return vreinterpretq_u16_u32(a);17847}17848 17849// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_u64(17850// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17851// CHECK-NEXT: [[ENTRY:.*:]]17852// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <8 x i16>17853// CHECK-NEXT: ret <8 x i16> [[TMP0]]17854//17855uint16x8_t test_vreinterpretq_u16_u64(uint64x2_t a) {17856 return vreinterpretq_u16_u64(a);17857}17858 17859// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_f16(17860// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {17861// CHECK-NEXT: [[ENTRY:.*:]]17862// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>17863// CHECK-NEXT: ret <8 x i16> [[TMP0]]17864//17865uint16x8_t test_vreinterpretq_u16_f16(float16x8_t a) {17866 return vreinterpretq_u16_f16(a);17867}17868 17869// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_f32(17870// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {17871// CHECK-NEXT: [[ENTRY:.*:]]17872// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>17873// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <8 x i16>17874// CHECK-NEXT: ret <8 x i16> [[TMP1]]17875//17876uint16x8_t test_vreinterpretq_u16_f32(float32x4_t a) {17877 return vreinterpretq_u16_f32(a);17878}17879 17880// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_p8(17881// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17882// CHECK-NEXT: [[ENTRY:.*:]]17883// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>17884// CHECK-NEXT: ret <8 x i16> [[TMP0]]17885//17886uint16x8_t test_vreinterpretq_u16_p8(poly8x16_t a) {17887 return vreinterpretq_u16_p8(a);17888}17889 17890// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_u16_p16(17891// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17892// CHECK-NEXT: [[ENTRY:.*:]]17893// CHECK-NEXT: ret <8 x i16> [[A]]17894//17895uint16x8_t test_vreinterpretq_u16_p16(poly16x8_t a) {17896 return vreinterpretq_u16_p16(a);17897}17898 17899// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_s8(17900// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17901// CHECK-NEXT: [[ENTRY:.*:]]17902// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <4 x i32>17903// CHECK-NEXT: ret <4 x i32> [[TMP0]]17904//17905uint32x4_t test_vreinterpretq_u32_s8(int8x16_t a) {17906 return vreinterpretq_u32_s8(a);17907}17908 17909// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_s16(17910// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17911// CHECK-NEXT: [[ENTRY:.*:]]17912// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <4 x i32>17913// CHECK-NEXT: ret <4 x i32> [[TMP0]]17914//17915uint32x4_t test_vreinterpretq_u32_s16(int16x8_t a) {17916 return vreinterpretq_u32_s16(a);17917}17918 17919// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_s32(17920// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {17921// CHECK-NEXT: [[ENTRY:.*:]]17922// CHECK-NEXT: ret <4 x i32> [[A]]17923//17924uint32x4_t test_vreinterpretq_u32_s32(int32x4_t a) {17925 return vreinterpretq_u32_s32(a);17926}17927 17928// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_s64(17929// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17930// CHECK-NEXT: [[ENTRY:.*:]]17931// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <4 x i32>17932// CHECK-NEXT: ret <4 x i32> [[TMP0]]17933//17934uint32x4_t test_vreinterpretq_u32_s64(int64x2_t a) {17935 return vreinterpretq_u32_s64(a);17936}17937 17938// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_u8(17939// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17940// CHECK-NEXT: [[ENTRY:.*:]]17941// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <4 x i32>17942// CHECK-NEXT: ret <4 x i32> [[TMP0]]17943//17944uint32x4_t test_vreinterpretq_u32_u8(uint8x16_t a) {17945 return vreinterpretq_u32_u8(a);17946}17947 17948// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_u16(17949// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {17950// CHECK-NEXT: [[ENTRY:.*:]]17951// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <4 x i32>17952// CHECK-NEXT: ret <4 x i32> [[TMP0]]17953//17954uint32x4_t test_vreinterpretq_u32_u16(uint16x8_t a) {17955 return vreinterpretq_u32_u16(a);17956}17957 17958// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_u64(17959// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {17960// CHECK-NEXT: [[ENTRY:.*:]]17961// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <4 x i32>17962// CHECK-NEXT: ret <4 x i32> [[TMP0]]17963//17964uint32x4_t test_vreinterpretq_u32_u64(uint64x2_t a) {17965 return vreinterpretq_u32_u64(a);17966}17967 17968// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_f16(17969// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {17970// CHECK-NEXT: [[ENTRY:.*:]]17971// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <4 x i32>17972// CHECK-NEXT: ret <4 x i32> [[TMP0]]17973//17974uint32x4_t test_vreinterpretq_u32_f16(float16x8_t a) {17975 return vreinterpretq_u32_f16(a);17976}17977 17978// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_f32(17979// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {17980// CHECK-NEXT: [[ENTRY:.*:]]17981// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>17982// CHECK-NEXT: ret <4 x i32> [[TMP0]]17983//17984uint32x4_t test_vreinterpretq_u32_f32(float32x4_t a) {17985 return vreinterpretq_u32_f32(a);17986}17987 17988// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_p8(17989// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {17990// CHECK-NEXT: [[ENTRY:.*:]]17991// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <4 x i32>17992// CHECK-NEXT: ret <4 x i32> [[TMP0]]17993//17994uint32x4_t test_vreinterpretq_u32_p8(poly8x16_t a) {17995 return vreinterpretq_u32_p8(a);17996}17997 17998// CHECK-LABEL: define <4 x i32> @test_vreinterpretq_u32_p16(17999// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18000// CHECK-NEXT: [[ENTRY:.*:]]18001// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <4 x i32>18002// CHECK-NEXT: ret <4 x i32> [[TMP0]]18003//18004uint32x4_t test_vreinterpretq_u32_p16(poly16x8_t a) {18005 return vreinterpretq_u32_p16(a);18006}18007 18008// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_s8(18009// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18010// CHECK-NEXT: [[ENTRY:.*:]]18011// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <2 x i64>18012// CHECK-NEXT: ret <2 x i64> [[TMP0]]18013//18014uint64x2_t test_vreinterpretq_u64_s8(int8x16_t a) {18015 return vreinterpretq_u64_s8(a);18016}18017 18018// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_s16(18019// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18020// CHECK-NEXT: [[ENTRY:.*:]]18021// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <2 x i64>18022// CHECK-NEXT: ret <2 x i64> [[TMP0]]18023//18024uint64x2_t test_vreinterpretq_u64_s16(int16x8_t a) {18025 return vreinterpretq_u64_s16(a);18026}18027 18028// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_s32(18029// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18030// CHECK-NEXT: [[ENTRY:.*:]]18031// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <2 x i64>18032// CHECK-NEXT: ret <2 x i64> [[TMP0]]18033//18034uint64x2_t test_vreinterpretq_u64_s32(int32x4_t a) {18035 return vreinterpretq_u64_s32(a);18036}18037 18038// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_s64(18039// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {18040// CHECK-NEXT: [[ENTRY:.*:]]18041// CHECK-NEXT: ret <2 x i64> [[A]]18042//18043uint64x2_t test_vreinterpretq_u64_s64(int64x2_t a) {18044 return vreinterpretq_u64_s64(a);18045}18046 18047// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_u8(18048// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18049// CHECK-NEXT: [[ENTRY:.*:]]18050// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <2 x i64>18051// CHECK-NEXT: ret <2 x i64> [[TMP0]]18052//18053uint64x2_t test_vreinterpretq_u64_u8(uint8x16_t a) {18054 return vreinterpretq_u64_u8(a);18055}18056 18057// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_u16(18058// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18059// CHECK-NEXT: [[ENTRY:.*:]]18060// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <2 x i64>18061// CHECK-NEXT: ret <2 x i64> [[TMP0]]18062//18063uint64x2_t test_vreinterpretq_u64_u16(uint16x8_t a) {18064 return vreinterpretq_u64_u16(a);18065}18066 18067// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_u32(18068// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18069// CHECK-NEXT: [[ENTRY:.*:]]18070// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <2 x i64>18071// CHECK-NEXT: ret <2 x i64> [[TMP0]]18072//18073uint64x2_t test_vreinterpretq_u64_u32(uint32x4_t a) {18074 return vreinterpretq_u64_u32(a);18075}18076 18077// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_f16(18078// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {18079// CHECK-NEXT: [[ENTRY:.*:]]18080// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <2 x i64>18081// CHECK-NEXT: ret <2 x i64> [[TMP0]]18082//18083uint64x2_t test_vreinterpretq_u64_f16(float16x8_t a) {18084 return vreinterpretq_u64_f16(a);18085}18086 18087// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_f32(18088// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {18089// CHECK-NEXT: [[ENTRY:.*:]]18090// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <2 x i64>18091// CHECK-NEXT: ret <2 x i64> [[TMP0]]18092//18093uint64x2_t test_vreinterpretq_u64_f32(float32x4_t a) {18094 return vreinterpretq_u64_f32(a);18095}18096 18097// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_p8(18098// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18099// CHECK-NEXT: [[ENTRY:.*:]]18100// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <2 x i64>18101// CHECK-NEXT: ret <2 x i64> [[TMP0]]18102//18103uint64x2_t test_vreinterpretq_u64_p8(poly8x16_t a) {18104 return vreinterpretq_u64_p8(a);18105}18106 18107// CHECK-LABEL: define <2 x i64> @test_vreinterpretq_u64_p16(18108// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18109// CHECK-NEXT: [[ENTRY:.*:]]18110// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <2 x i64>18111// CHECK-NEXT: ret <2 x i64> [[TMP0]]18112//18113uint64x2_t test_vreinterpretq_u64_p16(poly16x8_t a) {18114 return vreinterpretq_u64_p16(a);18115}18116 18117// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_s8(18118// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18119// CHECK-NEXT: [[ENTRY:.*:]]18120// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>18121// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <8 x half>18122// CHECK-NEXT: ret <8 x half> [[TMP1]]18123//18124float16x8_t test_vreinterpretq_f16_s8(int8x16_t a) {18125 return vreinterpretq_f16_s8(a);18126}18127 18128// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_s16(18129// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18130// CHECK-NEXT: [[ENTRY:.*:]]18131// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <8 x half>18132// CHECK-NEXT: ret <8 x half> [[TMP0]]18133//18134float16x8_t test_vreinterpretq_f16_s16(int16x8_t a) {18135 return vreinterpretq_f16_s16(a);18136}18137 18138// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_s32(18139// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18140// CHECK-NEXT: [[ENTRY:.*:]]18141// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <8 x half>18142// CHECK-NEXT: ret <8 x half> [[TMP0]]18143//18144float16x8_t test_vreinterpretq_f16_s32(int32x4_t a) {18145 return vreinterpretq_f16_s32(a);18146}18147 18148// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_s64(18149// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {18150// CHECK-NEXT: [[ENTRY:.*:]]18151// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <8 x half>18152// CHECK-NEXT: ret <8 x half> [[TMP0]]18153//18154float16x8_t test_vreinterpretq_f16_s64(int64x2_t a) {18155 return vreinterpretq_f16_s64(a);18156}18157 18158// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_u8(18159// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18160// CHECK-NEXT: [[ENTRY:.*:]]18161// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>18162// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <8 x half>18163// CHECK-NEXT: ret <8 x half> [[TMP1]]18164//18165float16x8_t test_vreinterpretq_f16_u8(uint8x16_t a) {18166 return vreinterpretq_f16_u8(a);18167}18168 18169// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_u16(18170// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18171// CHECK-NEXT: [[ENTRY:.*:]]18172// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <8 x half>18173// CHECK-NEXT: ret <8 x half> [[TMP0]]18174//18175float16x8_t test_vreinterpretq_f16_u16(uint16x8_t a) {18176 return vreinterpretq_f16_u16(a);18177}18178 18179// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_u32(18180// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18181// CHECK-NEXT: [[ENTRY:.*:]]18182// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <8 x half>18183// CHECK-NEXT: ret <8 x half> [[TMP0]]18184//18185float16x8_t test_vreinterpretq_f16_u32(uint32x4_t a) {18186 return vreinterpretq_f16_u32(a);18187}18188 18189// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_u64(18190// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {18191// CHECK-NEXT: [[ENTRY:.*:]]18192// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <8 x half>18193// CHECK-NEXT: ret <8 x half> [[TMP0]]18194//18195float16x8_t test_vreinterpretq_f16_u64(uint64x2_t a) {18196 return vreinterpretq_f16_u64(a);18197}18198 18199// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_f32(18200// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {18201// CHECK-NEXT: [[ENTRY:.*:]]18202// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>18203// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <8 x half>18204// CHECK-NEXT: ret <8 x half> [[TMP1]]18205//18206float16x8_t test_vreinterpretq_f16_f32(float32x4_t a) {18207 return vreinterpretq_f16_f32(a);18208}18209 18210// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_p8(18211// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18212// CHECK-NEXT: [[ENTRY:.*:]]18213// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>18214// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <8 x half>18215// CHECK-NEXT: ret <8 x half> [[TMP1]]18216//18217float16x8_t test_vreinterpretq_f16_p8(poly8x16_t a) {18218 return vreinterpretq_f16_p8(a);18219}18220 18221// CHECK-LABEL: define <8 x half> @test_vreinterpretq_f16_p16(18222// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18223// CHECK-NEXT: [[ENTRY:.*:]]18224// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <8 x half>18225// CHECK-NEXT: ret <8 x half> [[TMP0]]18226//18227float16x8_t test_vreinterpretq_f16_p16(poly16x8_t a) {18228 return vreinterpretq_f16_p16(a);18229}18230 18231// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_s8(18232// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18233// CHECK-NEXT: [[ENTRY:.*:]]18234// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <4 x i32>18235// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <4 x float>18236// CHECK-NEXT: ret <4 x float> [[TMP1]]18237//18238float32x4_t test_vreinterpretq_f32_s8(int8x16_t a) {18239 return vreinterpretq_f32_s8(a);18240}18241 18242// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_s16(18243// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18244// CHECK-NEXT: [[ENTRY:.*:]]18245// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <4 x i32>18246// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <4 x float>18247// CHECK-NEXT: ret <4 x float> [[TMP1]]18248//18249float32x4_t test_vreinterpretq_f32_s16(int16x8_t a) {18250 return vreinterpretq_f32_s16(a);18251}18252 18253// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_s32(18254// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18255// CHECK-NEXT: [[ENTRY:.*:]]18256// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <4 x float>18257// CHECK-NEXT: ret <4 x float> [[TMP0]]18258//18259float32x4_t test_vreinterpretq_f32_s32(int32x4_t a) {18260 return vreinterpretq_f32_s32(a);18261}18262 18263// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_s64(18264// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {18265// CHECK-NEXT: [[ENTRY:.*:]]18266// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <4 x float>18267// CHECK-NEXT: ret <4 x float> [[TMP0]]18268//18269float32x4_t test_vreinterpretq_f32_s64(int64x2_t a) {18270 return vreinterpretq_f32_s64(a);18271}18272 18273// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_u8(18274// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18275// CHECK-NEXT: [[ENTRY:.*:]]18276// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <4 x i32>18277// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <4 x float>18278// CHECK-NEXT: ret <4 x float> [[TMP1]]18279//18280float32x4_t test_vreinterpretq_f32_u8(uint8x16_t a) {18281 return vreinterpretq_f32_u8(a);18282}18283 18284// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_u16(18285// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18286// CHECK-NEXT: [[ENTRY:.*:]]18287// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <4 x i32>18288// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <4 x float>18289// CHECK-NEXT: ret <4 x float> [[TMP1]]18290//18291float32x4_t test_vreinterpretq_f32_u16(uint16x8_t a) {18292 return vreinterpretq_f32_u16(a);18293}18294 18295// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_u32(18296// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18297// CHECK-NEXT: [[ENTRY:.*:]]18298// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <4 x float>18299// CHECK-NEXT: ret <4 x float> [[TMP0]]18300//18301float32x4_t test_vreinterpretq_f32_u32(uint32x4_t a) {18302 return vreinterpretq_f32_u32(a);18303}18304 18305// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_u64(18306// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {18307// CHECK-NEXT: [[ENTRY:.*:]]18308// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <4 x float>18309// CHECK-NEXT: ret <4 x float> [[TMP0]]18310//18311float32x4_t test_vreinterpretq_f32_u64(uint64x2_t a) {18312 return vreinterpretq_f32_u64(a);18313}18314 18315// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_f16(18316// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {18317// CHECK-NEXT: [[ENTRY:.*:]]18318// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <4 x i32>18319// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <4 x float>18320// CHECK-NEXT: ret <4 x float> [[TMP1]]18321//18322float32x4_t test_vreinterpretq_f32_f16(float16x8_t a) {18323 return vreinterpretq_f32_f16(a);18324}18325 18326// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_p8(18327// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18328// CHECK-NEXT: [[ENTRY:.*:]]18329// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <4 x i32>18330// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <4 x float>18331// CHECK-NEXT: ret <4 x float> [[TMP1]]18332//18333float32x4_t test_vreinterpretq_f32_p8(poly8x16_t a) {18334 return vreinterpretq_f32_p8(a);18335}18336 18337// CHECK-LABEL: define <4 x float> @test_vreinterpretq_f32_p16(18338// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18339// CHECK-NEXT: [[ENTRY:.*:]]18340// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <4 x i32>18341// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <4 x float>18342// CHECK-NEXT: ret <4 x float> [[TMP1]]18343//18344float32x4_t test_vreinterpretq_f32_p16(poly16x8_t a) {18345 return vreinterpretq_f32_p16(a);18346}18347 18348// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_s8(18349// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18350// CHECK-NEXT: [[ENTRY:.*:]]18351// CHECK-NEXT: ret <16 x i8> [[A]]18352//18353poly8x16_t test_vreinterpretq_p8_s8(int8x16_t a) {18354 return vreinterpretq_p8_s8(a);18355}18356 18357// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_s16(18358// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18359// CHECK-NEXT: [[ENTRY:.*:]]18360// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>18361// CHECK-NEXT: ret <16 x i8> [[TMP0]]18362//18363poly8x16_t test_vreinterpretq_p8_s16(int16x8_t a) {18364 return vreinterpretq_p8_s16(a);18365}18366 18367// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_s32(18368// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18369// CHECK-NEXT: [[ENTRY:.*:]]18370// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>18371// CHECK-NEXT: ret <16 x i8> [[TMP0]]18372//18373poly8x16_t test_vreinterpretq_p8_s32(int32x4_t a) {18374 return vreinterpretq_p8_s32(a);18375}18376 18377// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_s64(18378// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {18379// CHECK-NEXT: [[ENTRY:.*:]]18380// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>18381// CHECK-NEXT: ret <16 x i8> [[TMP0]]18382//18383poly8x16_t test_vreinterpretq_p8_s64(int64x2_t a) {18384 return vreinterpretq_p8_s64(a);18385}18386 18387// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_u8(18388// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18389// CHECK-NEXT: [[ENTRY:.*:]]18390// CHECK-NEXT: ret <16 x i8> [[A]]18391//18392poly8x16_t test_vreinterpretq_p8_u8(uint8x16_t a) {18393 return vreinterpretq_p8_u8(a);18394}18395 18396// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_u16(18397// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18398// CHECK-NEXT: [[ENTRY:.*:]]18399// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>18400// CHECK-NEXT: ret <16 x i8> [[TMP0]]18401//18402poly8x16_t test_vreinterpretq_p8_u16(uint16x8_t a) {18403 return vreinterpretq_p8_u16(a);18404}18405 18406// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_u32(18407// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18408// CHECK-NEXT: [[ENTRY:.*:]]18409// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>18410// CHECK-NEXT: ret <16 x i8> [[TMP0]]18411//18412poly8x16_t test_vreinterpretq_p8_u32(uint32x4_t a) {18413 return vreinterpretq_p8_u32(a);18414}18415 18416// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_u64(18417// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {18418// CHECK-NEXT: [[ENTRY:.*:]]18419// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>18420// CHECK-NEXT: ret <16 x i8> [[TMP0]]18421//18422poly8x16_t test_vreinterpretq_p8_u64(uint64x2_t a) {18423 return vreinterpretq_p8_u64(a);18424}18425 18426// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_f16(18427// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {18428// CHECK-NEXT: [[ENTRY:.*:]]18429// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>18430// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>18431// CHECK-NEXT: ret <16 x i8> [[TMP1]]18432//18433poly8x16_t test_vreinterpretq_p8_f16(float16x8_t a) {18434 return vreinterpretq_p8_f16(a);18435}18436 18437// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_f32(18438// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {18439// CHECK-NEXT: [[ENTRY:.*:]]18440// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>18441// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>18442// CHECK-NEXT: ret <16 x i8> [[TMP1]]18443//18444poly8x16_t test_vreinterpretq_p8_f32(float32x4_t a) {18445 return vreinterpretq_p8_f32(a);18446}18447 18448// CHECK-LABEL: define <16 x i8> @test_vreinterpretq_p8_p16(18449// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18450// CHECK-NEXT: [[ENTRY:.*:]]18451// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>18452// CHECK-NEXT: ret <16 x i8> [[TMP0]]18453//18454poly8x16_t test_vreinterpretq_p8_p16(poly16x8_t a) {18455 return vreinterpretq_p8_p16(a);18456}18457 18458// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_s8(18459// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18460// CHECK-NEXT: [[ENTRY:.*:]]18461// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>18462// CHECK-NEXT: ret <8 x i16> [[TMP0]]18463//18464poly16x8_t test_vreinterpretq_p16_s8(int8x16_t a) {18465 return vreinterpretq_p16_s8(a);18466}18467 18468// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_s16(18469// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18470// CHECK-NEXT: [[ENTRY:.*:]]18471// CHECK-NEXT: ret <8 x i16> [[A]]18472//18473poly16x8_t test_vreinterpretq_p16_s16(int16x8_t a) {18474 return vreinterpretq_p16_s16(a);18475}18476 18477// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_s32(18478// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18479// CHECK-NEXT: [[ENTRY:.*:]]18480// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <8 x i16>18481// CHECK-NEXT: ret <8 x i16> [[TMP0]]18482//18483poly16x8_t test_vreinterpretq_p16_s32(int32x4_t a) {18484 return vreinterpretq_p16_s32(a);18485}18486 18487// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_s64(18488// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {18489// CHECK-NEXT: [[ENTRY:.*:]]18490// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <8 x i16>18491// CHECK-NEXT: ret <8 x i16> [[TMP0]]18492//18493poly16x8_t test_vreinterpretq_p16_s64(int64x2_t a) {18494 return vreinterpretq_p16_s64(a);18495}18496 18497// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_u8(18498// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18499// CHECK-NEXT: [[ENTRY:.*:]]18500// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>18501// CHECK-NEXT: ret <8 x i16> [[TMP0]]18502//18503poly16x8_t test_vreinterpretq_p16_u8(uint8x16_t a) {18504 return vreinterpretq_p16_u8(a);18505}18506 18507// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_u16(18508// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18509// CHECK-NEXT: [[ENTRY:.*:]]18510// CHECK-NEXT: ret <8 x i16> [[A]]18511//18512poly16x8_t test_vreinterpretq_p16_u16(uint16x8_t a) {18513 return vreinterpretq_p16_u16(a);18514}18515 18516// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_u32(18517// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18518// CHECK-NEXT: [[ENTRY:.*:]]18519// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <8 x i16>18520// CHECK-NEXT: ret <8 x i16> [[TMP0]]18521//18522poly16x8_t test_vreinterpretq_p16_u32(uint32x4_t a) {18523 return vreinterpretq_p16_u32(a);18524}18525 18526// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_u64(18527// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {18528// CHECK-NEXT: [[ENTRY:.*:]]18529// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <8 x i16>18530// CHECK-NEXT: ret <8 x i16> [[TMP0]]18531//18532poly16x8_t test_vreinterpretq_p16_u64(uint64x2_t a) {18533 return vreinterpretq_p16_u64(a);18534}18535 18536// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_f16(18537// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {18538// CHECK-NEXT: [[ENTRY:.*:]]18539// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>18540// CHECK-NEXT: ret <8 x i16> [[TMP0]]18541//18542poly16x8_t test_vreinterpretq_p16_f16(float16x8_t a) {18543 return vreinterpretq_p16_f16(a);18544}18545 18546// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_f32(18547// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {18548// CHECK-NEXT: [[ENTRY:.*:]]18549// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>18550// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <8 x i16>18551// CHECK-NEXT: ret <8 x i16> [[TMP1]]18552//18553poly16x8_t test_vreinterpretq_p16_f32(float32x4_t a) {18554 return vreinterpretq_p16_f32(a);18555}18556 18557// CHECK-LABEL: define <8 x i16> @test_vreinterpretq_p16_p8(18558// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18559// CHECK-NEXT: [[ENTRY:.*:]]18560// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A]] to <8 x i16>18561// CHECK-NEXT: ret <8 x i16> [[TMP0]]18562//18563poly16x8_t test_vreinterpretq_p16_p8(poly8x16_t a) {18564 return vreinterpretq_p16_p8(a);18565}18566 18567// CHECK-LABEL: define <8 x i8> @test_vrev16_s8(18568// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18569// CHECK-NEXT: [[ENTRY:.*:]]18570// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>18571// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]18572//18573int8x8_t test_vrev16_s8(int8x8_t a) {18574 return vrev16_s8(a);18575}18576 18577// CHECK-LABEL: define <8 x i8> @test_vrev16_u8(18578// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18579// CHECK-NEXT: [[ENTRY:.*:]]18580// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>18581// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]18582//18583uint8x8_t test_vrev16_u8(uint8x8_t a) {18584 return vrev16_u8(a);18585}18586 18587// CHECK-LABEL: define <8 x i8> @test_vrev16_p8(18588// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18589// CHECK-NEXT: [[ENTRY:.*:]]18590// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>18591// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]18592//18593poly8x8_t test_vrev16_p8(poly8x8_t a) {18594 return vrev16_p8(a);18595}18596 18597// CHECK-LABEL: define <16 x i8> @test_vrev16q_s8(18598// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18599// CHECK-NEXT: [[ENTRY:.*:]]18600// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>18601// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]18602//18603int8x16_t test_vrev16q_s8(int8x16_t a) {18604 return vrev16q_s8(a);18605}18606 18607// CHECK-LABEL: define <16 x i8> @test_vrev16q_u8(18608// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18609// CHECK-NEXT: [[ENTRY:.*:]]18610// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>18611// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]18612//18613uint8x16_t test_vrev16q_u8(uint8x16_t a) {18614 return vrev16q_u8(a);18615}18616 18617// CHECK-LABEL: define <16 x i8> @test_vrev16q_p8(18618// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18619// CHECK-NEXT: [[ENTRY:.*:]]18620// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>18621// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]18622//18623poly8x16_t test_vrev16q_p8(poly8x16_t a) {18624 return vrev16q_p8(a);18625}18626 18627// CHECK-LABEL: define <8 x i8> @test_vrev32_s8(18628// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18629// CHECK-NEXT: [[ENTRY:.*:]]18630// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>18631// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]18632//18633int8x8_t test_vrev32_s8(int8x8_t a) {18634 return vrev32_s8(a);18635}18636 18637// CHECK-LABEL: define <4 x i16> @test_vrev32_s16(18638// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18639// CHECK-NEXT: [[ENTRY:.*:]]18640// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[A]], <4 x i32> <i32 1, i32 0, i32 3, i32 2>18641// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]18642//18643int16x4_t test_vrev32_s16(int16x4_t a) {18644 return vrev32_s16(a);18645}18646 18647// CHECK-LABEL: define <8 x i8> @test_vrev32_u8(18648// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18649// CHECK-NEXT: [[ENTRY:.*:]]18650// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>18651// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]18652//18653uint8x8_t test_vrev32_u8(uint8x8_t a) {18654 return vrev32_u8(a);18655}18656 18657// CHECK-LABEL: define <4 x i16> @test_vrev32_u16(18658// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18659// CHECK-NEXT: [[ENTRY:.*:]]18660// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[A]], <4 x i32> <i32 1, i32 0, i32 3, i32 2>18661// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]18662//18663uint16x4_t test_vrev32_u16(uint16x4_t a) {18664 return vrev32_u16(a);18665}18666 18667// CHECK-LABEL: define <8 x i8> @test_vrev32_p8(18668// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18669// CHECK-NEXT: [[ENTRY:.*:]]18670// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>18671// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]18672//18673poly8x8_t test_vrev32_p8(poly8x8_t a) {18674 return vrev32_p8(a);18675}18676 18677// CHECK-LABEL: define <4 x i16> @test_vrev32_p16(18678// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18679// CHECK-NEXT: [[ENTRY:.*:]]18680// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[A]], <4 x i32> <i32 1, i32 0, i32 3, i32 2>18681// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]18682//18683poly16x4_t test_vrev32_p16(poly16x4_t a) {18684 return vrev32_p16(a);18685}18686 18687// CHECK-LABEL: define <16 x i8> @test_vrev32q_s8(18688// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18689// CHECK-NEXT: [[ENTRY:.*:]]18690// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>18691// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]18692//18693int8x16_t test_vrev32q_s8(int8x16_t a) {18694 return vrev32q_s8(a);18695}18696 18697// CHECK-LABEL: define <8 x i16> @test_vrev32q_s16(18698// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18699// CHECK-NEXT: [[ENTRY:.*:]]18700// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>18701// CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]]18702//18703int16x8_t test_vrev32q_s16(int16x8_t a) {18704 return vrev32q_s16(a);18705}18706 18707// CHECK-LABEL: define <16 x i8> @test_vrev32q_u8(18708// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18709// CHECK-NEXT: [[ENTRY:.*:]]18710// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>18711// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]18712//18713uint8x16_t test_vrev32q_u8(uint8x16_t a) {18714 return vrev32q_u8(a);18715}18716 18717// CHECK-LABEL: define <8 x i16> @test_vrev32q_u16(18718// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18719// CHECK-NEXT: [[ENTRY:.*:]]18720// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>18721// CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]]18722//18723uint16x8_t test_vrev32q_u16(uint16x8_t a) {18724 return vrev32q_u16(a);18725}18726 18727// CHECK-LABEL: define <16 x i8> @test_vrev32q_p8(18728// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18729// CHECK-NEXT: [[ENTRY:.*:]]18730// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>18731// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]18732//18733poly8x16_t test_vrev32q_p8(poly8x16_t a) {18734 return vrev32q_p8(a);18735}18736 18737// CHECK-LABEL: define <8 x i16> @test_vrev32q_p16(18738// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18739// CHECK-NEXT: [[ENTRY:.*:]]18740// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>18741// CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]]18742//18743poly16x8_t test_vrev32q_p16(poly16x8_t a) {18744 return vrev32q_p16(a);18745}18746 18747// CHECK-LABEL: define <8 x i8> @test_vrev64_s8(18748// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18749// CHECK-NEXT: [[ENTRY:.*:]]18750// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>18751// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]18752//18753int8x8_t test_vrev64_s8(int8x8_t a) {18754 return vrev64_s8(a);18755}18756 18757// CHECK-LABEL: define <4 x i16> @test_vrev64_s16(18758// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18759// CHECK-NEXT: [[ENTRY:.*:]]18760// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[A]], <4 x i32> <i32 3, i32 2, i32 1, i32 0>18761// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]18762//18763int16x4_t test_vrev64_s16(int16x4_t a) {18764 return vrev64_s16(a);18765}18766 18767// CHECK-LABEL: define <2 x i32> @test_vrev64_s32(18768// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18769// CHECK-NEXT: [[ENTRY:.*:]]18770// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> [[A]], <2 x i32> <i32 1, i32 0>18771// CHECK-NEXT: ret <2 x i32> [[SHUFFLE_I]]18772//18773int32x2_t test_vrev64_s32(int32x2_t a) {18774 return vrev64_s32(a);18775}18776 18777// CHECK-LABEL: define <8 x i8> @test_vrev64_u8(18778// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18779// CHECK-NEXT: [[ENTRY:.*:]]18780// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>18781// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]18782//18783uint8x8_t test_vrev64_u8(uint8x8_t a) {18784 return vrev64_u8(a);18785}18786 18787// CHECK-LABEL: define <4 x i16> @test_vrev64_u16(18788// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18789// CHECK-NEXT: [[ENTRY:.*:]]18790// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[A]], <4 x i32> <i32 3, i32 2, i32 1, i32 0>18791// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]18792//18793uint16x4_t test_vrev64_u16(uint16x4_t a) {18794 return vrev64_u16(a);18795}18796 18797// CHECK-LABEL: define <2 x i32> @test_vrev64_u32(18798// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18799// CHECK-NEXT: [[ENTRY:.*:]]18800// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> [[A]], <2 x i32> <i32 1, i32 0>18801// CHECK-NEXT: ret <2 x i32> [[SHUFFLE_I]]18802//18803uint32x2_t test_vrev64_u32(uint32x2_t a) {18804 return vrev64_u32(a);18805}18806 18807// CHECK-LABEL: define <8 x i8> @test_vrev64_p8(18808// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18809// CHECK-NEXT: [[ENTRY:.*:]]18810// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[A]], <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>18811// CHECK-NEXT: ret <8 x i8> [[SHUFFLE_I]]18812//18813poly8x8_t test_vrev64_p8(poly8x8_t a) {18814 return vrev64_p8(a);18815}18816 18817// CHECK-LABEL: define <4 x i16> @test_vrev64_p16(18818// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18819// CHECK-NEXT: [[ENTRY:.*:]]18820// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[A]], <4 x i32> <i32 3, i32 2, i32 1, i32 0>18821// CHECK-NEXT: ret <4 x i16> [[SHUFFLE_I]]18822//18823poly16x4_t test_vrev64_p16(poly16x4_t a) {18824 return vrev64_p16(a);18825}18826 18827// CHECK-LABEL: define <2 x float> @test_vrev64_f32(18828// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] {18829// CHECK-NEXT: [[ENTRY:.*:]]18830// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x float> [[A]], <2 x float> [[A]], <2 x i32> <i32 1, i32 0>18831// CHECK-NEXT: ret <2 x float> [[SHUFFLE_I]]18832//18833float32x2_t test_vrev64_f32(float32x2_t a) {18834 return vrev64_f32(a);18835}18836 18837// CHECK-LABEL: define <16 x i8> @test_vrev64q_s8(18838// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18839// CHECK-NEXT: [[ENTRY:.*:]]18840// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>18841// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]18842//18843int8x16_t test_vrev64q_s8(int8x16_t a) {18844 return vrev64q_s8(a);18845}18846 18847// CHECK-LABEL: define <8 x i16> @test_vrev64q_s16(18848// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18849// CHECK-NEXT: [[ENTRY:.*:]]18850// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>18851// CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]]18852//18853int16x8_t test_vrev64q_s16(int16x8_t a) {18854 return vrev64q_s16(a);18855}18856 18857// CHECK-LABEL: define <4 x i32> @test_vrev64q_s32(18858// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18859// CHECK-NEXT: [[ENTRY:.*:]]18860// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <4 x i32> <i32 1, i32 0, i32 3, i32 2>18861// CHECK-NEXT: ret <4 x i32> [[SHUFFLE_I]]18862//18863int32x4_t test_vrev64q_s32(int32x4_t a) {18864 return vrev64q_s32(a);18865}18866 18867// CHECK-LABEL: define <16 x i8> @test_vrev64q_u8(18868// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18869// CHECK-NEXT: [[ENTRY:.*:]]18870// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>18871// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]18872//18873uint8x16_t test_vrev64q_u8(uint8x16_t a) {18874 return vrev64q_u8(a);18875}18876 18877// CHECK-LABEL: define <8 x i16> @test_vrev64q_u16(18878// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18879// CHECK-NEXT: [[ENTRY:.*:]]18880// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>18881// CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]]18882//18883uint16x8_t test_vrev64q_u16(uint16x8_t a) {18884 return vrev64q_u16(a);18885}18886 18887// CHECK-LABEL: define <4 x i32> @test_vrev64q_u32(18888// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {18889// CHECK-NEXT: [[ENTRY:.*:]]18890// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <4 x i32> <i32 1, i32 0, i32 3, i32 2>18891// CHECK-NEXT: ret <4 x i32> [[SHUFFLE_I]]18892//18893uint32x4_t test_vrev64q_u32(uint32x4_t a) {18894 return vrev64q_u32(a);18895}18896 18897// CHECK-LABEL: define <16 x i8> @test_vrev64q_p8(18898// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] {18899// CHECK-NEXT: [[ENTRY:.*:]]18900// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>18901// CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]]18902//18903poly8x16_t test_vrev64q_p8(poly8x16_t a) {18904 return vrev64q_p8(a);18905}18906 18907// CHECK-LABEL: define <8 x i16> @test_vrev64q_p16(18908// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {18909// CHECK-NEXT: [[ENTRY:.*:]]18910// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>18911// CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]]18912//18913poly16x8_t test_vrev64q_p16(poly16x8_t a) {18914 return vrev64q_p16(a);18915}18916 18917// CHECK-LABEL: define <4 x float> @test_vrev64q_f32(18918// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {18919// CHECK-NEXT: [[ENTRY:.*:]]18920// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> [[A]], <4 x float> [[A]], <4 x i32> <i32 1, i32 0, i32 3, i32 2>18921// CHECK-NEXT: ret <4 x float> [[SHUFFLE_I]]18922//18923float32x4_t test_vrev64q_f32(float32x4_t a) {18924 return vrev64q_f32(a);18925}18926 18927// CHECK-LABEL: define <8 x i8> @test_vrhadd_s8(18928// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {18929// CHECK-NEXT: [[ENTRY:.*:]]18930// CHECK-NEXT: [[VRHADD_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])18931// CHECK-NEXT: ret <8 x i8> [[VRHADD_V_I]]18932//18933int8x8_t test_vrhadd_s8(int8x8_t a, int8x8_t b) {18934 return vrhadd_s8(a, b);18935}18936 18937// CHECK-LABEL: define <4 x i16> @test_vrhadd_s16(18938// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {18939// CHECK-NEXT: [[ENTRY:.*:]]18940// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>18941// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>18942// CHECK-NEXT: [[VRHADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>18943// CHECK-NEXT: [[VRHADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>18944// CHECK-NEXT: [[VRHADD_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16> [[VRHADD_V_I]], <4 x i16> [[VRHADD_V1_I]])18945// CHECK-NEXT: [[VRHADD_V3_I:%.*]] = bitcast <4 x i16> [[VRHADD_V2_I]] to <8 x i8>18946// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRHADD_V3_I]] to <4 x i16>18947// CHECK-NEXT: ret <4 x i16> [[TMP2]]18948//18949int16x4_t test_vrhadd_s16(int16x4_t a, int16x4_t b) {18950 return vrhadd_s16(a, b);18951}18952 18953// CHECK-LABEL: define <2 x i32> @test_vrhadd_s32(18954// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {18955// CHECK-NEXT: [[ENTRY:.*:]]18956// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>18957// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>18958// CHECK-NEXT: [[VRHADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>18959// CHECK-NEXT: [[VRHADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>18960// CHECK-NEXT: [[VRHADD_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32> [[VRHADD_V_I]], <2 x i32> [[VRHADD_V1_I]])18961// CHECK-NEXT: [[VRHADD_V3_I:%.*]] = bitcast <2 x i32> [[VRHADD_V2_I]] to <8 x i8>18962// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRHADD_V3_I]] to <2 x i32>18963// CHECK-NEXT: ret <2 x i32> [[TMP2]]18964//18965int32x2_t test_vrhadd_s32(int32x2_t a, int32x2_t b) {18966 return vrhadd_s32(a, b);18967}18968 18969// CHECK-LABEL: define <8 x i8> @test_vrhadd_u8(18970// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {18971// CHECK-NEXT: [[ENTRY:.*:]]18972// CHECK-NEXT: [[VRHADD_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])18973// CHECK-NEXT: ret <8 x i8> [[VRHADD_V_I]]18974//18975uint8x8_t test_vrhadd_u8(uint8x8_t a, uint8x8_t b) {18976 return vrhadd_u8(a, b);18977}18978 18979// CHECK-LABEL: define <4 x i16> @test_vrhadd_u16(18980// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {18981// CHECK-NEXT: [[ENTRY:.*:]]18982// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>18983// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>18984// CHECK-NEXT: [[VRHADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>18985// CHECK-NEXT: [[VRHADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>18986// CHECK-NEXT: [[VRHADD_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16> [[VRHADD_V_I]], <4 x i16> [[VRHADD_V1_I]])18987// CHECK-NEXT: [[VRHADD_V3_I:%.*]] = bitcast <4 x i16> [[VRHADD_V2_I]] to <8 x i8>18988// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRHADD_V3_I]] to <4 x i16>18989// CHECK-NEXT: ret <4 x i16> [[TMP2]]18990//18991uint16x4_t test_vrhadd_u16(uint16x4_t a, uint16x4_t b) {18992 return vrhadd_u16(a, b);18993}18994 18995// CHECK-LABEL: define <2 x i32> @test_vrhadd_u32(18996// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {18997// CHECK-NEXT: [[ENTRY:.*:]]18998// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>18999// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>19000// CHECK-NEXT: [[VRHADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>19001// CHECK-NEXT: [[VRHADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>19002// CHECK-NEXT: [[VRHADD_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32> [[VRHADD_V_I]], <2 x i32> [[VRHADD_V1_I]])19003// CHECK-NEXT: [[VRHADD_V3_I:%.*]] = bitcast <2 x i32> [[VRHADD_V2_I]] to <8 x i8>19004// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRHADD_V3_I]] to <2 x i32>19005// CHECK-NEXT: ret <2 x i32> [[TMP2]]19006//19007uint32x2_t test_vrhadd_u32(uint32x2_t a, uint32x2_t b) {19008 return vrhadd_u32(a, b);19009}19010 19011// CHECK-LABEL: define <16 x i8> @test_vrhaddq_s8(19012// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {19013// CHECK-NEXT: [[ENTRY:.*:]]19014// CHECK-NEXT: [[VRHADDQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])19015// CHECK-NEXT: ret <16 x i8> [[VRHADDQ_V_I]]19016//19017int8x16_t test_vrhaddq_s8(int8x16_t a, int8x16_t b) {19018 return vrhaddq_s8(a, b);19019}19020 19021// CHECK-LABEL: define <8 x i16> @test_vrhaddq_s16(19022// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {19023// CHECK-NEXT: [[ENTRY:.*:]]19024// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>19025// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>19026// CHECK-NEXT: [[VRHADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>19027// CHECK-NEXT: [[VRHADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>19028// CHECK-NEXT: [[VRHADDQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> [[VRHADDQ_V_I]], <8 x i16> [[VRHADDQ_V1_I]])19029// CHECK-NEXT: [[VRHADDQ_V3_I:%.*]] = bitcast <8 x i16> [[VRHADDQ_V2_I]] to <16 x i8>19030// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRHADDQ_V3_I]] to <8 x i16>19031// CHECK-NEXT: ret <8 x i16> [[TMP2]]19032//19033int16x8_t test_vrhaddq_s16(int16x8_t a, int16x8_t b) {19034 return vrhaddq_s16(a, b);19035}19036 19037// CHECK-LABEL: define <4 x i32> @test_vrhaddq_s32(19038// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {19039// CHECK-NEXT: [[ENTRY:.*:]]19040// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>19041// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>19042// CHECK-NEXT: [[VRHADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>19043// CHECK-NEXT: [[VRHADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>19044// CHECK-NEXT: [[VRHADDQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32> [[VRHADDQ_V_I]], <4 x i32> [[VRHADDQ_V1_I]])19045// CHECK-NEXT: [[VRHADDQ_V3_I:%.*]] = bitcast <4 x i32> [[VRHADDQ_V2_I]] to <16 x i8>19046// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRHADDQ_V3_I]] to <4 x i32>19047// CHECK-NEXT: ret <4 x i32> [[TMP2]]19048//19049int32x4_t test_vrhaddq_s32(int32x4_t a, int32x4_t b) {19050 return vrhaddq_s32(a, b);19051}19052 19053// CHECK-LABEL: define <16 x i8> @test_vrhaddq_u8(19054// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {19055// CHECK-NEXT: [[ENTRY:.*:]]19056// CHECK-NEXT: [[VRHADDQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])19057// CHECK-NEXT: ret <16 x i8> [[VRHADDQ_V_I]]19058//19059uint8x16_t test_vrhaddq_u8(uint8x16_t a, uint8x16_t b) {19060 return vrhaddq_u8(a, b);19061}19062 19063// CHECK-LABEL: define <8 x i16> @test_vrhaddq_u16(19064// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {19065// CHECK-NEXT: [[ENTRY:.*:]]19066// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>19067// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>19068// CHECK-NEXT: [[VRHADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>19069// CHECK-NEXT: [[VRHADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>19070// CHECK-NEXT: [[VRHADDQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> [[VRHADDQ_V_I]], <8 x i16> [[VRHADDQ_V1_I]])19071// CHECK-NEXT: [[VRHADDQ_V3_I:%.*]] = bitcast <8 x i16> [[VRHADDQ_V2_I]] to <16 x i8>19072// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRHADDQ_V3_I]] to <8 x i16>19073// CHECK-NEXT: ret <8 x i16> [[TMP2]]19074//19075uint16x8_t test_vrhaddq_u16(uint16x8_t a, uint16x8_t b) {19076 return vrhaddq_u16(a, b);19077}19078 19079// CHECK-LABEL: define <4 x i32> @test_vrhaddq_u32(19080// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {19081// CHECK-NEXT: [[ENTRY:.*:]]19082// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>19083// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>19084// CHECK-NEXT: [[VRHADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>19085// CHECK-NEXT: [[VRHADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>19086// CHECK-NEXT: [[VRHADDQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32> [[VRHADDQ_V_I]], <4 x i32> [[VRHADDQ_V1_I]])19087// CHECK-NEXT: [[VRHADDQ_V3_I:%.*]] = bitcast <4 x i32> [[VRHADDQ_V2_I]] to <16 x i8>19088// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRHADDQ_V3_I]] to <4 x i32>19089// CHECK-NEXT: ret <4 x i32> [[TMP2]]19090//19091uint32x4_t test_vrhaddq_u32(uint32x4_t a, uint32x4_t b) {19092 return vrhaddq_u32(a, b);19093}19094 19095// CHECK-LABEL: define <8 x i8> @test_vrshl_s8(19096// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {19097// CHECK-NEXT: [[ENTRY:.*:]]19098// CHECK-NEXT: [[VRSHL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])19099// CHECK-NEXT: ret <8 x i8> [[VRSHL_V_I]]19100//19101int8x8_t test_vrshl_s8(int8x8_t a, int8x8_t b) {19102 return vrshl_s8(a, b);19103}19104 19105// CHECK-LABEL: define <4 x i16> @test_vrshl_s16(19106// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {19107// CHECK-NEXT: [[ENTRY:.*:]]19108// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>19109// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>19110// CHECK-NEXT: [[VRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>19111// CHECK-NEXT: [[VRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>19112// CHECK-NEXT: [[VRSHL_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> [[VRSHL_V_I]], <4 x i16> [[VRSHL_V1_I]])19113// CHECK-NEXT: [[VRSHL_V3_I:%.*]] = bitcast <4 x i16> [[VRSHL_V2_I]] to <8 x i8>19114// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRSHL_V3_I]] to <4 x i16>19115// CHECK-NEXT: ret <4 x i16> [[TMP2]]19116//19117int16x4_t test_vrshl_s16(int16x4_t a, int16x4_t b) {19118 return vrshl_s16(a, b);19119}19120 19121// CHECK-LABEL: define <2 x i32> @test_vrshl_s32(19122// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {19123// CHECK-NEXT: [[ENTRY:.*:]]19124// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>19125// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>19126// CHECK-NEXT: [[VRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>19127// CHECK-NEXT: [[VRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>19128// CHECK-NEXT: [[VRSHL_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> [[VRSHL_V_I]], <2 x i32> [[VRSHL_V1_I]])19129// CHECK-NEXT: [[VRSHL_V3_I:%.*]] = bitcast <2 x i32> [[VRSHL_V2_I]] to <8 x i8>19130// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRSHL_V3_I]] to <2 x i32>19131// CHECK-NEXT: ret <2 x i32> [[TMP2]]19132//19133int32x2_t test_vrshl_s32(int32x2_t a, int32x2_t b) {19134 return vrshl_s32(a, b);19135}19136 19137// CHECK-LABEL: define <1 x i64> @test_vrshl_s64(19138// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {19139// CHECK-NEXT: [[ENTRY:.*:]]19140// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>19141// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>19142// CHECK-NEXT: [[VRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>19143// CHECK-NEXT: [[VRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>19144// CHECK-NEXT: [[VRSHL_V2_I:%.*]] = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> [[VRSHL_V_I]], <1 x i64> [[VRSHL_V1_I]])19145// CHECK-NEXT: [[VRSHL_V3_I:%.*]] = bitcast <1 x i64> [[VRSHL_V2_I]] to <8 x i8>19146// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRSHL_V3_I]] to i6419147// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 019148// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]19149//19150int64x1_t test_vrshl_s64(int64x1_t a, int64x1_t b) {19151 return vrshl_s64(a, b);19152}19153 19154// CHECK-LABEL: define <8 x i8> @test_vrshl_u8(19155// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {19156// CHECK-NEXT: [[ENTRY:.*:]]19157// CHECK-NEXT: [[VRSHL_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])19158// CHECK-NEXT: ret <8 x i8> [[VRSHL_V_I]]19159//19160uint8x8_t test_vrshl_u8(uint8x8_t a, int8x8_t b) {19161 return vrshl_u8(a, b);19162}19163 19164// CHECK-LABEL: define <4 x i16> @test_vrshl_u16(19165// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {19166// CHECK-NEXT: [[ENTRY:.*:]]19167// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>19168// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>19169// CHECK-NEXT: [[VRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>19170// CHECK-NEXT: [[VRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>19171// CHECK-NEXT: [[VRSHL_V2_I:%.*]] = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> [[VRSHL_V_I]], <4 x i16> [[VRSHL_V1_I]])19172// CHECK-NEXT: [[VRSHL_V3_I:%.*]] = bitcast <4 x i16> [[VRSHL_V2_I]] to <8 x i8>19173// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRSHL_V3_I]] to <4 x i16>19174// CHECK-NEXT: ret <4 x i16> [[TMP2]]19175//19176uint16x4_t test_vrshl_u16(uint16x4_t a, int16x4_t b) {19177 return vrshl_u16(a, b);19178}19179 19180// CHECK-LABEL: define <2 x i32> @test_vrshl_u32(19181// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {19182// CHECK-NEXT: [[ENTRY:.*:]]19183// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>19184// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>19185// CHECK-NEXT: [[VRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>19186// CHECK-NEXT: [[VRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>19187// CHECK-NEXT: [[VRSHL_V2_I:%.*]] = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> [[VRSHL_V_I]], <2 x i32> [[VRSHL_V1_I]])19188// CHECK-NEXT: [[VRSHL_V3_I:%.*]] = bitcast <2 x i32> [[VRSHL_V2_I]] to <8 x i8>19189// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRSHL_V3_I]] to <2 x i32>19190// CHECK-NEXT: ret <2 x i32> [[TMP2]]19191//19192uint32x2_t test_vrshl_u32(uint32x2_t a, int32x2_t b) {19193 return vrshl_u32(a, b);19194}19195 19196// CHECK-LABEL: define <1 x i64> @test_vrshl_u64(19197// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {19198// CHECK-NEXT: [[ENTRY:.*:]]19199// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>19200// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>19201// CHECK-NEXT: [[VRSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>19202// CHECK-NEXT: [[VRSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>19203// CHECK-NEXT: [[VRSHL_V2_I:%.*]] = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> [[VRSHL_V_I]], <1 x i64> [[VRSHL_V1_I]])19204// CHECK-NEXT: [[VRSHL_V3_I:%.*]] = bitcast <1 x i64> [[VRSHL_V2_I]] to <8 x i8>19205// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRSHL_V3_I]] to i6419206// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 019207// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]19208//19209uint64x1_t test_vrshl_u64(uint64x1_t a, int64x1_t b) {19210 return vrshl_u64(a, b);19211}19212 19213// CHECK-LABEL: define <16 x i8> @test_vrshlq_s8(19214// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {19215// CHECK-NEXT: [[ENTRY:.*:]]19216// CHECK-NEXT: [[VRSHLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])19217// CHECK-NEXT: ret <16 x i8> [[VRSHLQ_V_I]]19218//19219int8x16_t test_vrshlq_s8(int8x16_t a, int8x16_t b) {19220 return vrshlq_s8(a, b);19221}19222 19223// CHECK-LABEL: define <8 x i16> @test_vrshlq_s16(19224// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {19225// CHECK-NEXT: [[ENTRY:.*:]]19226// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>19227// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>19228// CHECK-NEXT: [[VRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>19229// CHECK-NEXT: [[VRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>19230// CHECK-NEXT: [[VRSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> [[VRSHLQ_V_I]], <8 x i16> [[VRSHLQ_V1_I]])19231// CHECK-NEXT: [[VRSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VRSHLQ_V2_I]] to <16 x i8>19232// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRSHLQ_V3_I]] to <8 x i16>19233// CHECK-NEXT: ret <8 x i16> [[TMP2]]19234//19235int16x8_t test_vrshlq_s16(int16x8_t a, int16x8_t b) {19236 return vrshlq_s16(a, b);19237}19238 19239// CHECK-LABEL: define <4 x i32> @test_vrshlq_s32(19240// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {19241// CHECK-NEXT: [[ENTRY:.*:]]19242// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>19243// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>19244// CHECK-NEXT: [[VRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>19245// CHECK-NEXT: [[VRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>19246// CHECK-NEXT: [[VRSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> [[VRSHLQ_V_I]], <4 x i32> [[VRSHLQ_V1_I]])19247// CHECK-NEXT: [[VRSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VRSHLQ_V2_I]] to <16 x i8>19248// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRSHLQ_V3_I]] to <4 x i32>19249// CHECK-NEXT: ret <4 x i32> [[TMP2]]19250//19251int32x4_t test_vrshlq_s32(int32x4_t a, int32x4_t b) {19252 return vrshlq_s32(a, b);19253}19254 19255// CHECK-LABEL: define <2 x i64> @test_vrshlq_s64(19256// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {19257// CHECK-NEXT: [[ENTRY:.*:]]19258// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>19259// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>19260// CHECK-NEXT: [[VRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>19261// CHECK-NEXT: [[VRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>19262// CHECK-NEXT: [[VRSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> [[VRSHLQ_V_I]], <2 x i64> [[VRSHLQ_V1_I]])19263// CHECK-NEXT: [[VRSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VRSHLQ_V2_I]] to <16 x i8>19264// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRSHLQ_V3_I]] to <2 x i64>19265// CHECK-NEXT: ret <2 x i64> [[TMP2]]19266//19267int64x2_t test_vrshlq_s64(int64x2_t a, int64x2_t b) {19268 return vrshlq_s64(a, b);19269}19270 19271// CHECK-LABEL: define <16 x i8> @test_vrshlq_u8(19272// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {19273// CHECK-NEXT: [[ENTRY:.*:]]19274// CHECK-NEXT: [[VRSHLQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])19275// CHECK-NEXT: ret <16 x i8> [[VRSHLQ_V_I]]19276//19277uint8x16_t test_vrshlq_u8(uint8x16_t a, int8x16_t b) {19278 return vrshlq_u8(a, b);19279}19280 19281// CHECK-LABEL: define <8 x i16> @test_vrshlq_u16(19282// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {19283// CHECK-NEXT: [[ENTRY:.*:]]19284// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>19285// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>19286// CHECK-NEXT: [[VRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>19287// CHECK-NEXT: [[VRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>19288// CHECK-NEXT: [[VRSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> [[VRSHLQ_V_I]], <8 x i16> [[VRSHLQ_V1_I]])19289// CHECK-NEXT: [[VRSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VRSHLQ_V2_I]] to <16 x i8>19290// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRSHLQ_V3_I]] to <8 x i16>19291// CHECK-NEXT: ret <8 x i16> [[TMP2]]19292//19293uint16x8_t test_vrshlq_u16(uint16x8_t a, int16x8_t b) {19294 return vrshlq_u16(a, b);19295}19296 19297// CHECK-LABEL: define <4 x i32> @test_vrshlq_u32(19298// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {19299// CHECK-NEXT: [[ENTRY:.*:]]19300// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>19301// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>19302// CHECK-NEXT: [[VRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>19303// CHECK-NEXT: [[VRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>19304// CHECK-NEXT: [[VRSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> [[VRSHLQ_V_I]], <4 x i32> [[VRSHLQ_V1_I]])19305// CHECK-NEXT: [[VRSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VRSHLQ_V2_I]] to <16 x i8>19306// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRSHLQ_V3_I]] to <4 x i32>19307// CHECK-NEXT: ret <4 x i32> [[TMP2]]19308//19309uint32x4_t test_vrshlq_u32(uint32x4_t a, int32x4_t b) {19310 return vrshlq_u32(a, b);19311}19312 19313// CHECK-LABEL: define <2 x i64> @test_vrshlq_u64(19314// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {19315// CHECK-NEXT: [[ENTRY:.*:]]19316// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>19317// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>19318// CHECK-NEXT: [[VRSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>19319// CHECK-NEXT: [[VRSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>19320// CHECK-NEXT: [[VRSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> [[VRSHLQ_V_I]], <2 x i64> [[VRSHLQ_V1_I]])19321// CHECK-NEXT: [[VRSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VRSHLQ_V2_I]] to <16 x i8>19322// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRSHLQ_V3_I]] to <2 x i64>19323// CHECK-NEXT: ret <2 x i64> [[TMP2]]19324//19325uint64x2_t test_vrshlq_u64(uint64x2_t a, int64x2_t b) {19326 return vrshlq_u64(a, b);19327}19328 19329// CHECK-LABEL: define <8 x i8> @test_vrshrn_n_s16(19330// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {19331// CHECK-NEXT: [[ENTRY:.*:]]19332// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>19333// CHECK-NEXT: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>19334// CHECK-NEXT: [[VRSHRN_N1:%.*]] = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> [[VRSHRN_N]], <8 x i16> splat (i16 -1))19335// CHECK-NEXT: ret <8 x i8> [[VRSHRN_N1]]19336//19337int8x8_t test_vrshrn_n_s16(int16x8_t a) {19338 return vrshrn_n_s16(a, 1);19339}19340 19341// CHECK-LABEL: define <4 x i16> @test_vrshrn_n_s32(19342// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {19343// CHECK-NEXT: [[ENTRY:.*:]]19344// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>19345// CHECK-NEXT: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>19346// CHECK-NEXT: [[VRSHRN_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> [[VRSHRN_N]], <4 x i32> splat (i32 -1))19347// CHECK-NEXT: ret <4 x i16> [[VRSHRN_N1]]19348//19349int16x4_t test_vrshrn_n_s32(int32x4_t a) {19350 return vrshrn_n_s32(a, 1);19351}19352 19353// CHECK-LABEL: define <2 x i32> @test_vrshrn_n_s64(19354// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {19355// CHECK-NEXT: [[ENTRY:.*:]]19356// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>19357// CHECK-NEXT: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>19358// CHECK-NEXT: [[VRSHRN_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> [[VRSHRN_N]], <2 x i64> splat (i64 -1))19359// CHECK-NEXT: ret <2 x i32> [[VRSHRN_N1]]19360//19361int32x2_t test_vrshrn_n_s64(int64x2_t a) {19362 return vrshrn_n_s64(a, 1);19363}19364 19365// CHECK-LABEL: define <8 x i8> @test_vrshrn_n_u16(19366// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {19367// CHECK-NEXT: [[ENTRY:.*:]]19368// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>19369// CHECK-NEXT: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>19370// CHECK-NEXT: [[VRSHRN_N1:%.*]] = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> [[VRSHRN_N]], <8 x i16> splat (i16 -1))19371// CHECK-NEXT: ret <8 x i8> [[VRSHRN_N1]]19372//19373uint8x8_t test_vrshrn_n_u16(uint16x8_t a) {19374 return vrshrn_n_u16(a, 1);19375}19376 19377// CHECK-LABEL: define <4 x i16> @test_vrshrn_n_u32(19378// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] {19379// CHECK-NEXT: [[ENTRY:.*:]]19380// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>19381// CHECK-NEXT: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>19382// CHECK-NEXT: [[VRSHRN_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> [[VRSHRN_N]], <4 x i32> splat (i32 -1))19383// CHECK-NEXT: ret <4 x i16> [[VRSHRN_N1]]19384//19385uint16x4_t test_vrshrn_n_u32(uint32x4_t a) {19386 return vrshrn_n_u32(a, 1);19387}19388 19389// CHECK-LABEL: define <2 x i32> @test_vrshrn_n_u64(19390// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {19391// CHECK-NEXT: [[ENTRY:.*:]]19392// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>19393// CHECK-NEXT: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>19394// CHECK-NEXT: [[VRSHRN_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> [[VRSHRN_N]], <2 x i64> splat (i64 -1))19395// CHECK-NEXT: ret <2 x i32> [[VRSHRN_N1]]19396//19397uint32x2_t test_vrshrn_n_u64(uint64x2_t a) {19398 return vrshrn_n_u64(a, 1);19399}19400 19401// CHECK-LABEL: define <8 x i8> @test_vrshr_n_s8(19402// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {19403// CHECK-NEXT: [[ENTRY:.*:]]19404// CHECK-NEXT: [[VRSHR_N:%.*]] = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 -1))19405// CHECK-NEXT: ret <8 x i8> [[VRSHR_N]]19406//19407int8x8_t test_vrshr_n_s8(int8x8_t a) {19408 return vrshr_n_s8(a, 1);19409}19410 19411// CHECK-LABEL: define <4 x i16> @test_vrshr_n_s16(19412// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {19413// CHECK-NEXT: [[ENTRY:.*:]]19414// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>19415// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>19416// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> [[VRSHR_N]], <4 x i16> splat (i16 -1))19417// CHECK-NEXT: ret <4 x i16> [[VRSHR_N1]]19418//19419int16x4_t test_vrshr_n_s16(int16x4_t a) {19420 return vrshr_n_s16(a, 1);19421}19422 19423// CHECK-LABEL: define <2 x i32> @test_vrshr_n_s32(19424// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {19425// CHECK-NEXT: [[ENTRY:.*:]]19426// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>19427// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>19428// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> [[VRSHR_N]], <2 x i32> splat (i32 -1))19429// CHECK-NEXT: ret <2 x i32> [[VRSHR_N1]]19430//19431int32x2_t test_vrshr_n_s32(int32x2_t a) {19432 return vrshr_n_s32(a, 1);19433}19434 19435// CHECK-LABEL: define <1 x i64> @test_vrshr_n_s64(19436// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] {19437// CHECK-NEXT: [[ENTRY:.*:]]19438// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>19439// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>19440// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> [[VRSHR_N]], <1 x i64> splat (i64 -1))19441// CHECK-NEXT: ret <1 x i64> [[VRSHR_N1]]19442//19443int64x1_t test_vrshr_n_s64(int64x1_t a) {19444 return vrshr_n_s64(a, 1);19445}19446 19447// CHECK-LABEL: define <8 x i8> @test_vrshr_n_u8(19448// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {19449// CHECK-NEXT: [[ENTRY:.*:]]19450// CHECK-NEXT: [[VRSHR_N:%.*]] = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 -1))19451// CHECK-NEXT: ret <8 x i8> [[VRSHR_N]]19452//19453uint8x8_t test_vrshr_n_u8(uint8x8_t a) {19454 return vrshr_n_u8(a, 1);19455}19456 19457// CHECK-LABEL: define <4 x i16> @test_vrshr_n_u16(19458// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {19459// CHECK-NEXT: [[ENTRY:.*:]]19460// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>19461// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>19462// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> [[VRSHR_N]], <4 x i16> splat (i16 -1))19463// CHECK-NEXT: ret <4 x i16> [[VRSHR_N1]]19464//19465uint16x4_t test_vrshr_n_u16(uint16x4_t a) {19466 return vrshr_n_u16(a, 1);19467}19468 19469// CHECK-LABEL: define <2 x i32> @test_vrshr_n_u32(19470// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] {File truncated to the first 1 MiB.