339 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 42// RUN: %clang_cc1 -triple armv5e-none-linux-gnueabi -emit-llvm %s -o - | FileCheck %s3 4enum memory_order {5 memory_order_relaxed, memory_order_consume, memory_order_acquire,6 memory_order_release, memory_order_acq_rel, memory_order_seq_cst7};8 9// CHECK-LABEL: define dso_local ptr @test_c11_atomic_fetch_add_int_ptr(10// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] {11// CHECK-NEXT: entry:12// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 413// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 414// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca ptr, align 415// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 416// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 417// CHECK-NEXT: store i32 12, ptr [[DOTATOMICTMP]], align 418// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 419// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 420// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 421// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ATOMIC_TEMP]], align 422// CHECK-NEXT: ret ptr [[TMP3]]23//24int *test_c11_atomic_fetch_add_int_ptr(_Atomic(int *) *p) {25 return __c11_atomic_fetch_add(p, 3, memory_order_seq_cst);26}27 28// CHECK-LABEL: define dso_local ptr @test_c11_atomic_fetch_sub_int_ptr(29// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {30// CHECK-NEXT: entry:31// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 432// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 433// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca ptr, align 434// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 435// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 436// CHECK-NEXT: store i32 20, ptr [[DOTATOMICTMP]], align 437// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 438// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw sub ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 439// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 440// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ATOMIC_TEMP]], align 441// CHECK-NEXT: ret ptr [[TMP3]]42//43int *test_c11_atomic_fetch_sub_int_ptr(_Atomic(int *) *p) {44 return __c11_atomic_fetch_sub(p, 5, memory_order_seq_cst);45}46 47// CHECK-LABEL: define dso_local i32 @test_c11_atomic_fetch_add_int(48// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {49// CHECK-NEXT: entry:50// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 451// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 452// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 453// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 454// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 455// CHECK-NEXT: store i32 3, ptr [[DOTATOMICTMP]], align 456// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 457// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 458// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 459// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 460// CHECK-NEXT: ret i32 [[TMP3]]61//62int test_c11_atomic_fetch_add_int(_Atomic(int) *p) {63 return __c11_atomic_fetch_add(p, 3, memory_order_seq_cst);64}65 66// CHECK-LABEL: define dso_local i32 @test_c11_atomic_fetch_sub_int(67// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {68// CHECK-NEXT: entry:69// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 470// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 471// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 472// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 473// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 474// CHECK-NEXT: store i32 5, ptr [[DOTATOMICTMP]], align 475// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 476// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw sub ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 477// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 478// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 479// CHECK-NEXT: ret i32 [[TMP3]]80//81int test_c11_atomic_fetch_sub_int(_Atomic(int) *p) {82 return __c11_atomic_fetch_sub(p, 5, memory_order_seq_cst);83}84 85// CHECK-LABEL: define dso_local ptr @fp2a(86// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {87// CHECK-NEXT: entry:88// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 489// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 490// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca ptr, align 491// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 492// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 493// CHECK-NEXT: store i32 4, ptr [[DOTATOMICTMP]], align 494// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 495// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw sub ptr [[TMP0]], i32 [[TMP1]] monotonic, align 496// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 497// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ATOMIC_TEMP]], align 498// CHECK-NEXT: ret ptr [[TMP3]]99//100int *fp2a(int **p) {101 // Note, the GNU builtins do not multiply by sizeof(T)!102 return __atomic_fetch_sub(p, 4, memory_order_relaxed);103}104 105// CHECK-LABEL: define dso_local i32 @test_atomic_fetch_add(106// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {107// CHECK-NEXT: entry:108// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4109// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4110// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4111// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4112// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4113// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4114// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4115// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4116// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 4117// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4118// CHECK-NEXT: ret i32 [[TMP3]]119//120int test_atomic_fetch_add(int *p) {121 return __atomic_fetch_add(p, 55, memory_order_seq_cst);122}123 124// CHECK-LABEL: define dso_local i32 @test_atomic_fetch_sub(125// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {126// CHECK-NEXT: entry:127// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4128// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4129// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4130// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4131// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4132// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4133// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4134// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw sub ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4135// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 4136// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4137// CHECK-NEXT: ret i32 [[TMP3]]138//139int test_atomic_fetch_sub(int *p) {140 return __atomic_fetch_sub(p, 55, memory_order_seq_cst);141}142 143// CHECK-LABEL: define dso_local i32 @test_atomic_fetch_and(144// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {145// CHECK-NEXT: entry:146// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4147// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4148// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4149// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4150// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4151// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4152// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4153// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw and ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4154// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 4155// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4156// CHECK-NEXT: ret i32 [[TMP3]]157//158int test_atomic_fetch_and(int *p) {159 return __atomic_fetch_and(p, 55, memory_order_seq_cst);160}161 162// CHECK-LABEL: define dso_local i32 @test_atomic_fetch_or(163// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {164// CHECK-NEXT: entry:165// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4166// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4167// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4168// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4169// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4170// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4171// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4172// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw or ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4173// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 4174// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4175// CHECK-NEXT: ret i32 [[TMP3]]176//177int test_atomic_fetch_or(int *p) {178 return __atomic_fetch_or(p, 55, memory_order_seq_cst);179}180 181// CHECK-LABEL: define dso_local i32 @test_atomic_fetch_xor(182// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {183// CHECK-NEXT: entry:184// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4185// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4186// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4187// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4188// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4189// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4190// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4191// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xor ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4192// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 4193// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4194// CHECK-NEXT: ret i32 [[TMP3]]195//196int test_atomic_fetch_xor(int *p) {197 return __atomic_fetch_xor(p, 55, memory_order_seq_cst);198}199 200// CHECK-LABEL: define dso_local i32 @test_atomic_fetch_nand(201// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {202// CHECK-NEXT: entry:203// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4204// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4205// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4206// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4207// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4208// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4209// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4210// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw nand ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4211// CHECK-NEXT: store i32 [[TMP2]], ptr [[ATOMIC_TEMP]], align 4212// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4213// CHECK-NEXT: ret i32 [[TMP3]]214//215int test_atomic_fetch_nand(int *p) {216 return __atomic_fetch_nand(p, 55, memory_order_seq_cst);217}218 219// CHECK-LABEL: define dso_local i32 @test_atomic_add_fetch(220// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {221// CHECK-NEXT: entry:222// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4223// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4224// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4225// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4226// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4227// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4228// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4229// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4230// CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], [[TMP1]]231// CHECK-NEXT: store i32 [[TMP3]], ptr [[ATOMIC_TEMP]], align 4232// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4233// CHECK-NEXT: ret i32 [[TMP4]]234//235int test_atomic_add_fetch(int *p) {236 return __atomic_add_fetch(p, 55, memory_order_seq_cst);237}238 239// CHECK-LABEL: define dso_local i32 @test_atomic_sub_fetch(240// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {241// CHECK-NEXT: entry:242// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4243// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4244// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4245// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4246// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4247// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4248// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4249// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw sub ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4250// CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[TMP1]]251// CHECK-NEXT: store i32 [[TMP3]], ptr [[ATOMIC_TEMP]], align 4252// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4253// CHECK-NEXT: ret i32 [[TMP4]]254//255int test_atomic_sub_fetch(int *p) {256 return __atomic_sub_fetch(p, 55, memory_order_seq_cst);257}258 259// CHECK-LABEL: define dso_local i32 @test_atomic_and_fetch(260// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {261// CHECK-NEXT: entry:262// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4263// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4264// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4265// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4266// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4267// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4268// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4269// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw and ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4270// CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[TMP1]]271// CHECK-NEXT: store i32 [[TMP3]], ptr [[ATOMIC_TEMP]], align 4272// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4273// CHECK-NEXT: ret i32 [[TMP4]]274//275int test_atomic_and_fetch(int *p) {276 return __atomic_and_fetch(p, 55, memory_order_seq_cst);277}278 279// CHECK-LABEL: define dso_local i32 @test_atomic_or_fetch(280// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {281// CHECK-NEXT: entry:282// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4283// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4284// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4285// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4286// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4287// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4288// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4289// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw or ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4290// CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[TMP1]]291// CHECK-NEXT: store i32 [[TMP3]], ptr [[ATOMIC_TEMP]], align 4292// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4293// CHECK-NEXT: ret i32 [[TMP4]]294//295int test_atomic_or_fetch(int *p) {296 return __atomic_or_fetch(p, 55, memory_order_seq_cst);297}298 299// CHECK-LABEL: define dso_local i32 @test_atomic_xor_fetch(300// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {301// CHECK-NEXT: entry:302// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4303// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4304// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4305// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4306// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4307// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4308// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4309// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xor ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4310// CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], [[TMP1]]311// CHECK-NEXT: store i32 [[TMP3]], ptr [[ATOMIC_TEMP]], align 4312// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4313// CHECK-NEXT: ret i32 [[TMP4]]314//315int test_atomic_xor_fetch(int *p) {316 return __atomic_xor_fetch(p, 55, memory_order_seq_cst);317}318 319// CHECK-LABEL: define dso_local i32 @test_atomic_nand_fetch(320// CHECK-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {321// CHECK-NEXT: entry:322// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4323// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4324// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4325// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4326// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 4327// CHECK-NEXT: store i32 55, ptr [[DOTATOMICTMP]], align 4328// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 4329// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw nand ptr [[TMP0]], i32 [[TMP1]] seq_cst, align 4330// CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[TMP1]]331// CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], -1332// CHECK-NEXT: store i32 [[TMP4]], ptr [[ATOMIC_TEMP]], align 4333// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4334// CHECK-NEXT: ret i32 [[TMP5]]335//336int test_atomic_nand_fetch(int *p) {337 return __atomic_nand_fetch(p, 55, memory_order_seq_cst);338}339