361 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 %s -emit-llvm -o - -triple=aarch64-none-elf | FileCheck %s3// REQUIRES: aarch64-registered-target4 5#include <stdatomic.h>6 7// CHECK-LABEL: define dso_local void @clear_relaxed(8// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {9// CHECK-NEXT: [[ENTRY:.*:]]10// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 811// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 812// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 813// CHECK-NEXT: store atomic i8 0, ptr [[TMP0]] monotonic, align 114// CHECK-NEXT: ret void15//16void clear_relaxed(char *ptr) {17 __atomic_clear(ptr, memory_order_relaxed);18}19 20// CHECK-LABEL: define dso_local void @clear_seq_cst(21// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {22// CHECK-NEXT: [[ENTRY:.*:]]23// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 824// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 825// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 826// CHECK-NEXT: store atomic i8 0, ptr [[TMP0]] seq_cst, align 127// CHECK-NEXT: ret void28//29void clear_seq_cst(char *ptr) {30 __atomic_clear(ptr, memory_order_seq_cst);31}32 33// CHECK-LABEL: define dso_local void @clear_release(34// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {35// CHECK-NEXT: [[ENTRY:.*:]]36// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 837// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 838// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 839// CHECK-NEXT: store atomic i8 0, ptr [[TMP0]] release, align 140// CHECK-NEXT: ret void41//42void clear_release(char *ptr) {43 __atomic_clear(ptr, memory_order_release);44}45 46// CHECK-LABEL: define dso_local void @clear_dynamic(47// CHECK-SAME: ptr noundef [[PTR:%.*]], i32 noundef [[ORDER:%.*]]) #[[ATTR0]] {48// CHECK-NEXT: [[ENTRY:.*:]]49// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 850// CHECK-NEXT: [[ORDER_ADDR:%.*]] = alloca i32, align 451// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 852// CHECK-NEXT: store i32 [[ORDER]], ptr [[ORDER_ADDR]], align 453// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 854// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ORDER_ADDR]], align 455// CHECK-NEXT: switch i32 [[TMP1]], label %[[MONOTONIC:.*]] [56// CHECK-NEXT: i32 3, label %[[RELEASE:.*]]57// CHECK-NEXT: i32 5, label %[[SEQCST:.*]]58// CHECK-NEXT: ]59// CHECK: [[MONOTONIC]]:60// CHECK-NEXT: store atomic i8 0, ptr [[TMP0]] monotonic, align 161// CHECK-NEXT: br label %[[ATOMIC_CONTINUE:.*]]62// CHECK: [[RELEASE]]:63// CHECK-NEXT: store atomic i8 0, ptr [[TMP0]] release, align 164// CHECK-NEXT: br label %[[ATOMIC_CONTINUE]]65// CHECK: [[SEQCST]]:66// CHECK-NEXT: store atomic i8 0, ptr [[TMP0]] seq_cst, align 167// CHECK-NEXT: br label %[[ATOMIC_CONTINUE]]68// CHECK: [[ATOMIC_CONTINUE]]:69// CHECK-NEXT: ret void70//71void clear_dynamic(char *ptr, int order) {72 __atomic_clear(ptr, order);73}74 75// CHECK-LABEL: define dso_local void @test_and_set_relaxed(76// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {77// CHECK-NEXT: [[ENTRY:.*:]]78// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 879// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 180// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 881// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 882// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 monotonic, align 183// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP1]], 084// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i885// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 186// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 187// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i188// CHECK-NEXT: ret void89//90void test_and_set_relaxed(char *ptr) {91 __atomic_test_and_set(ptr, memory_order_relaxed);92}93 94// CHECK-LABEL: define dso_local void @test_and_set_consume(95// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {96// CHECK-NEXT: [[ENTRY:.*:]]97// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 898// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 199// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8100// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8101// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 acquire, align 1102// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP1]], 0103// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i8104// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 1105// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 1106// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i1107// CHECK-NEXT: ret void108//109void test_and_set_consume(char *ptr) {110 __atomic_test_and_set(ptr, memory_order_consume);111}112 113// CHECK-LABEL: define dso_local void @test_and_set_acquire(114// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {115// CHECK-NEXT: [[ENTRY:.*:]]116// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8117// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1118// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8119// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8120// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 acquire, align 1121// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP1]], 0122// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i8123// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 1124// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 1125// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i1126// CHECK-NEXT: ret void127//128void test_and_set_acquire(char *ptr) {129 __atomic_test_and_set(ptr, memory_order_acquire);130}131 132// CHECK-LABEL: define dso_local void @test_and_set_release(133// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {134// CHECK-NEXT: [[ENTRY:.*:]]135// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8136// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1137// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8138// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8139// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 release, align 1140// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP1]], 0141// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i8142// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 1143// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 1144// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i1145// CHECK-NEXT: ret void146//147void test_and_set_release(char *ptr) {148 __atomic_test_and_set(ptr, memory_order_release);149}150 151// CHECK-LABEL: define dso_local void @test_and_set_acq_rel(152// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {153// CHECK-NEXT: [[ENTRY:.*:]]154// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8155// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1156// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8157// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8158// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 acq_rel, align 1159// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP1]], 0160// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i8161// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 1162// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 1163// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i1164// CHECK-NEXT: ret void165//166void test_and_set_acq_rel(char *ptr) {167 __atomic_test_and_set(ptr, memory_order_acq_rel);168}169 170// CHECK-LABEL: define dso_local void @test_and_set_seq_cst(171// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {172// CHECK-NEXT: [[ENTRY:.*:]]173// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8174// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1175// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8176// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8177// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 seq_cst, align 1178// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP1]], 0179// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i8180// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 1181// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 1182// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i1183// CHECK-NEXT: ret void184//185void test_and_set_seq_cst(char *ptr) {186 __atomic_test_and_set(ptr, memory_order_seq_cst);187}188 189// CHECK-LABEL: define dso_local void @test_and_set_dynamic(190// CHECK-SAME: ptr noundef [[PTR:%.*]], i32 noundef [[ORDER:%.*]]) #[[ATTR0]] {191// CHECK-NEXT: [[ENTRY:.*:]]192// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8193// CHECK-NEXT: [[ORDER_ADDR:%.*]] = alloca i32, align 4194// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1195// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8196// CHECK-NEXT: store i32 [[ORDER]], ptr [[ORDER_ADDR]], align 4197// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8198// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ORDER_ADDR]], align 4199// CHECK-NEXT: switch i32 [[TMP1]], label %[[MONOTONIC:.*]] [200// CHECK-NEXT: i32 1, label %[[ACQUIRE:.*]]201// CHECK-NEXT: i32 2, label %[[ACQUIRE]]202// CHECK-NEXT: i32 3, label %[[RELEASE:.*]]203// CHECK-NEXT: i32 4, label %[[ACQREL:.*]]204// CHECK-NEXT: i32 5, label %[[SEQCST:.*]]205// CHECK-NEXT: ]206// CHECK: [[MONOTONIC]]:207// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 monotonic, align 1208// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP2]], 0209// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i8210// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 1211// CHECK-NEXT: br label %[[ATOMIC_CONTINUE:.*]]212// CHECK: [[ACQUIRE]]:213// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 acquire, align 1214// CHECK-NEXT: [[TOBOOL1:%.*]] = icmp ne i8 [[TMP3]], 0215// CHECK-NEXT: [[TOBOOL_ZEXT1:%.*]] = zext i1 [[TOBOOL1]] to i8216// CHECK-NEXT: store i8 [[TOBOOL_ZEXT1]], ptr [[ATOMIC_TEMP]], align 1217// CHECK-NEXT: br label %[[ATOMIC_CONTINUE]]218// CHECK: [[RELEASE]]:219// CHECK-NEXT: [[TMP4:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 release, align 1220// CHECK-NEXT: [[TOBOOL2:%.*]] = icmp ne i8 [[TMP4]], 0221// CHECK-NEXT: [[TOBOOL_ZEXT2:%.*]] = zext i1 [[TOBOOL2]] to i8222// CHECK-NEXT: store i8 [[TOBOOL_ZEXT2]], ptr [[ATOMIC_TEMP]], align 1223// CHECK-NEXT: br label %[[ATOMIC_CONTINUE]]224// CHECK: [[ACQREL]]:225// CHECK-NEXT: [[TMP5:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 acq_rel, align 1226// CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i8 [[TMP5]], 0227// CHECK-NEXT: [[TOBOOL_ZEXT3:%.*]] = zext i1 [[TOBOOL3]] to i8228// CHECK-NEXT: store i8 [[TOBOOL_ZEXT3]], ptr [[ATOMIC_TEMP]], align 1229// CHECK-NEXT: br label %[[ATOMIC_CONTINUE]]230// CHECK: [[SEQCST]]:231// CHECK-NEXT: [[TMP6:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 seq_cst, align 1232// CHECK-NEXT: [[TOBOOL4:%.*]] = icmp ne i8 [[TMP6]], 0233// CHECK-NEXT: [[TOBOOL_ZEXT4:%.*]] = zext i1 [[TOBOOL4]] to i8234// CHECK-NEXT: store i8 [[TOBOOL_ZEXT4]], ptr [[ATOMIC_TEMP]], align 1235// CHECK-NEXT: br label %[[ATOMIC_CONTINUE]]236// CHECK: [[ATOMIC_CONTINUE]]:237// CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 1238// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1239// CHECK-NEXT: ret void240//241void test_and_set_dynamic(char *ptr, int order) {242 __atomic_test_and_set(ptr, order);243}244 245// CHECK-LABEL: define dso_local void @test_and_set_array(246// CHECK-SAME: ) #[[ATTR0]] {247// CHECK-NEXT: [[ENTRY:.*:]]248// CHECK-NEXT: [[X:%.*]] = alloca [10 x i32], align 4249// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1250// CHECK-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], ptr [[X]], i64 0, i64 0251// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw volatile xchg ptr [[ARRAYDECAY]], i8 1 seq_cst, align 4252// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP0]], 0253// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i8254// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 1255// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 1256// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i1257// CHECK-NEXT: ret void258//259void test_and_set_array() {260 volatile int x[10];261 __atomic_test_and_set(x, memory_order_seq_cst);262}263 264// These intrinsics accept any pointer type, including void and incomplete265// structs, and always access the first byte regardless of the actual type266// size.267 268struct incomplete;269 270// CHECK-LABEL: define dso_local void @clear_int(271// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {272// CHECK-NEXT: [[ENTRY:.*:]]273// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8274// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8275// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8276// CHECK-NEXT: store atomic i8 0, ptr [[TMP0]] monotonic, align 4277// CHECK-NEXT: ret void278//279void clear_int(int *ptr) {280 __atomic_clear(ptr, memory_order_relaxed);281}282// CHECK-LABEL: define dso_local void @clear_void(283// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {284// CHECK-NEXT: [[ENTRY:.*:]]285// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8286// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8287// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8288// CHECK-NEXT: store atomic i8 0, ptr [[TMP0]] monotonic, align 1289// CHECK-NEXT: ret void290//291void clear_void(void *ptr) {292 __atomic_clear(ptr, memory_order_relaxed);293}294// CHECK-LABEL: define dso_local void @clear_incomplete(295// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {296// CHECK-NEXT: [[ENTRY:.*:]]297// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8298// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8299// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8300// CHECK-NEXT: store atomic i8 0, ptr [[TMP0]] monotonic, align 1301// CHECK-NEXT: ret void302//303void clear_incomplete(struct incomplete *ptr) {304 __atomic_clear(ptr, memory_order_relaxed);305}306 307// CHECK-LABEL: define dso_local void @test_and_set_int(308// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {309// CHECK-NEXT: [[ENTRY:.*:]]310// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8311// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1312// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8313// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8314// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 monotonic, align 4315// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP1]], 0316// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i8317// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 1318// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 1319// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i1320// CHECK-NEXT: ret void321//322void test_and_set_int(int *ptr) {323 __atomic_test_and_set(ptr, memory_order_relaxed);324}325// CHECK-LABEL: define dso_local void @test_and_set_void(326// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {327// CHECK-NEXT: [[ENTRY:.*:]]328// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8329// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1330// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8331// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8332// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 monotonic, align 1333// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP1]], 0334// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i8335// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 1336// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 1337// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i1338// CHECK-NEXT: ret void339//340void test_and_set_void(void *ptr) {341 __atomic_test_and_set(ptr, memory_order_relaxed);342}343// CHECK-LABEL: define dso_local void @test_and_set_incomplete(344// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {345// CHECK-NEXT: [[ENTRY:.*:]]346// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8347// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1348// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8349// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8350// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[TMP0]], i8 1 monotonic, align 1351// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP1]], 0352// CHECK-NEXT: [[TOBOOL_ZEXT:%.*]] = zext i1 [[TOBOOL]] to i8353// CHECK-NEXT: store i8 [[TOBOOL_ZEXT]], ptr [[ATOMIC_TEMP]], align 1354// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ATOMIC_TEMP]], align 1355// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP2]] to i1356// CHECK-NEXT: ret void357//358void test_and_set_incomplete(struct incomplete *ptr) {359 __atomic_test_and_set(ptr, memory_order_relaxed);360}361