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1// RUN: %clang_cc1 -triple arm-linux-gnueabi -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM2// RUN: %clang_cc1 -triple powerpc-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC323// RUN: %clang_cc1 -triple powerpc64-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC644// RUN: %clang_cc1 -triple mipsel-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS325// RUN: %clang_cc1 -triple mipsisa32r6el-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS326// RUN: %clang_cc1 -triple mips64el-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS647// RUN: %clang_cc1 -triple mips64el-linux-gnuabi64 -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS648// RUN: %clang_cc1 -triple mipsisa64r6el-linux-gnuabi64 -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS649// RUN: %clang_cc1 -triple sparc-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARCV8 -check-prefix=SPARC10// RUN: %clang_cc1 -triple sparcv9-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARCV9 -check-prefix=SPARC11// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -emit-llvm %s -o - | FileCheck %s -check-prefix=NVPTX12 13unsigned char c1, c2;14unsigned short s1, s2;15unsigned int i1, i2;16unsigned long long ll1, ll2;17unsigned char a1[100], a2[100];18 19enum memory_order {20 memory_order_relaxed,21 memory_order_consume,22 memory_order_acquire,23 memory_order_release,24 memory_order_acq_rel,25 memory_order_seq_cst26};27 28void test1(void) {29 (void)__atomic_load(&c1, &c2, memory_order_seq_cst);30 (void)__atomic_store(&c1, &c2, memory_order_seq_cst);31 (void)__atomic_load(&s1, &s2, memory_order_seq_cst);32 (void)__atomic_store(&s1, &s2, memory_order_seq_cst);33 (void)__atomic_load(&i1, &i2, memory_order_seq_cst);34 (void)__atomic_store(&i1, &i2, memory_order_seq_cst);35 (void)__atomic_load(&ll1, &ll2, memory_order_seq_cst);36 (void)__atomic_store(&ll1, &ll2, memory_order_seq_cst);37 (void)__atomic_load(&a1, &a2, memory_order_seq_cst);38 (void)__atomic_store(&a1, &a2, memory_order_seq_cst);39 40// ARM-LABEL: define{{.*}} void @test141// ARM: = load atomic i8, ptr @c1 seq_cst, align 142// ARM: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 143// ARM: = load atomic i16, ptr @s1 seq_cst, align 244// ARM: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 245// ARM: = load atomic i32, ptr @i1 seq_cst, align 446// ARM: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 447// ARM: = load atomic i64, ptr @ll1 seq_cst, align 848// ARM: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 849// ARM: call{{.*}} void @__atomic_load(i32 noundef 100, ptr noundef @a1, ptr noundef @a250// ARM: call{{.*}} void @__atomic_store(i32 noundef 100, ptr noundef @a1, ptr noundef @a251 52// PPC32-LABEL: define{{.*}} void @test153// PPC32: = load atomic i8, ptr @c1 seq_cst, align 154// PPC32: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 155// PPC32: = load atomic i16, ptr @s1 seq_cst, align 256// PPC32: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 257// PPC32: = load atomic i32, ptr @i1 seq_cst, align 458// PPC32: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 459// PPC32: = load atomic i64, ptr @ll1 seq_cst, align 860// PPC32: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 861// PPC32: call void @__atomic_load(i32 noundef 100, ptr noundef @a1, ptr noundef @a262// PPC32: call void @__atomic_store(i32 noundef 100, ptr noundef @a1, ptr noundef @a263 64// PPC64-LABEL: define{{.*}} void @test165// PPC64: = load atomic i8, ptr @c1 seq_cst, align 166// PPC64: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 167// PPC64: = load atomic i16, ptr @s1 seq_cst, align 268// PPC64: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 269// PPC64: = load atomic i32, ptr @i1 seq_cst, align 470// PPC64: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 471// PPC64: = load atomic i64, ptr @ll1 seq_cst, align 872// PPC64: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 873// PPC64: call void @__atomic_load(i64 noundef 100, ptr noundef @a1, ptr noundef @a274// PPC64: call void @__atomic_store(i64 noundef 100, ptr noundef @a1, ptr noundef @a275 76// MIPS32-LABEL: define{{.*}} void @test177// MIPS32: = load atomic i8, ptr @c1 seq_cst, align 178// MIPS32: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 179// MIPS32: = load atomic i16, ptr @s1 seq_cst, align 280// MIPS32: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 281// MIPS32: = load atomic i32, ptr @i1 seq_cst, align 482// MIPS32: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 483// MIPS32: = load atomic i64, ptr @ll1 seq_cst, align 884// MIPS32: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 885// MIPS32: call void @__atomic_load(i32 noundef signext 100, ptr noundef @a1, ptr noundef @a286// MIPS32: call void @__atomic_store(i32 noundef signext 100, ptr noundef @a1, ptr noundef @a287 88// MIPS64-LABEL: define{{.*}} void @test189// MIPS64: = load atomic i8, ptr @c1 seq_cst, align 190// MIPS64: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 191// MIPS64: = load atomic i16, ptr @s1 seq_cst, align 292// MIPS64: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 293// MIPS64: = load atomic i32, ptr @i1 seq_cst, align 494// MIPS64: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 495// MIPS64: = load atomic i64, ptr @ll1 seq_cst, align 896// MIPS64: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 897// MIPS64: call void @__atomic_load(i64 noundef zeroext 100, ptr noundef @a1, ptr noundef @a298// MIPS64: call void @__atomic_store(i64 noundef zeroext 100, ptr noundef @a1, ptr noundef @a299 100// SPARC-LABEL: define{{.*}} void @test1101// SPARC: = load atomic i8, ptr @c1 seq_cst, align 1102// SPARC: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1103// SPARC: = load atomic i16, ptr @s1 seq_cst, align 2104// SPARC: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2105// SPARC: = load atomic i32, ptr @i1 seq_cst, align 4106// SPARC: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4107// SPARC: load atomic i64, ptr @ll1 seq_cst, align 8108// SPARC: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8109// SPARCV8: call void @__atomic_load(i32 noundef 100, ptr noundef @a1, ptr noundef @a2110// SPARCV8: call void @__atomic_store(i32 noundef 100, ptr noundef @a1, ptr noundef @a2111// SPARCV9: call void @__atomic_load(i64 noundef 100, ptr noundef @a1, ptr noundef @a2112// SPARCV9: call void @__atomic_store(i64 noundef 100, ptr noundef @a1, ptr noundef @a2113 114// NVPTX-LABEL: define{{.*}} void @test1115// NVPTX: = load atomic i8, ptr @c1 seq_cst, align 1116// NVPTX: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1117// NVPTX: = load atomic i16, ptr @s1 seq_cst, align 2118// NVPTX: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2119// NVPTX: = load atomic i32, ptr @i1 seq_cst, align 4120// NVPTX: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4121// NVPTX: = load atomic i64, ptr @ll1 seq_cst, align 8122// NVPTX: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8123// NVPTX: call void @__atomic_load(i64 noundef 100, ptr noundef @a1, ptr noundef @a2124// NVPTX: call void @__atomic_store(i64 noundef 100, ptr noundef @a1, ptr noundef @a2125 126}127