296 lines · c
1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 52// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s3 4typedef int v8i __attribute__((ext_vector_type(8)));5typedef _Bool v8b __attribute__((ext_vector_type(8)));6 7// CHECK-LABEL: define dso_local <8 x i32> @test_load(8// CHECK-SAME: i8 noundef [[M_COERCE:%.*]], ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] {9// CHECK-NEXT: [[ENTRY:.*:]]10// CHECK-NEXT: [[M:%.*]] = alloca i8, align 111// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i8, align 112// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 813// CHECK-NEXT: store i8 [[M_COERCE]], ptr [[M]], align 114// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[M]], align 115// CHECK-NEXT: [[M1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>16// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i1> [[M1]] to i817// CHECK-NEXT: store i8 [[TMP0]], ptr [[M_ADDR]], align 118// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 819// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[M_ADDR]], align 120// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>21// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[P_ADDR]], align 822// CHECK-NEXT: [[MASKED_LOAD:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr align 4 [[TMP2]], <8 x i1> [[TMP1]], <8 x i32> poison)23// CHECK-NEXT: ret <8 x i32> [[MASKED_LOAD]]24//25v8i test_load(v8b m, int *p) {26 return __builtin_masked_load(m, p);27}28 29// CHECK-LABEL: define dso_local <8 x i32> @test_load_passthru(30// CHECK-SAME: i8 noundef [[M_COERCE:%.*]], ptr noundef [[P:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP0:%.*]]) #[[ATTR0]] {31// CHECK-NEXT: [[ENTRY:.*:]]32// CHECK-NEXT: [[M:%.*]] = alloca i8, align 133// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i8, align 134// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 835// CHECK-NEXT: [[T_ADDR:%.*]] = alloca <8 x i32>, align 3236// CHECK-NEXT: store i8 [[M_COERCE]], ptr [[M]], align 137// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[M]], align 138// CHECK-NEXT: [[M1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>39// CHECK-NEXT: [[T:%.*]] = load <8 x i32>, ptr [[TMP0]], align 3240// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[M1]] to i841// CHECK-NEXT: store i8 [[TMP1]], ptr [[M_ADDR]], align 142// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 843// CHECK-NEXT: store <8 x i32> [[T]], ptr [[T_ADDR]], align 3244// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[M_ADDR]], align 145// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>46// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[P_ADDR]], align 847// CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr [[T_ADDR]], align 3248// CHECK-NEXT: [[MASKED_LOAD:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr align 4 [[TMP3]], <8 x i1> [[TMP2]], <8 x i32> [[TMP4]])49// CHECK-NEXT: ret <8 x i32> [[MASKED_LOAD]]50//51v8i test_load_passthru(v8b m, int *p, v8i t) {52 return __builtin_masked_load(m, p, t);53}54 55// CHECK-LABEL: define dso_local <8 x i32> @test_load_expand(56// CHECK-SAME: i8 noundef [[M_COERCE:%.*]], ptr noundef [[P:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP0:%.*]]) #[[ATTR0]] {57// CHECK-NEXT: [[ENTRY:.*:]]58// CHECK-NEXT: [[M:%.*]] = alloca i8, align 159// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i8, align 160// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 861// CHECK-NEXT: [[T_ADDR:%.*]] = alloca <8 x i32>, align 3262// CHECK-NEXT: store i8 [[M_COERCE]], ptr [[M]], align 163// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[M]], align 164// CHECK-NEXT: [[M1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>65// CHECK-NEXT: [[T:%.*]] = load <8 x i32>, ptr [[TMP0]], align 3266// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[M1]] to i867// CHECK-NEXT: store i8 [[TMP1]], ptr [[M_ADDR]], align 168// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 869// CHECK-NEXT: store <8 x i32> [[T]], ptr [[T_ADDR]], align 3270// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[M_ADDR]], align 171// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>72// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[P_ADDR]], align 873// CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr [[T_ADDR]], align 3274// CHECK-NEXT: [[MASKED_EXPAND_LOAD:%.*]] = call <8 x i32> @llvm.masked.expandload.v8i32(ptr [[TMP3]], <8 x i1> [[TMP2]], <8 x i32> [[TMP4]])75// CHECK-NEXT: ret <8 x i32> [[MASKED_EXPAND_LOAD]]76//77v8i test_load_expand(v8b m, int *p, v8i t) {78 return __builtin_masked_expand_load(m, p, t);79}80 81// CHECK-LABEL: define dso_local void @test_store(82// CHECK-SAME: i8 noundef [[M_COERCE:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP0:%.*]], ptr noundef [[P:%.*]]) #[[ATTR3:[0-9]+]] {83// CHECK-NEXT: [[ENTRY:.*:]]84// CHECK-NEXT: [[M:%.*]] = alloca i8, align 185// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i8, align 186// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <8 x i32>, align 3287// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 888// CHECK-NEXT: store i8 [[M_COERCE]], ptr [[M]], align 189// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[M]], align 190// CHECK-NEXT: [[M1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>91// CHECK-NEXT: [[V:%.*]] = load <8 x i32>, ptr [[TMP0]], align 3292// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[M1]] to i893// CHECK-NEXT: store i8 [[TMP1]], ptr [[M_ADDR]], align 194// CHECK-NEXT: store <8 x i32> [[V]], ptr [[V_ADDR]], align 3295// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 896// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[M_ADDR]], align 197// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>98// CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr [[V_ADDR]], align 3299// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[P_ADDR]], align 8100// CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> [[TMP3]], ptr align 4 [[TMP4]], <8 x i1> [[TMP2]])101// CHECK-NEXT: ret void102//103void test_store(v8b m, v8i v, int *p) {104 __builtin_masked_store(m, v, p);105}106 107// CHECK-LABEL: define dso_local void @test_compress_store(108// CHECK-SAME: i8 noundef [[M_COERCE:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP0:%.*]], ptr noundef [[P:%.*]]) #[[ATTR3]] {109// CHECK-NEXT: [[ENTRY:.*:]]110// CHECK-NEXT: [[M:%.*]] = alloca i8, align 1111// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i8, align 1112// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <8 x i32>, align 32113// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8114// CHECK-NEXT: store i8 [[M_COERCE]], ptr [[M]], align 1115// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[M]], align 1116// CHECK-NEXT: [[M1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>117// CHECK-NEXT: [[V:%.*]] = load <8 x i32>, ptr [[TMP0]], align 32118// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[M1]] to i8119// CHECK-NEXT: store i8 [[TMP1]], ptr [[M_ADDR]], align 1120// CHECK-NEXT: store <8 x i32> [[V]], ptr [[V_ADDR]], align 32121// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8122// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[M_ADDR]], align 1123// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>124// CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr [[V_ADDR]], align 32125// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[P_ADDR]], align 8126// CHECK-NEXT: call void @llvm.masked.compressstore.v8i32(<8 x i32> [[TMP3]], ptr [[TMP4]], <8 x i1> [[TMP2]])127// CHECK-NEXT: ret void128//129void test_compress_store(v8b m, v8i v, int *p) {130 __builtin_masked_compress_store(m, v, p);131}132 133// CHECK-LABEL: define dso_local <8 x i32> @test_gather(134// CHECK-SAME: i8 noundef [[MASK_COERCE:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP0:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {135// CHECK-NEXT: [[ENTRY:.*:]]136// CHECK-NEXT: [[MASK:%.*]] = alloca i8, align 1137// CHECK-NEXT: [[MASK_ADDR:%.*]] = alloca i8, align 1138// CHECK-NEXT: [[IDX_ADDR:%.*]] = alloca <8 x i32>, align 32139// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8140// CHECK-NEXT: store i8 [[MASK_COERCE]], ptr [[MASK]], align 1141// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[MASK]], align 1142// CHECK-NEXT: [[MASK1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>143// CHECK-NEXT: [[IDX:%.*]] = load <8 x i32>, ptr [[TMP0]], align 32144// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[MASK1]] to i8145// CHECK-NEXT: store i8 [[TMP1]], ptr [[MASK_ADDR]], align 1146// CHECK-NEXT: store <8 x i32> [[IDX]], ptr [[IDX_ADDR]], align 32147// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8148// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[MASK_ADDR]], align 1149// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>150// CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr [[IDX_ADDR]], align 32151// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8152// CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], <8 x i32> [[TMP3]]153// CHECK-NEXT: [[MASKED_GATHER:%.*]] = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> align 4 [[TMP5]], <8 x i1> [[TMP2]], <8 x i32> poison)154// CHECK-NEXT: ret <8 x i32> [[MASKED_GATHER]]155//156v8i test_gather(v8b mask, v8i idx, int *ptr) {157 return __builtin_masked_gather(mask, idx, ptr);158}159 160// CHECK-LABEL: define dso_local void @test_scatter(161// CHECK-SAME: i8 noundef [[MASK_COERCE:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP0:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP1:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR3]] {162// CHECK-NEXT: [[ENTRY:.*:]]163// CHECK-NEXT: [[MASK:%.*]] = alloca i8, align 1164// CHECK-NEXT: [[MASK_ADDR:%.*]] = alloca i8, align 1165// CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca <8 x i32>, align 32166// CHECK-NEXT: [[IDX_ADDR:%.*]] = alloca <8 x i32>, align 32167// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8168// CHECK-NEXT: store i8 [[MASK_COERCE]], ptr [[MASK]], align 1169// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[MASK]], align 1170// CHECK-NEXT: [[MASK1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>171// CHECK-NEXT: [[VAL:%.*]] = load <8 x i32>, ptr [[TMP0]], align 32172// CHECK-NEXT: [[IDX:%.*]] = load <8 x i32>, ptr [[TMP1]], align 32173// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i1> [[MASK1]] to i8174// CHECK-NEXT: store i8 [[TMP2]], ptr [[MASK_ADDR]], align 1175// CHECK-NEXT: store <8 x i32> [[VAL]], ptr [[VAL_ADDR]], align 32176// CHECK-NEXT: store <8 x i32> [[IDX]], ptr [[IDX_ADDR]], align 32177// CHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8178// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[MASK_ADDR]], align 1179// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>180// CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr [[VAL_ADDR]], align 32181// CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr [[IDX_ADDR]], align 32182// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8183// CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], <8 x i32> [[TMP4]]184// CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[TMP5]], <8 x ptr> align 4 [[TMP7]], <8 x i1> [[TMP3]])185// CHECK-NEXT: ret void186//187void test_scatter(v8b mask, v8i val, v8i idx, int *ptr) {188 __builtin_masked_scatter(mask, val, idx, ptr);189}190 191// CHECK-LABEL: define dso_local <8 x i32> @test_load_as(192// CHECK-SAME: i8 noundef [[MASK_COERCE:%.*]], ptr addrspace(42) noundef [[PTR:%.*]]) #[[ATTR0]] {193// CHECK-NEXT: [[ENTRY:.*:]]194// CHECK-NEXT: [[MASK:%.*]] = alloca i8, align 1195// CHECK-NEXT: [[MASK_ADDR:%.*]] = alloca i8, align 1196// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr addrspace(42), align 8197// CHECK-NEXT: store i8 [[MASK_COERCE]], ptr [[MASK]], align 1198// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[MASK]], align 1199// CHECK-NEXT: [[MASK1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>200// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i1> [[MASK1]] to i8201// CHECK-NEXT: store i8 [[TMP0]], ptr [[MASK_ADDR]], align 1202// CHECK-NEXT: store ptr addrspace(42) [[PTR]], ptr [[PTR_ADDR]], align 8203// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[MASK_ADDR]], align 1204// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>205// CHECK-NEXT: [[TMP2:%.*]] = load ptr addrspace(42), ptr [[PTR_ADDR]], align 8206// CHECK-NEXT: [[MASKED_LOAD:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p42(ptr addrspace(42) align 4 [[TMP2]], <8 x i1> [[TMP1]], <8 x i32> poison)207// CHECK-NEXT: ret <8 x i32> [[MASKED_LOAD]]208//209v8i test_load_as(v8b mask, int __attribute__((address_space(42))) * ptr) {210 return __builtin_masked_load(mask, ptr);211}212 213// CHECK-LABEL: define dso_local void @test_store_as(214// CHECK-SAME: i8 noundef [[M_COERCE:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP0:%.*]], ptr addrspace(42) noundef [[P:%.*]]) #[[ATTR3]] {215// CHECK-NEXT: [[ENTRY:.*:]]216// CHECK-NEXT: [[M:%.*]] = alloca i8, align 1217// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i8, align 1218// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <8 x i32>, align 32219// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(42), align 8220// CHECK-NEXT: store i8 [[M_COERCE]], ptr [[M]], align 1221// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[M]], align 1222// CHECK-NEXT: [[M1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>223// CHECK-NEXT: [[V:%.*]] = load <8 x i32>, ptr [[TMP0]], align 32224// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[M1]] to i8225// CHECK-NEXT: store i8 [[TMP1]], ptr [[M_ADDR]], align 1226// CHECK-NEXT: store <8 x i32> [[V]], ptr [[V_ADDR]], align 32227// CHECK-NEXT: store ptr addrspace(42) [[P]], ptr [[P_ADDR]], align 8228// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[M_ADDR]], align 1229// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>230// CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr [[V_ADDR]], align 32231// CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(42), ptr [[P_ADDR]], align 8232// CHECK-NEXT: call void @llvm.masked.store.v8i32.p42(<8 x i32> [[TMP3]], ptr addrspace(42) align 4 [[TMP4]], <8 x i1> [[TMP2]])233// CHECK-NEXT: ret void234//235void test_store_as(v8b m, v8i v, int __attribute__((address_space(42))) *p) {236 __builtin_masked_store(m, v, p);237}238 239// CHECK-LABEL: define dso_local <8 x i32> @test_gather_as(240// CHECK-SAME: i8 noundef [[MASK_COERCE:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP0:%.*]], ptr addrspace(42) noundef [[PTR:%.*]]) #[[ATTR0]] {241// CHECK-NEXT: [[ENTRY:.*:]]242// CHECK-NEXT: [[MASK:%.*]] = alloca i8, align 1243// CHECK-NEXT: [[MASK_ADDR:%.*]] = alloca i8, align 1244// CHECK-NEXT: [[IDX_ADDR:%.*]] = alloca <8 x i32>, align 32245// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr addrspace(42), align 8246// CHECK-NEXT: store i8 [[MASK_COERCE]], ptr [[MASK]], align 1247// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[MASK]], align 1248// CHECK-NEXT: [[MASK1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>249// CHECK-NEXT: [[IDX:%.*]] = load <8 x i32>, ptr [[TMP0]], align 32250// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[MASK1]] to i8251// CHECK-NEXT: store i8 [[TMP1]], ptr [[MASK_ADDR]], align 1252// CHECK-NEXT: store <8 x i32> [[IDX]], ptr [[IDX_ADDR]], align 32253// CHECK-NEXT: store ptr addrspace(42) [[PTR]], ptr [[PTR_ADDR]], align 8254// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[MASK_ADDR]], align 1255// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>256// CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr [[IDX_ADDR]], align 32257// CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(42), ptr [[PTR_ADDR]], align 8258// CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr addrspace(42) [[TMP4]], <8 x i32> [[TMP3]]259// CHECK-NEXT: [[MASKED_GATHER:%.*]] = call <8 x i32> @llvm.masked.gather.v8i32.v8p42(<8 x ptr addrspace(42)> align 4 [[TMP5]], <8 x i1> [[TMP2]], <8 x i32> poison)260// CHECK-NEXT: ret <8 x i32> [[MASKED_GATHER]]261//262v8i test_gather_as(v8b mask, v8i idx, int __attribute__((address_space(42))) *ptr) {263 return __builtin_masked_gather(mask, idx, ptr);264}265 266// CHECK-LABEL: define dso_local void @test_scatter_as(267// CHECK-SAME: i8 noundef [[MASK_COERCE:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP0:%.*]], ptr noundef byval(<8 x i32>) align 32 [[TMP1:%.*]], ptr addrspace(42) noundef [[PTR:%.*]]) #[[ATTR3]] {268// CHECK-NEXT: [[ENTRY:.*:]]269// CHECK-NEXT: [[MASK:%.*]] = alloca i8, align 1270// CHECK-NEXT: [[MASK_ADDR:%.*]] = alloca i8, align 1271// CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca <8 x i32>, align 32272// CHECK-NEXT: [[IDX_ADDR:%.*]] = alloca <8 x i32>, align 32273// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr addrspace(42), align 8274// CHECK-NEXT: store i8 [[MASK_COERCE]], ptr [[MASK]], align 1275// CHECK-NEXT: [[LOAD_BITS:%.*]] = load i8, ptr [[MASK]], align 1276// CHECK-NEXT: [[MASK1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>277// CHECK-NEXT: [[VAL:%.*]] = load <8 x i32>, ptr [[TMP0]], align 32278// CHECK-NEXT: [[IDX:%.*]] = load <8 x i32>, ptr [[TMP1]], align 32279// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i1> [[MASK1]] to i8280// CHECK-NEXT: store i8 [[TMP2]], ptr [[MASK_ADDR]], align 1281// CHECK-NEXT: store <8 x i32> [[VAL]], ptr [[VAL_ADDR]], align 32282// CHECK-NEXT: store <8 x i32> [[IDX]], ptr [[IDX_ADDR]], align 32283// CHECK-NEXT: store ptr addrspace(42) [[PTR]], ptr [[PTR_ADDR]], align 8284// CHECK-NEXT: [[LOAD_BITS2:%.*]] = load i8, ptr [[MASK_ADDR]], align 1285// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8 [[LOAD_BITS2]] to <8 x i1>286// CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr [[VAL_ADDR]], align 32287// CHECK-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr [[IDX_ADDR]], align 32288// CHECK-NEXT: [[TMP6:%.*]] = load ptr addrspace(42), ptr [[PTR_ADDR]], align 8289// CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr addrspace(42) [[TMP6]], <8 x i32> [[TMP4]]290// CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p42(<8 x i32> [[TMP5]], <8 x ptr addrspace(42)> align 4 [[TMP7]], <8 x i1> [[TMP3]])291// CHECK-NEXT: ret void292//293void test_scatter_as(v8b mask, v8i val, v8i idx, int __attribute__((address_space(42))) *ptr) {294 __builtin_masked_scatter(mask, val, idx, ptr);295}296