128 lines · c
1// RUN: %clang_cc1 -O1 -triple x86_64 %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=CHECK %s2 3// REQUIRES: aarch64-registered-target4// RUN: %clang_cc1 -O1 -triple aarch64 -target-feature +neon %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=CHECK,NEON %s5 6// REQUIRES: aarch64-registered-target7// RUN: %clang_cc1 -O1 -triple aarch64 -target-feature +sve %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=CHECK,SVE %s8 9// REQUIRES: riscv-registered-target10// RUN: %clang_cc1 -O1 -triple riscv64 -target-feature +v %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=CHECK,RISCV %s11 12/// Note that this does not make sense to check for x86 SIMD types, because13/// __m128i, __m256i, and __m512i do not specify the element type. There are no14/// "logical" number of elements in them.15 16typedef int int1 __attribute__((vector_size(4)));17typedef int int4 __attribute__((vector_size(16)));18typedef int int8 __attribute__((vector_size(32)));19typedef int int16 __attribute__((vector_size(64)));20typedef float float2 __attribute__((vector_size(8)));21typedef long extLong4 __attribute__((ext_vector_type(4)));22 23 24int test_builtin_vectorelements_int1() {25 // CHECK-LABEL: i32 @test_builtin_vectorelements_int1(26 // CHECK: ret i32 127 return __builtin_vectorelements(int1);28}29 30int test_builtin_vectorelements_int4() {31 // CHECK-LABEL: i32 @test_builtin_vectorelements_int4(32 // CHECK: ret i32 433 return __builtin_vectorelements(int4);34}35 36int test_builtin_vectorelements_int8() {37 // CHECK-LABEL: i32 @test_builtin_vectorelements_int8(38 // CHECK: ret i32 839 return __builtin_vectorelements(int8);40}41 42int test_builtin_vectorelements_int16() {43 // CHECK-LABEL: i32 @test_builtin_vectorelements_int16(44 // CHECK: ret i32 1645 return __builtin_vectorelements(int16);46}47 48int test_builtin_vectorelements_float2() {49 // CHECK-LABEL: i32 @test_builtin_vectorelements_float2(50 // CHECK: ret i32 251 return __builtin_vectorelements(float2);52}53 54int test_builtin_vectorelements_extLong4() {55 // CHECK-LABEL: i32 @test_builtin_vectorelements_extLong4(56 // CHECK: ret i32 457 return __builtin_vectorelements(extLong4);58}59 60int test_builtin_vectorelements_multiply_constant() {61 // CHECK-LABEL: i32 @test_builtin_vectorelements_multiply_constant(62 // CHECK: ret i32 3263 return __builtin_vectorelements(int16) * 2;64}65 66#if defined(__ARM_NEON)67#include <arm_neon.h>68 69int test_builtin_vectorelements_neon32x4() {70 // NEON: i32 @test_builtin_vectorelements_neon32x4(71 // NEON: ret i32 472 return __builtin_vectorelements(uint32x4_t);73}74 75int test_builtin_vectorelements_neon64x1() {76 // NEON: i32 @test_builtin_vectorelements_neon64x1(77 // NEON: ret i32 178 return __builtin_vectorelements(uint64x1_t);79}80#endif81 82#if defined(__ARM_FEATURE_SVE)83#include <arm_sve.h>84 85long test_builtin_vectorelements_sve32() {86 // SVE: i64 @test_builtin_vectorelements_sve32(87 // SVE: [[VSCALE:%.+]] = call i64 @llvm.vscale.i64()88 // SVE: [[RES:%.+]] = mul nuw i64 [[VSCALE]], 489 // SVE: ret i64 [[RES]]90 return __builtin_vectorelements(svuint32_t);91}92 93long test_builtin_vectorelements_sve8() {94 // SVE: i64 @test_builtin_vectorelements_sve8(95 // SVE: [[VSCALE:%.+]] = call i64 @llvm.vscale.i64()96 // SVE: [[RES:%.+]] = mul nuw i64 [[VSCALE]], 1697 // SVE: ret i64 [[RES]]98 return __builtin_vectorelements(svuint8_t);99}100#endif101 102#if defined(__riscv)103#include <riscv_vector.h>104 105long test_builtin_vectorelements_riscv8() {106 // RISCV: i64 @test_builtin_vectorelements_riscv8(107 // RISCV: [[VSCALE:%.+]] = call i64 @llvm.vscale.i64()108 // RISCV: [[RES:%.+]] = mul nuw i64 [[VSCALE]], 8109 // RISCV: ret i64 [[RES]]110 return __builtin_vectorelements(vuint8m1_t);111}112 113long test_builtin_vectorelements_riscv64() {114 // RISCV: i64 @test_builtin_vectorelements_riscv64(115 // RISCV: [[VSCALE:%.+]] = call i64 @llvm.vscale.i64()116 // RISCV: ret i64 [[VSCALE]]117 return __builtin_vectorelements(vuint64m1_t);118}119 120long test_builtin_vectorelements_riscv32m2() {121 // RISCV: i64 @test_builtin_vectorelements_riscv32m2(122 // RISCV: [[VSCALE:%.+]] = call i64 @llvm.vscale.i64()123 // RISCV: [[RES:%.+]] = mul nuw i64 [[VSCALE]], 4124 // RISCV: ret i64 [[RES]]125 return __builtin_vectorelements(vuint32m2_t);126}127#endif128