277 lines · c
1// RUN: %clang_cc1 -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s2 3#include <stdint.h>4 5void *f0(void)6{7 return __builtin_thread_pointer();8}9 10void f1(char *a, char *b) {11 // CHECK: call {{.*}} @__clear_cache12 __clear_cache(a,b);13}14 15float test_vcvtrf0(float f) {16 // CHECK: call float @llvm.arm.vcvtr.f32(float %f)17 return __builtin_arm_vcvtr_f(f, 0);18}19 20float test_vcvtrf1(float f) {21 // CHECK: call float @llvm.arm.vcvtru.f32(float %f)22 return __builtin_arm_vcvtr_f(f, 1);23}24 25double test_vcvtrd0(double d) {26 // CHECK: call float @llvm.arm.vcvtr.f64(double %d)27 return __builtin_arm_vcvtr_d(d, 0);28}29 30double test_vcvtrd1(double d) {31 // call float @llvm.arm.vcvtru.f64(double %d)32 return __builtin_arm_vcvtr_d(d, 1);33}34 35void test_eh_return_data_regno(void)36{37 // CHECK: store volatile i32 038 // CHECK: store volatile i32 139 volatile int res;40 res = __builtin_eh_return_data_regno(0);41 res = __builtin_eh_return_data_regno(1);42}43 44void nop(void) {45 // CHECK: call {{.*}} @llvm.arm.hint(i32 0)46 __builtin_arm_nop();47}48 49void yield(void) {50 // CHECK: call {{.*}} @llvm.arm.hint(i32 1)51 __builtin_arm_yield();52}53 54void wfe(void) {55 // CHECK: call {{.*}} @llvm.arm.hint(i32 2)56 __builtin_arm_wfe();57}58 59void wfi(void) {60 // CHECK: call {{.*}} @llvm.arm.hint(i32 3)61 __builtin_arm_wfi();62}63 64void sev(void) {65 // CHECK: call {{.*}} @llvm.arm.hint(i32 4)66 __builtin_arm_sev();67}68 69void sevl(void) {70 // CHECK: call {{.*}} @llvm.arm.hint(i32 5)71 __builtin_arm_sevl();72}73 74void dbg(void) {75 // CHECK: call {{.*}} @llvm.arm.dbg(i32 0)76 __builtin_arm_dbg(0);77}78 79void test_barrier(void) {80 //CHECK: call {{.*}} @llvm.arm.dmb(i32 1)81 //CHECK: call {{.*}} @llvm.arm.dsb(i32 2)82 //CHECK: call {{.*}} @llvm.arm.isb(i32 3)83 __builtin_arm_dmb(1);84 __builtin_arm_dsb(2);85 __builtin_arm_isb(3);86}87 88unsigned rbit(unsigned a) {89 // CHECK: call {{.*}} @llvm.bitreverse.i32(i32 %a)90 return __builtin_arm_rbit(a);91}92 93void prefetch(int i) {94 __builtin_arm_prefetch(&i, 0, 1);95 // CHECK: call {{.*}} @llvm.prefetch.p0(ptr %{{.*}}, i32 0, i32 3, i32 1)96 97 __builtin_arm_prefetch(&i, 1, 1);98 // CHECK: call {{.*}} @llvm.prefetch.p0(ptr %{{.*}}, i32 1, i32 3, i32 1)99 100 __builtin_arm_prefetch(&i, 1, 0);101 // CHECK: call {{.*}} @llvm.prefetch.p0(ptr %{{.*}}, i32 1, i32 3, i32 0)102}103 104void ldc(const void *i) {105 // CHECK: define{{.*}} void @ldc(ptr noundef %i)106 // CHECK: call void @llvm.arm.ldc(i32 1, i32 2, ptr %i)107 // CHECK-NEXT: ret void108 __builtin_arm_ldc(1, 2, i);109}110 111void ldcl(const void *i) {112 // CHECK: define{{.*}} void @ldcl(ptr noundef %i)113 // CHECK: call void @llvm.arm.ldcl(i32 1, i32 2, ptr %i)114 // CHECK-NEXT: ret void115 __builtin_arm_ldcl(1, 2, i);116}117 118void ldc2(const void *i) {119 // CHECK: define{{.*}} void @ldc2(ptr noundef %i)120 // CHECK: call void @llvm.arm.ldc2(i32 1, i32 2, ptr %i)121 // CHECK-NEXT: ret void122 __builtin_arm_ldc2(1, 2, i);123}124 125void ldc2l(const void *i) {126 // CHECK: define{{.*}} void @ldc2l(ptr noundef %i)127 // CHECK: call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %i)128 // CHECK-NEXT: ret void129 __builtin_arm_ldc2l(1, 2, i);130}131 132void stc(void *i) {133 // CHECK: define{{.*}} void @stc(ptr noundef %i)134 // CHECK: call void @llvm.arm.stc(i32 1, i32 2, ptr %i)135 // CHECK-NEXT: ret void136 __builtin_arm_stc(1, 2, i);137}138 139void stcl(void *i) {140 // CHECK: define{{.*}} void @stcl(ptr noundef %i)141 // CHECK: call void @llvm.arm.stcl(i32 1, i32 2, ptr %i)142 // CHECK-NEXT: ret void143 __builtin_arm_stcl(1, 2, i);144}145 146void stc2(void *i) {147 // CHECK: define{{.*}} void @stc2(ptr noundef %i)148 // CHECK: call void @llvm.arm.stc2(i32 1, i32 2, ptr %i)149 // CHECK-NEXT: ret void150 __builtin_arm_stc2(1, 2, i);151}152 153void stc2l(void *i) {154 // CHECK: define{{.*}} void @stc2l(ptr noundef %i)155 // CHECK: call void @llvm.arm.stc2l(i32 1, i32 2, ptr %i)156 // CHECK-NEXT: ret void157 __builtin_arm_stc2l(1, 2, i);158}159 160void cdp(void) {161 // CHECK: define{{.*}} void @cdp()162 // CHECK: call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)163 // CHECK-NEXT: ret void164 __builtin_arm_cdp(1, 2, 3, 4, 5, 6);165}166 167void cdp2(void) {168 // CHECK: define{{.*}} void @cdp2()169 // CHECK: call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)170 // CHECK-NEXT: ret void171 __builtin_arm_cdp2(1, 2, 3, 4, 5, 6);172}173 174unsigned mrc(void) {175 // CHECK: define{{.*}} i32 @mrc()176 // CHECK: [[R:%.*]] = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3)177 // CHECK-NEXT: ret i32 [[R]]178 return __builtin_arm_mrc(15, 0, 13, 0, 3);179}180 181unsigned mrc2(void) {182 // CHECK: define{{.*}} i32 @mrc2()183 // CHECK: [[R:%.*]] = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3)184 // CHECK-NEXT: ret i32 [[R]]185 return __builtin_arm_mrc2(15, 0, 13, 0, 3);186}187 188void mcr(unsigned a) {189 // CHECK: define{{.*}} void @mcr(i32 noundef [[A:%.*]])190 // CHECK: call void @llvm.arm.mcr(i32 15, i32 0, i32 [[A]], i32 13, i32 0, i32 3)191 __builtin_arm_mcr(15, 0, a, 13, 0, 3);192}193 194void mcr2(unsigned a) {195 // CHECK: define{{.*}} void @mcr2(i32 noundef [[A:%.*]])196 // CHECK: call void @llvm.arm.mcr2(i32 15, i32 0, i32 [[A]], i32 13, i32 0, i32 3)197 __builtin_arm_mcr2(15, 0, a, 13, 0, 3);198}199 200void mcrr(uint64_t a) {201 // CHECK: define{{.*}} void @mcrr(i64 noundef %{{.*}})202 // CHECK: call void @llvm.arm.mcrr(i32 15, i32 0, i32 %{{[0-9]+}}, i32 %{{[0-9]+}}, i32 0)203 __builtin_arm_mcrr(15, 0, a, 0);204}205 206void mcrr2(uint64_t a) {207 // CHECK: define{{.*}} void @mcrr2(i64 noundef %{{.*}})208 // CHECK: call void @llvm.arm.mcrr2(i32 15, i32 0, i32 %{{[0-9]+}}, i32 %{{[0-9]+}}, i32 0)209 __builtin_arm_mcrr2(15, 0, a, 0);210}211 212uint64_t mrrc(void) {213 // CHECK: define{{.*}} i64 @mrrc()214 // CHECK: call { i32, i32 } @llvm.arm.mrrc(i32 15, i32 0, i32 0)215 return __builtin_arm_mrrc(15, 0, 0);216}217 218uint64_t mrrc2(void) {219 // CHECK: define{{.*}} i64 @mrrc2()220 // CHECK: call { i32, i32 } @llvm.arm.mrrc2(i32 15, i32 0, i32 0)221 return __builtin_arm_mrrc2(15, 0, 0);222}223 224unsigned rsr(void) {225 // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_volatile_register.i32(metadata ![[M0:.*]])226 // CHECK-NEXT: ret i32 [[V0]]227 return __builtin_arm_rsr("cp1:2:c3:c4:5");228}229 230unsigned long long rsr64(void) {231 // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_volatile_register.i64(metadata ![[M1:.*]])232 // CHECK-NEXT: ret i64 [[V0]]233 return __builtin_arm_rsr64("cp1:2:c3");234}235 236void *rsrp(void) {237 // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_volatile_register.i32(metadata ![[M2:.*]])238 // CHECK-NEXT: [[V1:[%A-Za-z0-9.]+]] = inttoptr i32 [[V0]] to ptr239 // CHECK-NEXT: ret ptr [[V1]]240 return __builtin_arm_rsrp("sysreg");241}242 243void wsr(unsigned v) {244 // CHECK: call void @llvm.write_register.i32(metadata ![[M0]], i32 %v)245 __builtin_arm_wsr("cp1:2:c3:c4:5", v);246}247 248void wsr64(unsigned long long v) {249 // CHECK: call void @llvm.write_register.i64(metadata ![[M1]], i64 %v)250 __builtin_arm_wsr64("cp1:2:c3", v);251}252 253void wsrp(void *v) {254 // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint ptr %v to i32255 // CHECK-NEXT: call void @llvm.write_register.i32(metadata ![[M2]], i32 [[V0]])256 __builtin_arm_wsrp("sysreg", v);257}258 259unsigned int cls(uint32_t v) {260 // CHECK: call i32 @llvm.arm.cls(i32 %v)261 return __builtin_arm_cls(v);262}263 264unsigned int clsl(unsigned long v) {265 // CHECK: call i32 @llvm.arm.cls(i32 %v)266 return __builtin_arm_cls(v);267}268 269unsigned int clsll(uint64_t v) {270 // CHECK: call i32 @llvm.arm.cls64(i64 %v)271 return __builtin_arm_cls64(v);272}273 274// CHECK: ![[M0]] = !{!"cp1:2:c3:c4:5"}275// CHECK: ![[M1]] = !{!"cp1:2:c3"}276// CHECK: ![[M2]] = !{!"sysreg"}277