166 lines · c
1// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LINUX2// RUN: %clang_cc1 -triple aarch64-windows -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-WIN3// RUN: %clang_cc1 -triple arm64_32-apple-ios13 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s4#include <stdint.h>5 6void f0(void *a, void *b) {7 __clear_cache(a,b);8// CHECK: call {{.*}} @__clear_cache9}10 11void *tp (void) {12 return __builtin_thread_pointer ();13// CHECK-LINUX: call {{.*}} @llvm.thread.pointer.p0()14}15 16// CHECK: call {{.*}} @llvm.bitreverse.i32(i32 %a)17unsigned rbit(unsigned a) {18 return __builtin_arm_rbit(a);19}20 21// CHECK-WIN: [[A64:%[^ ]+]] = zext i32 %a to i6422// CHECK-WIN: call i64 @llvm.bitreverse.i64(i64 [[A64]])23// CHECK-LINUX: call i64 @llvm.bitreverse.i64(i64 %a)24unsigned long rbitl(unsigned long a) {25 return __builtin_arm_rbit64(a);26}27 28// CHECK: call {{.*}} @llvm.bitreverse.i64(i64 %a)29uint64_t rbit64(uint64_t a) {30 return __builtin_arm_rbit64(a);31}32 33void hints(void) {34 __builtin_arm_nop(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 0)35 __builtin_arm_yield(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 1)36 __builtin_arm_wfe(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 2)37 __builtin_arm_wfi(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 3)38 __builtin_arm_sev(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 4)39 __builtin_arm_sevl(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 5)40}41 42void barriers(void) {43 __builtin_arm_dmb(1); //CHECK: call {{.*}} @llvm.aarch64.dmb(i32 1)44 __builtin_arm_dsb(2); //CHECK: call {{.*}} @llvm.aarch64.dsb(i32 2)45 __builtin_arm_isb(3); //CHECK: call {{.*}} @llvm.aarch64.isb(i32 3)46}47 48void prefetch(void) {49 __builtin_arm_prefetch(0, 1, 2, 0, 1); // pstl3keep50 // CHECK: call {{.*}} @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1)51 52 __builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1keep53 // CHECK: call {{.*}} @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)54 55 __builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1strm56 // CHECK: call {{.*}} @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)57 58 __builtin_arm_prefetch(0, 0, 0, 0, 0); // plil1keep59 // CHECK: call {{.*}} @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0)60 61 __builtin_arm_prefetch(0, 0, 3, 0, 1); // pldslckeep62 // CHECK: call {{.*}} @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1)63}64 65__attribute__((target("v8.5a")))66int32_t jcvt(double v) {67 //CHECK-LABEL: @jcvt(68 //CHECK: call i32 @llvm.aarch64.fjcvtzs69 return __builtin_arm_jcvt(v);70}71 72__typeof__(__builtin_arm_rsr("1:2:3:4:5")) rsr(void);73 74uint32_t rsr(void) {75 // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])76 // CHECK-NEXT: trunc i64 [[V0]] to i3277 return __builtin_arm_rsr("1:2:3:4:5");78}79 80__typeof__(__builtin_arm_rsr64("1:2:3:4:5")) rsr64(void);81 82uint64_t rsr64(void) {83 // CHECK: call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])84 return __builtin_arm_rsr64("1:2:3:4:5");85}86 87void *rsrp(void) {88 // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])89 // CHECK-NEXT: inttoptr i64 [[V0]] to ptr90 return __builtin_arm_rsrp("1:2:3:4:5");91}92 93__typeof__(__builtin_arm_wsr("1:2:3:4:5", 0)) wsr(unsigned);94 95void wsr(unsigned v) {96 // CHECK: [[V0:[%A-Za-z0-9.]+]] = zext i32 %v to i6497 // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]])98 __builtin_arm_wsr("1:2:3:4:5", v);99}100 101__typeof__(__builtin_arm_wsr64("1:2:3:4:5", 0)) wsr64(uint64_t);102 103void wsr64(uint64_t v) {104 // CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %v)105 __builtin_arm_wsr64("1:2:3:4:5", v);106}107 108void wsrp(void *v) {109 // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint ptr %v to i64110 // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]])111 __builtin_arm_wsrp("1:2:3:4:5", v);112}113 114unsigned int cls(uint32_t v) {115 // CHECK: call i32 @llvm.aarch64.cls(i32 %v)116 return __builtin_arm_cls(v);117}118 119unsigned int clsl(unsigned long v) {120 // CHECK-WIN: [[V64:%[^ ]+]] = zext i32 %v to i64121 // CHECK-WIN: call i32 @llvm.aarch64.cls64(i64 [[V64]]122 // CHECK-LINUX: call i32 @llvm.aarch64.cls64(i64 %v)123 return __builtin_arm_cls64(v);124}125 126unsigned int clsll(uint64_t v) {127 // CHECK: call i32 @llvm.aarch64.cls64(i64 %v)128 return __builtin_arm_cls64(v);129}130 131// CHECK-LABEL: @rndr(132// CHECK-NEXT: entry:133// CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndr()134// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0135// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1136// CHECK-NEXT: store i64 [[TMP1]], ptr [[__ADDR:%.*]], align 8137// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32138// CHECK-NEXT: ret i32 [[TMP3]]139//140__attribute__((target("rand")))141int rndr(uint64_t *__addr) {142 return __builtin_arm_rndr(__addr);143}144 145// CHECK-LABEL: @rndrrs(146// CHECK-NEXT: entry:147// CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndrrs()148// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0149// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1150// CHECK-NEXT: store i64 [[TMP1]], ptr [[__ADDR:%.*]], align 8151// CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32152// CHECK-NEXT: ret i32 [[TMP3]]153//154__attribute__((target("rand")))155int rndrrs(uint64_t *__addr) {156 return __builtin_arm_rndrrs(__addr);157}158 159// CHECK-LABEL: @trap(160// CHECK: call void @llvm.aarch64.break(i32 42)161void trap() {162 __builtin_arm_trap(42);163}164 165// CHECK: ![[M0]] = !{!"1:2:3:4:5"}166