124 lines · c
1// RUN: %clang_cc1 -triple hexagon -target-cpu hexagonv66 -target-feature +hvxv66 -target-feature +hvx-length64b -emit-llvm -o - %s | FileCheck %s2// REQUIRES: hexagon-registered-target3 4// CHECK-LABEL: @test15// CHECK: call i32 @llvm.hexagon.M2.mnaci(i32 %0, i32 %1, i32 %2)6int test1(int rx, int rs, int rt) {7 return __builtin_HEXAGON_M2_mnaci(rx, rs, rt);8}9 10// CHECK-LABEL: @test211// CHECK: call double @llvm.hexagon.F2.dfadd(double %0, double %1)12double test2(double rss, double rtt) {13 return __builtin_HEXAGON_F2_dfadd(rss, rtt);14}15 16// CHECK-LABEL: @test317// CHECK: call double @llvm.hexagon.F2.dfsub(double %0, double %1)18double test3(double rss, double rtt) {19 return __builtin_HEXAGON_F2_dfsub(rss, rtt);20}21 22// CHECK-LABEL: @test423// CHECK: call i32 @llvm.hexagon.S2.mask(i32 1, i32 2)24int test4() {25 return __builtin_HEXAGON_S2_mask(1, 2);26}27 28typedef long HEXAGON_VecPred64 __attribute__((__vector_size__(64)))29 __attribute__((aligned(64)));30typedef long HEXAGON_Vect512 __attribute__((__vector_size__(64)))31 __attribute__((aligned(64)));32typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))33 __attribute__((aligned(128)));34 35// CHECK-LABEL: @test536// CHECK: call <16 x i32> @llvm.hexagon.V6.vaddcarrysat(<16 x i32> %{{[0-9]+}}, <16 x i32> %{{[0-9]+}}, <64 x i1> %{{[0-9]+}})37HEXAGON_Vect512 test5(void *in, void *out) {38 HEXAGON_Vect512 v1, v2;39 HEXAGON_Vect512 *p;40 HEXAGON_VecPred64 q1;41 42 p = (HEXAGON_Vect512 *)in;43 v1 = *p++;44 v2 = *p++;45 q1 = *p++;46 47 return __builtin_HEXAGON_V6_vaddcarrysat(v1, v2, __builtin_HEXAGON_V6_vandvrt(q1, -1));48}49 50// CHECK-LABEL: @test651// CHECK: call <16 x i32> @llvm.hexagon.V6.vrotr(<16 x i32> %{{[0-9]+}}, <16 x i32> %{{[0-9]+}})52HEXAGON_Vect512 test6(void *in, void *out) {53 HEXAGON_Vect512 v1, v2;54 HEXAGON_Vect512 *p;55 56 p = (HEXAGON_Vect512 *)in;57 v1 = *p++;58 v2 = *p++;59 60 return __builtin_HEXAGON_V6_vrotr(v1, v2);61}62 63// CHECK-LABEL: @test764// CHECK: call <16 x i32> @llvm.hexagon.V6.vsatdw(<16 x i32> %{{[0-9]+}}, <16 x i32> %{{[0-9]+}})65HEXAGON_Vect512 test7(void *in, void *out) {66 HEXAGON_Vect512 v1, v2;67 HEXAGON_Vect512 *p;68 69 p = (HEXAGON_Vect512 *)in;70 v1 = *p++;71 v2 = *p++;72 73 return __builtin_HEXAGON_V6_vsatdw(v1, v2);74}75 76// CHECK-LABEL: @test877// CHECK: call <32 x i32> @llvm.hexagon.V6.vasr.into(<32 x i32> %{{[0-9]+}}, <16 x i32> %{{[0-9]+}}, <16 x i32> %{{[0-9]+}})78HEXAGON_Vect1024 test8(void *in1, void *in2, void *out) {79 HEXAGON_Vect512 v1, v2;80 HEXAGON_Vect512 *p1;81 HEXAGON_Vect1024 *p2;82 HEXAGON_Vect1024 vr;83 84 p1 = (HEXAGON_Vect512 *)in1;85 v1 = *p1++;86 v2 = *p1++;87 p2 = (HEXAGON_Vect1024 *)in2;88 vr = *p2;89 90 return __builtin_HEXAGON_V6_vasr_into(vr, v1, v2);91}92 93// CHECK-LABEL: @test994// CHECK: call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarryo(<16 x i32> %{{[0-9]+}}, <16 x i32> %{{[0-9]+}})95HEXAGON_Vect512 test9(void *in, void *out) {96 HEXAGON_Vect512 v1, v2;97 HEXAGON_Vect512 *p;98 HEXAGON_VecPred64 q1;99 100 p = (HEXAGON_Vect512 *)in;101 v1 = *p++;102 v2 = *p++;103 q1 = *p++;104 105 return __builtin_HEXAGON_V6_vaddcarryo(v1, v2, &q1);106}107 108// CHECK-LABEL: @test10109// CHECK: call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarryo(<16 x i32> %{{[0-9]+}}, <16 x i32> %{{[0-9]+}})110HEXAGON_Vect512 test10(void *in, void *out) {111 HEXAGON_Vect512 v1, v2;112 HEXAGON_Vect512 *p;113 HEXAGON_VecPred64 q1;114 115 p = (HEXAGON_Vect512 *)in;116 v1 = *p++;117 v2 = *p++;118 q1 = *p++;119 120 return __builtin_HEXAGON_V6_vsubcarryo(v1, v2, &q1);121}122 123 124