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1// REQUIRES: mips-registered-target2// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s \3// RUN: -target-feature +dspr2 -o - \4// RUN: | FileCheck %s5 6typedef int q31;7typedef int i32;8typedef unsigned int ui32;9typedef long long a64;10 11typedef signed char v4i8 __attribute__ ((vector_size(4)));12typedef signed char v4q7 __attribute__ ((vector_size(4)));13typedef short v2i16 __attribute__ ((vector_size(4)));14typedef short v2q15 __attribute__ ((vector_size(4)));15 16void foo() {17 v2q15 v2q15_r, v2q15_a, v2q15_b, v2q15_c;18 v2i16 v2i16_r, v2i16_a, v2i16_b, v2i16_c;19 v4q7 v4q7_r, v4q7_a, v4q7_b;20 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c;21 q31 q31_r, q31_a, q31_b, q31_c;22 i32 i32_r, i32_a, i32_b, i32_c;23 ui32 ui32_r, ui32_a, ui32_b, ui32_c;24 a64 a64_r, a64_a, a64_b;25 26 // MIPS DSP Rev 127 28 v4i8_a = (v4i8) {1, 2, 3, 0xFF};29 v4i8_b = (v4i8) {2, 4, 6, 8};30 v4i8_r = __builtin_mips_addu_qb(v4i8_a, v4i8_b);31// CHECK: call <4 x i8> @llvm.mips.addu.qb32 v4i8_r = __builtin_mips_addu_s_qb(v4i8_a, v4i8_b);33// CHECK: call <4 x i8> @llvm.mips.addu.s.qb34 v4i8_r = __builtin_mips_subu_qb(v4i8_a, v4i8_b);35// CHECK: call <4 x i8> @llvm.mips.subu.qb36 v4i8_r = __builtin_mips_subu_s_qb(v4i8_a, v4i8_b);37// CHECK: call <4 x i8> @llvm.mips.subu.s.qb38 39 v2q15_a = (v2q15) {0x0000, 0x8000};40 v2q15_b = (v2q15) {0x8000, 0x8000};41 v2q15_r = __builtin_mips_addq_ph(v2q15_a, v2q15_b);42// CHECK: call <2 x i16> @llvm.mips.addq.ph43 v2q15_r = __builtin_mips_addq_s_ph(v2q15_a, v2q15_b);44// CHECK: call <2 x i16> @llvm.mips.addq.s.ph45 v2q15_r = __builtin_mips_subq_ph(v2q15_a, v2q15_b);46// CHECK: call <2 x i16> @llvm.mips.subq.ph47 v2q15_r = __builtin_mips_subq_s_ph(v2q15_a, v2q15_b);48// CHECK: call <2 x i16> @llvm.mips.subq.s.ph49 50 a64_a = 0x12345678;51 i32_b = 0x80000000;52 i32_c = 0x11112222;53 a64_r = __builtin_mips_madd(a64_a, i32_b, i32_c);54// CHECK: call i64 @llvm.mips.madd55 a64_a = 0x12345678;56 ui32_b = 0x80000000;57 ui32_c = 0x11112222;58 a64_r = __builtin_mips_maddu(a64_a, ui32_b, ui32_c);59// CHECK: call i64 @llvm.mips.maddu60 a64_a = 0x12345678;61 i32_b = 0x80000000;62 i32_c = 0x11112222;63 a64_r = __builtin_mips_msub(a64_a, i32_b, i32_c);64// CHECK: call i64 @llvm.mips.msub65 a64_a = 0x12345678;66 ui32_b = 0x80000000;67 ui32_c = 0x11112222;68 a64_r = __builtin_mips_msubu(a64_a, ui32_b, ui32_c);69// CHECK: call i64 @llvm.mips.msubu70 71 q31_a = 0x12345678;72 q31_b = 0x7FFFFFFF;73 q31_r = __builtin_mips_addq_s_w(q31_a, q31_b);74// CHECK: call i32 @llvm.mips.addq.s.w75 q31_r = __builtin_mips_subq_s_w(q31_a, q31_b);76// CHECK: call i32 @llvm.mips.subq.s.w77 78 i32_a = 0xFFFFFFFF;79 i32_b = 1;80 i32_r = __builtin_mips_addsc(i32_a, i32_b);81// CHECK: call i32 @llvm.mips.addsc82 i32_a = 0;83 i32_b = 1;84 i32_r = __builtin_mips_addwc(i32_a, i32_b);85// CHECK: call i32 @llvm.mips.addwc86 87 i32_a = 20;88 i32_b = 0x1402;89 i32_r = __builtin_mips_modsub(i32_a, i32_b);90// CHECK: call i32 @llvm.mips.modsub91 92 v4i8_a = (v4i8) {1, 2, 3, 4};93 i32_r = __builtin_mips_raddu_w_qb(v4i8_a);94// CHECK: call i32 @llvm.mips.raddu.w.qb95 96 v2q15_a = (v2q15) {0xFFFF, 0x8000};97 v2q15_r = __builtin_mips_absq_s_ph(v2q15_a);98// CHECK: call <2 x i16> @llvm.mips.absq.s.ph99 q31_a = 0x80000000;100 q31_r = __builtin_mips_absq_s_w(q31_a);101// CHECK: call i32 @llvm.mips.absq.s.w102 103 v2q15_a = (v2q15) {0x1234, 0x5678};104 v2q15_b = (v2q15) {0x1111, 0x2222};105 v4i8_r = __builtin_mips_precrq_qb_ph(v2q15_a, v2q15_b);106// CHECK: call <4 x i8> @llvm.mips.precrq.qb.ph107 108 v2q15_a = (v2q15) {0x7F79, 0xFFFF};109 v2q15_b = (v2q15) {0x7F81, 0x2000};110 v4i8_r = __builtin_mips_precrqu_s_qb_ph(v2q15_a, v2q15_b);111// CHECK: call <4 x i8> @llvm.mips.precrqu.s.qb.ph112 q31_a = 0x12345678;113 q31_b = 0x11112222;114 v2q15_r = __builtin_mips_precrq_ph_w(q31_a, q31_b);115// CHECK: call <2 x i16> @llvm.mips.precrq.ph.w116 q31_a = 0x7000FFFF;117 q31_b = 0x80000000;118 v2q15_r = __builtin_mips_precrq_rs_ph_w(q31_a, q31_b);119// CHECK: call <2 x i16> @llvm.mips.precrq.rs.ph.w120 v2q15_a = (v2q15) {0x1234, 0x5678};121 q31_r = __builtin_mips_preceq_w_phl(v2q15_a);122// CHECK: call i32 @llvm.mips.preceq.w.phl123 q31_r = __builtin_mips_preceq_w_phr(v2q15_a);124// CHECK: call i32 @llvm.mips.preceq.w.phr125 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};126 v2q15_r = __builtin_mips_precequ_ph_qbl(v4i8_a);127// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbl128 v2q15_r = __builtin_mips_precequ_ph_qbr(v4i8_a);129// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbr130 v2q15_r = __builtin_mips_precequ_ph_qbla(v4i8_a);131// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbla132 v2q15_r = __builtin_mips_precequ_ph_qbra(v4i8_a);133// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbra134 v2q15_r = __builtin_mips_preceu_ph_qbl(v4i8_a);135// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbl136 v2q15_r = __builtin_mips_preceu_ph_qbr(v4i8_a);137// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbr138 v2q15_r = __builtin_mips_preceu_ph_qbla(v4i8_a);139// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbla140 v2q15_r = __builtin_mips_preceu_ph_qbra(v4i8_a);141// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbra142 143 v4i8_a = (v4i8) {1, 2, 3, 4};144 v4i8_r = __builtin_mips_shll_qb(v4i8_a, 2);145// CHECK: call <4 x i8> @llvm.mips.shll.qb146 v4i8_a = (v4i8) {128, 64, 32, 16};147 v4i8_r = __builtin_mips_shrl_qb(v4i8_a, 2);148// CHECK: call <4 x i8> @llvm.mips.shrl.qb149 v2q15_a = (v2q15) {0x0001, 0x8000};150 v2q15_r = __builtin_mips_shll_ph(v2q15_a, 2);151// CHECK: call <2 x i16> @llvm.mips.shll.ph152 v2q15_r = __builtin_mips_shll_s_ph(v2q15_a, 2);153// CHECK: call <2 x i16> @llvm.mips.shll.s.ph154 v2q15_a = (v2q15) {0x7FFF, 0x8000};155 v2q15_r = __builtin_mips_shra_ph(v2q15_a, 2);156// CHECK: call <2 x i16> @llvm.mips.shra.ph157 v2q15_r = __builtin_mips_shra_r_ph(v2q15_a, 2);158// CHECK: call <2 x i16> @llvm.mips.shra.r.ph159 q31_a = 0x70000000;160 q31_r = __builtin_mips_shll_s_w(q31_a, 2);161// CHECK: call i32 @llvm.mips.shll.s.w162 q31_a = 0x7FFFFFFF;163 q31_r = __builtin_mips_shra_r_w(q31_a, 2);164// CHECK: call i32 @llvm.mips.shra.r.w165 a64_a = 0x1234567887654321LL;166 a64_r = __builtin_mips_shilo(a64_a, -8);167// CHECK: call i64 @llvm.mips.shilo168 169 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7};170 v2q15_b = (v2q15) {0x1234, 0x5678};171 v2q15_r = __builtin_mips_muleu_s_ph_qbl(v4i8_a, v2q15_b);172// CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbl173 v2q15_r = __builtin_mips_muleu_s_ph_qbr(v4i8_a, v2q15_b);174// CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbr175 v2q15_a = (v2q15) {0x7FFF, 0x8000};176 v2q15_b = (v2q15) {0x7FFF, 0x8000};177 v2q15_r = __builtin_mips_mulq_rs_ph(v2q15_a, v2q15_b);178// CHECK: call <2 x i16> @llvm.mips.mulq.rs.ph179 v2q15_a = (v2q15) {0x1234, 0x8000};180 v2q15_b = (v2q15) {0x5678, 0x8000};181 q31_r = __builtin_mips_muleq_s_w_phl(v2q15_a, v2q15_b);182// CHECK: call i32 @llvm.mips.muleq.s.w.phl183 q31_r = __builtin_mips_muleq_s_w_phr(v2q15_a, v2q15_b);184// CHECK: call i32 @llvm.mips.muleq.s.w.phr185 a64_a = 0;186 v2q15_a = (v2q15) {0x0001, 0x8000};187 v2q15_b = (v2q15) {0x0002, 0x8000};188 a64_r = __builtin_mips_mulsaq_s_w_ph(a64_a, v2q15_b, v2q15_c);189// CHECK: call i64 @llvm.mips.mulsaq.s.w.ph190 a64_a = 0;191 v2q15_b = (v2q15) {0x0001, 0x8000};192 v2q15_c = (v2q15) {0x0002, 0x8000};193 a64_r = __builtin_mips_maq_s_w_phl(a64_a, v2q15_b, v2q15_c);194// CHECK: call i64 @llvm.mips.maq.s.w.phl195 a64_r = __builtin_mips_maq_s_w_phr(a64_a, v2q15_b, v2q15_c);196// CHECK: call i64 @llvm.mips.maq.s.w.phr197 a64_a = 0x7FFFFFF0;198 a64_r = __builtin_mips_maq_sa_w_phl(a64_a, v2q15_b, v2q15_c);199// CHECK: call i64 @llvm.mips.maq.sa.w.phl200 a64_r = __builtin_mips_maq_sa_w_phr(a64_a, v2q15_b, v2q15_c);201// CHECK: call i64 @llvm.mips.maq.sa.w.phr202 i32_a = 0x80000000;203 i32_b = 0x11112222;204 a64_r = __builtin_mips_mult(i32_a, i32_b);205// CHECK: call i64 @llvm.mips.mult206 ui32_a = 0x80000000;207 ui32_b = 0x11112222;208 a64_r = __builtin_mips_multu(ui32_a, ui32_b);209// CHECK: call i64 @llvm.mips.multu210 211 a64_a = 0;212 v4i8_b = (v4i8) {1, 2, 3, 4};213 v4i8_c = (v4i8) {4, 5, 6, 7};214 a64_r = __builtin_mips_dpau_h_qbl(a64_a, v4i8_b, v4i8_c);215// CHECK: call i64 @llvm.mips.dpau.h.qbl216 a64_r = __builtin_mips_dpau_h_qbr(a64_a, v4i8_b, v4i8_c);217// CHECK: call i64 @llvm.mips.dpau.h.qbr218 a64_r = __builtin_mips_dpsu_h_qbl(a64_a, v4i8_b, v4i8_c);219// CHECK: call i64 @llvm.mips.dpsu.h.qbl220 a64_r = __builtin_mips_dpsu_h_qbr(a64_a, v4i8_b, v4i8_c);221// CHECK: call i64 @llvm.mips.dpsu.h.qbr222 a64_a = 0;223 v2q15_b = (v2q15) {0x0001, 0x8000};224 v2q15_c = (v2q15) {0x0002, 0x8000};225 a64_r = __builtin_mips_dpaq_s_w_ph(a64_a, v2q15_b, v2q15_c);226// CHECK: call i64 @llvm.mips.dpaq.s.w.ph227 a64_r = __builtin_mips_dpsq_s_w_ph(a64_a, v2q15_b, v2q15_c);228// CHECK: call i64 @llvm.mips.dpsq.s.w.ph229 a64_a = 0;230 q31_b = 0x80000000;231 q31_c = 0x80000000;232 a64_r = __builtin_mips_dpaq_sa_l_w(a64_a, q31_b, q31_c);233// CHECK: call i64 @llvm.mips.dpaq.sa.l.w234 a64_r = __builtin_mips_dpsq_sa_l_w(a64_a, q31_b, q31_c);235// CHECK: call i64 @llvm.mips.dpsq.sa.l.w236 237 v4i8_a = (v4i8) {1, 4, 10, 8};238 v4i8_b = (v4i8) {1, 2, 100, 8};239 __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);240// CHECK: call void @llvm.mips.cmpu.eq.qb241 __builtin_mips_cmpu_lt_qb(v4i8_a, v4i8_b);242// CHECK: call void @llvm.mips.cmpu.lt.qb243 __builtin_mips_cmpu_le_qb(v4i8_a, v4i8_b);244// CHECK: call void @llvm.mips.cmpu.le.qb245 i32_r = __builtin_mips_cmpgu_eq_qb(v4i8_a, v4i8_b);246// CHECK: call i32 @llvm.mips.cmpgu.eq.qb247 i32_r = __builtin_mips_cmpgu_lt_qb(v4i8_a, v4i8_b);248// CHECK: call i32 @llvm.mips.cmpgu.lt.qb249 i32_r = __builtin_mips_cmpgu_le_qb(v4i8_a, v4i8_b);250// CHECK: call i32 @llvm.mips.cmpgu.le.qb251 v2q15_a = (v2q15) {0x1111, 0x1234};252 v2q15_b = (v2q15) {0x4444, 0x1234};253 __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);254// CHECK: call void @llvm.mips.cmp.eq.ph255 __builtin_mips_cmp_lt_ph(v2q15_a, v2q15_b);256// CHECK: call void @llvm.mips.cmp.lt.ph257 __builtin_mips_cmp_le_ph(v2q15_a, v2q15_b);258// CHECK: call void @llvm.mips.cmp.le.ph259 260 a64_a = 0xFFFFF81230000000LL;261 i32_r = __builtin_mips_extr_s_h(a64_a, 4);262// CHECK: call i32 @llvm.mips.extr.s.h263 a64_a = 0x8123456712345678LL;264 i32_r = __builtin_mips_extr_w(a64_a, 31);265// CHECK: call i32 @llvm.mips.extr.w266 i32_r = __builtin_mips_extr_rs_w(a64_a, 31);267// CHECK: call i32 @llvm.mips.extr.rs.w268 i32_r = __builtin_mips_extr_r_w(a64_a, 31);269// CHECK: call i32 @llvm.mips.extr.r.w270 a64_a = 0x1234567887654321LL;271 i32_r = __builtin_mips_extp(a64_a, 3);272// CHECK: call i32 @llvm.mips.extp273 a64_a = 0x123456789ABCDEF0LL;274 i32_r = __builtin_mips_extpdp(a64_a, 7);275// CHECK: call i32 @llvm.mips.extpdp276 277 __builtin_mips_wrdsp(2052, 3);278// CHECK: call void @llvm.mips.wrdsp279 i32_r = __builtin_mips_rddsp(3);280// CHECK: call i32 @llvm.mips.rddsp281 i32_a = 0xFFFFFFFF;282 i32_b = 0x12345678;283 __builtin_mips_wrdsp((16<<7) + 4, 3);284// CHECK: call void @llvm.mips.wrdsp285 i32_r = __builtin_mips_insv(i32_a, i32_b);286// CHECK: call i32 @llvm.mips.insv287 i32_a = 0x1234;288 i32_r = __builtin_mips_bitrev(i32_a);289// CHECK: call i32 @llvm.mips.bitrev290 v2q15_a = (v2q15) {0x1111, 0x2222};291 v2q15_b = (v2q15) {0x3333, 0x4444};292 v2q15_r = __builtin_mips_packrl_ph(v2q15_a, v2q15_b);293// CHECK: call <2 x i16> @llvm.mips.packrl.ph294 i32_a = 100;295 v4i8_r = __builtin_mips_repl_qb(i32_a);296// CHECK: call <4 x i8> @llvm.mips.repl.qb297 i32_a = 0x1234;298 v2q15_r = __builtin_mips_repl_ph(i32_a);299// CHECK: call <2 x i16> @llvm.mips.repl.ph300 v4i8_a = (v4i8) {1, 4, 10, 8};301 v4i8_b = (v4i8) {1, 2, 100, 8};302 __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);303// CHECK: call void @llvm.mips.cmpu.eq.qb304 v4i8_r = __builtin_mips_pick_qb(v4i8_a, v4i8_b);305// CHECK: call <4 x i8> @llvm.mips.pick.qb306 v2q15_a = (v2q15) {0x1111, 0x1234};307 v2q15_b = (v2q15) {0x4444, 0x1234};308 __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);309// CHECK: call void @llvm.mips.cmp.eq.ph310 v2q15_r = __builtin_mips_pick_ph(v2q15_a, v2q15_b);311// CHECK: call <2 x i16> @llvm.mips.pick.ph312 a64_a = 0x1234567887654321LL;313 i32_b = 0x11112222;314 __builtin_mips_wrdsp(0, 1);315// CHECK: call void @llvm.mips.wrdsp316 a64_r = __builtin_mips_mthlip(a64_a, i32_b);317// CHECK: call i64 @llvm.mips.mthlip318 i32_r = __builtin_mips_bposge32();319// CHECK: call i32 @llvm.mips.bposge32320 char array_a[100];321 i32_r = __builtin_mips_lbux(array_a, 20);322// CHECK: call i32 @llvm.mips.lbux323 short array_b[100];324 i32_r = __builtin_mips_lhx(array_b, 20);325// CHECK: call i32 @llvm.mips.lhx326 int array_c[100];327 i32_r = __builtin_mips_lwx(array_c, 20);328// CHECK: call i32 @llvm.mips.lwx329 330 // MIPS DSP Rev 2331 332 v4q7_a = (v4q7) {0x81, 0xff, 0x80, 0x23};333 v4q7_r = __builtin_mips_absq_s_qb (v4q7_a);334// CHECK: call <4 x i8> @llvm.mips.absq.s.qb335 336 v2q15_a = (v2q15) {0x3334, 0x4444};337 v2q15_b = (v2q15) {0x1111, 0x2222};338 v2q15_r = __builtin_mips_addqh_ph(v2q15_a, v2q15_b);339// CHECK: call <2 x i16> @llvm.mips.addqh.ph340 v2q15_a = (v2q15) {0x3334, 0x4444};341 v2q15_b = (v2q15) {0x1111, 0x2222};342 v2q15_r = __builtin_mips_addqh_r_ph(v2q15_a, v2q15_b);343// CHECK: call <2 x i16> @llvm.mips.addqh.r.ph344 q31_a = 0x11111112;345 q31_b = 0x99999999;346 q31_r = __builtin_mips_addqh_w(q31_a, q31_b);347// CHECK: call i32 @llvm.mips.addqh.w348 q31_a = 0x11111112;349 q31_b = 0x99999999;350 q31_r = __builtin_mips_addqh_r_w(q31_a, q31_b);351// CHECK: call i32 @llvm.mips.addqh.r.w352 353 v2i16_a = (v2i16) {0xffff, 0x2468};354 v2i16_b = (v2i16) {0x1234, 0x1111};355 v2i16_r = __builtin_mips_addu_ph(v2i16_a, v2i16_b);356// CHECK: call <2 x i16> @llvm.mips.addu.ph357 v2i16_a = (v2i16) {0xffff, 0x2468};358 v2i16_b = (v2i16) {0x1234, 0x1111};359 v2i16_r = __builtin_mips_addu_s_ph(v2i16_a, v2i16_b);360// CHECK: call <2 x i16> @llvm.mips.addu.s.ph361 v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};362 v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};363 v4i8_r = __builtin_mips_adduh_qb(v4i8_a, v4i8_b);364// CHECK: call <4 x i8> @llvm.mips.adduh.qb365 v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};366 v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};367 v4i8_r = __builtin_mips_adduh_r_qb(v4i8_a, v4i8_b);368// CHECK: call <4 x i8> @llvm.mips.adduh.r.qb369 370 i32_a = 0x12345678;371 i32_b = 0x87654321;372 i32_r = __builtin_mips_append(i32_a, i32_b, 16);373// CHECK: call i32 @llvm.mips.append374 i32_a = 0x12345678;375 i32_b = 0x87654321;376 i32_r = __builtin_mips_balign(i32_a, i32_b, 3);377// CHECK: call i32 @llvm.mips.balign378 379 v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};380 v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};381 i32_r = __builtin_mips_cmpgdu_eq_qb(v4i8_a, v4i8_b);382// CHECK: call i32 @llvm.mips.cmpgdu.eq.qb383 v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};384 v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};385 i32_r = __builtin_mips_cmpgdu_lt_qb(v4i8_a, v4i8_b);386// CHECK: call i32 @llvm.mips.cmpgdu.lt.qb387 v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x54};388 v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};389 i32_r = __builtin_mips_cmpgdu_le_qb(v4i8_a, v4i8_b);390// CHECK: call i32 @llvm.mips.cmpgdu.le.qb391 392 a64_a = 0x12345678;393 v2i16_b = (v2i16) {0xffff, 0x1555};394 v2i16_c = (v2i16) {0x1234, 0x3322};395 a64_r = __builtin_mips_dpa_w_ph(a64_a, v2i16_b, v2i16_c);396// CHECK: call i64 @llvm.mips.dpa.w.ph397 a64_a = 0x12345678;398 v2i16_b = (v2i16) {0xffff, 0x1555};399 v2i16_c = (v2i16) {0x1234, 0x3322};400 a64_r = __builtin_mips_dps_w_ph(a64_a, v2i16_b, v2i16_c);401// CHECK: call i64 @llvm.mips.dps.w.ph402 403 a64_a = 0x70000000;404 v2q15_b = (v2q15) {0x4000, 0x2000};405 v2q15_c = (v2q15) {0x2000, 0x4000};406 a64_r = __builtin_mips_dpaqx_s_w_ph(a64_a, v2q15_b, v2q15_c);407// CHECK: call i64 @llvm.mips.dpaqx.s.w.ph408 a64_a = 0x70000000;409 v2q15_b = (v2q15) {0x4000, 0x2000};410 v2q15_c = (v2q15) {0x2000, 0x4000};411 a64_r = __builtin_mips_dpaqx_sa_w_ph(a64_a, v2q15_b, v2q15_c);412// CHECK: call i64 @llvm.mips.dpaqx.sa.w.ph413 a64_a = 0x1111222212345678LL;414 v2i16_b = (v2i16) {0x1, 0x2};415 v2i16_c = (v2i16) {0x3, 0x4};416 a64_r = __builtin_mips_dpax_w_ph(a64_a, v2i16_b, v2i16_c);417// CHECK: call i64 @llvm.mips.dpax.w.ph418 a64_a = 0x9999111112345678LL;419 v2i16_b = (v2i16) {0x1, 0x2};420 v2i16_c = (v2i16) {0x3, 0x4};421 a64_r = __builtin_mips_dpsx_w_ph(a64_a, v2i16_b, v2i16_c);422// CHECK: call i64 @llvm.mips.dpsx.w.ph423 a64_a = 0x70000000;424 v2q15_b = (v2q15) {0x4000, 0x2000};425 v2q15_c = (v2q15) {0x2000, 0x4000};426 a64_r = __builtin_mips_dpsqx_s_w_ph(a64_a, v2q15_b, v2q15_c);427// CHECK: call i64 @llvm.mips.dpsqx.s.w.ph428 a64_a = 0xFFFFFFFF80000000LL;429 v2q15_b = (v2q15) {0x4000, 0x2000};430 v2q15_c = (v2q15) {0x2000, 0x4000};431 a64_r = __builtin_mips_dpsqx_sa_w_ph(a64_a, v2q15_b, v2q15_c);432// CHECK: call i64 @llvm.mips.dpsqx.sa.w.ph433 434 v2i16_a = (v2i16) {0xffff, 0x2468};435 v2i16_b = (v2i16) {0x1234, 0x1111};436 v2i16_r = __builtin_mips_mul_ph(v2i16_a, v2i16_b);437// CHECK: call <2 x i16> @llvm.mips.mul.ph438 v2i16_a = (v2i16) {0x8000, 0x7fff};439 v2i16_b = (v2i16) {0x1234, 0x1111};440 v2i16_r = __builtin_mips_mul_s_ph(v2i16_a, v2i16_b);441// CHECK: call <2 x i16> @llvm.mips.mul.s.ph442 443 q31_a = 0x80000000;444 q31_b = 0x80000000; 445 q31_r = __builtin_mips_mulq_rs_w(q31_a, q31_b);446// CHECK: call i32 @llvm.mips.mulq.rs.w447 v2q15_a = (v2q15) {0xffff, 0x8000};448 v2q15_b = (v2q15) {0x1111, 0x8000};449 v2q15_r = __builtin_mips_mulq_s_ph(v2q15_a, v2q15_b);450// CHECK: call <2 x i16> @llvm.mips.mulq.s.ph451 q31_a = 0x00000002;452 q31_b = 0x80000000; 453 q31_r = __builtin_mips_mulq_s_w(q31_a, q31_b);454// CHECK: call i32 @llvm.mips.mulq.s.w455 a64_a = 0x19848419;456 v2i16_b = (v2i16) {0xffff, 0x8000};457 v2i16_c = (v2i16) {0x1111, 0x8000};458 a64_r = __builtin_mips_mulsa_w_ph(a64_a, v2i16_b, v2i16_c);459// CHECK: call i64 @llvm.mips.mulsa.w.ph460 461 v2i16_a = (v2i16) {0x1234, 0x5678};462 v2i16_b = (v2i16) {0x2233, 0x5566};463 v4i8_r = __builtin_mips_precr_qb_ph(v2i16_a, v2i16_b);464// CHECK: call <4 x i8> @llvm.mips.precr.qb.ph465 i32_a = 0x12345678;466 i32_b = 0x33334444;467 v2i16_r = __builtin_mips_precr_sra_ph_w(i32_a, i32_b, 4);468// CHECK: call <2 x i16> @llvm.mips.precr.sra.ph.w469 i32_a = 0x12345678;470 i32_b = 0x33334444;471 v2i16_r = __builtin_mips_precr_sra_r_ph_w(i32_a, i32_b, 4);472// CHECK: call <2 x i16> @llvm.mips.precr.sra.r.ph.w473 474 i32_a = 0x12345678;475 i32_b = 0x87654321;476 i32_r = __builtin_mips_prepend(i32_a, i32_b, 16);477// CHECK: call i32 @llvm.mips.prepend478 479 v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};480 v4i8_r = __builtin_mips_shra_qb(v4i8_a, 1);481// CHECK: call <4 x i8> @llvm.mips.shra.qb482 v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};483 i32_b = 1; 484 v4i8_r = __builtin_mips_shra_qb(v4i8_a, i32_b);485// CHECK: call <4 x i8> @llvm.mips.shra.qb486 v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};487 v4i8_r = __builtin_mips_shra_r_qb(v4i8_a, 1);488// CHECK: call <4 x i8> @llvm.mips.shra.r.qb489 v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};490 i32_b = 1; 491 v4i8_r = __builtin_mips_shra_r_qb(v4i8_a, i32_b);492// CHECK: call <4 x i8> @llvm.mips.shra.r.qb493 v2i16_a = (v2i16) {0x1357, 0x2468};494 v2i16_r = __builtin_mips_shrl_ph(v2i16_a, 4);495// CHECK: call <2 x i16> @llvm.mips.shrl.ph496 v2i16_a = (v2i16) {0x1357, 0x2468};497 i32_b = 8;498 v2i16_r = __builtin_mips_shrl_ph (v2i16_a, i32_b);499// CHECK: call <2 x i16> @llvm.mips.shrl.ph500 501 v2q15_a = (v2q15) {0x3334, 0x4444};502 v2q15_b = (v2q15) {0x1111, 0x2222};503 v2q15_r = __builtin_mips_subqh_ph(v2q15_a, v2q15_b);504// CHECK: call <2 x i16> @llvm.mips.subqh.ph505 v2q15_a = (v2q15) {0x3334, 0x4444};506 v2q15_b = (v2q15) {0x1111, 0x2222};507 v2q15_r = __builtin_mips_subqh_r_ph(v2q15_a, v2q15_b);508// CHECK: call <2 x i16> @llvm.mips.subqh.r.ph509 q31_a = 0x11111112;510 q31_b = 0x99999999;511 q31_r = __builtin_mips_subqh_w(q31_a, q31_b);512// CHECK: call i32 @llvm.mips.subqh.w513 q31_a = 0x11111112;514 q31_b = 0x99999999;515 q31_r = __builtin_mips_subqh_r_w(q31_a, q31_b);516// CHECK: call i32 @llvm.mips.subqh.r.w517 518 v2i16_a = (v2i16) {0x1357, 0x4455};519 v2i16_b = (v2i16) {0x3333, 0x4444};520 v2i16_r = __builtin_mips_subu_ph(v2i16_a, v2i16_b);521// CHECK: call <2 x i16> @llvm.mips.subu.ph522 v2i16_a = (v2i16) {0x1357, 0x4455};523 v2i16_b = (v2i16) {0x3333, 0x4444};524 v2i16_r = __builtin_mips_subu_s_ph(v2i16_a, v2i16_b);525// CHECK: call <2 x i16> @llvm.mips.subu.s.ph526 527 v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};528 v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};529 v4i8_r = __builtin_mips_subuh_qb(v4i8_a, v4i8_b);530// CHECK: call <4 x i8> @llvm.mips.subuh.qb531 v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};532 v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};533 v4i8_r = __builtin_mips_subuh_r_qb(v4i8_a, v4i8_b);534// CHECK: call <4 x i8> @llvm.mips.subuh.r.qb535}536 537void test_eh_return_data_regno()538{539 volatile int res;540 res = __builtin_eh_return_data_regno(0); // CHECK: store volatile i32 4541 res = __builtin_eh_return_data_regno(1); // CHECK: store volatile i32 5542}543