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1// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py2// RUN: %clang_cc1 %s -triple x86_64-unknown-unknown -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512fp16 -emit-llvm -o - | FileCheck %s3 4typedef double double8 __attribute__((ext_vector_type(8)));5 6// CHECK-LABEL: @fadd1(7// CHECK-NEXT: entry:8// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x double>, align 649// CHECK-NEXT: [[B_ADDR:%.*]] = alloca double, align 810// CHECK-NEXT: store <8 x double> [[A:%.*]], ptr [[A_ADDR]], align 6411// CHECK-NEXT: store double [[B:%.*]], ptr [[B_ADDR]], align 812// CHECK-NEXT: [[TMP0:%.*]] = load <8 x double>, ptr [[A_ADDR]], align 6413// CHECK-NEXT: [[TMP1:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v8f64(double 0.000000e+00, <8 x double> [[TMP0]])14// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[B_ADDR]], align 815// CHECK-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]]16// CHECK-NEXT: ret double [[ADD]]17//18double fadd1(double8 a, double b) {19 return __builtin_ia32_reduce_fadd_pd512(0.0, a) + b;20}21 22#pragma clang fp reassociate(on)23// CHECK-LABEL: @fadd2(24// CHECK-NEXT: entry:25// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x double>, align 6426// CHECK-NEXT: [[B_ADDR:%.*]] = alloca double, align 827// CHECK-NEXT: store <8 x double> [[A:%.*]], ptr [[A_ADDR]], align 6428// CHECK-NEXT: store double [[B:%.*]], ptr [[B_ADDR]], align 829// CHECK-NEXT: [[TMP0:%.*]] = load <8 x double>, ptr [[A_ADDR]], align 6430// CHECK-NEXT: [[TMP1:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v8f64(double 0.000000e+00, <8 x double> [[TMP0]])31// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[B_ADDR]], align 832// CHECK-NEXT: [[ADD:%.*]] = fadd reassoc double [[TMP1]], [[TMP2]]33// CHECK-NEXT: ret double [[ADD]]34//35double fadd2(double8 a, double b) {36 return __builtin_ia32_reduce_fadd_pd512(0.0, a) + b;37}38 39typedef float float16 __attribute__((ext_vector_type(16)));40 41#pragma clang fp reassociate(off)42// CHECK-LABEL: @fmul1(43// CHECK-NEXT: entry:44// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x float>, align 6445// CHECK-NEXT: [[B_ADDR:%.*]] = alloca float, align 446// CHECK-NEXT: store <16 x float> [[A:%.*]], ptr [[A_ADDR]], align 6447// CHECK-NEXT: store float [[B:%.*]], ptr [[B_ADDR]], align 448// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 6449// CHECK-NEXT: [[TMP1:%.*]] = call reassoc float @llvm.vector.reduce.fmul.v16f32(float 1.000000e+00, <16 x float> [[TMP0]])50// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[B_ADDR]], align 451// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[TMP2]]52// CHECK-NEXT: ret float [[ADD]]53//54float fmul1(float16 a, float b) {55 return __builtin_ia32_reduce_fmul_ps512(1.0f, a) + b;56}57 58typedef _Float16 half8 __attribute__((ext_vector_type(8)));59 60// CHECK-LABEL: @fmax1(61// CHECK-NEXT: entry:62// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <8 x half>, align 1663// CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 264// CHECK-NEXT: store <8 x half> [[A:%.*]], ptr [[A_ADDR]], align 1665// CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 266// CHECK-NEXT: [[TMP0:%.*]] = load <8 x half>, ptr [[A_ADDR]], align 1667// CHECK-NEXT: [[TMP1:%.*]] = call nnan half @llvm.vector.reduce.fmax.v8f16(<8 x half> [[TMP0]])68// CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[B_ADDR]], align 269// CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP1]], [[TMP2]]70// CHECK-NEXT: ret half [[ADD]]71//72_Float16 fmax1(half8 a, _Float16 b) {73 return __builtin_ia32_reduce_fmax_ph128(a) + b;74}75 76typedef _Float16 half16 __attribute__((ext_vector_type(16)));77 78// CHECK-LABEL: @fmin1(79// CHECK-NEXT: entry:80// CHECK-NEXT: [[A_ADDR:%.*]] = alloca <16 x half>, align 3281// CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 282// CHECK-NEXT: store <16 x half> [[A:%.*]], ptr [[A_ADDR]], align 3283// CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 284// CHECK-NEXT: [[TMP0:%.*]] = load <16 x half>, ptr [[A_ADDR]], align 3285// CHECK-NEXT: [[TMP1:%.*]] = call nnan half @llvm.vector.reduce.fmin.v16f16(<16 x half> [[TMP0]])86// CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[B_ADDR]], align 287// CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP1]], [[TMP2]]88// CHECK-NEXT: ret half [[ADD]]89//90_Float16 fmin1(half16 a, _Float16 b) {91 return __builtin_ia32_reduce_fmin_ph256(a) + b;92}93